Module 2 VLSI Design (18EC72)

MODULE 2
SYLLABUS:
Fabrication: CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS
Technologies, Layout Design Rules, (1.5 and 3.1 to 3.3 of TEXT2).
MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitances (3.5 to 3.6 of
TEXT1)

TEXT, REFERENCE & ADDITIONAL REFERENCE BOOKS

Book Title/Authors/Publication /Web links/Channel

“CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang &
T-1.
Yosuf Leblebici, Third Edition, Tata McGraw-Hill.

“CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste,

T-2.
and David Money Harris4th Edition, Pearson Education.

Table of Contents
2.1. CMOS Fabrication and Layout..................................................................................................... 3
2.1.1. Inverter Cross-Section ......................................................................................................... 3
2.1.2. Fabrication Process ............................................................................................................. 4
2.2. Layout Design Rules .................................................................................................................... 8
2.2.1. Design Rule Background ..................................................................................................... 9
2.2.1.1. Well Rules.................................................................................................................... 9
2.2.1.2. Transistor Rules ........................................................................................................... 9
2.2.1.3. Contact Rules There are several generally available contacts: ................................. 10
2.2.1.4. Metal Rules: .............................................................................................................. 10
2.2.1.5. Via Rules: ................................................................................................................... 11
2.2.1.6. Other Rules ............................................................................................................... 11
2.2.2. Gate Layouts ..................................................................................................................... 12
2.3. Stick Diagrams ........................................................................................................................... 12
2.4. CMOS Technologies .................................................................................................................. 14
2.4.1. Wafer Formation ............................................................................................................... 14
2.4.2. Photolithography .............................................................................................................. 15

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2.4.3. Well and Channel Formation ............................................................................................ 16

2.4.4. Silicon Dioxide (SiO2) ........................................................................................................ 17
2.4.5. Isolation............................................................................................................................. 17
2.4.6. Gate Oxide......................................................................................................................... 17
2.4.7. Gate and Source/Drain Formations .................................................................................. 18
2.4.8. Contacts and Metallization ............................................................................................... 18
2.5. Micron Design Rules ................................................................................................................. 19
2.6. MOSFET Scaling and Small-Geometry Effects ........................................................................... 20
2.6.1. Full Scaling (Constant-Field Scaling) .................................................................................. 21
2.6.1.1. Gate capacitance per Unit Area Co or Cox .................................................................. 22
2.6.1.2. Drain Current Ids ........................................................................................................ 22
2.6.1.3. Instantaneous Power P ............................................................................................. 22
2.6.2. Constant-Voltage Scaling .................................................................................................. 22
2.6.2.1. Drain Current Ids ........................................................................................................ 23
2.7. Short Channel Effects ................................................................................................................ 24
2.7.1. Velocity Saturation ............................................................................................................ 24
2.7.2. Threshold voltage –........................................................................................................... 24
2.7.3. Narrow-Channel Effects .................................................................................................... 25
2.7.4. Subthreshold Leakage ....................................................................................................... 26
2.7.5. Oxide Breakdown .............................................................................................................. 26
2.7.6. Hot Carrier Injection.......................................................................................................... 26
2.7.7. Electromigration ............................................................................................................... 27
2.7.8. Punch Through .................................................................................................................. 27
2.7.9. Drain Induced Barrier Lowering (DIBL) ............................................................................. 27
2.8. MOSFET Capacitance ................................................................................................................ 27
2.8.1. Oxide-Capacitance ............................................................................................................ 29
2.8.2. Overlap Capacitance ......................................................................................................... 29
2.8.3. Gate-to-Channel Capacitance ........................................................................................... 30
2.8.4. Gate to Source Capacitance (Cgs) : Cut-Off ...................................................................... 30
2.8.5. Gate to Drain Capacitance (Cgd) : Cut-Off ........................................................................ 31
2.8.6. Gate to Body Capacitance (Cgb) : Cut-Off ......................................................................... 31
2.8.7. Gate to Source Capacitance (Cgs) : Linear Region ............................................................ 31
2.8.8. Gate to Drain Capacitance (Cgd) : Linear Region .............................................................. 32
2.8.9. Gate to Body Capacitance (Cgb) : Linear Region............................................................... 32
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2.8.10. Gate to Source Capacitance (Cgs, Cgd, Cgb) : Saturation Region ..................................... 32
2.8.11. Junction Capacitance ........................................................................................................ 33
2.9. Question Bank ........................................................................................................................... 37

Fabrication
2.1. CMOS Fabrication and Layout
Transistors are fabricated on thin silicon wafers that serve as both a mechanical support and
an electrical common point called the substrate. Fabrication requires to define a set of masks
used to manufacture the different parts of the transistor. The size of the transistors and wires
is set by the mask dimensions and is limited by the resolution of the manufacturing process.
2.1.1. Inverter Cross-Section
Fig 2.1 shows a cross-section and corresponding schematic of an inverter. In this diagram, the
inverter is built on a p-type substrate. The pMOS transistor requires an n-type body region, so
an n-well is diffused into the substrate in its vicinity. The nMOS transistor has heavily doped
n-type source and drain regions and a polysilicon gate over a thin layer of silicon dioxide
(SiO2, also called gate oxide). n+ and p+ diffusion regions indicate heavily doped n-type and
p-type silicon. The pMOS transistor is a similar structure with p-type source and drain
regions. The polysilicon gates of the two transistors are tied together and form the input A.
The source of the nMOS transistor is connected to a metal ground line and the source of the
pMOS transistor is connected to a metal VDD line. The drains of the two transistors are
connected with metal to form the output Y. A thick layer of SiO2 called field oxide prevents
metal from shorting to other layers except where contacts are explicitly etched.

Fig 2.1 Inverter cross-section with well and substrate contacts.

The substrate must be tied to a low potential to avoid forward-biasing the p-n junction
between the p-type substrate and the n+ nMOS source or drain. Likewise, the n-well must be

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tied to a high potential. This is done by adding heavily doped substrate and well contacts, or
taps, to connect GND and VDD to the substrate and n-well, respectively.
2.1.2. Fabrication Process
The fabrication sequence consists of a series of steps in which layers of the chip are defined
through a process called photolithography. Because a whole wafer full of chips is processed
in each step, the cost of the chip is proportional to the chip area, rather than the number of
transistors.
The inverter could be defined by a hypothetical set of six masks: n-well, polysilicon, n+
diffusion, p+ diffusion, contacts, and metal. Masks specify where the components will be
manufactured on the chip. Fig 2.2(a) shows a top view of the six masks. The cross-section of
the inverter from Fig 2.1 was taken along the dashed line.

Fig 2.2 Inverter mask set

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The process begins with the creation of an n-well on a bare p-type silicon wafer. Fig 2.3
shows cross-sections of the wafer after each processing step involved in forming the n-well;
Fig 2.3(a) illustrates the bare substrate before processing. Forming the n-well requires adding
enough Group V dopants into the silicon substrate to change the substrate from p-type to n-
type in the region of the well. To define what regions receive n-wells, we grow a protective
layer of oxide over the entire wafer, then remove it where we want the wells. We then add the
n-type dopants; the dopants are blocked by the oxide, but enter the substrate and form the
wells where there is no oxide.

The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that causes

Si and O2 to react and become SiO2 on the wafer surface (Fig 2.3(b)). The oxide must be
patterned to define the n-well. An organic photoresist that softens where exposed to light is
spun onto the wafer (Fig 2.3(c)). The photoresist is exposed through the n-well mask (Fig
2.2(b)) that allows light to pass through only where the well should be. The softened

Fig 2.3 Cross-sections while manufacturing the n-well

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photoresist is removed to expose the oxide (Fig 2.3(d)). The oxide is etched with hydrofluoric
acid (HF) where it is not protected by the photoresist (Fig 2.3(e)), then the remaining
photoresist is stripped away using a mixture of acids called piranha etch (Fig 2.3(f)). The well
is formed where the substrate is not covered with oxide.
Two ways to add dopants are diffusion and ion implantation.
In the diffusion process, the wafer is placed in a furnace with a gas containing the dopants.
When heated, dopant atoms diffuse into the substrate. Notice how the well is wider than the
hole in the oxide on account of lateral diffusion (Fig 2.3(g)).
With ion implantation, dopant ions are accelerated through an electric field and blasted into
the substrate. In either method, the oxide layer prevents dopant atoms from entering the
substrate where no well is intended. Finally, the remaining oxide is stripped with HF to leave
the bare wafer with wells in the appropriate places (Fig 2.3(h)).
The transistor gates are formed next. These consist of polycrystalline silicon, generally called
polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then the wafer is
placed in a reactor with silane gas (SiH4) and heated again to grow the polysilicon layer

Fig 2.4 Cross-sections while manufacturing polysilicon and n-diffusion

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through a process called Chemical Vapor Deposition (CVD). The polysilicon is heavily
doped to form a reasonably good conductor. The resulting cross-section is shown in Fig
2.4(a).
As before, the wafer is patterned with photoresist and the polysilicon mask (Fig 2.2(c)),
leaving the polysilicon gates atop the thin gate oxide (Figure 2.4(b)). The n+ regions are
introduced for the transistor active area and the well contact. As with the well, a protective
layer of oxide is formed (Fig 2.4(c)) and patterned with the n-diffusion mask (Fig 2.2(d)) to
expose the areas where the dopants are needed (Fig 2.4(d)). The n+ regions in Fig 2.4(e) are
typically formed with ion implantation. The polysilicon gate over the nMOS transistor blocks
the diffusion so the source and drain are separated by a channel under the gate. This is called
a self-aligned process because the source and drain of the transistor are automatically formed
adjacent to the gate without the need to precisely align the masks. Finally, the protective
oxide is stripped (Fig 2.4(f)).
The process is repeated for the p-diffusion mask (Fig 2.2(e)) to give the structure of Fig
2.5(a). The field oxide is grown to insulate the wafer from metal and patterned with the
contact mask (Fig 2.2(f)) to leave contact cuts where metal should attach to diffusion or
polysilicon (Fig 2.5(b)). Finally, aluminum is sputtered over the entire wafer, filling the
contact cuts as well. Sputtering involves blasting aluminum into a vapor that evenly coats the
wafer. The metal is patterned with the metal mask (Fig 2.2(g)) and plasma etched to remove
metal everywhere except where wires should remain (Figure 2.5(c)). This completes the
simple fabrication process.

Fig 2.5 Cross-sections while manufacturing p-diffusion, contacts, and metal

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2.2. Layout Design Rules

Layout design rules describe how small features can be and how closely they can be reliably
packed in a particular manufacturing process. Manufacturing process rules are based on a
single parameter, 𝞴, that characterizes the resolution of the process. 𝞴 is generally half of the
minimum drawn transistor channel length also referred as feature size. This length is the
distance between the source and drain of a transistor and is set by the minimum width of a
polysilicon wire. For example, a 180 nm process has a minimum polysilicon width (and
hence transistor length) of 0.18 μm and uses design rules with 𝞴 = 0.09 μm. Lambda-based
rules make scaling layout trivial; the same layout can be moved to a new process simply by
specifying a new value of 𝞴.
The lambda-based design rules with two metal layers in an n-well process are as follows:
• Metal and diffusion have minimum width and spacing of 4𝞴.

• Contacts are 2 𝞴 × 2 𝞴 and must be surrounded by 1 𝞴 on the layers above and below.

• Polysilicon uses a width of 2 𝞴.

• Polysilicon overlaps diffusion by 2 𝞴 where a transistor is desired and has a spacing of
1𝞴 away where no transistor is desired.
• Polysilicon and contacts have a spacing of 3 𝞴 from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6 𝞴 and avoids nMOS transistors by 6 𝞴.
Fig 2.6 shows the basic MOSIS design rules for a process with two metal layers.

Fig 2.6 Simplified 𝞴 -based design rules

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2.2.1. Design Rule Background

2.2.1.1. Well Rules
The n-well is usually a deeper implant than the transistor source/drain implants, and
therefore, it is necessary to provide sufficient clearance between the n-well edges and the
adjacent n+ diffusions. The clearance between the well edge and an enclosed diffusion is
determined by the transition of the field oxide across the well boundary. Because the n-well
sheet resistance can be several kΩ per square, it is necessary to ground the well thoroughly by
providing a sufficient number of well taps.
2.2.1.2. Transistor Rules
CMOS transistors are generally defined by at least four physical masks. These are active
(also called diffusion), n-select, p-select and polysilicon (also called poly). The active mask
defines all areas where either n- or ptype diffusion is to be placed or where the gates of
transistors are to be placed. The gates of transistors are defined by the logical AND of the
polysilicon mask and the active mask, i.e., where polysilicon crosses diffusion. The select
layers define what type of diffusion is required. n-select surrounds active regions where n-
type diffusion is required. p-select surrounds areas where p-type diffusion is required. n-
diffusion areas inside p-well regions define nMOS transistors. n-diffusion areas inside n-well
regions define n-well contacts. Likewise, p-diffusion areas inside n-wells define pMOS
transistors. p-diffusion areas inside p-wells define p-well contacts. Poly is required to extend
beyond the edges of the active area. This is often termed the gate extension. Active must
extend beyond the poly gate so that diffused source and drain regions exist to carry charge
into and out of the channel. Poly and active regions that should not form a transistor must be
kept separated; this results in a spacing rule from active to polysilicon.

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Fig 2.7 CMOS n-well process transistor and well/substrate contact construction
Fig 2.7(a) shows the mask construction for the final structures that appear in Fig 2.7(b).
2.2.1.3. Contact Rules There are several generally available contacts:
• Metal to p-active (p-diffusion)
• Metal to n-active (n-diffusion)
• Metal to polysilicon
• Metal to well or substrate
Depending on the process, other contacts such as
buried polysilicon-active contacts may be allowed
for local interconnect. Because the substrate is
divided into well regions, each isolated well must be
tied to the appropriate supply voltage; i.e., the n-well
must be tied to VDD and the substrate or p-well
must be tied to GND with well or substrate contacts.
As metal makes a poor connection to the lightly
doped substrate or well. Hence, a heavily doped
active region is placed beneath the contact, as shown
at the source of the nMOS transistor in Fig 2.8.
2.2.1.4. Metal Rules:
Metal spacing may vary with the width of the metal line. That is, above some metal wire
width, the minimum spacing may be increased. This is due to etch characteristics of small
versus large metal wires. There may also be maximum metal width rules. That is, single

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metal wires cannot be greater than a certain width. If wider wires are desired, they are
constructed by paralleling a number of smaller wires and adding checkerboard links to tie the
wires together. Additionally, there may be spacing rules that are applied to long, closely
spaced parallel metal lines.

2.2.1.5. Via Rules:

Processes may vary in whether they allow stacked vias to be placed over polysilicon and
diffusion regions. Some processes allow vias to be placed within these areas, but do not allow
the vias to straddle the boundary of polysilicon or diffusion. Modern planarized processes
permit stacked vias, which reduces the area required to pass from a lower-level metal to a
high-level metal.

2.2.1.6. Other Rules

Some additional rules that might be present in some processes are as follows:

• Extension of polysilicon or metal beyond a contact or via

• Differing gate poly extensions depending on the device length
• Maximum width of a feature
• Minimum area of a feature (small pieces of photoresist can peel off and float away)
• Minimum notch sizes (small notches are rarely beneficial and can interfere with
resolution enhancement techniques)
pMOS transistors are often wider than
nMOS transistors because holes move more
slowly than electrons so the transistor has to
be wider to deliver the same current. Fig
2.9(a) shows a unit inverter layout with a
unit nMOS transistor and a double-sized
pMOS transistor. Fig 2.9(b) shows a
schematic for the inverter annotated with
Width/Length for each transistor. Fig 2.9(c)
shows a shorthand, specifying multiples of
unit width and assuming minimum length.
Fig 2.9 Inverter with dimensions labelled

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2.2.2. Gate Layouts

This comprises of a simple layout style based on a “line of diffusion” rule that is commonly
used for standard cells in automated layout systems.
• This style consists of four horizontal strips: metal ground at the bottom of the cell, n-
diffusion, p-diffusion, and metal power at the top.
• The power and ground lines are often called supply rails.
• Polysilicon lines run vertically to form transistor gates.
• Metal wires within the cell connect the transistors appropriately.
Fig 2.10 shows such a layout for an inverter. The input A can be connected from the top,

Fig 2.10 Inverter cell layout Fig 2.11 3-input NAND standard cell gate layouts
bottom, or left in polysilicon. The output Y is available at the right side of the cell in metal.
The well and substrate taps are placed under the power and ground rails, respectively. Fig
2.11 shows a 3-input NAND gate. The nMOS transistors are connected in series while the
pMOS transistors are connected in parallel. The height of the cell is 36 𝞴, or 40 𝞴 if the 4 𝞴
space between the cell and another wire above it is counted.

2.3. Stick Diagrams

Stick diagrams do not need to be drawn to scale. Fig 2.12 show stick diagrams for an inverter
and a 3-input NAND gate.

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Fig 2.12 Stick diagrams of inverter and 3-input NAND gate.t

The area of a layout can be easily estimated from the corresponding stick diagram even
though the diagram is not to scale.
Although schematics focus on transistors, layout area is usually determined by the metal
wires. Transistors are merely widgets
that fit under the wires. If the wires
have a width of 4 𝞴 and a spacing of 4
𝞴 to the next wire, the track pitch is 8
𝞴, as shown in Fig 2.13(a). This pitch
also leaves room for a transistor to be
placed between the wires (Fig
2.13(b)). Therefore, it is reasonable to
estimate the height and width of a cell
by counting the number of metal tracks and multiplying by 8 𝞴.

A slight complication is the required

spacing of 12 𝞴 between nMOS and
pMOS transistors set by the well, as
shown in Fig 2.14(a). This space can be
occupied by an additional track of wire,
shown in Fig 2.14(b).

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Fig 2.15 shows how to count tracks to estimate the size of a 3-input NAND. There are four
vertical wire tracks, multiplied by 8 𝞴 per track to give a cell width of 32𝞴. There are five
horizontal tracks, giving a cell height of 40𝞴.

Example: Sketch a stick diagram for a CMOS gate computing and

estimate the cell width and height.

2.4. CMOS Technologies

CMOS processing steps can be broadly divided into two parts. Transistors are formed in the
Front-End-of-Line (FEOL) phase, while wires are built in the Back-End-of-Line (BEOL)
phase.
2.4.1. Wafer Formation
The basic raw material used in CMOS fabs is a wafer or disk of silicon, roughly 75 mm to
300 mm in diameter and less than 1 mm thick. Wafers are cut from boules, cylindrical ingots

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of single-crystal silicon, that have been

pulled from a crucible of pure molten
silicon. This is known as the Czochralski
method and is currently the most common
method for producing single-crystal
material. Controlled amounts of impurities
are added to the melt to provide the crystal
with the required electrical properties. A
seed crystal is dipped into the melt to
initiate crystal growth. The silicon ingot
takes on the same crystal orientation as the
seed. A graphite radiator heated by radio-
frequency induction surrounds the quartz
crucible and maintains the temperature a
few degrees above the melting point of silicon (1425 °C). The atmosphere is typically helium
or argon to prevent the silicon from oxidizing. The seed is gradually withdrawn vertically
from the melt while simultaneously being rotated, as shown in Fig 2.17. The molten silicon
attaches itself to the seed and recrystallizes as it is withdrawn. The seed withdrawal and
rotation rates determine the diameter of the ingot.
2.4.2. Photolithography
The primary method for defining areas of interest on a wafer is by the use of photoresists.
The wafer is coated with the photoresist and subjected to selective illumination through the
photomask. After the initial patterning of photoresist, other barrier layers such as
polycrystalline silicon, silicon dioxide, or silicon nitride can be used as physical masks on the
chip. A photomask is
constructed with chromium
covered quartz glass. A UV
light source is used to
expose the photoresist.
Fig 2.18 illustrates the
lithography process. The
photomask has chrome
where light should be

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blocked. The UV light floods the mask from the backside and passes through the clear
sections of the mask to expose the organic
photoresist (PR) that has been coated on the wafer. A developer is then solvent used to
dissolve the soluble unexposed photoresist, leaving islands of insoluble exposed photoresist.
2.4.3. Well and Channel Formation
The following are main CMOS technologies:
• n-well process
• p-well process
• twin-well process
• triple-well process
In a p-well process, the nMOS transistors are built in a p-well and the pMOS transistor is
placed in the n-type substrate. In the n-well process, nMOS transistors are built in the p-type
substrate and the pMOS transistor is placed in the n-well. A twin-well process allows the
optimization of each transistor type. A third well can be added to create a triple-well process.
Wells and other features require regions of doped silicon. Varying proportions of donor and
acceptor dopants can be achieved using epitaxy, deposition, or implantation.
Epitaxy involves growing a single-crystal film on the silicon surface by subjecting the silicon
wafer surface to an elevated temperature and a source of dopant material.
Deposition involves placing dopant material onto the silicon surface and then driving it into
the bulk using a thermal diffusion step. This can be used to build deep junctions. A step
called chemical vapor deposition (CVD) can be used for the deposition. As its name suggests,
CVD occurs when heated gases react in the vicinity of the wafer and produce a product that is
deposited on the silicon surface.
Ion implantation involves bombarding the silicon substrate with highly energized donor or
acceptor atoms. When these atoms impinge on the silicon surface, they travel below the
surface of the silicon, forming regions with varying doping concentrations.
Fig 2.19 shows a typical triple-well structure. The nMOS transistor is situated in the p-well
located in the deep n-well. Other nMOS transistors could be built in different p-wells so that
they do not share the same body node. Transistors in a p-well in a triple-well process will
have different characteristics than transistors in the substrate because of the different doping
levels. The pMOS transistors are located in the shallow (normal) n-well. The figure shows the
cross-section of an inverter.

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Fig 2.19 Well structure in triple-well process

2.4.4. Silicon Dioxide (SiO2)
Various thicknesses of SiO2 may be required, depending on the particular process. Thin
oxides are required for transistor gates; thicker oxides might be required for higher voltage
devices. Oxidation of silicon is achieved by heating silicon wafers in an oxidizing
atmosphere.
The following are some common approaches:
• Wet oxidation––when the oxidizing atmosphere contains water vapor. The temperature is
usually between 900 °C and 1000 °C.
• Dry oxidation––when the oxidizing atmosphere is pure oxygen. Temperatures are in the
region of 1200 °C to achieve an acceptable growth rate. It is used to form thin, highly
controlled gate oxides, while wet oxidation may be used to form thick field oxides.
• Atomic layer deposition (ALD)––when a thin chemical layer (material A) is attached to a
surface and then a chemical (material B) is introduced to produce a thin layer of the
required layer (i.e., SiO2––this can also be used for other various dielectrics and metals).
The process is then repeated and the required layer is built up layer by layer.
2.4.5. Isolation
Individual devices in a CMOS process need to be isolated from one another so that they do
not have unexpected interactions. The transistor gate consists of a thin gate oxide layer.
Elsewhere, a thicker layer of field oxide separates polysilicon and metal wires from the
substrate. The source and drain of the transistors form reverse-biased p–n junctions with the
substrate or well, isolating them from their neighbors.
2.4.6. Gate Oxide
The next step in the process is to form the gate oxide for the transistors. As mentioned, this is
most commonly in the form of silicon dioxide (SiO2). In the case of STI-defined source/drain
regions, the gate oxide is grown on top of the planarized structure. The oxide structure is
called the gate stack because current technologies produce a stack that consists of a few

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atomic layers, each 3–4 Å thick, of SiO2 for reliability, overlaid with a few layers of an
oxynitrided oxide.
2.4.7. Gate and Source/Drain Formations
When silicon is deposited on SiO2 or other surfaces without crystal orientation, it forms
polycrystalline silicon, commonly called polysilicon or simply poly. An annealing process is
used to control the size of the single crystal domains and to improve the quality of the
polysilicon. The polysilicon gate serves as a mask to allow precise alignment of the source
and drain on either side of the gate. This process is called a self-aligned polysilicon gate
process. The steps to define the gate, source, and drain in a self-aligned polysilicon gate are
as follows:
• Grow gate oxide wherever transistors are required
• Deposit polysilicon on chip
• Pattern polysilicon (both gates and interconnect)
• Etch exposed gate oxide—i.e., the area of gate oxide where transistors are required that
was not covered by polysilicon; at this stage, the chip has windows down to the well or
substrate wherever a source/drain diffusion is required
• Implant pMOS and nMOS source/drain regions
2.4.8. Contacts and Metallization
Contact cuts are made to source, drain, and gate according to the contact mask. These are
holes etched in the dielectric after the source/drain step. Older processes commonly use
aluminum (Al) for wires, although newer ones offer copper (Cu) for lower resistance.
Tungsten (W) can be used as a plug to fill the contact
Metallization is the process of building wires to connect the devices. Conventional
metallization uses aluminum. Aluminum can be deposited either by evaporation or
sputtering.
Evaporation is performed by passing a high electrical current through a thick aluminum wire
in a vacuum chamber. Some of the aluminum atoms are vaporized and deposited on the
wafer.
Sputtering is achieved by generating a gas plasma by ionizing an inert gas using an RF or DC
electric field. The ions are focused on an aluminum target and the plasma dislodges metal
atoms, which are then deposited on the wafer.

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2.5. Micron Design Rules

Table 2.1 lists a set of micron design rules for a hypothetical 65 nm process. The rules differ
slightly but not immensely from lambda-based rules with 𝞴 = 0.035μm. Note that upper level
metal rules are highly variable depending on the metal thickness; thicker wires require greater
widths and spacings and bigger vias.

TABLE 3.1 Micron design rules for 65 nm process

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2.6. MOSFET Scaling and Small-Geometry Effects

The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as
scaling.
There are two basic types of scaling:
• constant-field scaling
• constant voltage scaling.
Scaling of MOS transistors causes the systematic reduction of overall dimensions of the
devices as allowed by the available technology, while preserving the geometric ratios found
in the larger devices. To describe device scaling, we introduce a constant scaling factor S >
1. All horizontal and vertical dimensions of the large-size transistor are then divided by this
scaling factor to obtain the scaled device.
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Fig 2.1 Scaling of a typical MOSFET by a scaling factor of S.

2.6.1. Full Scaling (Constant-Field Scaling)

This scaling option attempts to preserve the magnitude of internal electric fields in the
MOSFET, while the dimensions are scaled down by a factor of S. To achieve this goal, all
potentials must be scaled down proportionally, by the same scaling factor. Table 2.1 lists the
scaling factors for all significant dimensions, potentials, and doping densities of the MOS
transistor.

Table 2.1 Full scaling of MOSFET dimensions, potentials, and doping densities.

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Scaling Factors for Device Parameters

2.6.1.1. Gate capacitance per Unit Area Co or Cox

2.6.1.2. Drain Current Ids

Since all terminal voltages are scaled down by the factor S as well, the linear-mode drain
current of the scaled MOSFET can now be found as:

Similarly, the saturation-mode drain current is also reduced by the same scaling factor.

2.6.1.3. Instantaneous Power P

Full scaling reduces both the drain current and the drain-to-source voltage by a factor of S;
hence, the power dissipation of the transistor will be reduced by the factor S2 .

2.6.2. Constant-Voltage Scaling

In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in
full scaling. The power supply voltage and the terminal voltages, on the other hand, remain
unchanged. The doping densities must be increased by a factor of S2 in order to preserve the
charge-field relations. Table 3.2 shows the constant-voltage scaling of key dimensions,
voltages, and densities.

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Table 2.2 Constant-voltage scaling of MOSFET dimensions, potentials, and doping densities

2.6.2.1. Drain Current Ids

The gate oxide capacitance per unit area Cox is increased by a factor of S, which means that
the transconductance parameter is also increased by S. Since the terminal voltages remain
unchanged, the linear mode drain current of the scaled MOSFET can be written as:

Also, the saturation-mode drain current will be increased by a factor of S after constant
voltage scaling.

Since the drain current is increased by a factor of S while the drain-to-source voltage remains
unchanged, the power dissipation of the MOSFET increases by a factor of S.

Finally, the power density (power dissipation per unit area) is found to increase by a factor of
S3 after constant-voltage scaling, with possible adverse effects on device reliability.
Table 3.5.Effects of constant-voltage scaling upon key device characteristics.

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As the device dimensions are systematically reduced through full scaling or constant-voltage
scaling, various physical limitations become increasingly more prominent, and ultimately
restrict the amount of feasible scaling for some device dimensions.

2.7. Short Channel Effects

A MOSFET is called a short channel device when the channel length is close to the same size
as the depletion region thickness (L≈ xdm). It can also be defined as when the effective
channel length Leff is close to the same as the diffusion depth (Leff≈ xj)

2.7.1. Velocity Saturation

As the device gets smaller, the relative E-field energy tends to increase and the carriers in the
channel can reach higher and higher speeds. The long channel equations (i.e., the 1st order IV
expressions) shows a linear relationship between the E-field and the velocity of the carrier.
However, at a point, the carriers will reach a maximum speed due to collisions with other
electrons and other particles in the Silicon. At this point, there is no longer a linear
relationship between the applied E-field (VDS) and the carrier velocity, which ultimately
limits the increase in IDS. We can model this effect by altering the electron mobility term, un.

un where η is an empirical coefficient

2.7.2. Threshold voltage –
The threshold voltage expression for a long-channel MOSFET is,

The channel depletion region was assumed to be created only by the applied gate voltage, and
the depletion regions associated with the drain and source pn-junctions were neglected. The
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shape of this gate-induced bulk (channel) depletion region was assumed to be rectangular,
extending from the source to the drain. In short-channel MOS transistors, however, the n+
drain and source diffusion regions in the p-type substrate induce a significant amount of
depletion charge; consequently, the long-channel threshold voltage expression over estimates
the depletion charge supported by the gate voltage. The threshold voltage value is therefore
larger than the actual threshold voltage of the short-channel MOSFET.

where VT0 is the zero-bias threshold voltage for the conventional long channel ϪVT0 is the
threshold voltage shift due to the short-channel effect.

2.7.3. Narrow-Channel Effects

MOS transistors that have channel widths W on the same order of magnitude as the
maximum depletion region thickness xdm are defined as narrow-channel devices. The most
significant narrow-channel effect is that the actual threshold voltage of such a device is larger
than the conventional threshold voltage. The oxide thickness in the channel region is tox,
while the regions around the channel are covered by a thick field oxide (FOX). Since the gate
electrode also overlaps with the field oxide, a relatively shallow depletion region forms
underneath this FOX-overlap area as well. Consequently, the gate voltage must also support
this additional depletion charge in order to establish the conducting channel. The charge
contribution of this fringe depletion region to the overall channel depletion charge is
negligible in wider devices. For MOSFETs with small channel widths, however, the actual
threshold voltage increases as a result of this extra depletion charge.

The additional contribution to the threshold voltage due to narrow-channel effects can be
modeled as follows:

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2.7.4. Subthreshold Leakage

When VGS<VT, there is no inversion in the channel and hence, no charge carriers to carry
current from the Drain to Source. This
transition from no-inversion to inversion
doesn’t happen instantaneously. There is a
small amount of current that does flow
when VGS<VT. This current is
Subthreshold leakage current. As devices
get smaller, this current has become a
non-negligible quantity. Current in this
region follows the relationship:

2.7.5. Oxide Breakdown

The Oxide in a MOSFET serves as an insulator between the Gate electrode and the induced
channel in the semiconductor. As tox gets
thinner and thinner, it becomes difficult to
grow a planar surface. The thin parts of the
non-planar oxide can be so thin that they will
short out to the semiconductor. Another
problem is that electrons can be excited enough in the Gate to have the energy to jump
through the oxide. This effectively shorts the Gate to the Source/Drain.

2.7.6. Hot Carrier Injection

As geometries shrink and doping
densities increase, electrons can
be accelerated fast enough to
actually inject themselves into
the oxide layer. This causes
permanent change in the oxide
interface charge distribution,

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degrading the current-voltage characteristics of the MOSFET.

2.7.7. Electromigration
When the metal interconnect gets smaller, its current density increases. The ions in the
conductor will actually move due to the momentum of conducting electrons and diffusion
metal atoms. This can leave holes in the metals which lead to opens. This can also build up
regions of unwanted metal that may short to an adjacent trace.

2.7.8. Punch Through

When the depletion regions around the
Source and Drain get large enough to
actually touch. This is an extreme case of
channel modulation. This leads to a very
large diffusion layer and causes a rapid
increase in IDS versus VDS. This limits the
maximum operating voltage of the device in order to prevent damage due to the high electron
acceleration,

2.7.9. Drain Induced Barrier Lowering (DIBL)

If the gate length is scaled without properly scaling the Source/Drain regions, the Drain
voltage will cause an unproportionally large inversion layer. This inversion interferes with
the desired inversion layer being created by the Gate voltage. This effectively lowers the
Threshold voltage because it takes less energy to create inversion since the Drain is providing
some inversion itself.

2.8. MOSFET Capacitance

Capacitance = Charge / Volt = (C/V)
The charge in a semiconductor is a complex, 3-
dimensional, distribution due to the materials,
doping, and applied E-field. Simple
approximations for the MOSFET capacitances are
defined as lumped capacitance for an AC model of

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the transistors-each capacitance will have multiple contributions and different values
depending on the state of the transistor (i.e., cutoff, linear, saturation)

MOSFET Dimensions
Mask Length – The gate length drawn during fabrication is called the Drawn Length, LM. In
reality, the diffusion regions extend lightly under the gate by a distance, LD. This is called
overlap. The actual gate length (L) is given by:

MOSFET Dimensions
W= Channel Width
tox= Oxide thickness
xj= diffusion region depth
Y = diffusion region length
Channel-Stop Implants
In order to prevent the n+ diffusion regions from adjacent MOSFETS from influencing each
other, we use "channel-stop implants". This is a heavily doped region of opposite typed
material (i.e., p+ for an n-type). These electrically isolate each transistor from each other.
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MOSFET Capacitance
The various capacitances are categorized into two groups
1) Oxide Capacitances-capacitance due to the Gate oxide
2) Junction Capacitances -capacitance due to the Source/Drain diffusion regions

2.8.1. Oxide-Capacitance
Oxide Capacitance refers to capacitance which uses the gate oxide as the insulator between
the parallel plates of the capacitor. As a result, these capacitances always use the Gate as one
of the terminals of the capacitor.
There are these following capacitances:
Cgb= Gate to Body capacitance
Cgd= Gate to Drain capacitance
Cgs= Gate to Source capacitance
Each of these values will differ depending on the mode of operation of the MOSFET.

2.8.2. Overlap Capacitance

Capacitance from the Gate to the Source/Drain due to the overlap region (LD). This creates:

- where Cox is the unit-area capacitance (i.e., multiply by area to find total capacitance, F/m2
or F/um2)
This capacitance does NOT depend on the external bias of the MOSFET since the Gate and
the Source/Drain do not have their carrier density altered during bias.

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2.8.3. Gate-to-Channel Capacitance

The gate-to-channel configuration results in 3 capacitances (Cgb, Cgs, Cgd). These
capacitances change as a result of external bias since in effect, the "bottom plate" of the
capacitor is being moved around during depletion/inversion

2.8.4. Gate to Source Capacitance (Cgs) : Cut-Off

During Cut-off, there is no channel beneath the Gate. Since there is no channel that links the
Gate to the Source (i.e., no ΔQ), there is no Gate-to-Channel capacitance.

This leaves the overlap capacitance as the only component to Cgs in cut-off:

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2.8.5. Gate to Drain Capacitance (Cgd) : Cut-Off

Just as Cgs, during Cut-off, there is no channel beneath the Gate. Since there is no channel
that links the Gate to the Drain (i.e., no ΔQ), there is no Gate-to-Channel capacitance.

this leaves the overlap capacitance as the only component to Cgd in cut-off:

2.8.6. Gate to Body Capacitance (Cgb) : Cut-Off

There is a capacitor between the Gate and Body -
The bottom plate is the conductor formed by the p-
type silicon since it has majority charge carriers
and acts as a conductor.
The Gate-to-Body Capacitance is described as:

2.8.7. Gate to Source Capacitance (Cgs) : Linear Region

When operating in the linear region, a channel is
present in the substrate. This can be thought of as
a conductor (or metal plate) that contacts the
Source and Drain. This results in a capacitance
between the Gate and the Source/Drain. We split
this capacitance between the Source and Drain for simplicity
• the Gate-to-Channel contribution to CGS is (1/2)CoxWL The total CGS capacitance in
the linear region includes the overlap capacitance:
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2.8.8. Gate to Drain Capacitance (Cgd) : Linear Region

The Gate-to-Drain Capacitance is identical to the Gate-to-Source Capacitance in the Linear
region:

2.8.9. Gate to Body Capacitance (Cgb) : Linear Region

Since the channel (inversion layer) looks like a metal plate to the gate, the Gate can't actually
see the substrate anymore. This means that the capacitance between the Gate and Body is
zero when a channel is present

2.8.10. Gate to Source Capacitance (Cgs, Cgd, Cgb) : Saturation Region

When operating in the saturation region, the channel is pinched off. We make the assumption
that there is no longer a link between the Gate and Drain and roughly 2/3 of the channel is
still present linking the Gate to the Source (2L/3) 3). The pinched off channel still effectively
shields the gate from the body

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From these approximations, we can describe the capacitances in the saturation region

Summary of Oxide-Related Capacitance

2.8.11. Junction Capacitance

Junction Capacitance refers to capacitance between the diffusion regions of the Source &
Drain to the doped substrate surrounding them. They are called "junction" because these
capacitances are due to the PN junctions that are formed between the two materials. We are
concerned with the following junction capacitances: Csb= Source to Body capacitance Cdb=
Drain to Body capacitance. These capacitances are highly dependent on the bias voltages
since the effective distance between plates is the depth of the built-in depletion region that
forms at the PN junction

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1) n+ / p junction = diffusion region to substrate beneath gate

2) n+ / p+ junction = diffusion region to channel-stop implant in back (sidewall)
3) n+ / p+ junction = diffusion region to channel-stop implant on side (sidewall)
4) n+ / p+ junction = diffusion region to channel-stop implant in front (sidewall)
5) n+ / p junction = diffusion region to substrate underneath

The capacitance will be proportional to the area of the junction

1) Area = W·xj 2) Area = Y·xj 3) Area = W·xj 4) Area = Y·xj
5) Area = W·Y

To represent the capacitance for an abrupt, PN junction under reverse-bias it is required to

find the depletion region thickness. As a result, the carrier concentration of both materials is

given by:

the depletion thickness is given by:

- where the built in junction potential is given by:

- the depletion-region charge (Qj) can be written as:

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- substituting xdpn and rearranging terms, we get:

the capacitance of the junction is defined as:

- we can differentiate our expression for junction charge with respect to voltage to get the
capacitance as a function of junction voltage:

from this expression, we can define the zero-bias junction capacitance per unit area:

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Since the total capacitance depends on the external bias voltage, it can be a complicated to
find the equivalent capacitance when the bias voltage is a transient. For simplicity, it is
assumed that the voltage change across the junction is linear. Then the equivalent or average
capacitance is given by,

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2.9. Question Bank

1. Write all the mask steps for the inverter n- process.
2. Explain λ based design rules with neat diagram.
3. Draw the circuit and stick diagram for nMOS and CMOS implementation of Boolean
expression Z = ̅̅̅̅̅̅̅̅̅̅̅̅
AB + CD
4. Draw the schematic, stick diagram and layout for a CMOS NAND gate.
5. Explain the steps CMOS fabrication with neat diagram.
6. Explain the fabrication steps of CMOS p-well process with neat diagram and write the
mask sequence.
7. Sketch a stick diagram for a CMOS 4-input NOR gate and estimate the area
8. Consider the design of a CMOS compound OR-AND-INVERT (OAI21) gate
computing

a) sketch a transistor-level schematic

b) sketch a stick diagram
c) estimate the area from the stick diagram
9. Draw the layout of ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵 + 𝐶)𝐷 and estimate the area.
10. With neat diagram, explain lambda-based design rules for wires and contacts.
11. Write a note on i) Full Scaling and ii) Constant Voltage Scaling
12. Write a brief note on i) Narrow-Channel Effects ii) MOSFET Capacitances
13. Find the scaling factors for:
a) Saturation current b) Power dissipation/unit area c)Gate
Capacitance
14. What is scaling. Compute drain current, power, current density and power density for
constant field and constant voltage scaling.
15. Mention different types of MOSFET capacitances and explain with necessary
diagrams and equations.

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