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Assignment DEMC

This document contains an assignment from the Department of Electrical Engineering at Sant Gajanan Maharaj College of Engineering, Mahagaon for the academic year 2022-23. The assignment has 3 parts covering topics related to Boolean algebra, logic gates, digital logic families, adders/subtractors, multiplexers, decoders, encoders, flip-flops, and minimization of logic functions using sum of products and product of sums forms. Students are asked to solve problems, draw circuits, write short notes, and explain various concepts through a total of 27 questions across the 3 parts of the assignment.

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42 views3 pages

Assignment DEMC

This document contains an assignment from the Department of Electrical Engineering at Sant Gajanan Maharaj College of Engineering, Mahagaon for the academic year 2022-23. The assignment has 3 parts covering topics related to Boolean algebra, logic gates, digital logic families, adders/subtractors, multiplexers, decoders, encoders, flip-flops, and minimization of logic functions using sum of products and product of sums forms. Students are asked to solve problems, draw circuits, write short notes, and explain various concepts through a total of 27 questions across the 3 parts of the assignment.

Uploaded by

mallikarjunbpatil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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An ISO 9001-2015 Certified and NAAC B++ Institute

SANT GAJANAN MAHARAJ COLLEGE OF ENGINEERING, MAHAGAON


Department of Electrical Engineering
Academic Year 2022-23

Semester: V Subject: DEMC Sub code: Date: 13/10/2022

Assignment – I

Question Bloom’s
Q. No. COs’ PO’s
Cognitive Levels
a)(10110)2 = (?)8 = (?)10 = (?)16
b)(123.45)8 = (?)2 = (?)10 = (?)16
1. EE 311.1
c)(467.52)10 = (?)2 = (?)8 = (?)16
d) (DEF7)16 = (?)2 = (?)8 = (?)10
2.
Write a note on Rules in Boolean Algebra EE 311.1
3. Explain Associative, Commutative, Distributive Law and
EE 311.1
De-Morgan’s Theorem.
4. Write a note on Logic Gates and Draw the Truth Table. EE 311.1
5. Briefly Explain IC Digital Logic Families. EE 311.1
6. Apply reduction technique using Boolean Algebra by
EE 311.1
taking examples by your own.
7.
Draw a logic circuit for A). (A + B)(C + D)C EE 311.1
Draw a logic circuit for B) AB + AC.

8.
EE 311.1
Draw a truth table for W(X+Y)Z and PT(P+Z).

Prepared by Approved by HOD


Signature: Signature:
Name: Prof. M. B. Patil Name: Prof. V. G. Mathad

Page 1 of 3
Assignment – II

Question Bloom’s
Q. No. COs’ PO’s
Cognitive Levels
Design Circuit for Binary to Gray and Gray to Binary
1. EE 311.2
Conversion
2.
Design Circuit for Binary to Excess-3 and Excess-3 to Binary EE 311.2
3.
Explain Half Adder and Full Adder EE 311.2
4. Explain Half Substractor and Full Substractor EE 311.2
5.
Design Binary Parallel Adder and BCD Adder EE 311.2
6.
Explain 4:1 & 8:1 Multiplexer and 2 bit Comparator. EE 311.2
7.

Write a note on Decoder, Encoder & Ring Counter EE 311.2

8.
Explain SISO, SIPO, PISO, PIPO Shift Registers. EE 311.2
9. Explain with the Truth Table i) SR ii) D iii) T iv) JK v) MS
EE 311.2
Flip Flop

Prepared by Approved by HOD


Signature: Signature:
Name: Prof. M. B. Patil Name: Prof. V. G. Mathad
Assignment – III

Question Bloom’s
Q. No. COs’ PO’s
Cognitive Levels
2. Explain SOP and POS with Examples. EE 311.3
2.
Solve F(P,Q,R,S) = ∑(0,2,5,7,8,10,13,15) EE 311.3
3.
Solve F(A,B,C,D) = π(3,5,7,8,10,11,12,13) EE 311.3
Solve F = A`B`C`+A`BC` + ABC` d = A`B`C +A`BC +
4. EE 311.3
AB`C
5. Solve F = (A`+B+C`) (A`+B+C) ( A’+B’+C`)
EE 311.3
d = (A+B`+C’) (A`+B’+C ) (A+B`+C)
6.
Solve F(A,B,C,D) = π(3,7,8,10,11,13) + dc (0,2,9,15) EE 311.3
7.

Write a Short note on Don’t Care Condition EE 311.3

8.
Solve F(P,Q,R,S) = ∑(0,1,4,8,10,12,13,15) + dc (2,5) EE 311.3
9. Solve
F=(A`+B+C`+D)(A`+B+C+D’)(A’+B’+C`+D’)(A+B+C+D) EE 311.3
d=(A+B`+C’+D)(A`+B’+C+D)(A+B`+C+D)(A’+B+C+D)

Prepared by Approved by HOD


Signature: Signature:
Name: Prof. M. B. Patil Name: Prof. V. G. Mathad

Page 3 of 3

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