Digital Design &

Computer Architecture
Sarah Harris & David Harris

Chapter 3:
Sequential Logic
Design
 Chapter 3 :: Topics
• State Elements
– Bistable Circuit
– SR Latch
– D Latch
– D Flip-Flop
– Variations
• Synchronous Sequential Logic
• Finite State Machines
– Moore
– Mealy
– Factored
• Timing of Sequential Logic
– Clock Skew
– Synchronization
• Parallelism
Digital Design & Computer Architecture Sequential Logic Design 2
Chapter 3: Sequential Logic

State Elements
 Introduction
• Outputs of sequential logic depend on
current and prior input values – it has
memory.
• Some definitions:
– State: all the information about a circuit
necessary to explain its future behavior
– Latches and flip-flops: state elements that store
one bit of state
– Synchronous sequential circuits: Sequential
circuits using flip-flops sharing a common clock

Digital Design & Computer Architecture Sequential Logic Design 4

 Sequential Circuits
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store
information

Digital Design & Computer Architecture Sequential Logic Design 5

 State Elements
• State: everything about the prior inputs to
the circuit necessary to predict its future
behavior
• Usually just 1 bit, the last value captured
• State elements store state
– Bistable circuit
– SR Latch
– D Latch
– D Flip-flop

Digital Design & Computer Architecture Sequential Logic Design 6

Chapter 3: Sequential Logic

Bistable Circuit
 Bistable Circuit
• Fundamental building block of other state
elements
• Two outputs: Q, Q
• No inputs Same circuit!
I1 Q
Q Q
I2 I1

I2 Q

Back-to-back inverters Cross-coupled inverters

Digital Design & Computer Architecture Sequential Logic Design 8
 Bistable Circuit Analysis
• Consider the two possible cases:
0
I1 Q
– Q = 0: 1

then Q = 1, Q = 0 (consistent)
0 1
I2 Q

– Q = 1: I1
1
Q
0
then Q = 0, Q = 1 (consistent)
1 0
I2 Q

• Stores 1 bit of state in the state variable, Q (or Q)

• But there are no inputs to control the state

Digital Design & Computer Architecture Sequential Logic Design 9

Chapter 3: Sequential Logic

SR Latch
 SR (Set/Reset) Latch
• SR Latch R
N1 Q

N2 Q
S

• Consider the four possible cases:

– S = 1, R = 0
– S = 0, R = 1
– S = 0, R = 0
– S = 1, R = 1

Digital Design & Computer Architecture Sequential Logic Design 11

 SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
then Q = 1 and Q = 0 0

Set the output 1

1 N2
0
Q
S

– S = 0, R = 1: 1
R 0
then Q = 0 and Q = 1 1
N1 Q

Reset the output 0

1
0 N2 Q
S

Digital Design & Computer Architecture Sequential Logic Design 12

 SR Latch Analysis
– S = 0, R = 0: Qprev = 0 Qprev = 1

then Q = Qprev R
0
N1
0
Q
R
0
N1
1
Q
1 0
Memory!
0 1
1 0
0 N2 Q N2 Q
S S 0

– S = 1, R = 1: R
1
N1
0
Q
0
then Q = 0, Q = 0
0
Invalid State S
1 N2
0
Q

Q ≠ NOT Q
Digital Design & Computer Architecture Sequential Logic Design 13
 SR Latch
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R inputs
– Set: Make the output 1
S = 1, R = 0, Q = 1 SR Latch
Symbol
– Reset: Make the output 0
S = 0, R = 1, Q = 0 R Q
– Memory: Retain value
S = 0, R = 0, Q = Qprev S Q

• Must do something to avoid invalid state (when

S = R = 1)
Digital Design & Computer Architecture Sequential Logic Design 14
Chapter 3: Sequential Logic

D Latch
 D Latch
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function
D Latch
– When CLK = 1,
Symbol
D passes through to Q (transparent) CLK
– When CLK = 0, D Q
Q holds its previous value (opaque) Q
• Avoids invalid case when
Q ≠ NOT Q
16
Digital Design & Computer Architecture Sequential Logic Design
 D Latch Internal Circuit
CLK R CLK
D R Q Q
D Q
S S Q Q
D Q

CLK D D S R Q Q
0 X X 0 0 Qprev Qprev
1 0 1 0 1 0 1
1 1 0 1 0 1 0

Digital Design & Computer Architecture Sequential Logic Design 17

Chapter 3: Sequential Logic

D Flip-Flop
 D Flip-Flop
• Inputs: CLK, D
D Flip-Flop
• Function: Symbols

– Samples D on rising edge of CLK

D Q
• When CLK rises from 0 to 1, D
Q
passes through to Q
• Otherwise, Q holds its previous
value
– Q changes only on rising edge of CLK
• Called edge-triggered CLK
– Activated on the clock edge Clock edges

Digital Design & Computer Architecture Sequential Logic Design 19

 D Flip-Flop Internal Circuit
• Two back-to-back D latches (L1 and L2) controlled by
complementary clocks CLK
• When CLK = 0
– L1 is transparent
CLK CLK
– L2 is opaque N1
– D passes through to N1 D D Q D Q Q

• When CLK = 1 L1 Q L2 Q Q
– L2 is transparent
– L1 is opaque
– N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises from 0 1)
– D passes through to Q

Digital Design & Computer Architecture Sequential Logic Design 20

 D Latch vs. D Flip-Flop
CLK
D Q D Q
Q Q
D Latch D Flip-flop

CLK

Q (latch)

Q (flop)

Digital Design & Computer Architecture Sequential Logic Design 21

 Chapter 3: Sequential Logic

Variations on a Flop
 Registers: One or More Flip-flops
CLK

Easier to draw!
D3 D Q Q3

CLK
D2 D Q Q2
4 4
D3:0 Q3:0
D1 D Q Q1
4-bit Register

D0 D Q Q0
Two ways to draw a register
4-bit Register 23

Digital Design & Computer Architecture Sequential Logic Design

 Enabled Flip-Flops
• Inputs: CLK, D, EN
– The enable input (EN) controls when new data (D) is stored
• Function
– EN = 1: D passes through to Q on the clock edge
– EN = 0: the flip-flop retains its previous state
Internal
Circuit
Symbol
EN CLK

0
D Q Q D Q
D 1
EN

Digital Design & Computer Architecture Sequential Logic Design 24

 Resettable Flip-Flops
• Inputs: CLK, D, Reset
• Function:
– Reset = 1: Q is forced to 0
– Reset = 0: flip-flop behaves as ordinary D flip-flop

Symbols

D Q
r
Reset

Digital Design & Computer Architecture Sequential Logic Design 25

 Resettable Flip-Flops
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?
Internal
Circuit
CLK

D
D Q Q
Reset

Digital Design & Computer Architecture Sequential Logic Design 26

 Settable Flip-Flops
• Inputs: CLK, D, Set
• Function:
– Set = 1: Q is set to 1
– Set = 0: the flip-flop behaves as ordinary D flip-flop

Symbols

D Q
s
Set

Digital Design & Computer Architecture Sequential Logic Design 27

Chapter 3: Sequential Logic

Synchronous
Sequential Logic
 Sequential Logic
• Sequential circuits: all circuits that aren’t
combinational
• A problematic circuit:
X
X Y Z Y
Z

0 1 2 3 4 5 6 7 8 time (ns)

• No inputs and 1-3 outputs

• Astable circuit, oscillates
• Period depends on inverter delay
• It has a cyclic path: output fed back to input

Digital Design & Computer Architecture Sequential Logic Design 29

 Synchronous Sequential Logic Design
• Breaks cyclic paths by inserting registers
• Registers contain state of the system
• State changes at clock edge: system synchronized to the
clock
• Rules of synchronous sequential circuit composition:
– Every circuit element is either a register or a combinational circuit
– At least one circuit element is a register
– All registers receive the same clock
– Every cyclic path contains at least one register
• Two common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines

Digital Design & Computer Architecture Sequential Logic Design 30

 Synchronous Sequential Logic Design
• Breaks cyclic paths by inserting registers
• Registers contain state of the system
• State changes at clock edge: system synchronized to the
clock
• Rules of synchronous sequential circuit composition:
– Every circuit element is either a register or a combinational circuit
– At least one circuit element is a register
– All registers receive the same clock
– Every cyclic path contains at least one register
• Two common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines

Digital Design & Computer Architecture Sequential Logic Design 31

 Chapter 3: Sequential Logic

FSMs:
Finite State Machines
 Finite State Machine (FSM)
• Consists of:
– State register CLK

• Stores current state S’ S

• Loads next state at clock edge Next
State
Current
State

– Combinational logic
• Computes the next state
• Computes the outputs
Next State Output
Logic Logic

CL Next
State
CL Outputs

Digital Design & Computer Architecture Sequential Logic Design 33

 Finite State Machines (FSMs)
• Next state determined by current state and inputs
• Two types of finite state machines differ in output
logic:
– Moore FSM: outputs depend only on current state
– Mealy FSM: outputs depend on current state and inputs
Moore FSM

CLK
M next k
next
k N
inputs state
state state output
outputs
logic
logic

Mealy FSM

CLK
M next k
next
k state N
inputs state
state output
outputs
logic
logic

Digital Design & Computer Architecture Sequential Logic Design 34

 Finite State Machines (FSMs)
• Next state determined by current state and inputs
• Two types of finite state machines differ in output
logic:
– Moore FSM: outputs depend only on current state
– Mealy FSM: outputs depend on current state and inputs
Moore FSM

CLK
M next k
next
k N
inputs state
state state output
outputs
logic
logic

Mealy FSM

CLK
M next k
next
k state N
inputs state
state output
outputs
logic
logic

Digital Design & Computer Architecture Sequential Logic Design 35

 FSM Design Procedure
1. Identify inputs and outputs
2. Sketch state transition diagram
3. Write state transition table and output table
- Moore FSM: write separate tables
- Mealy FSM: write combined state transition and
output table
4. Select state encodings
5. Rewrite state transition table and output table
with state encodings
6. Write Boolean equations for next state and
output logic
7. Sketch the circuit schematic
Digital Design & Computer Architecture Sequential Logic Design 36
 FSM Design Procedure
1. Identify inputs and outputs
2. Sketch state transition diagram
3. Write state transition table and output table
- Moore FSM: write separate tables
- Mealy FSM: write combined state transition and
output table
4. Select state encodings
5. Rewrite state transition table and output table
with state encodings
6. Write Boolean equations for next state and
output logic
7. Sketch the circuit schematic
Digital Design & Computer Architecture Sequential Logic Design 37
 Chapter 3: Sequential Logic

Moore FSM Example

 FSM Example
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB

Bravado
Dining
Hall
LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields

Digital Design & Computer Architecture Sequential Logic Design 39

 FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
CLK

TA Traffic LA
Light
TB Controller LB

Reset

Digital Design & Computer Architecture Sequential Logic Design 40

 FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
T
• Transitions: Arcs Reset A

S0 T S1 A

LA: green LA: yellow

LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB

Digital Design & Computer Architecture Sequential Logic Design 41

 FSM State Transition Table
Current State Inputs Next State
S TA TB S'
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2
S3 X X S0
TA
Reset
S0 TA S1

S : Current State
LA: green LA: yellow
LB: red LB: red

S’: Next State S3 S2

LA: red LA: red
LB: yellow LB: green
TB
TB

Digital Design & Computer Architecture Sequential Logic Design 42

 FSM Encoded State Transition Table
Current State Inputs Next State
S1 S0 TA TB S'1 S'0
0 S0 0 0 X 0 S1 1
0 S0 0 1 X 0 S0 0
0 S1 1 X X 1 S2 0
1 S2 0 X 0 1 S3 1
1 S2 0 X 1 1 S2 0
1 S3 1 X X 0 S0 0

State Encoding
S'1 = S1S0 + S1S0TB + S1S0TB = S1S0 + S1S0 = S1 ⊕ S0 S0 00
S'0 = S1S0TA + S1S0TB S1 01
S2 10
S3 11
Digital Design & Computer Architecture Sequential Logic Design 43
 FSM Output Table
Current State Outputs
S1 S0 LA1 LA0 LB1 LB0
0 S0 0 0 green 0 1 red 0
0 S1 1 0 yellow 1 1 red 0
1 S2 0 1 red 0 0 green 0
1 S3 1 1 red 0 0 yellow 1

Reset
TA
Output Encoding
LA1 = S1S0 + S1S0 = S1
S0 TA S1
LA: green LA: yellow

green 00
LB: red LB: red

LA0 = S1S0
S3
LA: red
LB: yellow
LB1 = S1S0 + S1S0 = S1
S2
LA: red
LB: green
yellow 01
TB

LB0 = S1S0
TB

red 10
Digital Design & Computer Architecture Sequential Logic Design 44
 FSM Schematic
Next State Current State
CLK LA1
S'1 S1
LA0

TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0

Next State Logic State Register Output Logic

S'1 = S1 ⊕ S0 LA1 = S1
S'0 = S1S0TA + S1S0TB LA0 = S1S0
LB1 = S1
LB0 = S1S0
Digital Design & Computer Architecture Sequential Logic Design 45
 FSM Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB

Digital Design & Computer Architecture Sequential Logic Design 46

 FSM Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)
TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB

Digital Design & Computer Architecture Sequential Logic Design 47

 State Encodings
• Binary encoding:
– i.e., for four states, 00, 01, 10, 11
• One-hot encoding
– One state bit per state
– Only one state bit HIGH at once
– i.e., for 4 states, 0001, 0010, 0100, 1000
– Requires more flip-flops
– Often next state and output logic is simpler

Digital Design & Computer Architecture Sequential Logic Design 48

 1-Hot State Encoding Example
Current State Inputs Next State
S3 S2 S1 S0 TA TB S’3 S’2 S’1 S’0
0 0 S0 0 1 0 X 0 0 S1 1 0
0 0 S0 0 1 1 X 0 0 S0 0 1
0 0 S1 1 0 X X 0 1 S2 0 0
0 1 S2 0 0 X 0 1 0 S3 0 0
0 1 S2 0 0 X 1 0 1 S2 0 0
1 0 S3 0 0 X X 0 0 S0 0 1
TA
Reset

S’3 = S23TS2BS1S0TB NO! S0 TA S1 State 1-Hot Encoding

LA: green LA: yellow
LB: red LB: red
S0 0001
S’2 = S1 + S2TB
S1 0010
S’1 = S0TA S3 S2 S2 0100
S’0 = S0TA + S3
LA: red LA: red
LB: yellow LB: green
TB
TB
S3 1000
Digital Design & Computer Architecture Sequential Logic Design 49
 Chapter 3: Sequential Logic

Mealy FSM Example

 Moore vs. Mealy FSMs
Alyssa P. Hacker has a snail that crawls down a paper tape with
1’s and 0’s on it. The snail smiles whenever the last two digits it
has crawled over are 01. Design Moore and Mealy FSMs of the
snail’s brain.

Digital Design & Computer Architecture Sequential Logic Design 51

 State Transition Diagrams
Moore FSM
Reset
0 1

S0 S1 S2
0 0 1
1 0 0
1

Mealy FSM
Reset
0/0

S0 S1
1/0 0/0

1/1

Digital Design & Computer Architecture Sequential Logic Design 52

 Moore FSM State Transition Table
Current
State Inputs Next State
S1 S0 A S'1 S'0 State Encoding
0 0 0 0 1
0 0 1 0 0 S0 00
0 1 0 0 1 S1 01
0 1 1 1 0
S2 10
1 0 0 0 1
1 Moore
0 FSM 1 0 0
S1’ = S01A
S0A
Reset
0 1
S0’ = A
S0 S1 S2
0 0 1
1 0 0
1

Digital Design & Computer Architecture Sequential Logic Design 53

 Moore FSM Output Table
Current State Output State Encoding
S1 S0 Y
S0 00
0 0 0
0 1 0 S1 01
1 0 1 S2 10
Y = S1 S0
Moore FSM
Reset
0 1

S0 S1 S2
0 0 1
1 0 0
1

Digital Design & Computer Architecture Sequential Logic Design 54

 Mealy State Transition & Output Table

Current Next
State Input State Output
State Encoding
S0 A S'0 Y
0 0 1 0 S0 0
0 1 0 0
S1 1
1 0 1 0
1 1 0 1
Mealy FSM S0’ = A
Reset
0/0
Y = S0 A

S0 S1
1/0 0/0

1/1

Digital Design & Computer Architecture Sequential Logic Design 55

 Moore FSM Schematic
Next State Equations
S1’ = S0A A CLK
S0’ = A S'1 S1
Y
Output Equation
Y = S1
S'0 S0

r
Reset

Digital Design & Computer Architecture Sequential Logic Design 56

 Mealy FSM Schematic
Next State Equation
S0’ = A
A

CLK
Output Equation
S'0 S0 Y
Y = S0A

r
Reset

Digital Design & Computer Architecture Sequential Logic Design 57

 Moore and Mealy Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11

CLK

Reset

A 0 1 0 1 1 0 1 1 1
Moore Machine
S ?? S0 S1 S2 S1 S2 S0 S1 S2 S0

Y
Mealy Machine
S ?? S0 S1 S0 S1 S0 S1 S0

Moore FSM Mealy FSM

Reset Reset
Mealy FSM: asserts Y immediately
0/0
when input pattern 01 is detected
0 1

S0 S1 S2 S0 S1
1
0
0
0
0
1
1/0 0/0 Moore FSM: asserts Y one cycle after
input pattern 01 is detected
1
1/1

Digital Design & Computer Architecture Sequential Logic Design 58

Chapter 3: Sequential Logic

Factored FSMs
 Factoring FSMs
• Break complex FSMs into smaller interacting
FSMs
• Example: Modify traffic light controller to
have Parade Mode.
– Two more inputs: P, R
– When P = 1, enter Parade Mode & Bravado Blvd
light stays green
– When R = 1, leave Parade Mode

Digital Design & Computer Architecture Sequential Logic Design 60

 Parade FSMs
P
Unfactored FSM R Controller LA
TA FSM LB
TB

P
Factored FSM
Mode
R FSM

TA Lights LA

TB FSM LB

Controller
FSM

Digital Design & Computer Architecture Sequential Logic Design 61

 Unfactored FSM

Digital Design & Computer Architecture Sequential Logic Design 62

 Factored FSM
TA
Reset
S0 TA S1
LA: green LA: yellow
LB: red LB: red

P
Reset
S3 S2 P
S0 S1
LA: red LA: red
M: 0 M: 1
LB: yellow LB: green R
MTB
M + TB R
Lights FSM Mode FSM

Digital Design & Computer Architecture Sequential Logic Design 63

Chapter 3: Sequential Logic

Timing
 Timing
• Flip-flop samples D at clock edge
• D must be stable when sampled
• Similar to a photograph, D must be stable
around clock edge

Digital Design & Computer Architecture Sequential Logic Design 65

 Input Timing Constraints
• Setup time: tsetup = time before clock edge data must be
stable (i.e. not changing)
• Hold time: thold = time after clock edge data must be stable
• Aperture time: ta = time around clock edge data must be
stable (ta = tsetup + thold)

CLK

D Q D

tsetup thold

ta

Digital Design & Computer Architecture Sequential Logic Design 66

 Output Timing Constraints
• Propagation delay: tpcq = time after clock edge that Q is
guaranteed to be stable (i.e., to stop changing): maximum
delay
• Contamination delay: tccq = time after clock edge that Q
might be unstable (i.e., start changing): minimum delay

CLK

Q
D Q
tccq
tpcq

Digital Design & Computer Architecture Sequential Logic Design 67

 Dynamic Discipline
• Synchronous sequential circuit inputs must
be stable during aperture (setup and hold)
time around clock edge
• Specifically, inputs must be stable
– at least tsetup before the clock edge
– at least until thold after the clock edge

Digital Design & Computer Architecture Sequential Logic Design 68

 Dynamic Discipline
• The delay between registers has a minimum
and maximum delay, dependent on the
delays of the circuit elements
CLK CLK
Q1 CL D2

R1 R2
Tc
CLK

Q1

D2

Digital Design & Computer Architecture Sequential Logic Design 69

 Setup Time Constraint
• Depends on the maximum delay from register R1
through combinational logic to R2
• The input to register R2 must be stable at least tsetup
before clock edge
Also called:
CLK CLK Cycle Time Constraint
Q1 CL D2

R1 R2
Tc ≥ tpcq + tpd + tsetup
Tc tpd ≤ Tc – (tpcq + tsetup)
CLK

Q1
(tpcq + tsetup):
D2 sequencing overhead
tpcq tpd tsetup

Digital Design & Computer Architecture Sequential Logic Design 70

 Hold Time Constraint
• Depends on the minimum delay from register R1
through the combinational logic to R2
• The input to register R2 must be stable for at least thold
after the clock edge
CLK CLK
Q1 CL D2

R1 R2 thold < tccq + tcd

CLK tcd > thold - tccq
Q1

D2
tccq tcd
thold

Digital Design & Computer Architecture Sequential Logic Design 71

 Timing Analysis
• Calculate both constraints:
– Setup time constraint (aka cycle time
constraint)
– Hold time constraint
• If the hold time constraint isn’t met, the
circuit won’t work reliably at any frequency

Digital Design & Computer Architecture Sequential Logic Design 72

 Timing Analysis Example
CLK CLK Timing Characteristics
A
tccq = 30 ps

Flip-Flops
B
tpcq = 50 ps
tsetup = 60 ps
X' X
C thold = 70 ps
Y' Y
D

Logic delays:
per gate
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps

Setup time constraint: Hold time constraint:

TTcc ≥≥ (50
tpcq ++ 105
tpd ++tsetup
60) ps = 215 ps tccq + tcd > thold ?
fc = 1/Tc = 4.65 GHz (30 + 25) ps > 70 ps ? No!
Won’t run reliably at any frequency
Digital Design & Computer Architecture Sequential Logic Design 73
 Timing Analysis Example
AddHow
buffers to fix?paths
on short
CLK CLK Timing Characteristics
A
tccq = 30 ps

Flip-Flops
B
tpcq = 50 ps
tsetup = 60 ps
X' X
C thold = 70 ps
Y' Y
D

Logic delays:
per gate
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 2 x 25 ps = 50 ps

Setup time constraint: Hold time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = 1/Tc = 4.65 GHz (30 + 50) ps > 70 ps ? Yes!

Digital Design & Computer Architecture Sequential Logic Design 74

Chapter 3: Sequential Logic

Clock Skew
 Clock Skew
• The clock doesn’t arrive at all registers at same time
• Skew: difference between two clock edges
• Perform worst case analysis to guarantee dynamic
discipline is not violated for any register – many
registers in a system!
delay CLK

CLK1 CLK2
Q1 C D2
L

R1 R2

t skew

CLK1

CLK2

CLK

Digital Design & Computer Architecture Sequential Logic Design 76

 Setup Time Constraint with Skew
• In the worst case, CLK2 is earlier than CLK1
CLK1 CLK2
Q1 CL D2
Tc - tskew ≥ tpcq + tpd + tsetup
R1 R2
Tc
CLK1
Tc - tskew Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤ Tc – (tpcq + tsetup + tskew)
Q1

D2

tpcq tpd tsetup tskew

Digital Design & Computer Architecture Sequential Logic Design 77

 Hold Time Constraint with Skew
• In the worst case, CLK2 is later than CLK1
CLK1 CLK2
Q1 CL D2

R1 R2

CLK1

CLK2 tccq + tcd > thold + tskew

Q1
tcd > thold + tskew – tccq
D2
tccq tcd

tskew thold

Digital Design & Computer Architecture Sequential Logic Design 78

Chapter 3: Sequential Logic

Synchronization
 Violating the Dynamic Discipline
Asynchronous (for example, user) tsetup thold

inputs might violate the dynamic CLK

discipline
taperture

CLK
button
D

Case I
D
Q Q

Case II
Q

Case III
???
Q

Digital Design & Computer Architecture Sequential Logic Design 80

 Metastability
• Bistable devices: two stable states, and a
metastable state between them
• Flip-flop: two stable states (1 and 0) and one
metastable state
• If flip-flop lands in metastable state, could stay there
for an undetermined amount of time

metastable

stable stable

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 Flip-Flop Internals
• Flip-flop has feedback: if Q is somewhere between
1 and 0, cross-coupled gates drive output to either
rail (1 or 0) R
N1 Q

N2 Q
S

• Metastable signal: if it hasn’t resolved to 1 or 0

• If flip-flop input changes at random time, probability
that output Q is metastable after waiting some time, t:
P(tres > t) = (T0/Tc ) e-t/τ

tres : time to resolve to 1 or 0

T0, τ : properties of the circuit

Digital Design & Computer Architecture Sequential Logic Design 82

 Metastability
• Intuitively:
T0/Tc: probability input changes at a bad time (during
aperture time)
P(tres > t) = (T0/Tc ) e-t/τ

τ: time constant for how fast flip-flop moves away from

metastability
P(tres > t) = (T0/Tc ) e-t/τ

• If flip-flop samples metastable input, if you wait long

enough (t), the output will have resolved to 1 or 0 with
high probability.

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 Synchronizers
• Asynchronous inputs are inevitable (user interfaces,
systems with different clocks interacting, etc.)
• Synchronizer goal: make the probability of failure (the
output Q still being metastable) low
• Synchronizer cannot make the probability of failure 0

CLK
SYNC

D Q

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 Synchronizer Internals
• Synchronizer: built with two back-to-back flip-flops
• Suppose D is transitioning when sampled by F1
• Internal signal D2 has (Tc - tsetup) time to resolve to 1
or 0 CLK CLK
D2
D Q
F1 F2
Tc

CLK

D2 metastable

tres tsetup tpcq

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 Synchronizer Internals
• Synchronizer: built with two back-to-back flip-flops
• Suppose D is transitioning when sampled by F1
• Internal signal D2 has (Tc - tsetup) time to resolve to 1
or 0 CLK CLK
D2
D Q
F1 F2
Tc

CLK

D2 metastable

tres tsetup tpcq

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 Synchronizer Probability of Failure
For each sample, probability of failure is:
P(failure) = (T0/Tc ) e-(Tc - tsetup)/τ
CLK CLK
D2
D Q
F1 F2
Tc

CLK

D2 metastable

tres tsetup tpcq

Digital Design & Computer Architecture Sequential Logic Design 87

 Synchronizer Mean Time Between Failure
• If asynchronous input changes once per second,
probability of failure per second is P(failure).
• If input changes N times per second, probability of failure
per second is:
P(failure)/second = (NT0/Tc) e-(Tc - tsetup)/τ

• Synchronizer fails, on average, 1/[P(failure)/second]

• Called mean time between failures, MTBF:

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - tsetup)/τ

Digital Design & Computer Architecture Sequential Logic Design 88

 Example Synchronizer
CLK CLK
D2
D Q
F1 F2

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps
N = 10 events per second
• What is the probability of failure? MTBF?
P(failure) = (150 ps/2 ns))/τe-(1.9 ns)/200 ps
P(failure)/second = (NT0/Tc) e-(T -ct setup

= 5.6 × 10-6
MTBF = 1/[P(failure)/second]
P(failure)/second = 10 × (5.6 × 10-6 )
= 5.6 × 10-5 / second
MTBF = 1/[P(failure)/second] ≈ 5 hours

Digital Design & Computer Architecture Sequential Logic Design 89

Chapter 3: Sequential Logic

Parallelism
 Parallelism
• Two types of parallelism:
– Spatial parallelism
• duplicate hardware performs multiple tasks at once
– Temporal parallelism
• task is broken into multiple stages
• also called pipelining
• for example, an assembly line

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 Parallelism
• Token: Group of inputs processed to
produce group of outputs
• Latency: Time for one token to pass from
start to end
• Throughput: Number of tokens produced
per unit time

Parallelism increases throughput

Digital Design & Computer Architecture Sequential Logic Design 92

 Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
– 5 minutes to roll cookies
– 15 minutes to bake
• What is the latency and throughput without parallelism?

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 1 tray/ 1/3 hour = 3 trays/hour

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 Parallelism Example
• What is the latency and throughput if Ben
uses parallelism?
– Spatial parallelism: Ben asks Allysa P. Hacker to
help, using her own oven
– Temporal parallelism:
• two stages: rolling and baking
• He uses two trays
• While first batch is baking, he rolls the
second batch, etc.

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 Spatial Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50

Time
Tray 1 Ben 1 Ben 1
Roll
Parallelism

Tray 2 Alyssa 1 Alyssa 1

Spatial

Bake
Tray 3 Ben 2 Ben 2
Legend
Tray 4 Alyssa 2 Alyssa 2

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 2 trays/ 1/3 hour = 6 trays/hour

Digital Design & Computer Architecture Sequential Logic Design 95

 Temporal Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50

Time
Tray 1 Ben 1 Ben 1
Parallelism
Temporal

Tray 2 Ben 2 Ben 2

Tray 3 Ben 3 Ben 3

Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 1 trays/ 1/4 hour = 4 trays/hour

Using both techniques, the throughput would be 8 trays/hour

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 About these Notes
Digital Design and Computer Architecture Lecture Notes
© 2021 Sarah Harris and David Harris

These notes may be used and modified for educational and/or

non-commercial purposes so long as the source is attributed.

Digital Design & Computer Architecture Sequential Logic Design 97