Unit 5 Notes
Unit 5 Notes
Unit 5 Notes
UNIT V
5.1.1. RC OSCILLATORS
All the oscillators using tuned LC circuits operate well at high frequencies. At
low frequencies, as the inductors and capacitors required for the timing circuit would
be very bulky, RC oscillators are found to be more suitable. Two important RC
oscillators are (i) RC phase shift oscillator and (ii) Wien Bridge oscillator.
If in a wien bridge feedback network if two resistances and capacitors are not equal,
then the frequency of oscillations is given by
The voltage +βVsat acts as Vref at the (+) input terminal. The output is
connected also to the (-) input terminal through an integrating low-pass RC network.
When the voltage Vc across the capacitor C just exceeds Vref, switching takes place
resulting in a square wave output. To understand the operation of the circuit, let us
consider that initially the output is at +Vsat as shown in fig.5.2(b)
The capacitor C with its voltage shown as Vc starts charging through resistor R
towards +Vsat. The voltage at (+) input terminal is held at βVsat as indicated by
the use of R1-R2 potential divider network. The charging of C continues until the
voltage Vc at the (-) input terminal is just greater than the voltage at the (+) input
terminal, + βVsat.When this happens as shown at point b of Fig(b), the output is
switched down to –Vsat. The voltage + βVo across the capacitor now start
discharging through resistance R and charging towards –Vsat. The capacitor voltage
Vc now increases more and more negative, and at point c just exceeds – βVsat. The
output now switches back to +Vsat and the cycle repeats.
Summarizing
Where Vfin is the final value of the voltage and V ini is the initial voltage. Considering
the charging of the capacitor from point a towards +Vsat,
At t=T1, the voltage across the capacitor reaches +βVsat and switches at point b.
Therefore, capacitor voltage Vc at time T1 is
That is
And
Loop Analysis: let us consider that the output Vo’ of comparator A1 is +Vsat initially.
The integrator integrates +Vsat and produces a negative going ramp at its output as
shown in Fig.5.3 (b). Hence, the voltages at the two ends of the voltage divider
formed by R2-R3 are +Vsat at the output of A1 and –Vsat at the output of A2. At the
instant t=T1, when the negative going ramp reaches a value of _Vramp, represented
as point a in Fig.5.3 (b), the effective value at the point P becomes slightly less than
0V. This switches the op-amp A1 to its negative saturation level –Vsat.
With the output of A1 at Vsat, the op-amp A2 starts integrating and increases
its output in the positive direction. At the instant t=T2, shown as point b in Fig.5.3 (b)
the voltage at P becomes just more than 0V. This switches the output of op-amp A1
from –Vsat to +Vsat. This cycle repeats itself, and generates a triangular waveform.
191ROS402T LINEAR INTEGRATED CIRCUITS UNIT V
166
Fig. 5.3 Triangular waveform generator (a) circuit diagram and (b) waveforms at vo’ and vo
To determine the amplitude and frequency of the triangular waveform: When the
comparator output is at +Vsat, the effective voltage at point P is
-----------(1)
Thus the peak to peak amplitude of the triangular wave is
----------(2)
The time taken for the output of A2 to switch from –Vramp to +Vramp is
half of the time period, i.e. T/2. From the basis integrator output equation,
The sawtooth wave generator circuit is shown in Fig 5.4. The op-amp A1
functions as a ramp generator and the op-amp A2 function as a comparator. The
input reference signal Vi of value less than zero is connected to the inverting input of
the op-amp. Since Vi is negative, the output of op-amp A1 can only ramp up.
The rate of raise is given by VoR/t=Vi/RiC. The ramp voltage VoR is monitored
by the comparator A2. The output VoR is connected to the noninverting terminal of op-
amp A2, and a reference voltage. Set by a potentiometer V ref is connected to the
inverting input of comparator. When the capacitor C charges, and when the voltage
VoR is below Vref, the output of comparator is negative. Then the transistors Q 1 and
Q2 do not conduct. The dodes D1 and D2 protect the transistors from excessive
reverse bias voltages.
Fig.5.4 Sawtooth wave generator (a) circuit diagram (b) Sawtooth wave and
comparator outputs and (c) Sawtooth wave design.
When VoR rises and just exceeds Vref, the output Voc of comparator goes to
positive saturation. This action forward biases the transistor Q2 into saturation. The
saturated transistor then acts as a switch across the capacitor C, which charges
quickly making the output Voc come down essentially to 0V. The positive saturation
Voc of A2 also makes the transistor Q1 ON, and the Vref or negative input of op-amp
A2 drops to 0V. As the capacitor C discharges rapidly making VoR zero volts, it drops
below Vref. This causes the comparator output to become negatively saturated. This
action switches the transistor Q2 OFF, and C begins charging linearly, and the cycle
repeats.
.
The frequency is the reciprocal of the time period. Therefore,
The main part of waveform generator is a VCO that generates the triangular
wave and square waves. Sine wave is generated from triangular wave by passing
the later through an on-chip wave shaper. Sawtooth and pulse waveforms are
obtained by the use of highly asymmetric duty cycle for the oscillator. The most
common VCO circuit configurations are grounded capacitor and emitter coupled
types. The grounded capacitor arrangement is used in the waveform generator
ICL8038. The principle of operation of a grounded capacitor type VCO is shown in
Fig.5.5(a) When the switch S is in position 1, the capacitor C charges at a rate fixed
by the current source tH. When voltage vTR across the capacitor reaches the upper
threshold of Schmitt trigger, it changes state and flips the switch S to position 2.
The capacitor C now discharges through the current sink iL. When vTR reaches
the lower threshold level of Schmitt trigger, it triggers flipping the switch S to position
1. This sequence produces the waveforms shown in Fig.5.5 (b). The current source
iH and current sink iL can be made programmable through the control voltage Vi.
(a) (b)
Fig. 5.5 Grounded capacitor type of VCO (a) circuit arrangement (b) waveforms
Fig.5.6 shows the functional block diagram of 555 IC timer. The positive dc
power supply terminal is connected to pin8 (VCC) and negative terminal is
connected to pin 1(Gnd). The ground pin acts as a common ground for all voltage
references while using the IC. The output (Pin3) can assume a HIGH level (0.5V less
than VCC) or a LOW level(approximately 0.1v).
The standby (stable) state makes the output Q’ of flip-flop HIGH. This
makes the output of inverting power amplifier LOW. When a negative going trigger
pulse is applied to Pin 2, as the negative edge of the trigger passes through 1/3
(Vcc), the output of the LC becomes HIGH and its sets the control FF making Q=1
and Q’=0. When the threshold voltage at pin 6 exceeds 2/3(Vcc), the output of UC
goes HIGH. This action resets the control FF with Q=0 and Q’=1.
The reset terminal (pin 4) allows the resetting of the timer by grounding the
pin 4 or reducing its voltage level below 0.4V. This makes the output low overriding
the operation of lower comparator. When not used, the reset terminal is connected to
Vcc. Transistor Q2 isolates the reset input from the FF and transistor Q1. The
reference voltage Vref is made available internally from Vcc. Transistor Q1 acts as a
discharge transistor. When output (pin 3) is high, Q1 is OFF making the discharge
terminal (pin 7) open. When the output is low, Q1 is forward biased to ON condition.
Then, the Discharge terminal appears as a short circuit to ground.
The lower comparator (LC) is biased at (1/3)Vcc and it remains in the standby
state as long as the trigger (pin 2) input is held above (1/3)Vcc. When triggered by a
negative going pulse, the output of the lower comparator goes HIGH setting the FF
with Q=1 and Q’=0. This turns the transistor Q1 OFF, and the output goes HIGH.
Since the timing capacitor is now unclamped, the voltage across it now rises
exponentially through R towards Vcc with time constant RC. After a period of time,
the capacitor voltage will equal (2/3)Vcc and upper comparator resets the internal
FF. This makes Q’=1 and the transistor Q1 is ON. This in turn discharges the
capacitor rapidly to ground potential. As a consequence, the output now returns to
the standby state or ground.
When the capacitor voltage Vc just goes above (2/3)Vcc the upper
comparator triggers and the output remains at zero until another trigger pulse is
applied.
During the second negative edge of the square, the output of monostable
multivibrator remains HIGH. However, during the third negative edge of the square
wave signal, the mono-shot once again triggers ON. In this manner, the output pulse
can be made any integral fraction of the input triggering square-wave signal. The
waveform of the input square wave and output of monoshot are shown in Fig 5.7 (b)
for a frequency divided-by two operation.
Fig.5.7(c) Pulse width modulator using monostable multivibrator (i) circuit diagram (ii)
input and output waveforms
Fig. 5.8 The functional block diagram of Astable Multivibrator using IC 555
5.8.1 Applications of Astable Multivibrator
The important applications of the astable multivibrator are FSK generator,
Pulse position modulator and Schmitt trigger.
FSK generator: A timer IC 555 connected for FSK generation is shown in Fig 5.8
(a). The FSK method transmits data by identifying the logic 0 and 1 by means of two
preset frequencies. The digital data input frequency is normally 150Hz. Here, when
the input is HIGH, QM is OFF. This makes the timer work in normal astable mode
with the present frequency defined by
When the input goes LOW, QM is ON and it connects resistance R C across RA. The
effective resistance RA\\ RC in series with RB now forms the charging path. Therefore,
the output frequency f2 is
when it reaches 0.7V the transistor Q1 turns ON, and supplies the additional current
to the load. From transistor theory, the additional current is ß times the base current.
------------(1)
The output current Io is given by
----------------(2)
Substituting Eq 2 in Eq 1
between the terminals current limit (CL) and current sense (CS) of the IC 723.
Transistors Q7 through Q13 and resistors R10 and R11 form the error amplifier. The
transistors Q11 and Q12 with their non-inverting and inverting input terminals produce
a differential amplifier. The transistor Q13 acts as the current source for the
differential amplifier.
The current limit transistor Q3 starts conducting only when its base to emitter
voltage VBE is approximately 0.7V, that is, VCL must become sufficiently large to
exceed the drop across R3 by a minimum of 0.7V. That is
At this point, current limit starts occurring. As the load resistance decreases,
the load voltage drops, and VR3 also reduces. As a consequence, a smaller value of
VCL is then required to maintain VBE of Q3 at 0.7V. Then, as transistor Q3 starts
conducting, transistor Q1 starts to turn OFF, and the load current decreases. The
drop across R3 further reduces, increasing the conduction of Q3 and reducing
conduction of Q1. The load current IL further reduces. This process continues until
Vo becomes 0V and load current becomes a minimum. If the load resistance is
brought to its nominal operating value, the circuit resumes its normal regulation
action.
The internal block diagram and Pin configuration Of IC µA 78S40 are shown
in Fig 5.17. It is a pulse width modulated type of switching regulator. Switching diode
D1 and an op-amp. The reference voltage is available at pin 8. The oscillator is
controllable for its duty cycle with the use of an active current limit circuit. The
internal switching frequency of oscillator is set by the timing capacitor CT, connected
between Pin 12 and ground pin 11.
The initial duty cycle can be modified by the current limit circuiting which is
activated at pin 14(Ipk) and comparator outputs controlled by pins 9 and 10. The
typical frequency range of oscillator is between 100 Hz and 100KHz.
The output transistor can operate at 40V and supply current up to 1.5A. The
transistor Q2 operated by the output of SR flip-flop drives the base of Q1. The
transistors Q1 and Q2 can be connected as a Darlington pair. Increased base drive
to Q1 can be applied by connecting to the flip flop through an AND gate. The
comparator is a high gain amplifier and the unconnected op-amp can be used for
voltage polarity changes, when required.
When the output is at the desired voltage level, the comparator output is high
and no effect on the circuit operation is observed. Assume that the output voltage is
more than the required value. Then, the voltage at the inverting input comparator is
higher than the required value. Then, the voltage at the inverting at the inverting
input of the comparator is higher than Vref, and the comparator switches to negative
saturation, and this is applied to one input of the AND gate through the latch. This
makes output of AND gate low and Q1 is turned OFF. When the capacitor CT times
out, the oscillator turns Q1 ON again until IPK is reached or output voltage is once
again more than the desired value.
When the output voltage drops lower than the required value, the average
discharge current of inductor L1 increases. This increases the time t ON, since it
needs more time to charge the inductor to IPK. Increase in tON raises the voltage Vo to
the desired value. When Vo increases, the inductor discharges less during tOFF, and
IPK is reached faster when Q1 is ON. This causes tOFF to reduce.
Active RC filters using ICs have advantages of not using inductors and of
offering easy implementation high performance low pass, high-pass, band-pass and
band-elimination filters. The resistor values needed for these filters are generally
much too large for fabrication on a monolithic IC chip. Integrated resistors have poor
temperature and linearity characteristics. Large value resistors (≥10K Ω) take up an
excessive amount of chip area. This is the major reason that active filters have not
previously been fully integrated in MOS technology.
For the range of frequencies within which the op-amp operates satisfactorily, it
is not possible in MOS technology to implement RC products of sufficient magnitude
and accuracy. On the other hand, in the case of switched capacitor filter, the Rc
products are set by capacitor ratios and the switch period. In MOS technology the
accuracy and the values of these quantities are suitable for the implementation of
selective filters. The large resistor values required for active filter are easily
simulated by the combination of small value capacitors and MOS switching
transistors. The equivalent resistor value obtained is high enough such that the filter
capacitance value should be small enough to be easily incorporated on a monolithic
IC chip.
It is the basic type of filter. This is called as universal filter because it can be
used to synthesize any type of filters such as Band pass, Low-pass, High-pass,
notch and all-pass. The block diagram of MF5 was shown here. It consists of an
operational amplifier, two positive integrators and summing node. A MOS switch is
controlled by the logic input given at pin 5.
This switch is useful in connecting one of the inputs of first integrator to either
ground or to the output of the second integrator. The way in which the external
resistors are connected determines the characteristics of the filter. The maximum
recommended clock frequency is 1 MHZ. There were three modes of operation and
out of all modes, mode 3 is best. All the modes have three outputs with the
combinations of different filter functions. And MF5 Can Operate with single or split
power supply. The clock frequency to center frequency ration is selected with a help
of pin 9. There were two ratio options 50:1 and 100:1.
The device can also be used as highly accurate frequency to voltage (F/V)
converter, accepting virtually any input frequency waveform and providing a linearly
proportional voltage output. A complete V/F and F/V system only requires the
addition of two capacitors, three resistors, and reference voltage.
Pin configuration:
Freq/2 Out
This output is an open drain N channel FET which provides a square wave
one half the frequency of the pulse frequency output. The Freq/2 output will change
state on the rising edge of pulse Freq Out. This output requires a pull up resistors
and interfaces directly with MOS,CMOS and TTL logic.
Output Common
The sources of both the Freq/2 and the Pulse Freq Out are connected to this
pin. An output level swing from the drain voltage to ground or to the Vss supply may
obtained by connecting this pin to the appropriate point.
RBIAS
An external resistor, connected to Vss, sets the bias point for the TC9400.
Increasing the maximum frequency of the TC9400 beyond 100KHz is limited by the
pulse width of the Pulse Output. Reducing RBIAS will decrease the pulse width and
increase the maximum operating frequency, but linearity errors will also increase.
RBIAS can be reduced to 20 KΩ, which will typically produce maximum full scale
frequency of 500KHz.
Amplifier Out
This is the output pin of the operational amplifier. During V/F operation , a
negative going ramp signal is available at this pin. In the F/V mode a voltage
proportional to the frequency input is generated.
Zero Adjust
This pin is the noninverting input of the operational amplifier. The low
frequency set point is determined by adjusting the voltage at this pin.
IIN
This is the inverting input of the operational amplifier and the summing
junction when connected in the V/F mode. An input current of 10µA is specified, but
an overrange current up to 50 µA can be used without detrimental effect to the circuit
operation. IIN connects the summing junction of an op amp. Voltage sources cannot
be attached directly, but must be buffered by external resistors.
VREF
A reference voltage from either a precision source or the V SS supply is applied
to this pin. Accuracy of the TC9400 is dependent on the voltage regulation and
temperature characteristic of the reference circuitry.
The lower limit of the output swing is set by the threshold detector, which
causes the reference voltage to be applied to the reference capacitor for a time
period long enough to charge the capacitor to the reference voltage. This action
reduces the charge on the integrating capacitor by a fixed amount (q = CREF ×
VREF), causing the op amp output to step up a finite amount.
At the end of the charging period, CREF is shorted out. This dissipates the
charge stored on the reference capacitor, so that when the output again crosses
zero the system is ready to recycle. In this manner, the continued discharging of the
integrating capacitor by the input is balanced out by fixed charges from the reference
voltage.
191ROS402T LINEAR INTEGRATED CIRCUITS UNIT V
190
The op-amp output will continue to decrease until it crosses the –3.0V
threshold of the "self-start" comparator. When this happens, an internal resistor is
connected to the op-amp input, which forces the output to go positive until the
TC9400 is in its normal operating mode. The TC9400 utilizes low power CMOS
processing for low input bias and offset currents with very low power dissipation. The
open-drain N-channel output FETs provide high voltage and high current sink
capability.
fout = Kv Vi
In other words, it converts analog signals to digital form. The primary reason for this
type of conversion is that a pulse train can be transmitted and decoded much more
accurately than analog signal, especially if the transmission path is long and noisy.
As shown in the block diagram conversion takes place in two steps: Initially,
input voltage is converted to the current drive, and then current controlled oscillator
(CCO) produces pulses whose frequency is linearly proportional to the input current.
The input voltage is converted to the current drive with the help of op-amp and BJT
combination. The op-amp provides base current to ensure Vn = Vp. Thus I = Vi/R.
The CCO parameter is such that
Let us assume C=1nF, R=10K and Vcc = 15V. Now variation of Vi from 1mV to 10V
gives current and hence frequency variations as follows.
The Ros (20K pot) is connected to minimize the V-I conversion error at the low
end . It does this by making input offset error of op-amp zero.VT is a voltage linearly
proportional to absolute temperature T. It is given by
always less than 1 mA. To understand circuit operation, let us consider switch SW is
open.With SW open, current I flows into capacitor C1 and causes the output of op-
amp A1(V01) to ramp downward, as shown in Fig5.22 (b)
Substituting TH + TL we get,
From the above Eq we can notice that duty cycle is also proportional to the input
signal V.
An op-amp audio amplifier is shown in Fig 5.23. The –V input to the op-amp is
connected to ground. This means that the op-amp output always has some positive
191ROS402T LINEAR INTEGRATED CIRCUITS UNIT V
195
value. Note that the coupling capacitor between the output of the op-amp and
speaker is used to reference the speaker voltage around 0V. That is, it removes the
positive dc reference from the op-amp output. Also C5 is included in the Vcc line to
prevent any transient current caused by the operation of the op-amp from being
coupled back to Q1 through the power supply.
By avoiding the tuned input and output circuits, the MC 1550 can be used as
a video amplifier. As it uses a cascade amplifier pair, the video amplifier is called as
Cascode Video amplifier.
The properly terminate the co-axial cable carrying the video signal, a 50Ω resistance
is connected between the pins 1 and 4 of MC 1550. Such a small resistance has
very negligible effect on the biasing of the transistor Q1. The load resistance RL is
directly inserted in the collector of the transistor Q3.The transistor Q3 acts as a
common base stage and the video output is taken from the collector of Q3.
LED photodiode shown in figure, here the infrared LED acts as a light source
& photodiode is used as a detector.
The advantage of using the photodiode is its high linearity. When the pulse at
the input goes high, the LED turns ON. It emits light. This light is focused on the
photodiode.
In response to this light the photocurrent will start flowing though the photodiode.
As soon as the input pulse reduces to zero, the LED turns OFF & the photocurrent
through the photodiode reduces to zero. Thus the pulse at the input is coupled to the
output side.
When the pulse at the input goes high, the LED turns ON. The light emitted by
the LED is focused on the CB junction of the phototransistor. In response to this light
photocurrent starts flowing which acts as a base current for the phototransistor.
Advantages of Optocoupler:
Control circuits are well protected due to electrical isolation.
Wideband signal transmission is possible.
Due to unidirectional signal transfer, noise from the output side does not get
coupled to the input side.
Interfacing with logic circuits is easily possible.
It is small size & light weight device.
Disadvantages:
Slow speed.
Possibility of signal coupling for high power signals.
Applications:
Optocouplers are used basically to isolate low power circuits from high power
circuits.
At the same time the control signals are coupled from the control circuits to
the high power circuits.
Some of such applications are,
Note that the input & output waveforms are 180º out of phase as the output is taken
at the collector of the phototransistor.
(iii)Response Time:
Response time indicates how fast an optocoupler can change its output state.
Response time largely depends on the detector transistor, input current & load
resistance.
(v) VCE(max) : This is the maximum permissible dc voltage that can be allowed to flow
in the output transistor or output photodiode.
(vi) IL (max) : This is the maximum permissible dc current that CAN BE ALLOWED TO
FLOW IN THE INPUT led. Typical values vary from 40 mA to 100mA.
(vii) Bandwidth: This is the maximum signal frequency that can be usefully passed
through the optocoupler when the device is operated in its normal mode. Typical
values vary from 20KHz to 500 KHz.
5.17. IC OPTOCOUPLER
Fig 5.26 shows an isolation amplifier in which a LED photo transistor couplers
are used as an opt isolators. As shown in Fig first LED phototransistor coupler is
used in the feedback loop of amplifier A1 and the second LED phototransistor
coupler is used at the input of amplifier A2. Both LED phototransistor couplers are
used with matched characteristic, are driven by the same amplifier, amplifier A1. Due
to the matched characteristic of the two LED photo transistor pairs the non linear
characteristic and temperature dependence get compensated.
Thus optical transmitter, optical fiber and optical receiver are the three
important components of a fiber optic system. But in practice when light propagates
along the fiber, it experiences an attenuation and delay distortion. The variable fiber
length and other conditions, distort the signal. Hence a quantizing circuit is generally
used after an optical receiver. The quantizer squares the signal and conforms to the
standard interface levels.
The two important advantages of fiber optic system over copper wire conventional
systems are,
1. The low level of attenuation on high frequency signals. This is hat is required for
long distance telephone lines and computer networks.
2. a lack of RFI radiation and a low sensitivity to EMI noise which increases the
accuracy and the security of the data transmission.
1.What is an Oscillator?
191ROS402T LINEAR INTEGRATED CIRCUITS UNIT V
204
2. What are the conditions to be satisfied for sustained oscillations? (or) State
Barkhausen’s Criterion.(May 15)
The Magnitude condition |Aβ|=1
The Phase shift around the closed loop is 0° or 360°
5. What is a multivibrator?
Multivibrators are a group of regenerative circuits that are used extensively in timing
applications. It is a wave shaping circuit which gives symmetric or asymmetric
square output. It has two states either stable or quasi- stable depending on the type
of multivibrator.
Bistable multivibrator is one that maintains a given output voltage level unless an
external trigger is applied . Application of an external trigger signal causes a change
of state, and this output level is maintained indefinitely until an second trigger is
applied . Thus, it requires two external triggers before it returns to its initial state .
10. What are the modes of operation of a 555 Timer? (OR) list two types of
multivibrator (may 2014)
555mer has two basic operating modes, namely
1.Astable mode 2.Monostable mode.
14. Give the formula for period of oscillations in an opamp astable circuit.(MAY
2013) F=1/T= 1.44/((RA+RB*2)*C)
28. What are the limitations of three terminal regulators? (May/June 2012)
1. Required input step down transformer is bulky and expensive
It is an important feature due to which the IC automatically gets turned off if internal
temperature becomes very high. The output current will drop and remain there until
the IC has cooled significantly.
36. What is frequency to voltage converter?
A converter which generates an output voltage (VO) that is linearly proportional to the
frequency of the input waveform (fI) is called frequency to voltage converter.
is a very large common mode voltage difference between the input and output sides
of the device.
42. List the advantage of fiber optic system over copper wire conventional
system.
The advantages of fiber optic system over copper wire system are,
A low level of attenuation on high frequency signals. This is what is required
for long distance telephone lines and the computer networks.
A lack of RFI radiation and a low sensitivity to EMI noise, which increases the
accuracy and the security of the data transmissions.
43. What is Signal to Noise Ratio (S/N).
In analog and digital communications, signal-to-noise ratio, often written S/N or SNR,
is a measure of signal strength relative to background noise. The ratio is usually
measured in decibels (dB). If the incoming signal strength in microvolts is V s, and the
noise level, also in microvolts, is Vn, then the signal-to-noise ratio, S/N, in decibels is
given by the formula
S/N = 20 log10 (Vs/Vn)
44. Draw the internal circuit for audio power amplifier. (Apr-2010)
1. (i) How is voltage regulators classified? Explain a series voltage regulator. (8)
(ii) What is an opto coupler? Briefly explain its characteristics. (8)( May -
2010)
2. With a neat circuit diagram and internal functional diagram explain the
working of 555 timers in astable mode. (16) ( May - 2010)
3. (i) How can the current drive capability be increased while using three
terminal voltage regulators?
(ii) Design an adjustable voltage regulator circuit using LM317 for the
following specifications : Input dc voltage = l3.5 V Output DC voltage = 5 to 9 V
Load current (maximum) =1 A [16]( Dec-2010)
4. Describe the working of IC723 voltage regulator and explain the importance of
current limiting techniques. [16] ( Dec-2010)
5. (i) Draw the circuit using op-amp to generate triangular wave. Explain its
operation.(8)
(ii) With a neat diagram, explain the working of step-down switching
regulator.(8)(May - 2011)
6. (i) With suitable diagram, explain the working of a switched capacitor filter.
Also explain how resistor can be realized using switched capacitor filter.(8)
(ii)with necessary diagrams explain the operation of frequency to voltage
converters.(8) (May - 2011)
(i)with a neat functional block diagram, explain the working of IC555 in astable
mode(8) (Dec - 2011)
(ii) Describe in detail the working principle of IC 8038 function generator.(8)
7. (i) With a neat functional diagram explain the operation of LM 380 power
amplifier.(8)
(ii) Explain the operation of switched capacitor filter. What are the advantages
and disadvantages of this type of filter? (Dec - 2011)
8. Sketch the functional block diagram of the following and explain their working
principle:( May - 2012)
(i)IC 555 Timer. (8) (ii) General purpose voltage regulator IC 723. (8)
9. (i) With neat diagram, explain the working principle of isolation amplifier. (8)
(ii) With neat diagram, explain the principle of operation of optocouplers. (8)
(May - 2012)
10. Draw the functional block diagram, explain the working of IC555 in astable
mode and derive expression for frequency.( Dec - 2012)
11. (i) Draw and explain the function block diagram of a 723 IC regulator and
make the necessary changes to make it as low voltage regulator. ( Dec -
2012)(May15)
(ii) Write short notes on( Dec - 2012)
(i) opto couplers (ii) switching regulators
12. State the advantages of IC voltage regulators. Explain the features and
internal structure of general purpose linear IC723 regulator. Design a regulator
using IC 723 to meet the following specifications: v0=5v: I0=100Ma,vin= 15+- 20%
Isc=150mA vsense=0.7v(May – 2013)
14. (i)Explain the working of monostable multivibrator with necessary diagram and
drive for ON time and recovery time.(10)(May 15)
(ii)what are opto couplers?( Dec - 2013)
16. With neat diagram explain IC723 General Purpose regulator. (16)( May -
2014)