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Ordering number : ENN7110

Monolithic Digital IC

LB11827
Three-Phase Brushless Motor Driver for OA Products

Overview Package Dimensions

The LB11827 is a three-phase brushless motor driver that unit: mm
is optimal for driving drum and paper feed motors in laser 3147B-DIP28H
printers and plain paper copiers. This IC adopts a direct
PWM drive technique for minimal power loss. Flexible [LB11827]
control of motor speed in response to an externally 28 15
provided clock frequency (corresponding to the FG
frequency) can be implemented by using the LB11827 in

11.2
12.7
8.4
conjunction with the Sanyo LB11825M. R1.7

0.4
Functions and Features 1 20.0 14
• Three-phase bipolar drive (30 V, 3.5 A) 27.0

• Direct PWM drive

4.0
• Built-in low side inductive kickback absorbing diode

4.0
• Speed discriminator + PLL speed control
• Speed locked state detection output 1.93 1.78 0.6 1.0

• Built-in forward/reverse switching circuit

• Full complement of built-in protection circuits, SANYO: DIP28H (500 mil)

including current limiter circuit, thermal protection

circuit, and motor constraint protection circuit.

Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Supply voltage VCC max 30 V
Output current IOm ax T ≤ 500 ms 3.5 A
Allowable power dissipation 1 Pd max1 Independent IC 3 W
Allowable power dissipation 2 Pd max2 When infinitely large heat sink 20 W
Operating temperature Topr –20 to +80 °C
Storage temperature Tstg –55 to +150 °C

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
 LB11827

Absolute Maximum Ratings at Ta = 25°C

Parameter Symbol Conditions Ratings Unit
Supply voltage range 1 VCC 9.5 to 28 V
Regulator voltage output current IREG 0 to – 30 mA
LD output current ILD 0 to 15 mA

Electrical Characteristics at Ta = 25°C, VCC = VM = 24 V

Ratings
Parameter Symbol Conditions Unit
min typ max
Supply current 1 ICC1 23 30 mA
Supply current 2 ICC2 When stopped 3.5 5 mA
[Output Block]
Output saturation voltage 1 VOsat1 IO = 1.0 A, VO (SINK)+ VO (SOURCE) 2.0 2.5 V
Output saturation voltage 2 VOsat2 IO = 2.0 A, VO (SINK)+ VO (SOURCE) 2.6 3.2 V
Output leakage current VOleak 100 µA
Lower side diode forward voltage 1 VD1 ID = –1.0 A 1.2 1.5 V
Lower side diode forward voltage 2 VD2 ID = –2.0 A 1.5 2.0 V
[5 V Regulator Voltage Output]
Output voltage VREG IO = –5 mA 4.65 5.00 5.35 V
Voltage regulation ∆VREG1 VCC = 9.5 to 28 V 30 100 mV
Load regulation ∆VREG2 IO = –5 to –20 mA 20 100 mV
[Hall Amplifier]
Input bias current IHB –2 –0.5 µA
Common-mode input voltage range VICM 1.5 VREG–1.5 V
Hall input sensitivity 80 mVP-P
Hysteresis ∆VIN 15 24 42 mV
Input voltage low→ high VSLH 12 mV
Input voltage high→ low VSHL –12 mV
[PWM Oscillator Circuit]
Output H level voltage VOH(PWM) 2.5 2.8 3.1 V
Output L level voltage VOL(PWM) 1.2 1.5 1.8 V
Oscillator frequency f(PWM) C = 3900 pF 18 kHz
Amplitude V(PWM) 1.05 1.30 1.55 VP-P
[CSD Circuit]
Operating voltage VOH(CSD) 3.6 3.9 4.2 V
External C charging current ICHG –17 –12 –9 µA
Operating time T(CSD) C = 10 µF Design target value* 3.3 s
[Current Limiter Operation]
Limiter VRF VCC–VM 0.45 0.5 0.55 V
[Thermal Shutdown Operation]
Thermal shutdown operating temperature TSD Design target value* (junction temperature) 150 180 °C
Hysteresis ∆TSD Design target value* (junction temperature) 50 °C
[FG Amplifier]
Input offset voltage VIO(FG) –10 10 mV
Input bias current IB(FG) –1 1 µA
Output H level voltage VOH(FG) IFGO = –0.2 mA VREG–1.2 VREG–0.8 V
Output L level voltage VOL(FG) IFGO = 0.2 mA 0.8 1.2 V
FG input sensitivity Gain: 100 3 mV
Schmitt amplitude for the next stage Design target value* 100 180 250 mV
Operating frequency range 2 kHz
Open-loop gain f(FG) = 2 kHz 45 51 dB
Note: * These are design target values and are not tested.

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 LB11827

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Ratings
Parameter Symbol Conditions Unit
min typ max
[Speed Discriminator]
Output H level voltage VOH(D) IDO = –0.1 mA VREG–1.0 VREG–0.7 V
Output L level voltage VOL(D) IDO = 0.1 mA 0.8 1.1 V
Number of counts 512
[PLL Output]
Output H level voltage VOH(P) IPO = –0.1 mA VREG–1.8 VREG–1.5 VREG–1.2 V
Output L level voltage VOL(P) IPO = 0.1 mA 1.2 1.5 1.8 V
[Lock Detection]
Output L level voltage VOL(LD) ILD = 10 mA 0.15 0.5 V
Lock range 6.25 %
[Integrator]
Input bias current IB(INT) –0.4 0.4 µA
Output H level voltage VOH(INT) IINTO = –0.2 mA VREG–1.2 VREG–0.8 V
Output L level voltage VOL(INT) IINTO = 0.2 mA 0.8 1.2 V
Open-loop gain f(INT) = 1 kHz 45 51 dB
Gain width product Design target value* 450 kHz
Reference voltage Design target value* –5% VREG/2 5% V
[Clock Input Pin]
Operating frequency range fOSC 1 MHz
L level pin voltage VOSCL IOSC = –0.5 mA 1.55 V
H level pin current IOSCH VOSC = VOSCL+0.5 V 0.4 mA
[Start/Stop Pin]
H level input voltage range VIH(S/S) 3.5 VREG V
L level input voltage range VIL(S/S) 0 1.5 V
Input open voltage VIO(S/S) VREG–0.5 VREG V
Hysteresis ∆VIN 0.35 0.50 0.65 V
H level input current IIH(S/S) V(S/S) = VREG –10 0 10 µA
L level input current IIL(S/S) V(S/S) = 0 V –280 –210 µA
[Forward/Reverse Pin]
H level input voltage range VIH(F/R) 3.5 VREG V
L level input voltage range VIL(F/R) 0 1.5 V
Input open voltage VIO(F/R) VREG–0.5 VREG V
Hysteresis ∆VIN 0.35 0.50 0.65 V
H level input current IIH(F/R) V(F/R) = VREG –10 0 10 µA
L level input current IIL(F/R) V(F/R) = 0 V –280 –210 µA
Note: * These are design target values and are not tested.
 LB11827

Infinitely large heat sink

Allowable power dissipation, Pdmax—W

With no heat sink

Ambient temperature, Ta —°C

Truth Table
Source F/R = "L" F/R = "H"
Sink IN1 IN2 IN3 IN1 IN2 IN3
1 OUT2 → OUT1 H L H L H L
2 OUT3 → OUT1 H L L L H H
3 OUT3 → OUT2 H H L L L H
4 OUT1 → OUT2 L H L H L H
5 OUT1 → OUT3 L H H H L L
6 OUT2 → OUT3 L L H H H L

The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation.

fFG(servo) = fCLK/<number of counts>

= fCLK/512

Pin Assignment

OUT1 F/R IN3+ IN3- IN2+ IN2- IN1+ IN1- GND1 S/S FGIN+ FGIN- FGOUT LD
28 27 26 25 24 23 22 21 20 19 18 17 16 15

LB11827

1 2 3 4 5 6 7 8 9 10 11 12 13 14
OUT2 OUT3 GND2 VCC VM VREG PWM CSD XI XO INTOUT INTIN POUT DOUT

Top view
 LB11827

Equivalent Circuit Block Diagram and Peripheral Circuits

 LB11827

Pin Description
Pin No. Pin Function Equivalent circuit

28 OUT1 VCC
Motor drive output pin
1 OUT2 300 Ω VM
Connect the Schottky diode between the output – VCC. 5
2 OUT3

3 GND2 Output GND pin

1 2 28

Power and output current detection pins of the output. Connect a

low resistance (Rf) between this pin and VCC.
5 VM
The output current is limited to the current value set with IOUT =
VRF/Rf. 3

4 VCC Power pin (Other than the output)

VCC

Stabilized power supply output pin (5 V output) 6

6 VREG Connect a capacitor (about 0.1 µF) between this pin and GND for
stabilization

VREG

Pin to set the PWM oscillation frequency.

7 PWM Connect a capacitor between this pin and GND.
200 Ω
This can be set to about 18 kHz with C =3900 pF. 7
2 kΩ

VREG

Pin to set the operation time of motor lock protection circuit.

8 CSD Connection of a capacitor (about 10 µF) between CSD and GND 300 Ω
can set the protection operation time of about 3.3seconds. 8
1 kΩ

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 LB11827

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Pin No. Pin Function Equivalent circuit

VREG

Clock input pin, which enters the clock signal (1 MHz or less) to
9 XI
the XI pin via resistor (about 5.1 kΩ).
10 XO
Keep the XO pin open. 10

VREG

INT
11 Integrating amplifier output (speed control pin). 11
OUT

40 kΩ
PWM Comparator

VREG

INT
12 Integrating amplifier input pin
IN
300 Ω
12

VREG

300 Ω
13
13 POUT PLL output pin

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 LB11827

Continued from preceding page.

Pin No. Pin Function Equivalent circuit

VREG

Speed discriminator output. 300 Ω

14 DOUT 14
Accelerate: high, decelerate: low

VREG

Speed lock detection output. 15

15 LD L when the motor speed is within the speed lock range (±6.25%).
Voltage resistance 30 Vmax

VREG

FG
16 FG amplifier output pin 16
OUT

40 kΩ

FG schmitt comparator

VREG
20 kΩ

17 FGIN–

FG Reset
FG amplifier input pin.
Connection of a capacitor (about 0.1 µF) between FGIN and 300 Ω 300 Ω
GND causes initial reset to the logic circuit. 18 17
20 kΩ

18 FGIN+

VREG

Start/stop control pin.

Low: 0 V to 1.5 V
22 kΩ

19 S/S High: 3.5 V to VREG

H level when open. 2 kΩ
19
Hysteresis width about 0.5 V

Continued on next page.

 LB11827

Continued from preceding page.

Pin No. Pin Function Equivalent circuit

20 GND1 GND pin (Other than the output)

VREG

22 IN1+ Hall amplifier input.

21 IN1– IN+ > IN– is the input high state, and the reverse is the input low
state. 300 Ω 300 Ω
24 IN2+ 21 23 25 22 24 26
It is recommended that the Hall signal has an amplitude of 100m
23 IN2–
Vp-p (differential) or more.
26 IN3+
Connect a capacitor between the IN+ and IN– inputs if there is
25 IN3– noise in the Hall sensor signals.

VREG

Forward/reverse control pin

Low: 0 V to 1.5 V

22 kΩ
27 F/R High: 3.5 V to VREG
H level when open
2 kΩ
Hysteresis width about 0.5 V 27

Function Description
1. Speed control circuit
This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit
outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase
error signal once for each cycle of FG.
As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock
frequency.
fFG(servo) = fCLK/512
fCLK: Clock frequency
This IC achieves variable speed control with ease when combined with LB11825M.

2. Output drive circuit

This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated
at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the
output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between
OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a
short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output
current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or
schottky diode externally.

3. Current limiting circuit

The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp, Rf:
current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
 LB11827

4. Power save circuit

This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias
current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given.

5. Reference clock
This is entered from the external signal source (1 MHz max) via a resistor (reference: about 5.1 kΩ) in series with the
XI pin. The XO pin is left open.
Input signal source levels:
Low-level voltage: 0 to 0.8 V
High-level voltage: 2.5 to 5.0 V

6. Speed lock range

The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes
to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive
output changes according to the speed error, causing control to keep the motor speed within the lock range.

7. PWM frequency
PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin.
fPWM ≈ 1/(14,400 × C)
It is recommended to keep the PWM frequency at 15 – 25 kHz. GND of a capacitor to be connected must be connected
to the GND1 pin with the shortest possible wiring.

8. Hall input signal

The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42 mV max). Considering
the effect of noise, the input with the amplitude of 100 mV or more is recommended.
When the output waveform is disturbed due to noise effects at a time of changeover of the output phase, connect a
capacitor between Hall input pins (+ and -) at a point as near as possible to the pin.

9. F/R changeover
Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay
attention to following points.
• For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is
necessary to prevent exceeding of the rated voltage (30 V) due to rise of VCC voltage at a time of changeover
(because the motor current returns instantaneously to the power supply). When this problem exists, increase the
capacity of a capacitor between VCC and GND.
• When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the
upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive
voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (3.5 A).
(F/R changeover speed is dangerous.)

10. Motor lock protection circuit

A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked.
When the LD output is “H” (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This
time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with
the capacity of 10 µF (variance about ±30%).

Set time (s) ≈ 0.33 × C (µF)

When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time,
etc.
Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock
protection circuit is not to be used, connect the CSD pin to GND.
When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be
discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is
 LB11827

necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to
restart in the motor start transient condition.)
Stop time (ms) ≥ 15 × C (µF)

11. Power supply stabilization

This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is
therefore necessary to connect a capacitor with a sufficient capacity (several ten µF or more) between the VCC pin and
GND for stabilization. GND of a capacitor to be connected must be connected to the GND2 pin (GND of the power
block) at a point as near as possible to the pin. If a capacitor (electrolytic) cannot be provided near the pin because of
existence of a heat sink, etc., provide a ceramic capacitor of about 0.1 µF near the pin.
When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power
line is particularly readily oscillated. The larger capacity need be selected.

12. VREG stabilization

The VREG pin (5 V regulator output) that is a power supply for control circuit must be provided with a stabilizing
capacitor (about 0.1 µF). GND of a capacitor to be connected must be connected to the GND1 pin with the shortest
possible wiring.

13. Constant of integrating amplifier parts

Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange
them by keeping the largest possible distance from the motor.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of December, 2003. Specifications and information herein are
subject to change without notice.