2015-16 + 2016-17 - 2817-18QUANTUM SERIES SRI ae NNN For B.Tech Students of Third Year of All Engineering Colleges Affiliated to Dr. A.P.J. Abdul Kalam Technical University, Uttar Pradesh, Lucknow (Formerly Uttar Pradesh Technical University) VLSI Technology By Ankit Tyagi ™ Zs Quantum Page QUANT!JM PAGE PVT. LTD. Ghaziabad m New Delhi‘Apram Singh Quantum Publications® (A Unit of Quantum Page Pvt. Ltd,) Plot No. 69/27, Site - 4, Industrial Area, Sahibabad, Ghaziabad-201 010 PUBLISHED BY: Phone 0120-4160479 Email: pagequantum@gmailcom Website: wwv.quantumpage cain Delhi Office : 1/6590, East Robtas Nagar, Shahdara, Delhi-110082 © Au Recits Reserve [No port of ht publoaton maybe wpredaced or transmited, in any form or by any moon, without permission [rai enaredi wk vl rom ae | teivedeberdsbleFeyetarhasben mato eee | amg, tower sete he pair no othr fare be cay rcp fy ron pled ran anete eps oe sbs | Sateen rary ers, onisios aap | ingot of wo hs ormati, VLSI Technology (EC : Sem-5) 1" Edition : 2020-21 == C ONTENTS ‘KEC-053 : VLSI TECHNOLOGY UNIT: INTRODUCTIONTO ICTECHNOLOGY (1-1 Fto 1-20F) ‘SSI, MSI, LSI, VLSI Integrated Circuits, Crystal Growth and Wafer Preparation: Electronic Grade Silicon, Czochralski Crystal Growth, silicon Shaping, Processing Considerations, Wafer Cleaning, ‘Technology » Basic Concepts, Wet cleaning, Dry cleaning, LUNIT2 ; EPITAXY AND OXIDATION (2-1 Fto2-21F) Epitaxy: Vapor Phase Epitaxy, Molecular Beam Epitaxy Silicon on Insulators, Epitaxial Evaluation. ‘Oxidation: Growth Kinetics, Thin Oxides, Oxidation Techniques and Systems, Oxides Properties, UNITS : LITHOGRAPHY (8-1 Fto3-17F) Lithography: Optical Lithography, Electron beam lithography, Photo masks, Wet Chemical Etching Dielectric and Polysilicon Film Deposition: Deposition Processes ‘of Polysilicon, Silicon Dioxide, Silicon Nitride UNIT-4: DIFFUSION ANDION-MPLANTATION (4-1 Fto4-21 F) Diffusion: Models of diffusion in solids, Fick's 1-Dimensional diffusion equation, Diffusion of Impurities in Silicon and Silicon Dioxide, Diffusion Equations, Diffusion Profiles, Diffusion Furnace, Sold, Liquid and Gaseous Sources. Ton-Implantation: Ion-Implantation Technique, Range Theory Implantation Equipment. UNITS : METALLIZATION & PACKAGING OF VLSI DEVICES (-1F to 5-30F) Metallization: Metallization Application, Metallization Choices, Physical Vapor Deposition, Vacuum Deposition, Sputtering, Apparatus Packaging of VLSI devices: Package Types, Packaging Design Consideration, VLSI Assembly Technologies, Package Fabrication Technologies, CMOS fabrication steps. SHORT QUESTIONS ($Q.1F toSQ-17 F) 16 T0 2017-18) (SP-1F to SP-15 F) SOLVED PAPERS (201Introduction to IC Technology 1-2F (BC-Sem-5) Introduction to IC Technology PART-1 rated Introduction to IC Technology : SSI, MSI, LSI, VLSI Integrate ‘Circuits, Crystal Growth and Wafer Preparation : Electronic Grade Silicon, Czcchralski Crystal Growth. “CONCEPT OUTLINE ‘+ BGS, a polycrystalline material of high purty, is the raw material forthe preparation of single-crystal silicon. + Caochralski growth is the process used to grow most of the | ~ ~ CONTENTS crystals from which Questlooe- Anewen Tain weeny Larto cip || | Pare Sa, MSH LS, VST Long Answer Type and Medium Answer Type Questions Integrated Cirsts eee Catal Growth and War Pear Tee] Detne the term St, MS, LS, VLSE and UL, Fictronte Grade Silico, oral Cryetal Growth : Cunha ry x arta: Silicon Shopng, Processing 1-19F to L19P <—_ Considerations, Wafer Cleaning ‘Technology-Basic Concepts, \ ‘Wet Cleasing, Dry Cleaning 1-1 F(EC-Sem-5) Depending upon the number of active devices per chip, there are different levels of integration ; i SSI: ‘When the active devices per chip are less than 100, then itis referred ‘as small scale integration (SSI). Most ofthe SSI chips use integrated resistors, diodes and bipolar transistors. MSI When the count of active devices per chip is between 100 and 1000, then itis referred as medium scale integration (MSD. In most of the MSI chips, BJTs and enhancement mode MOSFETs are integrated iii, LSI: In large scale integration (LSI), the number of active devices per chip ranges between 1000 and 100,000. In general, LSI chips use MOS. ‘transistors; as it requires less number of steps for integration, Thus more number of components can be produced on the chip with MOS. transistors than with the bipolar transistors, vist: When the active devices per chip are ever hundreds of thousands, then itis referred as very large scale integration (VLSD). Almost all ‘modern chips employ VLSI techniqueVLSI Technology 1-3FEC-Sem-5) vist: Recently a nev level of integration has been introduced whichis known Soultra large scale integration (ULSD. In ULSI technique, more than ‘one million active devices are integrated on a single chip. Pentium ‘microprocessors use ULSI technology. Table 1.1.1. S.No, Level of integration Number of active devices per chip 1_| Small scale integration (SS) |) ess than 100 2_| Medium seale integration (MSD) 100- 10000 3._| Large seale integration (LSD 1000 - 100000 “| Verylarge scale integration (VLSD) Over 100000 | & | Ultralarge seale integration (ULSD | Over 1 million ‘Que 1a) ] Explain electronic grade silicon with neat diagram. 1 Electronic-Grade Silicon (BGS), a polycrystalline material ofhigh purity, is the raw material for the preparation of single-crystal silicon. 2 BGSis undoubtedly one of the purest materials available. The major impurities are boron, carbon, and residual donors. 3, Toobtain EGS requires a multistep process. First, Metallurgical-Grade Silicon (MGS) is produced in a submerged-electrode arc furnace, as, shown in Fig. 1.2.1 Quertsite, Coal, Submerged Bletrode (Coke, Wood Chi 3 9 0,50, #0 Me TR Sosy, 80. sit, -813810+00 aeeeeeeeeeeaee ‘oped ne Permace Fig. 1.2.1, Schomaticof a 7 ‘ott reponse soe 1-4F (EC-Sem-5) 4 Introduction to IC Technology ‘The furnace is charged with quartzite, a relatively pure form of sand (Si0,), and carbon in the form of coal, coke, and wood chips. In the furnace a number of reactions take place, the overall reaction being ‘SiC{eolid) + SiO, (solid) + Si (liquid) + Si0 (gas) + CO (gas) ‘The process is power intensive, requiring 13 kWh/kg, and MGS in drawn off and solidified at a purity of 98 %, ‘The MGS used in the making of metal alloys is not sufficiently pure to use in the manufacture of solid-state devices, ‘The next process step isto pulverize the silicon mechanically and react it with anhydrous hydrogen chloride to form trichlorosilane (SiHCl,), according tothe reaction Si(eolid) + 3HC\ gas) -> SiHCL,(gas) + Hy(gas) + heat (1.2.2) ‘The reaction takes place in a fluidized bed at a nominal temperature of 300°C using a catalyst. Here silicon tetrachloride and the chlorides of impurities are formed. 2a Reaction Chamber Silicon Bridge Slim Rod, 4 mm Diameter Polycrystalline Silicon Rod Quartz Bell Graphite Holder Insulation <— Power Input SiHCly + Hy Pig. 1.22. Schematic ofa CVD reartor used for BGS production. At this point the purification process occurs. Trichlorosilane is fiquid at room temperature, as are many of the unwanted chlorides. Purification is therefore done by fractional distillation.VLSI Technology 1-5F CSem.s) Jo. BGS is prepared from the purified SiHCl in achemical vapor deposit {CvD) process similar to the epitaxial CVD process. The chemical reaction {sa hydrogen reduction of trichlorosilane. ‘2SiH1Cl,(gas) + 2H,(gas) > 2Si(solid)+ HCI (gas) (123) 11 ‘This reaction is conducted in the type of system shown in Fig. 1.2.2.4 eaistance heated rodof silicon, called a“slim rod” serves asthe nucleation point forthe deposition of silicon 12, Acomplete process eyele takes many hours and results in rods of EGS, ‘hich are polyerystalline in structure, up to 0.2 m in diameter and several meters in length 13. BGS canbe cut from these rods as single chunks or crushed into nuggets QueI3. | Write a short note on Czochrasiski proce: ABTU 2015-16, Marks 05] ‘Answer 1. Fig. 1.3.1 shows the schematic of a CZ system which can be used for both silicon and GaAs crystal growth, Here, the melt is contained in a crucible and kept in a molten condition by heating. 2 Aseed crystal, suitably oriented, is suspended over the crucible in a chuck Fr gromth, the sedis inserted into the melt until its end i molten. 1-6F (EC-Sem-5) Introduction to 10 Technology 3. Ibisnow slowly withdrawn, resulting ina single crystal which grows by progressive freezing at the liquid-solid interface. A pull rate of about 50.100 mm/h: is typical for both silicon and GaAs, 4, Provisions are also made to rotate the crystal, and sometimes the crucible as well, during the pulling operation. 5, A series of annular heat shields are provided between the growth region and the walls of the reactor, in order to control radial thermal sgradients during the solidification process. 6 Forsilicon the entire assembly is enclosed within an envelope which is, ‘water-cooled and flushed with an inert 7. With GaAs,on the other hand, itis important to prevent decomposition of the melt during crystal growth by maintaining an overpressure of about 1.0 atm of arsenic. & It is necessary that the latent heat of fusion be removed from the crystal-melt system during the growth process. This heat is lost by ‘radiation from the crystal surface and by thermal conduction along the crystal axis ‘Que 1d. | Describe CZ process in detail with neat diagram. What is the pull rate in CZ technique ? How the pull rate is controlled ARTU 2017-18, Marks 10 during the CZ erystal growth process ‘Answer A. CZ process: Refer @. 13, Page 1-5F, Unit-1. B. Pull rate in CZ technique : 1. The pull rateinfluences the incorporation of impurities into the crystal and is a factor in defect generation. Generally, when the temperature gradient in the melt is small, the heat transferred to the erystal is the latent heat of fusion. 3. Asaresult, the pull rate generally varies inversely with the diameter as shown in Fig. 1.4.1. 4. Pull rate affects the defect properties of CZ crystals in the following way. The condensation of thermal point defects (ie., vacancies and silicon self-interstitials) into small dislocation loops (termed microdefects) occurs as the crystal cools from the solidification temperature. 5. The number of defects depends on the cooling rate, which is a function of pall rate end diameter, at temperatures above 950 °C. 6. Apull rate of mm/min eliminates defect formation by quenching the point defects in the lattice before they can agglomerate 7. We observe from Fig. 1.4.1 that large diameters preclude this pull rate for crystal diameters above 75 mm.VLSI Technology 1-TF ©C-Sem.g) Large defects such as edge dislocations are not influenced by the poiny defect condensation process. a. ‘Arelated phenomenon is the remelting of the erystal that occurs because ® rtemperature instabilities in the melt caused by thermal convection. ‘This condition can also be suppressed by attaining a pull rate of 10 vp mm/min, which is half the maximum attainable pull rate, as /Theoretical growth rate 60 Solidifind without single-crystal e structure z fas ; z Solidified with single-crystal £ structure g Esot ull rate needed to 1.5} suppress remelt ol, 20 30 40 50 60 70 80 90 Diameter (mm) mata Que LB] A silicon ingot with 0.5 x 10'* boron atoms/cm’ is to be grown by CZ method. What should be the concentration of boron in the melt to obtain the required doping concentration? The ‘segregation coefficient of the boron is 0.8, [ARTU 2017-18, Marks 10, Given : C, = 0.5 x 10° B atoms/em®, k, = 0.8 for boron To Find : Concentration of boron. 1. The concentration of dopant in the solid phase of silicon is given by, Cs ral “yr 2 Assume My= 2M. 1-8F (EC-Sem-5) Introduction to IC Technology 3, We want a concentration of C; = 0.5 x 10% atoms of B/em® halfway through the final grown ingot, ie, when Co oea-0.257"7 = 5.90 x 10!5B atoms/em*. BRI eaptain crystal structure with te types. =a Crystal structure + ‘The erystal structure is formed by associating every lattice point with an assembly ofatoms or molecules or ions, which are identical in composition, ‘arrangement and orientation. 2. Following are the different types of crystal structures : Body Centred Cubic Structure (BCC) : 1. BCCsstructure has atoms at its each corner and one atom in its centre. Tozal atoms in BCC = /8 x 8+ 1= 2 atoms ‘The coordination number of BCC arrangement is 8 and packing factor is 0.68. ‘The BOC structure can be generally seen in Lithium, Potassium, Sodium SS L Fig. 1.6.1. BCC.VLSI Technology 1-9F EC-Sem.5) i. Face Centred Cubie Structure (FCC): Lteeonsists of atoms at its each corner and one atom at centre of each face ‘Total atoms in FCC unit cell= V8 x 8+ /2x6=1+3=4atoms 2 The coordination number is 12 and packing factor is 0.74 for FCC arrangement 3. The FOC structure can be generally seen in Copper, Gold, Silver and Lead ete Fig. 1.62. FCC. ii, Hexagonal Close-Packed Structure (HCP) : 1. The unit celis like a hexagonal prism in HCP. 2 There are twelve corners and each corner have an atom and one atom atthe centre of each ofthe two hexagonal faces and three atoms in the body of the cell. In total, seventeen atoms take part in formation of @ HCP unitell Total atoms in HCP = 12x 2 +342% 1-6 atoms 2 ‘This is identical to FCC, having coor fon wing coordination number 12 and packing TRSHCP structureis generally seen in Zine, Magnesium and Beryllium Fig.1.6.3; Hep, Seat Classify the defect in crystal structure 1-10F (EC-Sem-5) Introduction to IC Technology Classifications of defects : i. Poin’ defects: : 1. Point defects take several forms as shown in Fig. 1.7.1 Any non-silicon ‘atom incorporated into the latice at either a substitutional (.e., replacing ‘a host silicon atom) or interstitial ((.e., between silicon atoms) site is considered a point defect. 2. This is true whether the atom is an intentional dopant or unintentional impurity. Missing atoms create a vacancy in the lattice called a “Schottly defect” which is also considered a point defect. 3, silicon atom in an interstitial lattice site with an associated vacancy is called a “Frenkel defect.” 4, Vacancies and interstitials have equilibrium concentrations that depend on temperature. Impurity in Interstitial Site oe silicon oe oe oe einterstitial Silicon “ae RY Frenkel Impurity on Substitutional Site 'Vacaney or Schottky defect Fig. 1.7.4. The location and types of point defects in a simple lattice. 5. Point defects are important in the kinetics of diffusion and oxidation. ‘The diffusion of many impurities depends on the vacancy concentration, as does the oxidation rate of silicon. 6. Vacancies and interstitials are also associated with defect formation in processing, i. Dislocations : 1, Dislocations form the second class of defects. Two general categories of dislocations are screw and line (edge), the terms being aptly descriptive of their shape. 2, Fig. 1.7.2isa schematic representation of a line dislocation in a cubic lattice; it can be seen as an extra plane of atoms AB inserted into the lattice. 3 Thelline of dislocation would be perpendicular to the plane of the page. 4, Dislocations in a lattice are dynamic defects; that is, they can move under applied stress, disassociate into two or more dislocations, or ‘combine with other dislocations. 5. Avvector notation developed by Burgers characterizes dislocations in the crystal as to their length and direction, The vector notation is also used to describe dislocation interactions.1ALF EC-Sem.5) Fig, 1.72, An edge dislocation in a cubic lattice created by an extra plane of atoms. The line of the dislocation perpendicular to the page. ii, Area (planar) defects: 1. Twoarea defects are twins and grain bound 2. Twinning represents a change in the crystal orientation across a twin plane, such that certain symmetry (like a mirror image) exists across that plane. In silicon, the twin plane is (111). 3. Agrain boundary represents a transition between crystals having no particular orientation relationship to one another. 4. Grain boundaries are more disordered than twins and separate grains of single erystals in polycrystalline silicon, 6. Area defects, such as twins or grain boundaries, represent a large area discontinuity inthe lattice. press & The crstalon either side ofthe discontinuity may be otherwise perfect ae fects appear during crystal growth, but crystals having such fects are not considered usable for IC manufacture and are discarded. iv. Volume defects: 1. Volume or an jor three-dimensional defects form when a cluster of point defects Inpurigratse tee dimensional void or a pore. Conversely a cluster of a5 ms may join to form a three-dimensional precipitate. e size of a volume defect may centimeters or sometimes larger, Such defects have a trem and perormancs ofthe ensue effet o influence onthe behaviour Que18. |] Discuss the crystal hardening techniques. Tange from a few nanometers to a a 1-12F (EC-Sem-5) 1. The generation of thermally induced glide dislocations can be reduced if the crystal is strengthened, 20 as to increase its critical resolved shear stress. 2. Inailicon growth, for example, this occurs to some extent by the rearporation of oxygen due to the corrosive action ofthe SiO, crucible walls 3. InGaAs, the intentional doping with group III and V impurities has been used for this purpose. 4. ‘The mechanism of solution hardening ix not fully understood at the present time. 5, Ithas been proposed that itis caused by the strain field created by the lattice misfit due to the impurity, which inhibits the propagation dislocations, once they are formed. Introduction to IC Technology O—OE—E—EeE————— 6 The energy of movement of dislocations is much lower than their ‘energy of formation, which may account for the effectiveness of this technique. 7. Isoelectronic doping is not used commercially for a number of reasons. 8 First, although the material is almost dislocation-free, itis extremely brittle so that itis hard to manufacture into slices, and tends to fracture during device fabrications. 8. Next, the addition offndium to the Gass increases its lattice parameter, so that any subsequent growth on its surface occurs under conditions oflattice mismatch. 10. Finally, it was shown that double annealing of GaAs provided crystals, which met the requirements for threshold voltage uniformity of field effect transistor device across a slice without a need for solid solution hardening. ‘Que 1.9. | How the evaluation of crystals can be done ? Answer 1. Routine evaluation oferystals involves testing their resistivity, evaluating their crystal perfection, and examining their mechanical properties, such as size and mass. 2. Other less routine evaluationsinclude measuring the crystals oxygen, carbon, and heavy metal content. 3. The evaluations of heavy metal content are made by minority carrier measurements or neutron activation analysis. After growth, the crystal is usually weighed, then inspected visually. Gross crystalline imperfections such as twinning are visible easily.13 ECS. ee eee vist Technol < ingot containing suc defetsare cut from the boule, 6 Seton eal that are imepulary shaped “ Wafer font surface Dev : pear gfe g¥ 8 pulkstacting > "00 00 0 ‘aa 02 2, fF 00 Cay As remy be CA ettered Cz imparity \”sgobile impurities Fig. 1.9.4. Sehomati ofa denaded tone in & wafer cross Section asd ditting cites @ and 8 are zones denuded of defects, ane represents the region of intrinsic gettering. i 1, Next the butt end of the ingot, or a slice cut from that position, is preferentially etched to reveal defects such as dislocations. 4 Acommon etchant is Sirts etch, which isa one/one mixture of HF acid dnd fivermolar chromic nei ‘This same etch can be used on polish and processed wafers to delineate other types of micro defects orimpurity precipitates. 10. Cracks can be detected by a method that uses ultrasonic waves. PART-2 Silicon Shaping, Processing Considerations, Wafer Cleaning ‘Technology-Basic Concepts, Wet Cleaning, Dry Cleaning. I Questions-Answers Que LA] Discuss ai , a different shaping operations involved in Preparing wafers with diagram. AKTU 2016-17, Marks 7.5 ‘Anewer of two steps : ‘The shaping operations consist ingot are removed : re and tang ends of the ir ‘Tez n the wafer preparation is toremove the tapered erystal m the boule. This process is known as ends.i-., seed and tang er end cropping. . 1-14F C-Sem-5) 2 Introduction to IC Technology “The portion of the ingot that fails the resistivity and perfection evaluation should also be cut away. ‘The surface of the ingot is ground to get a uniform diameter across the length of the ingot : In this step, we have to define the diameter of the material ‘The required diameter is achieved by surface grinding, ‘mechanical operation. : Silicon ingots are grown slightly oversized because the automatic ‘Gameter control in crystal growth cannot maintain the needed diameter tolerance and erystal cannot be grown perfectly round. ‘After diameter grinding, one or more flats are ground along the length of the ingot as shown in Fig. 1.10.1. Preparing crystal z ee! os 1.40.1, Flat grind along the length of the ignot. ‘The larger flat is known as primary flat, which is used as a mechanical locator in automated processing equipment to position the wafer. Italso serves to orient the IC device relative to the erystal. ‘The smallest flat is called secondary flat and used to identify the orientation and type of the material as shown in Fig. 1.10.2. (pe oo ee which is a (111) o-type Mat (1111 p-type Primary Primary flat F |e fat 30" Secondary flat Ty Secondary fat 1100} n-type 1001 p-type Fig. 1.10.2, Primary and secondary flats in n-type and p-type Si wafer at different orientations.ist Technology |A. Electronic grade silicon : Refer Q. 1.2, Page 1-3F, Unit-1. B. Polishing process of silicon : / 1. Polishing is the fine: step. Its purpose is to provide a smooth, specular | surface on which device featuces can be photo engrave, 2. Fig. 1.11.1 shows a typical polishing machine and a schematic of the process. 4. The process requires considerable operator attention for loading and unloading. ‘4. Tteanbe conducted as a single wafer or batch-wafer process depending on the equipment. 5. Wafers are mounted on a fixture, pressed against the pad under high pressure, and rotated relative to the pad. 6. Amixture of polishing slurry and water, dripped onto the pad, does the polishing. 7. The porosity of the pad is a factor in carrying slurry to the wafer for polishing. & The slurry isa colloidal suspension of the SiO, particles in an aqueous solution of sodium hydroxide. 9. In the mechanical step, the silica particles in the slurry abrade the oxidized silicon away. 10. Polishing rate and surface finish are complex functions of pressure, pad bropertie, rotation speed, slurry composition, and pH of the polishing solution. Pressure Polishing pad LALLA, Schemati¢ of polishing process, Introduction to IC Technology ‘FaSTABE] Discuss the processing considerations of silicon wafers. Tn the IC processing of silicon wafers, itis usually necessary to maintain the parity ond perfection of the material and it is done by three method: i. Chemical cleaning + Silicon wafers are usually cleaned chemically to remove organic films, heavy metals, and particulates. ‘The ammonium hydroxide and sulfuric acid based mixtures will also remove organic contaminants. ‘These cleaning solutions leave the surface of a wafer in a hydrophilic state due to the oxidizing nature of the peroxide. Since the chemically grown oxide can contain impurities from the chemicals, it is usually removed by a short immersion in dilute hydrofluoric acid fi, Gettering Treatments : Many VLSI circuits require low junction leakage currents. Narrow- base bipolar transistors are sensitive to conductive impurity precipitates, which act like shorts between emitter and collector. 2. ‘These elements are located at interstitial or substitution lattice sites and are generation-recombination centres for carriers. 3. Gettering is a general term taken to mean a process that removes harmful impurities or defects from the regions in wafer where devices are fabricated. 4, Among these techniques are ways to pretreat silicon wafers prior to IC processing, Pregettering provides a wafer with sinks that ean absorb impurities as they are introduced during device processing. One technique of removing impurities involves intentionally damaging the back surface of the wafer. Mechanical abrasion methods such as lapping or sand blasting have been used for this purpose. 6. A more controllable process uses damage created by a focused heat beam. This process requires a threshold energy density of 5 J/em* 7. One configuration of this technique involves using a Q-pulsed, Nd : ‘YAG laser. The laser beam is rastered along the back surface to create an array of micromachined spots. & Depending on the energy density and proximity of the spots, the silicon lattice is damaged and/or strained by the high-energy pulse, 9. During thermal processing, dislocations emanate from the spots. If the stresses placed on ‘he wafer during furnace processing are low, the dislocations remain | valized on the back surfaceaanaen 1-17F C-Sem.s) ea eat es Se rer. te ee ed 2 ter edges cool rapidly by radiation to the surroundings, but the | Se ee | ae ae Peer} obsT where, a = Coefficient of thermal expansion, E-= Young's modulus. AT = Temperature difference across the wafer. 4 Str are usually kept to acceptable level by. withdrawing wafers from the furnace slowly to minimize the ‘temperature gradient or by lowering the furnace temperature to the point where the yield strength at the removal temperature exceeds the stresses imposed, 5. Oxygen precipitates can reduce the yield strength up to five fold. ‘QueTAST] Why is cleaning of silicon wafer necessary before any processing steps ? Explain the crystal structure, [ARO z0n6-17 ark 10] = z A. Reason: The silicon surfce must, difaion, which may difasin role 2 Thecratal defect may produce lacalized impurity concentration. Thi .. legradtion ofjunction charactovetieg ence the silicon crystals must be made highly perfect B. Crystal st : Crystal structure : Refer Q. 1.6, Page 1-8P, Unite. Que 114.] What is the objective of ‘one method of wafer cleaning. be prevented against contaminants during interfere seriously with the uniformity of the wafer cleaning ? Explai 1-18F (EC-Sem-5) Introduction to IC Technology A. Objective of wafer cleaning : The objective of wafer cleaning is the removal of particle and chemical impurities from the semiconductor surface without damaging or deleteriously altering the substrate surface. B. RCA: 1. One highly successful approach to cleaning silicon, known as “RCA clean,” isto use two solutions in sequence. 2. ‘The first of these consists of 1: 1:5 to 1: 2: 7 volumes of NH,OH H,0,:H,0. 8, Here, the H,0, functions to oxidize all remaining organic contaminants on the surface, which are present because of incomplete removal of photoresist, and also because of airborn materials and physical handling. 4. The NH,OH is effective in removing heavy metals such as cadmium, cobalt, copper, iron, mercury, nickel, and silver by forming amino complexes with them, 5. Next, a solution consisting of HCl: H,O,: H,O ina 1:1:6to1:2:8 volume ratio is used to remove aluminum, magnesium, and the light alkali ions, and to prevent displacement replating from the solution, 6. ach of these steps is carried out for 10-20 min at 75-85°C, under conditions of rapid agitation. Nitrogen gas bubbling through the etchants is often used for this purpose. 7. Finally, wafers are blown dry and stored in a clean environment until further processing. 8. Results with this cleaning technique make it quite suitable for bipolar as ‘well as MOS microcircuits, so that it is in wide use in industry at the present time. queris)] Write a short note on dry cleaning method. “Answer 1. A major disadvantage of all wet cleaning systems is the use of large amounts of hazardous/toxic liquids. 2. Increasingly, interest has focused on the use of “dry” cleaning processes, with their inherent advantage of greatly reduced chemical usage 3, An additional advantage is that they can be readily integrated into automated manufacturing tools. 4. Anumber of different chemicals can be used in dry cleaning processes. ‘Anhydrous HF, as well as HF/H,O vapor, has been used for oxide removal.L19F C-Seq i oF (C-Sam: a e id HCl followed ae yus NH,OH, NF, an gases, followed by a ringe j 5 Anny fed water, have also been used for removing heavy metal ang ae let light to prod. sai aned wth lilt Ht 0 produce one and 5 roon raid moving organic photoresist realy, and woh ce anng esc of Gada 1 ret sabe teen din onuntion with HP/HO vapor fry Cater of ses 8. Finally, plasma discharges have also been used for cleaning purposes, VERY IMPORTANT QUESTIONS Following questions are very important. These questions) ‘may be asked in your SESSIONALS as well as UNIVERSITY EXAMINATION. Q.1. Write a short note on Czochrasiski process. mas Refer Q. 13. @2. Describe CZ process in detail with neat diagram. What i the pull rate in CZ technique ? How the pull rate controlled during the CZ crystal growth process ? AME Refer Q. 14, - @.3. Asilicon ingot with 0.5 x 10" boron atoms/em? is to be grow, by CZ method. What should be the concentration of bora Thee melt to obtain the required doping concentration? MME Refer Q. 15, oefficient of the boron is 0.8. 4, Discuss difte : wafers with dia eetaping operations involved in preparing am Refer Q. 1.10, @5. Explain electroni the polishing procera silicon with neat diagram. Explai? Mme Refer Q ay em Of ilicon in detail, 26. Discuss the AME Refer Q. 112 BS Considerations of silicon wafer 20 (EC-Sem-5) Introduction to IC Technology @.7. Why is cleaning of silicon wafer necessary before any processing steps ? Explain the crystal structure. was: Refer Q. 1.15. Q.8. What is the objective of wafer cleaning ? Explain any one method of wafer cleaning. ‘ase: Refer Q. 1.14. ©00| Paret : CONTENTS Epitaxy : Vapor-Phase Epitaxy, .. Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial Evaluation Oxidation : Growth Kineties, ‘Thin Oxides, Oxidation Techniques and Systems, Oxides Properties 2-1 F &C-Sem.5) .- 2-2F to 1-108 2-LIF to 2-20F 2-2F (EC-Sem-5) Epitaxy and Oxidation PART] ae t Epitaxy Ve -Phose Epitaxy, ‘Molecular Beam } gir aise Epitaxial Evaluation, = ye] 7 CONCEPT GUTLINE 7 + Rpltaxy offers doping profiles and material properties, | + Silicon on Insulator (SOD) is a recent non epitaxial approach to providing single-erystal silicon. Questions-Answers Long Answer Type and Medium Answer Type Questions QueRA. | What is epitaxial growth ? What are the advantages of epitaxial process over diffusion and Czochralski process ? AKTU 2016-16, Marks 05 ‘Answer A. Epitaxial growth : Epitaxial growth is the process used to grow athin crystalline layer on a crystalline surface (substrate). The substrate wafer acts as seed crystal. In this process, erystal is grown below melting point, which uses an evaporation method. B. Advantage of epitaxial process over diffusion process: 1. Epitaxial process offers device engineers a means to control the doping profiles whichis not attainable through diffusion process. 2 The physical and chemical properties ofthe wafer can be made different using epitaxial proces. C. Advantage of epitaxial process over Czochralski process : 1. Unlike the Czochralski process, crystalline thin films can be grown below the melting poin: using epitaxial proces WAR] Discus Vepor Phase Epitaxy WPE. 1. In vapor-phase epitaxy (VPB), which is « subset of chemical vapor deposition (CVD), transport of the element(s) occurs in the form of volatile species which flow toward the substrate.vustTechaology __#SFEC Sem) = pina carr, tw seis may be adored (or chemise) Aside ere where they react form the element) of which syer is composed; alternatively, one or more species may ther {he ag this form before being adsorbed on the surface. nly vrface temperature is high, and the species are free to move by Te dffsion, until eventual incorporation, at kink sites, into the growth ayer. 4. This process continues asthe epitaxial film builds up. FRR eptain basi traneport proces in VPE. Famer] Let us consider the Reynolds number R,, a dimensionless parameter that characterizes the type of fluid flow in the reactor, R= DP # D, = Diameter of reaction tube Gas velocity p= Gas density where, as viscosity ‘The carrier gas is usually hydrogen. A boundary layer of reduced gas velocity will form above the susceptor and at walls of the reaction chamber. The thickness ofthe boundary layer y is defined as [pet TR where x is distance along the reaction chamber. Tee -suzes of species going to and coming from the wafer surface are functions of several variables, including temperature, system Py ssur Feactant concentration and layer thickness. The flux is defined a= Ddn dy ‘and approximated as where n, and n ef tee the pe stream and surface reactant concentratioe®. Dea ; as-phase diffusivity which j ; temperature andy? tbh is function 0 2-4F (EC-Sem-5) Epitaxy and Oxidation joundary layer thickness, ‘J = Reactant flux of molecules per unit area per unit time. ‘Under steady state conditions, the flux of reactant across the boundary layer is equated by a chemical reaction at the silicon surface where the film is growing. Inapproximate terms Jahn, where , = chemical reaction rate constant representing ws AD : D ee eee ‘GheFA. | Describe dopant profile in brief. ‘AKTU 2015-16, Marks 05, Tnawer | a‘ 10. Incorporating dopant atoms into the epitaxial layer involves the same considerations as the growth process requires. Hydrides of the impurity atoms are used as the source of dopant. ‘Thermodynamic calculation indicates the hydrides are relatively stable because of large volume of hydrogen present in the reaction. Arsine is being absorbed on the surface, decomposed, and being incorporated into the growing layer. 2AsH, (gas) —> 2As(solid) + 3H, (gas) 2As (solid) —> 2As"(solid) + 22° Interactions take place between the doping process and growth process. In the case of boron and arsenic the formation of chlorides of these species is a competing reaction, ‘The growth rate of film influences the amount of dopant incorporated in the silicon. At low growth rates equilibrium is established between the solid and the gas phases, which is not achieved at higher growth rates. Dopant is released from the substrate through solid-state diffusion and evaporation, ‘This dopant is reincorporated into the growing layer either by diffusion through the gas phase or at interface.2-5F (CSem.5 visiTeehoology Fea Boptain auto doping process que a5, mer as an enhanced transition region between the layer gpd the aubetrate. shape of doping profile, close to the substrate, is dominated Fe atom the substrate and is complementary cre v< ADI) v= Growth velocity D = Substrate dopant diffusion constant {= Deposition time ‘Auto doping isa time-dependent phenomenon. The dopant evaporating from the wafer surface is supplied from the wafer interior by solid. state diffusion, ‘Thus, the flux of dopant from an exposed surface is not constant, but decreases with time. 5. Once the auto doping is diminished, the intentional doping predominates, and the profile becomes Nat. 6. Theertentofthe auto doping tail is a function of the substrate dopant species and reaction parameters such as temperature and growth rate, 7. Auto doping limits the minimum layer thickness that can be grown with controlled doping as well as the minimum doping level. Que 2.8, | What are susceptors? How it is used in epitaxial layers? ‘Answer | 1. Susceptors in epitaxial reactors are the analogs of erucibles in the erystal growing process. 2% They provide mechanical support forthe wafers and are the source of a ee energy for the reaction in induction-heated reactors. ‘geometric shape or configuration of the suscey 7 = a -ptor usually provides aa for recta, Like crucibles the susceptor must be mechanically ‘Honea non-contaminating othe process. ‘Susceptor must not react with the process reactants and. by products. 5. Induction , field" heed reactors require a material that will eouple to the RF te, but graphite susceptors require @ § The preferred material is graphit relatively impure and sof. coating because they are ro 2-6 F (EC-Sem-5) Epitaxy and Oxidation 26FECSem5) “itary and Oxidation 8 9%. 10. uw. 12, 13. M4 16 16 1. inorgy forthe reaction has beon supplied by heating the susceptor inductively. 2 ‘The energy is then transported to the wafer by conduction and radiation. Motor-generator sets at 10 kHlz or selGexcited RF oscillators at S00-Fie are used for heating. ‘A watercooled coil is placed close to the susceptor so coupling ean occur. ‘Tho col canbe inside or outside the reaction chamber depending on the design ofthe reactor. — ‘ant heating, a newer way of supplying energy to the reaction Etamber, proves more uniform heating than inductive Resting provides ‘The energy is supplied by banks of quartz halogen lamps. In most eases, process control involves maintaining gas flows sd tomperaturevat the desired values In modern equipment, the process cycle is generally microprocessor controlled, andthe operator has only to bring wafers to the reactor and take the faished wafers amy Three basic reactor configurations are shown in Fig. 2.6.1. > Gas Flow + Rf Heating + Radiant Heating Horizontal Radiant Barrel Fig, 2.6.1. Schétiatie of three common reactors, ‘There are: Horizontal : Horizontal reactors offer low cost construction. Vertical or Pancake : Pancake reactors are capable of very uniform deposition, but suffer from mechanical complexity. iii, Barrel : Radiated-heated barrel reactors are also capable of uniform Que 2.7, deposition, but are not suited for extended operation. Discuss about the epitaxial defects. ial 1 Defects arising from the substrate wafer can be related to the bulk Properties of the wafer or its surface finish, Impurity precipitates are one kind of surface defect that nucleate on an epitaxial stacking fault. Process related defects include slip. Dislocations accompany the formation of slip and of impurity precipitates from contamination.3] Technology n rade the quality of thin ‘These precipitates have been shown to degr: oxiey Tern eed in MOSFET gates. 5, Fig 2.71 is an example of an existing line dislocation continuing inty epitaxial layer. 2-TF (EC-Semg) ——s ‘Pig. 7.1, Common defects occurring in epitaxial layers, 6. Atemperature gradient exists normal to the substrate in an RF-heated reactor. 7. Slip due to this gradient (during epitaxy) is produced in the following 8. Heat flow from the susceptor through the wafer equals subsequent radiation from the front surface and is given approximately by _ Kat dx ‘where Kis the thermal conduetivity of silicon, SiO, (solid) + 2H, 3. The basic process involves shared valence electrons between silicon and oxygen; the silicon-oxygen bond structure is covalent. 4. During the course ofthe oxidation process, the Si-SiO, interface moves into the silicon. Its volume expands, however, so that the external SiO, surface is not coplanar with the original silicon surface. 5. Based on the densities and molecular weights of Si and SiO,, we can show that for growth of an oxide of thickness d, a layer of silicon with & thickness of 0.44d is consumed. 6. Fig. 2.12.1 shows the growth of Si0,. The framework of a model to describe silicon oxidation has been created, Silicon substrate Fig. 2.12.1, 2-12 F (EC-Sem-5) Epitaxy and Oxidation 7. Radioactive tracer, marker, and infrared isotope shift experiments have established that oxidation proceeds by the diffusion of the oxidizing species through the oxide to the Si-SiO, interface, where the oxidation reaction occurs. ‘Que 218. | Why oxidation is done ? Explain the chemistry and ‘Answer Reason : Oxidation is done to form a high quality oxide in a controlled and repeatable manner. This mechanism serves as a mask against implant or diffusion of dopant into silicon and to provide surface passivation. Deal-Grove’s model : Deal and Grove's model describes the kinetics of silicon oxidation, ‘The model is generally valid for temperatures between 700 and 1300 °C, partial pressures between 0.2.and 1.0 atm, and oxide thicknesses between 300 and 20,000 A for oxygen and water ambient. Fig. 2.18.1 shows the silicon substrate covered by an oxide layer that is in contact with the gas phase. Posse By oom Py Fig. 218.1. The oxidizing species are transported from the bulk of the gas phase to the gas-oxide interface with flux F,, are transported across the existing oxide toward the silicon with flux F,, and react at the Si-SiO, interface with the silicon with flux Fy, For steady state, F, = F, = Fy. The gas-phase flux F, can be linearly approximated by assuming that the flux of oxidant from the bulk of the21S (EC VLSI Technology Sem mnal to the diffe 10 the gas-oxide interface is proporti esi og ae a tinea a duidant concentration adjacent to the oxide surface Cy, P= hglCo-Cs) tere hgis toga phase mcs raster cefcent, 46 Torolate the equilibrium oxidizing species concentration in the oxide that in the gas phase, we have Henry's law, ; C,= Hps and C= Hpg where, C, = The equilibrium concentration in the oxide at the outer surface. Equilibrium bulk concentration in the oxide. | ‘The partial pressure in the gas adjacent to the oxide surface. ‘Po= The partial pressure in the bulk of the gas. 7. Using Henry's law along with the ideal gas law (-c,) ‘f= Gas-phase mass transfer coefficient. Oxidation is a non-equilibrium process with the driving force being the deviation of concentration from equilibrium. ‘The flux ofthis oxidizing species across the oxide is taken to follow Fick’ Jaw at any point d in the oxide layer. Following the steady-state assumption, F, must be the same at any point within the oxide, resulting in c Ps where, 10. DC, -C) BC, -C) d, where Dis the diffusion coefficient, C, is the oxidizing species concentrati ide adj i ent the a ntration in the oxide adjacent to 4, is the oxide thickness, ‘Assuming that the flux \s proportional to, Fy= uu. corresponding to the Si-SiO, interface reactio# FyzkC, where h, is the ra oxidation. constant of chemical surface reaction for silico# WRT] Desens i be the effect of impurities and damage on tht oxidation rate, AKTU 2016-17, Marks id 2-14F (EC-Sem-5) Epitaxy and Oxidation Tasner] pee Effects of impurities are: Water A significant acceleration in the oxidation rate was observed by increasing ‘the ppm of water vapour. In these experiments, the oxygen was from a liquid source and the oxidation chamber was a double wall, fused-silica tube with N, flowing between the walls. A precombustor and cold trap is used to achieve less than 1 ppm moisture level, Sodium : High concentration of sodium influence the oxidation rate by changing the bond structure in the oxide, thereby enhancing the diffusion and concentration of the oxygen molecules in the oxide. Halogen : Certain halogen species are intentionally introduced into the oxidation ambient to improve both the oxide and the underlying silicon properties (Oxide improvements include a reduction in sodium ion contamination, increased dielectric breakdown strength, and a reduced interface trap density. Ator near the Si-SiO, interface, chlorine is instrumental in converting certain impurities in the silicon to volatile chlorides, resulting in gettering, effect Areduction in oxidation-induced stacking faults is also observed. Care must be taken in handling and using the halogens mentioned since the system's metallic parts and exhaust can corrode. High concentration of halogen at high temperature can pit the silicon surface. Effect of damage : The silicon is usually damaged by ion-implantation of a non-electrically active species, or a group Lil or V dopant, separating damage effects from dopant effect is also difficult. Group III and V elements: ‘The common dopant elements in this group. when present in the silicon at high concentration levels, can enhance the oxidation behaviour. ‘The dopant impurities are redistributed at the growing Si-SiO, interface, ‘Theeffect results in a discontinuous concentration profile atthe interface, the dopant segregates either into the silicon or into the oxide ‘The redistribution of the impurity at the interface influences the oxidation behaviour. If the dopant segregates into the oxide and remains there, the bond structure in the silica weakens.2G F (EC-Sem, ‘VLSI Technology a — cq structure permits an increased iNCOrPOration, gag «a wt Me hens ; exidation rate. the sath oeegie into the oxide but then diffuse rapidly throug, 7 Ire: on the oxidation Kinetics Gace ] Why oxidation isnecessary in IC fabrication? Caleutayy the oxide thickness. Show that x Fae for short time and toX= [B@+1) for long time where X = oxic AKTU 2017-18, Marks Aaswer | : ide thickness. ‘A. Reason : Oxidation is done to form a high quality oxide in a controll and repeatable manner. This mechanism serves as a most against impl or diffusion of dopant into silicon and to provide surface passivation. B. Toshow: | 1. Tocaleulate the rate of oxide growth, we define N, as the number d oxidant molecules incorporated into a unit volume of the oxide layer. 2 Since the oxide has 2.2 x 102 SiO, molecules/em® and one O, molecu is incorporated into each Si0, molecule, N, equals 2.2 « 10% em~®for dq oxygen 3. The number for water-vapor oxidation is twice as big because two Hy) 1olecules are incorporated into each SiO, molecule. 4 ‘imbinng various equation and assuming ‘that an oxide may be presetl 'y fom a previous processing step or may grow before tht assumptions in the model are valid, that is, X = ‘quation can be generated, at t= 0, the following BeAKe Bion (2.183) where, conf “ ole 2168 3 Be 2C* . N, (2159) te Bitar of 5. The quantity B (2.164 ty trey _ the Presents Presence of the ints, ese time coordinate to account fo rt, 2-16F (EC-Sem-5) Epitaxy and Oxidation 6 1. 10, Eq, (2.15.1) is the well-known, mixed linear-parabolie relationship. Solving eq. (2.15.1) for X as a function of time gives, x ter aR [be e waa - One limiting case occurs for long oxidation times when t >> t and t>> AY4B. eof 215.5) X=Bt (2.15.6) Eq. (2.15.6)is the parabolic law, where B is the parabolic rate constant, ‘The other limiting case occurs for short oxidation times when (40 << AMAB. B X= Fe+0 2.15. Eq. (2.15.7) is the linear law, where B/A is the linear rate constant. Eq, (2.15.6) and (2.15.7) are the diffusion-controlled and reaction- controlled cases, respectively. Que 2.16. | Discuss the kinetics of thin oxide growth. =e 1 ‘The structure of the oxide very close to the silicon-oxide interface and the oxidation process itself both involve uncertainties. ‘Thin oxide growth is influenced by the cleaning techniques used and the purity of the gases used. ‘The wafers were chemically cleaned, dried in nitrogen, and loaded into the furnace in an argon ambient. Native oxide thickness and subsequent oxide growth when the ambient ‘was switched to dry O, were measured using in situ ellipsometry. The enhancement in oxidation rate was found to decay exponentially with thickness. The extent of thickness enhancement is not a strong function of surface orientation, doping level, or oxygen partial pressure. Reduced pressure oxidation offers an attractive way of growing thin oxides in a controlled manner. Oxides between 30 and 140 A thick have been grown at 900 to 1000°C using oxygen at a pressure of 0.25 to 2.0 Torr. ‘The observed kinetics are parabolic, and the rate constants agree with values extrapolated from atmospheric pressure. Oxides obtained by this technique etch at the same rate as dry oxides obtained at 950°C and 1 atm. ‘The equal etch rate indicates a similar composition and structure between the two oxides. The intrinsic breakdown fields are high (10 to 13 MV/em) and distributed over a narrow range.2-ATF EC-Sem.s) a the reduced pressure oxides are very unif ations are tt Jar to thicker oxides prepared at atmoapheri, as sequence has been devised in which a unifo Proete of small defect density is formed at a moderate qeeperature (1000°C or lesa) using a dry O,-HCL cond step consists of a heat treatment in Nj, Oy, and HCl a 12 Tard vide passivation and to bring the oxide thickness tothe desired level. 18, Such processing scheme takes advantage of beneficial effects occurring in both the lower and higher temperature ranges. TERRIA] wat is pronation cleaning? 1 Before being placed in a high temperature furnace, wafers must be leaned t eliminate both organic and inorganic contamination arising from previous processing steps and handling. 2 Such contamination can degrade the electrical characteristics of the vices and can contribute to reliability problems. 3. Particulate matter is removed by either mechanical or ultrasonic scrubbing. 4. Immersion processing techniques were the preferred chemical cleaning methods until the development of centrifugal spray methods, which eliminate the build-up of contaminants as cleaning progresses. 5. Thechemical cleaning procedure usually involves removing the organie contamination, followed by inorganic ion and atom removal. 6 A-common leaning procedure uses a H,0-H,0,-NH,OH mixture to remove organic contamination by the solvating action of ammonium hydroxide and the oxidizing effect ofthe peroxide ‘This process can also complex some comy group I and II metals. ‘To remove heavy metals a H,0-H,0,-HC1 solution commonly used. ‘This soltion prevents repatinghy forming soluble complexes with the {eajveion, andthe process performed between 75 and 85°C for 10 = followed by a quench, rinse, and spin dry. eee i : silicon raha ausideration for optimizing the cleaning procedure for 10. Modece dita Cbigh-temperature operations. ee Si iffusion (oxidation) furnaces are microprocessor controlled to Provide repeatable flow conte segueneing, temperature control, and gas low (mass 11. The micros varius perametny | BEevides a feedback lop for comparing the changes. sired ones, and for making the appropriate 2-18F (EC-Sem-5) yg a Explain plasma oxidation technique for the growth of oxide layer. Explain the application of Si0, layer in IC fabrication. [AKTU 2016-17, Marks 10) ‘A. Plasma oxidation technique : 1. The anodic plasma-oxidation process offers the possibilty of growing high-quality technique. 2, ‘This process has all the advantages associated with low temperature processing, such as minimized movement of previous diffusions and suppression of defect formation. 3. Anodic plasma oxidation can grow reasonably thick oxides at low temperatures. 4, Plasma oxidation is alow temperature vacuum process, usually carried out in pure oxygen discharge. 5, The plasma is produced either by a high-frequently discharge or a DC clectron souree 6. ‘Thegrowth rate ofthe oxide typically increases with increasing substrate temperature, plasma density, and substrate dopant concentration. B. Application of SiO, layer in IC fabrication: 1. Tt acts as a diffusion mask permitting selective diffusions into silicon wafer through the window etched into oxide. 2. Ttis used for surface passivation which is nothing but creating protective SiO, layer on the wafer surface. It protects the junction from moisture ‘and other atmospheric contaminants. 3, Ttserves as an insulator on the water surface. Its high relative dielectric constant, which enables metal line to pass over the active silicon regions. SiO, acts as the active gate electrode in MOS device structure. Itis used to isolate one device from another. Itprovideselectrica isolation of multilevel metallization used in VLSI. ‘Que2A9. | Explain in detail about the masking properties of SiO,. “Answer 1. Asilicon dioxide layer ean provide a selective mask against the diffasion of dopant atoms at elevated temperatures. 2 A predeposition of dopant by ion implantation, chemical dffsion or pheon techniques typically results in a dopant source ator nen the surface of the oxide. eae3 in detail. 219F (EC-Sem, VLSI Technology I Bem 6) wre drive-in step, diffusion in the oxide mys, 1 arin igh eer gion inthe sion tat the dopa oem jlfuse through the oxide in the masked region and reach thy fener va _ nts necessary to prevent the inversion ofa igh Sane chute oppose conctiviy b oor cating common impurities a conventional devi pained se8 ea marking properties result when the oxide i part 6 The impurity mas epity onde “past” phase, and prevents iy impurities from reaching the SiO, Si interface. sre aun of fin constants fr various dopantsin S10, depend on the concentration, properties, and structure of the SiO, |The commonly used n-type impurities P, Sband As as well as the most Fae gps taparty. ahve very anal difroncoeficen Ered compl with oxide masking GeokIh ] Describe the various charges present in oxidation layer ARTU 2016-17, Marks 7.5 daswer | 2 Various charges and traps are associated with the thermally oxidized silicon, some of which are related tothe transition region. ‘A charge at the interface can induce a charge of the opposite polarity in the underlying silicon, thereby affecting the ideal characteristics of the MOS device. This results in both yield and reliability problems. Mobile ionie \ charge (Q,) } SiO, Onide trapped (care (@e Fixed oxide Sid, Ped charge iQ.) a ; Fig. 2.20.4, Fig. 2.20.1 shows ger 7 WN Qi Beal tyPes of charges. These charges are described 2-20 F (EC-Sem-5) 10 Epitaxy and Oxidation where, Q=The not effective charge per unit area (Coulombs/em4) at Si-$i0, interface, N=Th net number of charges per unit area at the (0, interface, and 4 = The electri charge Located at the S:-SiO, interface, interface-rapped charger Qy have energy states in the silicon-forbidden bandgap and can interact electrically withthe underlying silion, ‘These charges are thought o result from several sources, including structural defects related to the oxidation process, metalic impurities or bond: breaking processes ‘The fixed oxide charge Q; (usually positive) is located in the oxide within: approximately 30 A of the $:-SiO, interface. Q, cannot be charged or discharged. Its density ranges from 10!°/ cm? to 10!*/ em®, depending on oxidation and annealing conditions as well a orientation. Qin related to the oxidation process itself. The mobile ionic charge Q, is attributed to alkali ions auch as sodium. potassium, and lithium inthe oxide as well as tonegaive fons and heav mnetals. ‘The alkali ions are mobile even at room temperature, when electric fields ae present. Densities range from 10" /em? to 10'#/cm? or higher and are related to processing materials, chemicals, ambient, or handling. VERY IMPORTANT QUESTIONS | Following questions are very important. These questions ‘may be asked in your SESSIONALS as wellas | UNIVERSITY EXAMINATION, | What is epitaxial growth ? What are the advantages of epitaxial process over diffusion and Czochralski process 7 Refer Q.2.1 Describe dopant profile in brief. Refer Q. 2.4 Explain molecular beam epitaxy in detail. What are its advantages over VPE ? Refer Q. 29.WISI Technology 2-21 F (EC-Sem.5) as) 14, Describe the silicon on insulator with neat dia; @4 iscuse about the epitaxial defects. rams as Refer Q 2.10 Q.5. Why oxidation is done? Explain the chemistry and kinetics of growth using Deal-Grove's model. mam Refer Q. 2.13 Q.6. Describe the effect of impurities and damage on the oxidation rate. wa Refer @. 2.14. Q.7. Why oxidation is necessary in IC fabrication ? Calculate the oid tists. Show tat X= [ye te, Al A? /4B. B reduces toX= 7 (+1) forshort time andtoX= /B@+1) for long time, where X = oxide thickness. mam Refer Q. 2.16. @8. Explain plasma oxidation technique for the growth of oxide layer. Explain the application of Si i ricati ane Forgan the application of Si0, layer in IC fabrication. ©08 Lithography and Polysilicon Film Deposition CONTENT! | Part-t + Lithography Optical ono 22F to $10F Lithogrephy, Bletron | | Beam Lithography | Photomasks, Wet Chemical Etching | Part-2 : Dielectric and Polysilicon S-10F to $-16F Film Deposition : Deposition Processes of Polysilicon, \ Silicon Dioxide, Silicon Nitride Neer os Reems, Siicon Nie es 3-1F (EC-Sem-5)csem-5) Lithography & Polysilcon Film Deposit, idee pst technology 3-9 F (EC-Sem-5) 1 3, The exposing radiation is transmitted through the “lear” parts of « 5 Zh a} Lithography, Blectron Beam Lithogra, mas Oi ae hie why | 5 the circuit pattern of opaque chromium blocks some ofthe radiation oromasks, | Bictype of chromium glass maski used with leravalt (UV) light a Other types of exposing radiation are electrons, X-rays, or ions. CONCEPT OUTLINE ‘4. Shadow (proximity) printing may be employed where the gap between a er etapa pth ade by lmproesing track and wafer is small + Aithograph isa less expensive picture made by impressing i AlitngraP nat, embossed slabs, each covered with pressingin | 5, 1nthecase ofa nonexistent gap, the method i called contact printing Gra particulr colour, onto a piece of stout paper. 6. Or some sort of image forming system (a lens, for example) may be + Photoressts are of two types interposed between mask and wafer. i Negative resist 1, ‘Therefor, lithography for integrated circuit manufacturing is analogous | i Pecteresit qe lithography ofthe art worl ——_ 1g The artist corresponds to the circuit designer. The slabs are masks for the various circuit levels. 9. The press corresponds to the exposure system, which not only exposes ‘each level but also aligns it to a completed level. 40. ‘The ink may be compared either with the exposing radiation or with the radiation-sensitive resist, And the paper can represent the wafer into ‘which the patterns will be etched, using the resist as a stencil 11. Optical lithography has peretrated the “1 um barrier” of resolution. 5] 12. As other lithographic techniques such as those using electron, X-ray, or ion radiation have improved, so has optical lithography. ‘Que34, | Explain lithography with neat schematic diagram. AKTU 2016-17, Marl Answer 13, For these competing methods large teams of capable people have been 1 Fes 1.1 illuatraes schematically the lithographic process used ty beaded — . ben arose on Gon tobe ricate circuit chips everal methods have only one or two key problems remaining Exposing radiation solved. Solution generally requires application of standard, but difficult Mask a Glass and meticulous, engineering. ‘Chromium (800 A) os i , anti ) Atimnbrmag tom may osuny Que $2, | Explain proximity printing and projection printing and 4 portion ofthis space | compare these two. ‘ARTU 2017-18, Marks 10) a a Resist | wae [ZQudeor multiple layers of device A. Proximity printing: substrate Q ae 1. _ Proximity printing has the advantage of longer mask life because there Develop sno contact between the mask and the wafer. ee 2. Typical separations between mask and wafer are in the range of 20 to 50 im, Resolution is not as good as in contact printing or projection es" ae 3. Proximity printing in the schematic form of a mask with a long slit of eparated| lane (wafer) by agape. width W separated from « parallel image pl Fig. 24.1, aeLithography & Polysilicon Film Depositigg s4F EC-Sem-5) ne Position yarger than the wavelength 2.of the imaging 1 toma a nt re actin ne the diffraction that forms the image of "he slit s a function only f 5. ‘and g which we shall call thy of 4, the particular combination of 2» parameter @ where; Q= W208) B. Projection printing : 1. Projection printing offers higher resolution than proximity printing together with large separation between mask and wafer. 2. Four important performance parameters of a printer are resolution, level-to-level alignment accuracy, throughput, and depth of focus. 3, The resolution of an optical imaging system of numerical aperture NA = sin a with light of wavelength A is, according to Rayleigh’s criterion, 0.611/sin « - the separation of two barely resolved point sources. 4. The Rayleigh depth of focus is given by + (2 sin? a). However, near the limiting resolution of the system, the contrest in the image is uselessly Now, consider a general optical system with no aberrations. ‘An aberration is a departure oftthe i e p imaging wavefront from the spherical ope fhatia aspherical wave diverging from a point in the object plane as spherical wave converging to a point in the image ‘The f number of the system is F = D,/2R and the numerical aperture i8 NA =sin a= R/J(D? + R®) = RID, where, Ris the radius of the exit pupil, and D, isthe dist ito the: ‘ance from this pupil to the image plane, isi Technology 9. 10, u 12 13, 14. It is also called the point-spread function 15. Thus, the smaller the 3-5 F (EC-Sem-5) ‘We want to recall briefly some results from the theory ofimage formation Wemto show how the transfer functions differ for coherent and incoherent imaging systems. For coherent object illumination all points in the object have wave ‘amplitudes with fixed phase relationships, and all phases have the same time dependence. ‘the field amplitude at point x, y, in the image plane (the wafer) will be called U, (9) It is caused by a filed distribution U,(x,, y,) in the object plane (the mash). We define a pupil function P(x, y) to represent the transmission of the vjund exit pupil, or hole, shown in Fig. 3.2.2, For points (x,y) within the pupil, P= 1; for points outside, P=0, The simplest objects a point source atx, =0. ‘The image of this source has the form 4 COnject plane «Exit pupil of ‘image plane imaging system Fig. 3.22. Nsy3) = Gag Oh Ol Fos = (3) ery ‘Thisis the well-known Airy pattern. J, isthe first-order Bessel function because the projection system int i i snted by the diameter spreads the point into the circular image represented bs i {torie the distance from the origin to the first zero ofJ,) of the patter in2.4 pF. wavelength and the f number (or the larger the NA) of the projection system, the better the resolution.s Lithography & Polsiticon Film Depositing ) 5 Projection printing Projection printing offers low 4 resolution. There is low room for improvement. GuodS. | Explain in detail about the optical lithography. ‘Answer ‘A. Optical lithography : Optical lithography comprises the formation of Orta ath vinble or ultraviolet radiation ina photoresist using conta, proximity, or projection printing. i. Optical resists: 1 Photoresats are of two types. A negative resist on exposure to light caer less soluble in a developer solution, while a positive resis become more soluble. 2 Commercial negative resists, consist of two parts : a chemically inert polysoprene rubber, which is the film-forming components and s photoactive agent. 43. The photoactive agent on exposure to light reacts with the rubber tn formcrosslinks between rubber molecules, making the rubber less soluble {nan organic developer solvent. 4. The reactive species formed during the exposure can react with oxygen and be rendered ineffetive for crosslinking. 5. Therefore resist is usually exposed in nitrogen atmosphere i, Contact and proximity printing : a. Contact printing : 1. Incontact printing a photomask is pressed against the resist-covered wafer with pressures typically in the range of 0.05 atm to 0.3 atm and exposured by light of wavelength near 400 mm. Nery highreacaton 1m inewidthis possible, but because of pati ssuiformity ofthe contact, resolution may vary considerably ser ‘Toprovide better contact over the wh over the whole wafer, a thin (0.2 mm) flexible ‘ask has ben used; 0.4 ym ines have ben formed in 30.98 um resist rk al produes defects in both the mask andthe wafer so thatthe period of use, or thin, may have to be discarded after a short Proximity printing: Projection seer eet @-8.2, Page 3-8F, Unit3. Printing : Refer Q.3.2, Page 3-F, Unit-3 LSI Technology we A proximity printer operates with a 10 mm mask-wafer 1p and a wavelength of 430 nm. Another printer uses a sap Mwavelength 250 nm. Which offers higher resolution? ee Fawr | 2 We know that 0= W |= Ne A. 42043 ym, g=10 um, Bo 1=0.25 um, g= 40 um, ‘Therefore A gives higher resolution. ‘GueSS. | Write a short note on electron lithography. eal 1. Electron lithography offers higher resolution than optical lithography pecause of the small wavelength of the 10-50 keV electrons. 2, Theresolution ofelectron lithography systems isnot limited by diffraction, put by electron seattering in the resist and by the various aberrations of the electron optics. 4, Scanning electron-beam systems have been under development for two decades, and commercial systems are available. 4. The EBES (Electron Beam Exposure System) machine has proved to be the best photomask pattern generator. It is widely used in mask shops. Because of the serial nature of the pattern writing, throughput is much less than for optical systems. 5. However, some special products such as microwave transistors have for ‘many years been manufactured by direct wafer patterning 6 Inthe first application to low-volume integrated circuits, some levels were patterned optically and some by electron beam. Que3.6. | Explain in detail about the genera with suitable diagram. ‘Answer |. The first use of electron-beam pattern generat photomask making. Fig. 36.1 shows two methods of making a photomask. On the Ish 9 reticle is patterned with an optical pattern generator thet is 2 machine ‘which under computer control, exposes and places pattern clement & form the chip image at 10x seale and which can make 60 to 100 esPoS Per minute. 3. The pattern element is the image of an illumi size of photomask tors has been in inated aperture of variableography & Polysilicon Film Depo 8 se ee 1 in a step-ropeat camera, w) sired mask area. ically controlled. The master interferometrically controlled. ’ . 5 Stepping secur rn projection printer or enpied and the cop iu inter. ed in acontact Prin oo attern generator is used to make ic, 6. an acento cae ofcomple hips hy dee : of optical vp can require 20 hours or more of optical patte mnerator time. : ae right, Fig. 3.6.1 shows the moro officient method of el & On the rghrning, The mask may be either a 1x mask or a5 xq) Toot retile for use in a wafer stepper. (Generate 10 x reticle by (a) E-beam pattern generator or| (2) Optical PG Generate master mask directly with E-beam PG. ‘This may be 1 x mask or 5 xreticle ‘Step reticle with 10 x reduction camera to make master mask Copy by contact printing Copy by contact printing |Fig: 9.6.1 Two) paths for generation of a photomask. Wee RAG| Explain the kinetics of wet etching. How gold is etched? ARTO 2017-18, Marks 05] A. Wet chemical etching : 1. Wet chemical etching of any material can be considered as a sequence of three steps : ‘Transport of the reactant to the surface. Reaction at the surface. ‘Movement of reaction products into the volume of etchant solution. Anetch process which is limited by the rate of surface reaction will tend ieahanes surface roughness and promote faceting, since the surface seeeteiae,2 Strong function of localized defects and crystallograpbit rientation. peep Etching can be limited by the rate of diffusi a if the etchant through * ton moving layer which covers the surface 7 ‘yLSI Technology eras 3-9F C-Sem. ‘typically, a doubling of etch rate occure any any 4 Temperature. ate occurs with each 10° ‘Asa result, the development of ech processes 5 Gnvironment requires that attention be paid tee es man fe e : be paid to theee : to the choice of chemicals and their concentrates oi" addition The temperature-dependent characteristic ofc advantage in situations where its easental to hens gene ae? contamination toa minimum, seine 7, Here, the strategy isto use a high dilution with deionized water, maintain a reasonable etch rateby operating at an leva tempeh In other situations, where precise etch control is desire 8 oled etch solution is indicated. re 9. Anumberof chemical reagents, and their mixtures, are used for eehing purposes. 10, Many of these are available in transistor-grade” purity and are preferred in order to minimize contamination of the semiconductor during processing 11, Water is an intrinsic component of all of these reagents. Moreover, deionized water is invariably used as a diluent. rise in 1, Mixtures of nitric acid and hydrochloric acid (in a mixing ratio of 1:3 also called aqua regia) are able toetch gold at room temperature. 2, The very strong oxidative effect of this mixture stems from the formation of nitrosyl chloride (NOCD via HNO, +3 HCL—+ NOCI + 2.C1+2H,0, 3. While free Cl radicals formed in the solution keep the noble metal dissolved as Cl-complex (tetrachloro gold-(IIl)-acid = HAUCl,). HNO,/HCI mixtures are not stable and decompose accompanied by the formation of nitrogen oxides and C\,. 4, ‘The etch rate of aqua regia for gold is approx. 10 wm/min (at room temperature) and can be increased to several 10 ym/min at elevated temperatures. GueFS. | Explain semiconductor etching. Answer 1. Insemiconduetor etching, the primary oxidizing speciesis (OH)"-OR én. this is formed by the dissociation of water, which is present in t etchant, as given by H,0 = (OH)-+H* fl xr oxidation of the ‘The formation of an oxide presents a barrier to further oxida’ I semi-conductor, sothat itis necessary toad aditioal chemicels 1 dissolution into compounds or complexes, which are #0& Polysilicon Film Depositi S10F (BC-Sem-5) ee Lithography on 4) Stirring removes these from the semicondvetor surface so that furthep i oxidation can proceed. 44. The choice of complexing age! acids and bases ean be used, i OE ea is limited by the availability of high. 5 Inga ten yar malic contanatn «Ton tyra acids the invariable coe fr sion etching systema, Gav eystems often use aulfurie phosphoric, anditrie acid, or ammonium hydroxide GuedHT] What are PR materials ? What are the properties of ‘ARTU 2017-18, Marks 05] rts for this purpose is quite wide; both in addition to salts involving (CN, ) ang different PR? Gael AL PRmaterials: 1 The photorefractive (PR effet is a reversible photoinduced refractive sper change in materials combining photosensitivity, transport, and clectrooptical effects 2. The materials which exhibit photorefractive effect are known as photorefractive (PR) materials. Properties of photorefractive (PR) materials : 1. Large effective nonlinearity : One of the main features of photorefractive materials is the larg effective nonlinearity with inherent Sptical real-time information processing properties using all three dimensions in space. 2 Large nonlinear response : i PRmaterials have a large nonlinear response at low intensities in the nillivatt range. ji The response time of the materials varies from microseconds for semiconductor materials to seconds for some electro-optic crystals, & Beam-coupling effect : ‘An important property of a number of photorefractive erystals is the beam-coupling effect-a transfer of energy between two coherently intersecting beams inside the crystal. 4. Thisuniqur property ofnonecpreal energy transfer has ed to number of application in the general context of image processing. PART-2 Dielectric and Polysilicon Film Depositic iti ; ition : Deposition Processes of Plysilicon, Silicon Diowide, Silicon Nitride. vist Technology a a So ‘Long Answer Type and Medi ae = S11 F BC-Sem.5) ‘GEEGAU.| Explain in detail about the deposition process reactions 1 ioe | ‘The choice of a particular reaction is often determined by the deposition Toe creature, th lm properties, and artinengecreeas eorlton ‘The most common reactions for depositing silicon dioxide for VLSI circuits are oxidizing silane, SiH, with oxygen at 400 to 450°C decomposing tetraethoxysilane, Si(OC,H,),, at 650 to 750°C and reacting dichlorosilane, SiCl,H,, with nitrous oxide at 850 to 900°C. ‘Doped oxides are prepared by adding a dopant to the deposition reaction. ‘The hydrides-arsine, phosphine, or diborane are often used because they are readily available gases; however, halides or organic compounds such as phosphorus tribromide or trimethylphosphite can also be used. Silicon nitride is prepared by reacting silane and ammonia at atmospheric pressure at 700 to 900°C, or by reacting dichlorosilane and ammonia at enced presuret 700°C Plasma-deposited silicon nitride is deposited by reacting silane with ‘ammonia or nitrogen in a glow discharge between 200 and 350°C. ‘This reaction is useful for depositing passivation coatings over finished devices where higher temperatures cause unwanted reactions between Si+ 2H, SiH, + xN,O—> SiO, + 2H, #3% the reaction determines tl small amounts of nitrous he film ‘The quantity of nitrous oxide in composition and resistivity 3 silicon, eryeture containing erst amorphous silicon, silicon dioxide, and silicon moFEC-Sem-5) Lithography & Polyilicon Film Depositoy sa ms) —_ therapy PO" ston ec stion depends on the deposition temperature, thy amount of nitrous oxide, : a are of pnt-depostion anes 4 siPOS usd in VLSI ireuits contains between 25 and 40 at % oxygen Gur Fb | Discuss in about silicon dioxide ( er a dioxide films can be deposited with or without dopants. 2. Undoped silicon dioxide is used as an insulating layer between multilevel smetaltizations, an ion-implantation or diffusion mask, a capping layer ‘ver doped regions to prevent outdiffusion during heat eyeles, and to increase the thickness of thermally grown oxides. ‘8. Phosphorus-doped silicon dioxide is used as an insulator between metal layers, asa final passivation over devices, and as a gettering source 4. Oxides doped with phosphorus, arsenic, o boron are used occasionally as diffusion sources, 5, The processing sequence for silicon dioxide depends onits specific use in the device. 6. Oxides used as insulators between conducting layers are deposited, densified by annealing, and etched to open windows. A solution containing fluoride ora CHF; plasma etches the oxide. Phosphorus-doped oxides, used in the flowed glass process, are heated toa temperature between 950 and 1100°C so that the oxide softens and flows, providing a smooth topography which improves the step coverage of the next metallization. Phosphorus-doped oxides used for passivation are deposited at temperatures lower than 400 °C, and areas for bonding are opened by Que 847] Explain the deposition methods of silicon dioxide. Answer 1. Several deposition methods are characterized by diffe temperatures, ‘The chemie ne chemical reaction for phosphorus doped oxides are Sill +0,—+ Sio, + 2, Unter noma ith, 2P,0,+6H, ler normal deposi wae Tapa ion conditions, hydrogen is formed rather than nce, The dees ‘carried out at atmospheric pressure in & ) are used to produce silicon dioxide. They. rent chemical reactions, reactors and sehnology om ——__BtF ase sjieon dioxide deposits at temperature near gog Stesureby reacting diesoroaane with nteouyooge SiCI,H, +2N,0— 80, +2N, + 210) ion gives excellent uniformit ‘This deposition svts formity andi used to deposit layers over polysilicon, however, this oxide frequently contains oS tmounts of chlorine that may react withthe poleiicon anderen racking. eause sare formed by adding small Doped oxides are f ing small amounts of the dopant h 6. Pevng the deposition. Because the dopant hydrides are voor tans ee Gopant compounds are often used, Dopant halides or organic compounds are safer than hydrides but ess 7 ccavenient beeause they must usualy be vapourzed from solid or iqul sources. ‘Gussie What are the properties of SiO, ? ‘Answer Properties of SiO, are: i. Composition : SiO, deposited at low temperatures contains hydrogen. ‘This hydrogen is bonded within the silicon-orygen network as silanol (SiOH), hydride (SiH) or water (H,0). ‘Thickness : Film thickness is measured by a stylus instrument, reflectance spectroscopy, ellipsometry, or a prism coupler, Automated instruments suitable for routine use are available for all these techniques. While all four techniques are generally suitable for measuring silicon dioxide films, each has specific limitations. . Structure : Deposited silicon dioxide has an amorphous structure consisting of SiO,. Its structure is similar to that of fused silica. ‘Cand ata reduced iv, Reactivity : SiO, deposited at low temperature reacts with atmospheric moisture, especially ifthe oxide contains phosphorus. The phosphorus oxygen double bond undergoes a reversible hydrolysis, ¥. Refractive index and stress : The refractive index of SiO, is 1488 at @ wavelength of 0.6328 um. Stress in SiO, depends on deposition temperature, deposition rate, annealing treatments, dopant concentration, water content and film porosity ‘ Silicon nitride used : ; Silicon nitride (Si,N,) is used for passivating si P Sfesion of water serves as an extremely good barrier tothe diffusion of w= icon devices because it and sodium.Lithography &Poysiicon Film Deposition $-16F (EC-Sem-5) > ce impurtin cave devin metaization to correde oF devices to 2 These ome unstable. mn iE ro de is alo used as ask th lective oxidation of silicon, 3 a cin nitride oxidizes slowly and prevents the underlying silicon from oxidizing 5. Thos proces of eeective oxidation produces nearly planar devieg structures. 6 Siliconnitride is chemically deposited by reacting silane and ammonia at preazure at temperature between 700 and 900°C or semaspherc Prowonlane and ammonin at reduced pressure i {Smperatures between 700 and 800°C. The chemical reactions are 3SiH, +4NH,—> SigN, + 12H, 3SiC1,H, + 4NH,—> SigN, + 6HC1+ 6H, ‘The reduced-pressure technique has the advantage of good uniformity ‘and high wafer throughput. & Thermal growth of silicon nitride by exposing silicon to ammonia at temperatures between 1000 and 1100 °C has been investigated, but the resulting films contain oxygen and are very thin (< 10 mm. B. Deposition variables : L. Silicon nitride depositions at reduced pressure are controlled by temperature, total pressure, reactant concentrations, and temperature ‘gradients in the furnace. 2 The temperature dependence of the deposition rate is similar to that of polysilicon. 3. The activation energy for the silicon nitride deposition is about 1.8 eV (41 kealmole. 4. The deposition rate increases with increasing total pressure or dichlorosilane partial pressure, and decreases with an increasing ammonia to dichlorosilane ratio 5. Atemperature ramp, with the furnace tube hotter at the exhaust end, is required for uniform depositions. _Y ERY IMPORTANT QUESTIONS | Following questions are very important, These questions may be asked in your SESSION; /ALS as well as ks UNIVERSITY EXAMINATION. QL. Explain lith BOE Ree. 31 aehY With neat schematic diagram. vist Technology _ ——____ M17 Fec-8em.5) . Explain proximity printi @ Poppare these two e 4 Projection printing and gum Refer Q.3.2. 3, Explain the kinetics of wet etching, How Se Refer Q 37 a Q.4. What are PR materials ? What are the properties of different PR? sree wax Refer Q.3.9. Q.5. Explain the structure of polysilicon. gu. Refer Q. 3.12. Q.6. Discuss in about silicon dioxide (Si0,). au. Refer Q. 3.16. Q.7. How is the silicon nitride used ? Explain its deposition variables. mx, Refer Q. 3.19. O80Diffusion & Ion-Implantation ee CONTENTS 4 Diffusion : Models of Diffosion in Solids, Fick’s 1-Dimensional Diffusion Equation Part-t 4.2F to 4-6F Part-2. + Diffusion of Impurities in 4-6F to 410F Silicon and Sieon Diese, Diffsion Equations, Diffusion Profiles | Parts + Dittsion Furnace, Solid, Liguid.... 10F to 4-198 | and Gaseous Sources [Part + tonmpantatin [ Too-Implantation 4-1SF to 4-20F ‘Technique, Range Theory, Implantation Equipment 41 F(EC-Sem.5) perecsems) Diffusion and lon-tmplantation nae PART-1 Diffusion : Models of Diffusion in Solids, i im Dimensional Difusion Eguatign, We Questions-Answers : ‘ | Tong Answer Type and Medium Answer Type Questions GEEAM Discuss diffusion, Find diffusion constant for: Interstitial diffusion i, Substitutional diffusion ARTO 2015-16, Marks 75 ‘Answer Diffusion : 1. Diffusion is a relat'vely straightforward process by which impurities may be introduced into selected regions of a semiconductor, for the purpose of altering ts electronic properties. Both single and multiple diffusion steps can be used for this purpose. Diffusion describes the process by which atoms move ina erystal lattice. In silicon technology, diffusion allows the formation of Sources and drain for metal-oxide-semiconductor (MOS) devices. ‘The active reg bipolar transistors. Its extensively used because it is ideally adapted to batch processes where many slices are handled in a single operation. Interstitial diffusion : Itinvolves impurity jumps via interstitial voids. ‘These voids are arranged tetrahedrally in the zinc-blende lattice. Although same are occupied by point defects, their equilibrium concentration is low, even at normal diffusion temperature (100- 1100° C). Bach tetrahedral void ean readily accommodate an interstitial atom. However, there is an energy barrier which must be surmounted in order for interstitially located impurity atoms to jump from one void to the next. This barrier for interstitial diffusers is periodic in nature, as shown in Fig. 4.1.1 jump frequeney, v, is the frequency with w! Avctuations occur with sufficiently large magnitu Potential barrier, Let, E T= Pereee per hich thermal energy ide to overcome this migration, in eV tivation energy ofimpurity ‘emperature of the lattice, in K43F EC Sem sol vast Tecan ___—— 108-1006 etree rth nbich atoms strike the potential bar, r ‘his w depicted in Fig. 41. gy distribution the probability thet atoy B,, i given by Pn (Ady ic 1 2 3 4 ° 8. Thdiffusivity ofan interstitial impurity is given by, 9, Substituting eq 4.1.2) into eq. (4.1.1) then we get, D=D, ens? where Dis the diffusivity, pis the diffusion constant, and £,, is the activation energy of diffusion. i, Substitutional Diffusion : 1. The jumping of substitutional diffusers requires first that there be available vacant sites into which they can move. 2. These vacant sites are Schottky defect, with energy of formation given E,(=26 eV for silicon), 3. Thus the atoms fraction of such defects in a crystal is e“#/*". The charge state of these defects, which is related to the impurity concentratioo, ‘must also be included inthe calculation of diffusivity. 1 ml barrier asciatd with impurity migration by this proses than the probe iy of stoms having thermal eneray in excessol cena lues for E,, range from 0,6 to 1.2.eV- that each jue san nghas four tetrahedrally situated neighbours * inone of four different ways. Oe AV, eH hit = AV, e-neEour -Sem-5) AF BC-Sem Diffusion and fon-Implantation 5 entation Values ofE, +E, (=E,), predicted from this sim 6. Walvgptly Target than those actully cheered, 0% 8 foundto his is because the binding energy between an impurity a 1. Mighboring atom is less then that between two adjacent meen Inte The diffusivity for a substitutional impurity is thus p= Sf ease = Dye-Fakt we] Explain Fick’s law of diffusion, ” oR, jve the diffusion equation. How the depth of diffusion is contrelled ering diffusion process ? Give the solution of Fick's Law. ‘ARTO 201718, Marks 10] Fick's law of diffusion : 1. Fick assumed that in a dilute liquid or gaseous solution, in the absence of convection, the transfer of solute atoms per unit area in a one- dimensional flow can be described by the following equation, 2C(x,) = DoS wl4.2.1) x where, J is the rate of transfer of solute per unit area or the diffusion flux, Cis the concentration of solute, xis the coordinate axis in the direction of the solute flow, tis the diffusion time, and Dis the diffusivity or diffusion constant. 2, Eq, (4.2.1) states that the local rate of ranaer Coca a feat solute i r ‘ime is | rrtior patration radon othe sulted defines the proportionality contan’ he diffusivity of the solute. 3. The negative sign on the right-hand side of ‘matter flows in the direction of decreasing $0 gradient is negative). Eq, (4.2.1) is called Fick's first law of diffusion - From the law of conservation of matter, the change of rae concentration with time must be the same asthe Toe desreaie diffusion flux, in the absence of a source oF & f eg, (4.2.1) states that the Jute concentration ie.,the sink.£-5F (BC-Sem. OS vist Tectnology _ ais!) fs (4.29) i ting on (421)itn 0g (42.2) sie Fick's second law of diffag it 6 ne dimensional 2m, ‘son 2005) = 2 [pee 425) a tthe solute is low, the diffusivity at a giv Sed as aconstant, and eq. (4.2.3) becomes, When the concentration temperature can be consid (424) Ba, 24s often referred to as Fick's second law of diffusion ae Raag] What is Fikes law of diffusion ? Boron is diffused into an netype single crystal substrate with doping concentration of ao ee eae me diffusion time is 1 br, surface concentration oc 10! em and depth of junction is 2 um, determine diffusivity, ‘ARTU 2015-16, Marks 08] ‘Answer | A. Fiek’s law of diffusion : Refer Q. 4.2, Page 4~4F, Unit-4, B. Numerical: Given :x=2x10-* m=2x10"4em,t™=1 hr = 3600 see 6,=10%em-? To Find: Diffusivity. 1. The diffusion equation is, Ci, t= oe. vai ‘By setting x = 9 we obtain the surface concentration & = 10% em-# Dt ‘here Qi the total impurity in atomsfem?, C= ent C, = C10, 0 4% 3600 D. 10") exp | 10 36 10% 1015 -Sem-5) Diffusion an ppc sen ____Dilwionsnd oo plain ae dose is 10" atomslem? — Sassred : and the j red ‘jurface concentration of 1 = iilien 1D = 2.3 10-8 atomslem?, x= ” (jen D = 23% 1 fe 210° = 10°, N10 tong 1, We know. Nu, 0= Ny on(-25) a 4Dt 1x 10= x10") eng 20880 1 )= 10 1.0869 « 10* E5077 75788 =28 mins PAR’ Diffusion of Impurities in Silicon and Silicon Dioxide, Diffusion Equations, Diffusion Profiles Questions-Answers Long Answer Type and Medium Answer Type Questions ‘Que 4.5:"| Describe the impurity behaviour in silicon. ie 1 The movement of impurities belonging to table is caused by a combination of sul interstitialey diffusion. Their motion is thus strongly influenced by the concentration an charge state of lattice point defects. "ofthe periodic group I and V of the pes Ibstitutional diffusion and theSTP ECS, — i) . - ) vist Technol 9 smpurities aluminium, DOrOD,galigg ji ,e p-type inPee impurities antimony, ar 4. They include th Fhe n-type impurities antimony, raenie st indium, 28 We ars -titially in silicon belongs to group, 7 which Inpusitis : odie table : ie be etl such as ithium, potassium and sod, 5. Theseincl — lium and hydrogen. ttn Stes naion and are usually electri, 6 Theyaeeu inactive i ition elements diffuse by interstitial-substitu 7. Most transition Gin both types of sites. _— ‘mechanism and ond types — ‘Tre diweiation ofthe substitationalintoan interstitial anda vag, {sthe mechanism involved in most eases ‘Toe kick out mechanism defines the diffusional movement of gold yg platinum in silicon. TEAR bopein about ehe deopIving impurities, Aoswer | Deep-lying impurities can be described as follows : se a ‘These impurities usually diffuse by an interstitial-substitutions| mechanism, at about five to six orders of magnitude faster than substitutional diffusers. 2 Asa result, considerable error ean occur ftom out-diffusion effects when the specimens are cooled to room temperature. 4. Attempts at rapid quenching usually result in the generation of alae ‘number of erystal defects and obscure the interpretation of data. i. Their movement is described by a diffusivity which is a function ofboth conentationand temperature. : 1 On freezing, s active and en -lying impurities end up in both electronically ly inactive st ‘ a Widely from come atv sites The fractions ofeach type cits 2 Thus about 90 5 of cor the gold reside: ctive sites, while the nrepmning figure foraickel sonly 1d ee 3. The analysis of rity oe complex, since analytical techniques su cletronically active OMY Provide information on the part th seconda ‘in information onthe ent a” 888 sPectrometry techniques eso" impurity content, content, Diffusion and to re Dionne ronal active part ofl teas dan . meee ‘Thus their average diffusion mace one o more 400? 16° py p-n junction techniques, as for sagem? cannot be measures * 88 for substitutional dopants ¥ ion energy between an interstitial 4, The iMotrain field associated with adilocation sn neighborhood ofthis dislocation, iffusion pr dominated by th us the diffusion process is the dec ature of 2 Tata, and the experimental data are dificult tg a Seaninefully adition, many of these impurities form compounds with : oa ‘certain ranges of diffusion temperature, silicon ese tend to sogregate in clusters in the silicon lattice and are often + Meetronically inactive. Material doped with these impurities is usually sensitive to heat treatments, =| Describe the term diffusion equation with the help of diagram. substitutional di ends tofsvor dserng 5 Fick's second law may be derived by applying considerations of continuity 2 Consider the flow of particles in a crystal of cross section A, between planes P, and P, separated by dx, as shown in Fig. 3.2. 3, The rate of accumulation of particles in the region between planes is an A (2) dx 4. This can also be written as the difference between the fluxes flowing into and out of the region. 1 : Fig. 4.7.1. Diffusing Mus, The lax entering the region at Ps Aj and the fx At P, is AG + di). The net flux entering the region * Hence, Jeaving the region thus -Adi+9 eC VISI Technology FECSem aM aea-ad oe a 6 Butdj= ide de. Hence, av 8(pal) a £02) (42g 7. Eq. (4.7.2) involves only measurable quantities such a5 volun, concentration, diffusion depth and diffusion time. GRETA] Detine shoot resistance. Describe a method fori measurement. ‘ARTY 2015-16, Marks) Anetta. A. Sheet resistance: 1. Theresistance of a uniform structure of width w, thickness t, and length Lisgiven by L Re 05g) 484) where pis resistivity of the material in Q em, In integrated circuits, the diffusion lines are normally uniform ia thickness, therefore, we ean absorb ¢ into resistivity pand define a new variable p, called sheet resistance, which has dimensions of Ohm (0) Thus, eq. (4.8.1) becomes 1 R= o_O (482) where / = w, the structure becomes square with R = p, 4. Thus sheet resistance ofa layer is the resistance measured between the opposite sides ofa square ofthat layer, regardless ofits actual dimensions Hence p, is often express as /a (Ohm per squre) B. Method: 1, Inmierocircuit fabrication, the sheet resistance ofa diffused layer cat be directly measured if it is made in the patterned shape shown in Fig. 4.8.1 2 Here, as shown for a p-channel MOS transistor, a p-tyPt source/drain diffusion is made into an n-type substrate. 3. Aconstant current is applied across the points AB, and the voltage developed across CD is read with the aid of a high-impedance voltmet= With reference to Fig. 4.8.1 vw 7 4 Fig, 4.8.1. Source/drain resstanie tet patter, since Wi direc found PART-3 /is known for a specific test pattern, the sheet resistance is ‘The diffusion furnace itself is a major source ofimpurty entaminaten- Commercial diffusion tubes, made of fused quartz, are typically 96-97 % pure, thus they must be cleaned upon installation, and slso regularly during service. ‘Typically this is accomplished by flowing anhydrous anon an gas through them for 15-30 min at diffusion temperatures. This toleach out impurities waich are removed by conversion Volatile halides. The firebricks and heater element source of alta ion and copper contamination totheir nore in adiffusion furnace are 2 maine yuctor slices, there In addition, since they are hotter than the semicon’ 6 l " ‘of these impuriti isa thermal gradient which assists the \ranaren® o he quart walls into the diffusion tube, ky rapid movement thro The use of a high- jh-density mullite liner ‘a high-purity, high-density rr of alumina and zirconia) is common practice aS er to the transport of alkali ions. fof mistures his serves 86 ##11F EC-Sem,5) A ust Teele” otis usually accomplished vwsrteol ———— tofTis usually accomplished by moving te, his type are expecially important 10S based fabric, puree re on of the furnace 'nethe dopant source to § ners ypeare contamination critically afectg ye Spl Ft technique depend: roc aby ave devices. i suceees oF tis eechnugue Sepends crically onthe vapor prearun re ners cn alo be sed, and will lock, + gee soHfe® i ; 1 lew i i rer ie ses, his cess a Wo.empertire urna, why ce ower aha ‘expensive than mullite liners, they hayy siderably 072 & Although considerably re Fyrnace-associated contamination jt however, the source boat and the slices can be maintained se at potential for reducing often, ee var efor systems 6, ORame temperature, avoiding the need for atwosane furnace ted incorporation of heavy metallic impurities (such as iro, Discuss gaseous and liquid diffusion systems. 8 eral ete) results inafallin minority earrer lifetime, andin gy doers inthe leakage current in p-n junctions. (ARTO DOT6-17 Warkao) ‘Thustheirremovalisimportant for bipolar as well as field effect devices, One approach here is to use dopant sources which are halogenie compounds. = 111. With these the halogen is liberated during diffusion, and reacts with * Gaseous 1, Gaseous 80 aay metalic impurities in the incoming gas, as well as with impurit ‘rth the semiconductor that reach its surface during their rapid again, itis common practice to use an excess dopant gas concentration, these systeme are relatively insensitive to the gasflow rate source diffusion system wurces are even more convenient than the liquid ones. movement at high temperatures. sothat 12, This reaction converts them totheir more volatile halides, which leave Fig. 4.11.1 shows the schematic for a typical diffusion system using « the system by incorporation into the gas stream. gaseous dopant source, 18, The use of a halogenie dopant source thus effectively getters the 4 Here provision is made foran ambient carrier gas in which the difusion semiconductor. takes place 11 These sources must be used with eare, however, since excessive use __§,_Inaddltion, a chemical trap is often incorporated to dispose of unreacted can result in local dissolution of the semiconductor and cause its pitting. dopant gases, which are often highly dangerous. 6 All vapor transport methods rely on the fact that the surface Write a short n ji iffusi ‘Qetid] short note on solid source diffusion system. concentration of the incorporated dopant is solid-solubility-limited. so aowes,_| that itis relatively insensitive to the vapor pressure of the reactant 1 Fig.4.10.1 shows a sketct it oe Pe. {l0dshowsa shethotthedifsionsystemin which a platinum 7. Sil, massive depletion ofthe source reactant is possible i als ‘a solid source of t thecarrer wth the semicondoci taopane sPecies upstream From down the diffusion Lube Slices on 2 In operation, the carrier gas tre deposits them on the semicondl ecie tes po from this source and carrier Platinum Slices on fy ~ quart diffusion Valves and flow meters Valves and flow oe To vent : nts ta \™ vent fs Carrier ©} Chemical trap mene. ome Gaseous souree diusion syste413 F (Ei 'CSem.s) ist Technology EEC Sem) on occurs during transport ofthe reactant yj tional depleti Semen ; a Thus its ficult to maintain doping uniformity over ll the ging + entia difusion run, and even over the surface area ofeach indivi slice. these problems are exacerbated with the present trend to " ee these Pimeters, and the use of a large nutaber of slices in aw rum which necessitates close spacing’s between individual slices, B. Liquid-Source diffusion system : 1 Liquid source systems are extremely convenient since the doping «can be readily initiated (or terminated) by control ofthe gas through ti, bubbler. 2 Inaddition, the amount of dopant transported to the slices is relative ‘easy to control in these systems, by adjustment of the bubbler temperature. 3. Finally, anumber of halogenic dopant compounds are available as liquids, 4. Use of these sources greatly reduces heavy metal contamination in diffusion systems. Slices on ae eS Valves and Quartz Yalvesand —— gitsin tbe Liquid source ‘Temperature controlied bath Fig. 4.11.2: Liquid-eouree diffusion eyetem. , [Part-4 | on-Implantation ; ion-Implantation Technioue, Range Theor Implantation Equipment. : »m-5) Diffusi parece fusion and lon-Implantation wel Explain ion-implantation and mention it advantages sl 8 advant over diffusion: AKTU 2015-16, Marks 05 ing ion-implantation, dopant atoms are vaporized, acelera 1. Brected atasilicon substrate. lerated, and ‘They enter the crystal lattice, collide with silicon atoms, and gradually Jose energy, finally coming to rest at somedepth within the lattice. 4, Theaverage depth canbe controlled by adjusting the acceleration ney. |. The dopant dose can be controlled by monitoring the ion current during implantation. 5, The principle side effect-disruption of the silicon lattice caused by the ion collisions -is removed by subsequent heat treatments. 6 Jon-implantation therefore satisfies the conditions for a generally useful doping process. 1, Implantation energies range from 1 keV to 1 MeV, resulting in ion distributions with average depths ranging from 100 A to 10 um. B. Advantages : 1. Short process times, good homogeneity and reproducibility ofthe profiles. 2 Exact control of the amount of implanted ions by measuring the current 3. Relatively low temperatures during the process. 4 Various materials can be used for masking, ¢., oxide, nitride, and resist. 5. Implantation through thin layers,e.g.,SiQzis possible. 6 Low penetration depth of the implanted ions. Que LIS. | expiain the basic working principle of ion implantst® Process with all necessary equations. Compare between the diffusios spare between Oe ARTO 2017-18, Marks 10 and ion-implantation process. Jon-implantation ; Refer @. 4.12, Page +!visi Tecnology 3B, Comparison :___— Se ncanbe defiedea | Ton-implantati “anbe definedas the| Ion-implantation ig : jit of impurities inside a| temperature process yey los] change the chemical ang er to) | enatans properties of materials» fp Bren torial to iedoneat high temperatures. | Tt done at low temperature, 3, [Amount of dopant cannot be controlled. ‘Comparatively less expensive. Amount of dopant controlled. More expensive becauseit specificequipment, can 4 ——] ena] Discuss about the ion sources with one example, 1 on sources usually consis of i Compounds ofthe desired species, and ii Ameans for their ionization prior to delivery to the accelerator columns, 2, Thechoice of materials for ion sourcesis very wide, almost any ionizable compound can be used here. Gaseous materials are more convenient to use than solid ones, since they avoid the necessity of using a vaporization chamber, and can be replenished without opening the system. 4 Ionization ofthe source material is usually done by passing the vapor through a hot cathode electronic discharge. Cold cathode and r.. discharges are also used in some machines. 5. Electrons are accelerated towards an anode which is typically at 100V. ‘A magnetic field is provided so as to force the electrons to move ina spiral trajectory, thus increasing the ionizing efficiency of the source. 6 Also provided is a means for extracti itive i ing the positive ions from this discharge by means of an anode biased at 15-20 kV. 7. Asaconsequence, the output ofa source of this type consists of ios at an energy of 15-20 keV, 8 The outlet of the ionizer of the ionizer is either circular or in the form of & 3 ae and defines the geometry of the ion beam. 4.14.1 shows a cf the features day eae rofagasfed ion source and illustrates many » Fig. 4.14.1. A Nielien-type gascous soit, effectiveness of an ion source is measured by the 10. ot delivered to the accelerator, and: ultimately tothe ten” ifisthe ion current in amperes) for species feharge as hen 3 Mperate at which ions arrive atthe targets ile per ator 7? where q is the electronic charge in coulombs, Thus a singly ionized beam delivers 6.25 « 10" Tions/sto the target. Finally, if is the target area in cm, and tis the implantation time io seconds, the ion dose is given by 2 B 2,625 210° snsen? Alarge beam current is thus highly desirable in commercial systems ‘where many wafers must be handled with a minimum of machine time, Gaedas. | Explain the details about mass separation. “inewer 1. The use of mass separation techniques provides a unique distinction between ion-implantation and diffusion, in that a variety of dopants ‘can be handled in a single machine, with complete freedom from contamination with each other. 2 The most commonly employed technique utilizes magnetic analyzer. 5. Its principle is based on the dynamics of cbarged and velocity v, moving at right angles to a uniform magns aflux density B. 4. These particles will experience a force F such that F=qu xB) i audiver Thereby re 5. This tends to move them ina circular path of fe and oppose centrifugal force mv*/r. These forces must u sa homogeneous-feld rls ofmassm rn etic field withvisi Technology isrel i Tn addition, the velocity ofthe particles is related to theireney,, ATP ECG, lL 8) ‘ a Luts 4 a 2 . 48g where Vis the: accelerating | potential. 7. Combining eq-' (4.15.1) and (4.15.2), the radius of the ion Path is, Fire s uy aS riven extraction volt and magnetic flux der 8 Tas fr a Bt Cy proportional othe oars root fhe ae a, Mapotres fr thre diferent masses are shown in Fg. 4161 10, Fromthis, itis seen that ions of any particular mass can be seectjy the appropriate placement of an exit slit. Ion beam Fig. 4.13.1, Mass separation through a slit. Que 4.16. | How the range is distributed in ion-implantation ? Answer 1. Each implanted ion has a random path as it moves through the target, losing energy by nuclear and electronic stopping, 2 Since each implantation dose contains more than 10° ions/em? their average behaviour can be well predicted. 3, The average total path length in silicon is called the range R, andis comiposed of a mixture of vertical and lateral motion. ‘The average depth of the ‘implanted ions is called the projected range, A, and the distribution of ions about that depth can be approximated as Gaussian with standard deviation. Oy, 5. The lateral motion of the ions to a le 3s standard deviation a, rages iveioeen Fig. 4.16.1, Far from a and write the ion concer sstribution witb The ion ranges is shown schematically in the mask edge, we can neglect the lateral moti tration n(x) as nlx) = ngexp | aie- RF a] (4.16) 5) pr ecSem9) _Dilftsioo os plantation esa thenintepraiges aie ion joseis 4, then integrating eq, (4.16 1) «. 7 ete concentration m a 16:0 Gve0us an expreanon for the (4.16.2) poral, an arbitrary distribution n(x) can be characterized vents. The normalized first momen gfe 7zedin terms nt ofan ion distri Ce orange. ion distribution ig For convenience, higher moments are usually taken about R 8 ie m= +f" G-Ry =e 2) n(x (4.163) second, third, and fourth moments are typically expresedin terms 9 the following parameters Im, (Skewness) y = 7 (4.165) (Kurtosis) p= (4.166) Vacuum Y Semiconductor | Y t Ton beam mel Za . ! Figi416.1. The total path longth R is long? than the projected range, 10. Qualitatively, skewness measures the asymmetry of te distribution ~ Positive skewness places the peak of the distribution closer to the surface than R,, 1. Kurtosis measures how flat the top of a distribution is. Gaussian distributions have a skewness of 0 and a kurtosis of 3. 12 Incases where the kurtosis is not available, a universal expression is often used, (418. P=28+247 e167 Deserihe basic layout of implantation equipment. =VLSI Technology +19F EO-Sem,5 4 | ‘The basic requirement for an ion-implantation system is beam of ions ofa particular type and energy to the surfa, wafer. {0 deliver eof a siet ig. 4.17.1 shows a schematic view of a medium-energy ion im, Following the ion path, we begin on the left-hand side with ¢ voltage enclosure containing many of the system components ‘gas soure feed a small quantity of source gas such as Bint the source where a heated filament causes the molecules to breakup en charged fragments. This ion plasma contains the desired ion togethe species from other fragments and contamination. An extraction voltage, around 20 kV, causes th out ofthe ion source into the analyzer ‘The pressure in the remainder of the machine is key minimize ion scattering by gas molecules. ‘The magnetic field ofthe analyzer is chosen such that only ions with the desired charge to mass ratio can travel through without being blocket by the analyzer walls, Surviving ions continue to the acceleration tube, where they are accelerated to the implantation energy as they move from high voltage to ground, Plante, the high, fer with many othe, e charged ions to moyy pt below 10 Torry Acceleration Analyzer tube magnet, Y sean plates Xsean plates Wafer (target Position) Resolving on Source Beam line & so ly cada supply source _ diffusion pumps Fig. dtr, 10. The wafer is offset slightly from: the ion tube so that ions neutralied dures re ts of tho acoleration vb ‘vel, will not be deflected onto the wafer =, is required to repair lattice damage 1 Aeitutional sites where they will be electrically acti ime success of annealing is often measured ne jopant that is electrically active, as fo fuleffect technique. ‘The Hall effect measures an average effective do in terms of the fraction of C und experimentally using png, which san integral a over Jocal doping densities and local mobilities evaluated per unit of surface area. = [Pn where pis the mobility, nis the number of carriers, and 438, ‘the junction depth. Ifthe mobility is not a strong function of depth. Nj... measures the total ‘number of electrically active dopant atoms. Ifannealing activates all ofthe implanted atoms, this wll be equal to the dose ©. For VLSI, the challenge in annealing isnot simply to repair damage and activate dopant, which any long, high-temperature anneal will achieve, but to do while minimizing diffusion so that shallow implants remain shallow. ‘Thishas motivated much recent work in rapid thermal annealing (RTA), Where annealing times are on the order of seconds. a . VERY IMPORTANT QUESTIONS tions: questions are very important. These ques! ‘may be asked in your SESSIONALS as well as UNIVERSITY EXAMINATION. ———— Ee 1. Discuss diffusion. Find diffusion constant for: