MTD5P06V

Preferred Device

Power MOSFET
5 Amps, 60 Volts P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge http://onsemi.com
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage V(BR)DSS RDS(on) TYP ID MAX
transients. 60 V 340 mW 5.0 A

Features
• Avalanche Energy Specified P−Channel
• IDSS and VDS(on) Specified at Elevated Temperature D
• Pb−Free Packages are Available

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

G
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 60 Vdc
S
Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 60 Vdc
Gate−to−Source Voltage
− Continuous VGS ± 15 Vdc MARKING
− Non−repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk DIAGRAM
Drain Current − Continuous @ 25°C ID 5 Adc 4
− Continuous @ 100°C ID 4 Drain
− Single Pulse (tp ≤ 10 ms) IDM 18 Apk 4

Total Power Dissipation @ 25°C PD 40 W

P06VG
DPAK

YWW
Derate above 25°C 0.27 W/°C 1 2 CASE 369C
Total Power Dissipation @ TA = 25°C (Note 2) 2.1 W 3 STYLE 2

5
Operating and Storage Temperature Range TJ, Tstg −55 to °C
175 2
1 3
Drain
Single Pulse Drain−to−Source Avalanche EAS 125 mJ Gate Source
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 5 Apk, L = 10 mH, RG = 25 W)
Y = Year
Thermal Resistance °C/W WW = Work Week
Junction−to−Case RqJC 3.75 5P06V = Device Code
Junction−to−Ambient (Note 1) RqJA 100 G = Pb−Free Package
Junction−to−Ambient (Note 2) RqJA 71.4
Maximum Lead Temperature for Soldering TL 260 °C
Purposes, 1/8″ from Case for 10 seconds ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum Device Package Shipping †
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
MTD5P06V DPAK 75 Units/Rail
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended MTD5P06VT4 DPAK 2500/Tape & Reel
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size. MTD5P06VT4G DPAK 2500/Tape & Reel
(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

Preferred devices are recommended choices for future use

and best overall value.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

July, 2006 − Rev. 6 MTD5P06V/D
 MTD5P06V

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 − −
Temperature Coefficient (Positive) − 61.2 − mV/°C
Zero Gate Voltage Drain Current IDSS mAdc
(VDS = 60 Vdc, VGS = 0 Vdc) − − 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 100
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS − − 100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 250 mAdc) 2.0 2.8 4.0
Threshold Temperature Coefficient (Negative) − 4.7 − mV/°C
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) − 0.34 0.45 W
Drain−Source On−Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 5 Adc) − − 2.7
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C) − − 2.6
Forward Transconductance gFS Mhos
(VDS = 15 Vdc, ID = 2.5 Adc) 1.5 3.6 −

DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 367 510 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, Coss − 140 200
f = 1.0 MHz)
Transfer Capacitance Crss − 29 60
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(on) − 11 20 ns
Rise Time (VDD = 30 Vdc, ID = 5 Adc, tr − 26 50
Turn−Off Delay Time VGS = 10 Vdc, RG = 9.1 W) td(off) − 17 30
Fall Time tf − 19 40
Gate Charge QT − 12 20 nC
(See Figure 8)
Q1 − 3.0 −
(VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc)
Q2 − 5.0 −
Q3 − 5.0 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage VSD Vdc
(IS = 5 Adc, VGS = 0 Vdc)
− 1.72 3.5
(IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C)
− 1.34 −
Reverse Recovery Time trr − 97 − ns

(IS = 5 Adc, VGS = 0 Vdc, ta − 73 −

dIS/dt = 100 A/ms) tb − 24 −
Reverse Recovery Stored Charge QRR − 0.42 − mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD nH
(Measured from the drain lead 0.25″ from package to center of die) − 4.5 −
Internal Source Inductance LS nH
(Measured from the source lead 0.25″ from package to source bond pad) − 7.5 −

3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperature.

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 MTD5P06V

TYPICAL ELECTRICAL CHARACTERISTICS

10 10
VGS = 10V 8V VDS ≥ 10 V TJ = −55°C
9V 7V 9
25°C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

8 TJ = 25°C 8 100°C
7
6V
6 6
5
4 4
3
5V
2 2
4V 1
0 0
0 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.6 0.4
VGS = 10 V TJ = 25°C
0.55
TJ = 100°C VGS = 10 V
0.5 0.35

0.45

0.4 0.3 15 V
25°C
0.35

0.3 0.25

0.25 − 55°C

0.2 0.2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage

1.8 100
R DS(on) , DRAIN−TO−SOURCE RESISTANCE

VGS = 10 V VGS = 0 V
1.6 ID = 2.5 A

1.4
I DSS , LEAKAGE (nA)
(NORMALIZED)

1.2

1 10 TJ = 125°C

0.8

0.6

0.4

0.2 1
−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−To−Source Leakage

Temperature Current versus Voltage

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 MTD5P06V

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on−state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load;
voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1000
VDS = 0 V TJ = 25°C
900 Ciss
800
C, CAPACITANCE (pF)

700
600 Crss
500
400 Ciss

300 Coss
200
100 Crss
VGS = 0 V
0
10 5 0 5 10 15 20 25
VGS VDS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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 MTD5P06V

10 60 100
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS TJ = 25°C
9 QT 54
ID = 5 A
8 48 VDD = 30 V
7 Q2 42 VGS = 10 V tr
Q1

t, TIME (ns)
6 td(off)
36
tf
5 30 10 td(on)
4 24
3 18
2 Q3 TJ = 25°C 12
1 VDS ID = 5 A 6
0 0 1
0 2 4 6 8 10 12 14 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

5
4.5 TJ = 25°C
VGS = 0 V
4
IS , SOURCE CURRENT (AMPS)

3.5
3
2.5
2
1.5
1
0.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the reliable operation, the stored energy from circuit inductance
maximum simultaneous drain−to−source voltage and drain dissipated in the transistor while in avalanche must be less
current that a transistor can handle safely when it is forward than the rated limit and adjusted for operating conditions
biased. Curves are based upon maximum peak junction differing from those specified. Although industry practice is
temperature and a case temperature (TC) of 25°C. Peak to rate in terms of energy, avalanche energy capability is not
repetitive pulsed power limits are determined by using the a constant. The energy rating decreases non−linearly with an
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance−General temperature.
Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 ms. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum
exceed (TJ(MAX) − TC)/(RqJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated E−FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 MTD5P06V

SAFE OPERATING AREA

100 140
VGS = 20 V ID = 5 A

EAS, SINGLE PULSE DRAIN−TO−SOURCE

SINGLE PULSE
120
I D , DRAIN CURRENT (AMPS)

TC = 25°C

AVALANCHE ENERGY (mJ)

100
10
80
100 ms
60
1 ms
1 10 ms 40
RDS(on) LIMIT dc
THERMAL LIMIT 20
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
0.1 P(pk)
RqJC(t) = r(t) RqJC
0.05
D CURVES APPLY FOR POWER
0.02 PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) RqJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 MTD5P06V

PACKAGE DIMENSIONS

DPAK
CASE 369C−01
ISSUE O

NOTES:
−T− SEATING
PLANE 1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
B C 2. CONTROLLING DIMENSION: INCH.

V R E INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
4
C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.018 0.023 0.46 0.58
S F 0.037 0.045 0.94 1.14
1 2 3
U G 0.180 BSC 4.58 BSC
K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
F L 0.090 BSC 2.29 BSC
J
R 0.180 0.215 4.57 5.45
L H S 0.025 0.040 0.63 1.01
U 0.020 −−− 0.51 −−−
D 2 PL V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
G 0.13 (0.005) M T STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

SOLDERING FOOTPRINT*

6.20 3.0
0.244 0.118
2.58
0.101

5.80 1.6 6.172

0.228 0.063 0.243

SCALE 3:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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