1) 

  How many clock pulses are confined by each machine cycle of Peripheral-Interface
Controllers?

a. 4
b. 8
c. 12
d. 16

ANSWER: (a) 4

2)   Which flags are more likely to get affected in status registers by Arithmetic and Logical
Unit (ALU) of PIC 16 CXX on the basis of instructions execution?

a. Carry (C) Flags

b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above

ANSWER: (d) All of the above

3)   What is the execution speed of instructions in PIC especially while operating at the
maximum value of clock rate?

a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs

ANSWER: (b) 0.2 μs

4)   Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?

a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above

ANSWER:  (b)Brown-out reset

5)   Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman
architecture?

a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above

ANSWER: (d) All of the above

6)   Which among the below specified major functionalities is/are associated with the
programmable timers of PIC?

a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs

a. Only C
b. C & D
c. A, B & D
d. A, B & C

ANSWER: (d) A, B & C

7)   Which timer/s possess an ability to prevent an endless loop hanging condition of PIC
along with its own on-chip RC oscillator by contributing to its reliable operation?

a. Power-Up Timer (PWRT)

b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above

ANSWER: (c) Watchdog Timer (WDT)

8)   Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?

a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)

ANSWER: (b) Program Counter Latch (PCLATH) Register

9)   Which register/s is/are mandatory to get loaded at the beginning before loading or
transferring the contents to corresponding destination registers?

a. W
b. INDF
c. PCL
d. All of the above
ANSWER: (a) W

10)   How many RPO status bits are required for the selection of two register banks?

a. 1
b. 2
c. 8
d. 16

ANSWER: (a) 1

11)   The RPO status register bit has the potential to determine the effective address
of______

a. Direct Addressing Mode

b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode

ANSWER: (a) Direct Addressing Mode

12)   Which status bits exhibit carry from lower 4 bits during 8-bit addition and are
especially beneficial for BCD addition?

a. Carry bit (C)

b. Digits Carry bit (DC)
c. Both a & b
d. None of the above

ANSWER: (b) Digits Carry bit (DC)

13)   Which statement is precise in relation to FSR, INDF and indirect addressing mode?

a. Address byte must be written in FSR before executing INDF instruction in indirect addressing
mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing
mode
c. Address byte must be written in FSR at the same time during the execution of INDF
instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect
addressing mode

a. Only A
b. Only B
c. Only A & B
d. A & D

ANSWER: (a) Only A

14)   Which among the below stated registers specify the address reachability within 7 bits
of address independent of RP0 status bit register?

a. PCL
b. FSR
c. INTCON
d. All of the above

ANSWER: (d) All of the above

15)   Where do the contents of PCLATH get transferred in the higher location of program
counter while writing in PCL (Program Counter Latch)?

a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit

ANSWER: (c) 13th bit

16)   Which condition/s of MCLR (master clear) pin allow to reset the PIC?

a. High
b. Low
c. Moderate
d. All of the above

ANSWER:(b)  Low

17)   Generation of Power-on-reset pulse can occur only after __________

a. the detection of increment in VDD from 1.5 V to 2.1 V

b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor

ANSWER:  (a) the detection of increment in VDD from 1.5 V to 2.1 V

18)   What is the rate of power up delay provided by an oscillator start-up timer while
operating at XT, LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles

ANSWER: (b) 1024 cycles

19)   Which kind of mode is favourable for MCLR pin for indulging in reset operations?

a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode

ANSWER: (b) Sleep mode

20)   What is the purpose of using the start-up timers in an oscillator circuit of PIC?

a. For ensuring the inception and stabilization of an oscillator in a proper manner

b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers

ANSWER: (a) For ensuring the inception and stabilization of an oscillator in a proper
manner

21)   Which program location is allocated to the program counter by the reset function in
Power-on-Reset (POR) action modes?

a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations

ANSWER: (a) Initial address

22)   When does it become very essential to use the external RC components for the reset
circuits?

a. Only if initialization is necessary for RAM locations

b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly

ANSWER: (b) Only if VDD power-up slope is insufficient at a requisite level

23)   Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR)
feature?

a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71

a. A & B
b. C & D
c. A & C
d. B & D

ANSWER: (b) C & D

24)   Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be

completely unique and distinct from other microcontrollers?

a. It can reset the PIC automatically in running condition

b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above

ANSWER: (a) It can reset the PIC automatically in running condition

25)   What happens when the supply voltage falls below 4V during the power-up timer
delay of 72ms in PIC?

a. CPU resets PIC once again in BOR mode

b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again

ANSWER: (a) CPU resets PIC once again in BOR mode

26)   What output is generated by OSC2 pin in PIC oscillator comprising RC components

for sychronizing the peripherals with PIC microcontroller?

a. (1/2) x frequency of OSC1

b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1

ANSWER:(c)  (1/8) x frequency of OSC1

27)   Which form of clocking mechanism is highly efficient and reliable for crystal or
ceramic clock sources for operating at the range of 5- 200 kHz in PIC?

a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)

ANSWER: (b) LP (Low-Power Clocking)

28)   Which significant feature/s of crystal source contribute/s to its maximum predilection

and utility as compared to other clock sources?

a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above

ANSWER: (a) All of the above

29)   What is the executable frequency range of High speed (HS) clocking method by using
cystal/ ceramic/ resonator or any other external clock source?

a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz

ANSWER: (d) 4-20 MHz

30)   How many bits are required for addressing 2K & 4K program memories of PIC
16C61 respectively?

a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits

ANSWER: (c) 11 & 12 bits

31)   What location is attributed to ‘goto Mainline’ instruction in the program memory of

PIC 16C61?

a. 000H
b. 004H
c. 001H
d. 011H

ANSWER: (a) 000H

32)   When do the special address 004H get automatically loaded into the program counter?

a. After the execution of RESET action in program counter

b. After the execution of ‘goto Mainline ‘ instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value

ANSWER: (c) At the occurrence of interrupt into the program counter

33)   How many bits are utilized by the instruction of direct addressing mode in order to
address the register files in PIC?

a. 2
b. 5
c. 7
d. 8

ANSWER:(c) 7

34)   Which registers are adopted by CPU and peripheral modules so as to control and
handle the operation of device inhibited in RFS?

a. General Purpose Register

b. Special Purpose Register
c. Special Function Registers
d. All of the above

ANSWER: (c) Special Function Registers

35)   Which among the below specified registors are addressable only from bank1 of RFS?

a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)

ANSWER: (a) PORTA (05H)

36)   Which register acts as an input-output control as well as data direction register for
PORTA in bank 2 of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)

ANSWER: (c) TRISA (85H)

37)   Which bank of RFS has a provision of addressing the status register?

a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2

ANSWER: (c) Either Bank 1 or Bank 2

38)   Which bit of OPTION register has a potential to decide the falling or rising edge
sensitivity for the external interrupt INT?

a. RBPU
b. INTEDG
c. PSA
d. RTS

ANSWER: (b) INTEDG

39)   Where are the prescalar assignments applied with a usage of PSA bit?

a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer

ANSWER: (c) Either RTCC or Watchdog timer

40)   Where is the exact specified location of an interrupt flag associated with analog-to-
digital converter?

a. INTCON
b. ADCON0
c. ADRES
d. PCLATH

ANSWER: (b) ADCON0

41)   Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an
INTCON register?

a. GIE
b. ADIE
c. RBIE
d. TOIE

ANSWER: (a) GIE

42)   When does it become possible for a bit to get accessed from bank ‘0’ in the direct
addressing mode of PICs?

a. Only when RPO bit is set ‘zero’

b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict

ANSWER: (a) Only when RPO bit is set ‘zero’

43)   When does it become feasible for portB pins (RB4 to RB7) to support its unique
feature of ‘interrupt on change’?

a. By configuring all the pins (RB4-RB7) as inputs

b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs

ANSWER: (a) By configuring all the pins (RB4-RB7) as inputs

44)   Which digital operations are performed over the detected mismatch outputs with an
intention to generate a single output RB port change output?

a. OR
b. AND
c. EX-OR
d. NAND

ANSWER: (a) OR

45)   What is the purpose of acquiring two different bits from INTCON register for
performing any interrupt operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above

ANSWER: (b) One for enabling the interrupt & one for its occurrence detection

46)   Which among the below specified combination of interrupts belong to the category of
the PIC 16C61 / 71?

a. External, Timer/Counter & serial Port Interrupts

b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts

ANSWER: (c) External, Timer 0 & Port B Interrupts

47)   Which condition results in setting the GIE bit of INTCON automatically?

a. Execution of retfie instruction at the beginning of ISR

b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit

ANSWER: (b) Execution of retfie instruction at the end of ISR

48)   What kind of external edge-sensitive interrupt is generated due to transition effect at

pin RBO/INT?

a. INT
b. RBO
c. INTF
d. All of the above

ANSWER:(a)  INT

49)   Which bit-register pair plays a significant role in configuring the rising or falling edge
triggering levels in external interrupts of PIC 16C61/71?

a. INTF bit – INTCON register

b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register

ANSWER: (b) INTEDG bit – OPTION register

50)   Consider the following statements. Which of them is /are incorrect?

a. By enabling INTE bit of an external interrupt can wake up the processor before entering into
sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.

a. A & B
b. C & D
c. Only A
d. Only C

ANSWER: (b) C & D

51)   What is the purpose of setting TOIE bit in INTCON along with GIE bit?

a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
d. None of the above

ANSWER: (a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow
interrupt

52)   Where do the conversion interrupt flag (ADIF) end after an accomplishment of

analog-to-digital (ADC) conversion process?

a. INTCON
b. ADCON0
c. OPTION
d. None of the above

ANSWER: (b) ADCON0

53)   How much time is required for conversion per channel if PIC 16C71 possesses four
analog channels, each comprising of 8-bits?

a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs

ANSWER: (c) 20 μs
54)   How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’
of PIC 16C61?

a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles

ANSWER: (a) 2-cycles

55)   Which command enables the PIC to enter into the power down mode during the
operation of watchdog timer (WDT)?

a. SLEEP
b. RESET
c. STATUS
d. CLR

ANSWER: (a) SLEEP

56)   Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ &
‘0’ respectively in ADC Status Register?

a. AIN0
b. AIN1
c. AIN2
d. AIN3

ANSWER: (c) AIN2

57)   Which bit is mandatory to get initiated or set for executing the process of analog to
digital conversion in ADCON0?

a. ADIF
b. ADON
c. Go/!Done
d. ADSC1

ANSWER: (c) Go/!Done

58)   What would be the value of ADC clock source, if both the ADC clock bits are selected
to be ‘1’?

a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC

ANSWER: (d) FRC

59)   The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated
by __________

a. PCFG1 & PCG0

b. VREF
c. ADON
d. All of the above

ANSWER: (a) PCFG1 & PCG0

60)   Which among the below mentioned aspect issues are supported by

capture/compare/PWM modules corresponding to time in PIC 16F877?

a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above

ANSWER: (d) All of the above

61)   Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of
rising/falling edge detection?

a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode

ANSWER: (a) Capture Mode

62)   What among the below specified functions is related to PWM mode?

a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned
frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge

ANSWER: (b) Generation of rectangular wave with programmable duty cycle with an user
assigned frequency
63)   What happens when the program control enters the Interrupt Service Subroutine
(ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of CCP1
Module in capture mode?

a. CCP1F bit gets cleared in PIR1 by detecting new capture event

b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR

ANSWER: (a) CCP1F bit gets cleared in PIR1 by detecting new capture event

64)   Which register is suitable for the corresponding count, if the measurement of pulse
width is less than 65,535 μs along with the frequency of 4 MHz?

a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register

ANSWER: (c) 16-bit register

65)   The capture operation in counter mode is feasible when mode of CCP module is
_________

a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization

ANSWER: (a)  synchronized

66)   What is the fundamental role exhibited by the CCP module in compare mode in
addition to timer 1?

a. To vary the pin status in accordance to the precisely controlled time

b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels

ANSWER: (a) To vary the pin status in accordance to the precisely controlled time

67)   How does the pin RC2/CCP1 get configured while initializing the CCP module in the
compare mode of operation?

a. As an input by writing it in TRISC register

b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization

ANSWER: (b) As an output by writing it in TRISC register

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