i nt = mbination: ire |The following sequences of bits (right-mos bit first) appear on the inputs toa T4LSK3A (Abit pple cary adder), Determine the resulting sequence of bits on each output AO 1001 Bo olin Al 1110 BI 1100 A2 0000 B2 1010 a3 Lott Bs 0010 2. The below figure shows the circuit ofa 4-bit carry: ‘delays ofthe circuit elements are given in Table below. udder. The worst-case propagation [=> a ral sol 2, sn} sont tHe atom | atm | ath mm] ats om copfon cat Slow cmp © conf ae on SG Device Path Delay i. Determine the worst-case propagation delays to ‘Alene [Mae et = Se iol C2A from PO and from C-1., epee TET aan iy why CZA aed CO ae etal MO Tain par = ewrpat | 2 ‘except for propagation delays. on_[rop=snps| 2] i, Decne ti wort ae propagation delays to MB _Tevkpt ete x C2B from PO and from C-1. Given the following i comprising a 3x8 decoder with negated outputs and a 2x4 ‘decoder with normal outputs, what isthe Boolean function for G in terms of A,B,C. How ‘do you label intermediate outputs Yo and Y1?4. Given the following cieuit comprising a 2:4 decoder with normal outputs and one enable, ‘what isthe simplified SOP expression of Boolean function H in terms of A,B&C? ‘5 Implement the following function using 2:4 decoder with active high enable & active HIGH output and only one logic gate ¥ = F(A,B,C,D) = ¥m(@,t1) ‘6 Implement a circuit for a 10:4 encoder (with Do to Dy as the inputs and Yo to Ys as the ‘outputs, Y3 being MSB) with 4 no. of OR gates as shown in the below block. The inputs for OR gates ean be anything from Do to Ds. If gate G2 is faulty (stuck-at- 0) then, which inputs will be effected? », D, >. D, >. D, >» >, > >, 7. A priority encoder is an encoder circuit with priority. If 2 or more inputs are equal to 1, the input withthe highest priority will take precedence. The truth table of a4-input priority encoder is shown below. An output V is added which is set tol when one or more inputs ‘are equal to 1; otherwise V is O. The two outputs x and y are not inspected when V equals 0 and hence they are specified as don't care outputs. Note that whercas x's in output ccolumns represent don't care outputs, the x's in the input columns are useful for representing a truth table in compact form. For example, input X100 represents the 2 input combinations: 0100 and 1100. Derive the simplified SOP expressions for X,Y and V, and draw the logic diagram.8 Implement a) flwl,w2,w3) = Y(0,1,2,3,4,5,7) using 3-8 decoder and OR gate. by fiw, w2,w3) = Sm(0 45,6) using 3-8 decoder and AND gate 6) f(a,b,c) = B +c using 4-8 decoder and OR gate 9. Resigned at last to be banned from the island, you now, tum your attention to American dol, where the judges are in dire need of some digital Assistance to resolve issues concerning which contestant should be allowed to remain in the vocal competition. Afier watching the program for several hundred hours, you determine the following “vote encoding”. (Note that pairs of like votes appear to cancel cach other). Y |Z | Contestant Paula | Simon| Stays Yer slzlslz\z]z\z Of course the above table doesn’t make sense, but neither do most of the judges on the show! 2) In an interesting twist, you are asked to implement this circuit using only 2 input XOR ‘gates (74X86 chips), a breadboard, some wires, some SPST switches, an LED, resistors and a power supply. +) Implement the above design using multiplexer. ©) Finally compare and contrast the logic cireuit realization. Which would be easier to build? Which would use the fewest parts/wires? Which would be easier to modify? 10, Show, how to make an 8:1 MUX using 2 no, of 4:1 MUX & I no. of 2:1 MUX. 11. Show, how to make an 8:1 MUX using I no, of 4:1 MUX & 4 no, of 2:1 MUX. 12, Show, how to make an 8:1 MUX using 2.no, of 4:1 MUX & 2 no, of tristate buffers. 13. Show, how to make an 8:1 MUX using 3:8 decoder and tristate buffers. 14, Show, how to make an 8:1 MUX using a 3:8 decoder and few logic gates. 15, Show, how to use an 8:1 MUX to make a 4:1 MUX. 16, Design a 6:1 multiplexer using 2:1 multiplexer. 17. Simplify f(a,b.4) = Ym(2.4,5,6,10) + D(12,13,14,15) and implement the SOP expression using 4:1 MUX,18, Design a circuit that can shift a4 bit vector W = w3w2w1w0 1 bit position to right when ‘a control signal Shift is equal to 1. Let the output of circuit be 4 bit vector Y= y3y2yly0 and a signal k such that if S then y3 = el and k= w0, if Shift = 0 Y = W and k =. 19, Implement a circuit with control inputs (S2.i,$:), 4 data inputs (Ds,D:,D1,Dv where Ds being MSB) and 4 outputs (Vs, ¥2,¥1, Yowhere Ys being MSB). Use only 8:1 Muxes for the implementation. The functionality is described in the below table. 31s [s Operation ‘Shift Right and pad with 1 0 1 | 0 | Shit Lehand pad with O Oa [a | Shi La and pc with 3 +e] e Rotate Right te Pass twee | salem) Pee through 20. Implement the following functions using i) 2:1 MUX and NOT gates ii) 4:1 MUX a) F(A,B,C) = AC+BE D)F(P.Q.R) = PR+OR+PQ 21. Implement the functionality ofa full adder using 2:1 Muxes only. 22, Implement the functionality of 1:8 Demux using 2 no, of 2:4 decoders with enable inputs and few other logic gates (maximum of 3 gates). 23. Implement AND gate & OR gate using the below shown X type gate (No such gate exists practically) whose output is P’Q when P & Q are its inputs. e— PQ a— 24, Find a minimum three level NOR gate circuit to realize F F(A,B,C,D) = ¥-m(1,2,4,5,6,10,12,14) 25, Find a minimum three level NAND gate circuit to realize F F(A,B,C,D) = Ym(2,46,8,10,11,12,14,15) 26.16 bit ripple carry adder is realized using 16 identical full adders (FA). The carry propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 1S ns. Find the worst case delay of this 16 bit adder