Lab Workbook Introduction to Clock Constraints

Introduction to Clock Constraints

2018.3

Abstract
This lab reviews the process of creating and generating clocks.
This lab supports both Verilog and VHDL design files. However, the lab instructions and graphics
are limited to Verilog usage.
This lab should take approximately 25 minutes.

Objectives
After completing this lab, you will be able to:
 Create clocks by using the Timing Constraints window
 Associate jitter specification to a created clock
 Generate a clock report (report_clock)
 Implement the design

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Lab Workbook Introduction to Clock Constraints

Introduction
The wave_gen design used in this lab is a programmable waveform generator.

Figure 7-1: wave_gen Design Block Diagram

This design records specific information via RS-232 serial communication and stores this data in
memory. After data has been stored, it can be retrieved via the RS-232 communications channel,
or played out via a bank of LEDs or a DAC. The wave_gen design implements the RS-232 com-
munication channel, the waveform generator and connection to the external DAC, and a simple
parser to implement a small number of "commands" to control the waveform generation.
This lab will show you how to create clocks and generate clock constraints using the Timing
Constraint window. You will use report_clocks to understand the clocks that are used in the de-
sign. This lab will also review the process of generating and reading static timing analysis re-
ports.
The diagram below shows the systematic approach recommended for applying timing con-
straints and incrementally progressing towards closure. There are three broad stages in the Per-
formance Baselining procedure recommended by Xilinx, which enables the designer to achieve
timing closure progressively.
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Lab Workbook Introduction to Clock Constraints

 This lab will focus on optimizing internal paths (Baseline) as explained in the below figure:
 Define all primary clocks and generated clocks. Check for the clocks in the design (pe-
riod, edge relationships).
 Specify asynchronous (unrelated) clock groups: All clocks are assumed to be related to
each other unless otherwise specified. The phases between any two clocks are derived
from their individual clock definitions; timing paths between such clock domains are ana-
lyzed using these derived requirements. To avoid this redundant timing analysis and re-
porting of timing failure, asynchronous clock groups need to be specified. When there
are such asynchronous inter-clock paths specified, the design must use appropriate syn-
chronization techniques to capture data reliably at the target clock domain.
Note: Specifying asynchronous clocks step is covered in "Applying Clock Groups Constraints"
topic.
 With a complete clock definition as above, all FPGA internal paths (single-cycle paths)
can be analyzed for timing. The feasibility of closing timing for the single-cycle internal
paths can be assessed with reasonable confidence. 

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Introduction to Clock Constraints Lab Workbook

Figure 7-2: Focus in this Lab

General Flow
Step 3:
Step 1: Step 2: Step 4: Step 5:
Creating the
Opening Generating Creating a Implement-
Clock &
the a Clock Generated ing the
Specifying
Project Report Clock Design
Jitter

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Lab Workbook Introduction to Clock Constraints

Opening the wave_gen.xpr Project Step 1

The first step is to open the wave_gen.xpr project in the Vivado® IDE and then
open the synthesized design database to launch the Timing Constraints window.

2-1. [Linux users]: Launch VirtualBox from the Start menu and start the
Ubuntu_VM virtual machine.

3-2. [Linux users]: Copy the files from the shared Windows folder to your
training directory using the following Linux command.
[host]$ source /media/sf_training/setup_TopicCluster.sh Clk-
Constr_Intro
If you do not recall how to perform these tasks, refer to the "Board, OS, COM,
and IP Address Tasks" section in the Lab Reference Guide.

There are a number of ways to launch the Vivado Design Suite. The two most
popular mechanisms are shown here.

4-3. This can be done in two standard ways, use your preferred method.
5-4-1. [Windows 7 users]: Select Start > All Programs > Xilinx Design Tools > Vivado
2018.3 > Vivado 2018.3.

Figure 7-3: Launching the Vivado Design Suite from the Start Menu

[Windows 10 users]: Select Start > Xilinx Design Tools > Vivado 2018.3.

You can also double-click the Vivado Design Suite shortcut icon ( ) from the Win-
dows desktop.

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Introduction to Clock Constraints Lab Workbook

[Linux users]: Press <Ctrl + Alt + T> to open a new terminal window, type vivado, and
press <Enter> to launch the Vivado Design Suite environment.
The Vivado Design Suite opens to the Welcome window. From the Welcome window you
can create a new project, open an existing project, or enter Tcl commands directly into
the Vivado Design Suite as well as access documentation and examples.

Figure 7-4: Vivado Design Suite Welcome Screen

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Lab Workbook Introduction to Clock Constraints

6-5. Open the existing Vivado Design Suite project wave_gen.xpr.

7-6-2. Click Open Project from the Quick Start section (1).
The Open Project dialog box opens (2).
8-7-3. [Windows users]: Browse to the C:\training\ClkConstr_Intro\lab\[KCU105 | KC7xx]\
verilog directory in the Look in field (3).
[Linux users]: Browse to the /home/xilinx/training/ClkConstr_Intro/lab/
[KCU105 | KC7xx]/verilog directory in the Look in field (3).
Note: The drop-down arrow shows the directory hierarchy.
9-8-4. Select wave_gen.xpr (4).

Figure 7-5: Opening an Existing Project

10-9-5. Click OK to open the selected project (5).

The project now opens in the Vivado Design Suite.

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11-10. Examine the provided XDC file.

12-11-6. Expand Constraints (1) > constrs_1 in the Hierarchy tab of the Sources view.
13-12-7. Double-click wave_gen_timing.xdc to open it in the text editor.

Question 1
Are there are any constraints currently in the design?

14-13-8. Click X in the text editor window to close the opened XDC file.

15-14. Open the synthesized design.

16-15-9. Click Open Synthesized Design under Synthesis in the Flow Navigator.

Alternatively, you can select Flow > Open Synthesized Design.

Figure 7-6: Opening the Synthesized Design

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Lab Workbook Introduction to Clock Constraints

Generating a Clock Report Step 17

You will review the clock networks in the design to view the generated clocks
hierarchy and fanout of each clock defined in the design. All the clocks in the
design need to be identified through this step for applying clock constraints.

18-16. Generate a Clocks Networks report.

19-17-10. Click Report Clock Networks in the Flow Navigator under Synthesized Design.
Alternatively, you can select Reports > Timing > Report Clock Networks.
The Report Clock Networks dialog box opens.
20-18-11. Click OK.
Clock Networks report gives the network fanout of each clock net in the open design
and provides a hierarchical tree view of the clock network.

21-19. Review the Clock Networks report.

22-20-12. Expand the Unconstrained folder in the Clock Networks report.
None of the clocks in the design has been constrained at this time and all clocks appear
as Unconstrained. If there were already constrained clocks, they will appear outside the
Unconstrained group.
23-21-13. Expand clk_pin_p.
This will expand the clock network tree up to mmcm(e3)_adv_inst.
24-22-14. Click the Maximize icon in the Clock Networks -network_1 window.
25-23-15. Follow the steps listed below to view a complete hierarchy of the clock network.
o KCU105 Verilog users:
 Expand mmcme3_adv_inst > CLKFBOUT > clkfbout_clk_core > CLKFBIN
 Expand mmcme3_adv_inst > CLK_OUT0 > clk_out1_clk_core > clk_out1
 Expand mmcme3_adv_inst > CLK_OUT1 > clk_out2_clk_core > clk_out2 >
BUFGCE > BUFGCE_clk_samp_i0 > clk_samp
o KC7xx Verilog users:
 Expand mmcm_adv_inst > CLKFBOUT > clkfbout_clk_core > CLKFBIN
 Expand mmcm_adv_inst > CLK_OUT0 > clk_out1_clk_core > clk_out1
 Expand mmcm_adv_inst > CLK_OUT1 > clk_out2_clk_core > clk_out2 >
BUFHCE > BUFHCE_clk_samp_i0 > clk_samp
26-24-16. Observe the fanout of the clkout1, clkout0, and clk clock objects.

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The Clock Networks window should look the figure below.

Figure 7-7: Clock Networks Report (KCU105, Verilog)

Note: For 7 series users, the graphic will be slightly different with respect to the MMCM
primitive name, clock buffer names, and fanouts.
27-25-17. Click the Restore icon in the Clock Networks -report_1 window.
28-26-18. Close the Clock Networks tab.

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Lab Workbook Introduction to Clock Constraints

Creating the Clock and Specifying Associated Jitter Step 29

The next thing is to define a clock object in the design. Now you will define
clk_pin_p as a clock object, associate jitter specification to the clock object, and
then use the report_clocks command to see all the clocks available in the
design.

30-27. Open the Timing Constraints window.

31-28-19. Select Window > Timing Constraints.
The Timing Constraints window can also be opened by clicking Edit Timing Constraints
under Synthesized Design in the Flow Navigator.
The Timing Constraints window opens in the main workspace area.

Figure 7-8: Timing Constraints Window in the Vivado IDE

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32-29. Launch the Create Clock dialog box.

33-30-20. Double-click Create Clock (0) in the Timing Constraints window.
The number in the parentheses represents the number of similar constraints in the de-
sign. In this case, this is zero because there are no objects defined as clock objects in the
design provided; i.e., there are zero create_clock constraints in the design.
The Create Clock dialog box opens.

Figure 7-9: Create Clock Dialog Box

34-31-21. Click Reference to read the command reference about the selected command,
i.e., create_clock.
35-32-22. Click Close in the Command Reference: create_clock dialog box.
36-33-23. Enter clk_pin_p in Clock name field.

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Lab Workbook Introduction to Clock Constraints

37-34. Associate the clock input port to the clock definition.

38-35-24. Click the icon next to the Source objects field.

The Specify Clock Source Objects dialog box opens.
39-36-25. Ensure that I/O Ports is selected from the Find names of type drop-down list.
40-37-26. Specify the search options as NAME CONTAINS clk_pin* to search clocks with
clk_pin in the name.
41-38-27. Click Find to initiate the search.
42-39-28. Select clk_pin_p from the Results > Found window.

43-40-29. Click the icon to add clk_pin_p to the Selected section.

Figure 7-10: Specify Clock Source Objects Dialog Box

44-41-30. Click Set.

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45-42. Describe the period property and review the waveform details of the clock
object.
46-43-31. Enter the period value in the Period field under the Waveform section in the
Create Clock dialog box.
KCU105 users: Enter 3.333 ns to specify a clock of 300 MHz.
KC7xx users: Enter 5.000 ns to specify a clock of 200 MHz.
47-44-32. Ensure that the Rise at field is set to '0' and Fall at field is set to half of the given
period to have 50% duty cycle.

Figure 7-11: Create Clock Dialog Box after Defining clk_pin_p Port as a Clock Object

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Lab Workbook Introduction to Clock Constraints

48-45-33. Click OK to create the clock.

After the clock is created, the Timing Constraints window should look like the figure be-
low.

Figure 7-12: Timing Constraints Window after Entering create_clock

Notice the create_clock XDC command for the created clock in the All Constraints
section of the Timing Constraints window.

49-46. Assume the clock is ideal and enter the clock input jitter information.
50-47-34. Double-click Clocks (1) > Set Input Jitter using the Timing Constraints window.
The Set Input Jitter Dialog box opens.
51-48-35. Enter 0 in the Input Jitter field assuming that the clock is ideal.
Note: 0 is the default value for jitter; therefore, this specification is redundant. It is shown
here for completeness.

52-49-36. Click the icon next to the Clock field.

Specify the Input Jitter Clock dialog box opens.

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53-50. Set the jitter for the defined clock object.

54-51-37. Note that Clocks is selected for the Find names of type option.
55-52-38. Accept the default settings for the Options field.
56-53-39. Click Find in the Specify the Input Jitter Clock window to initiate the search.
57-54-40. Select clk_pin_p from the Results > Found section.

58-55-41. Click the icon to add clk_pin_p to the selected names.

Figure 7-13: Specify the Clock for Input Jitter Dialog Box

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59-56-42. Click OK.

Figure 7-14: Set Input Jitter Dialog Box

60-57-43. Click OK in the Set Input Jitter dialog box.

61-58. Generate the clocks report.

62-59-44. Select Window > Tcl Console if the Tcl Console is not already selected (at the
bottom of the Vivado GUI).
63-60-45. Enter the following command using the Tcl Console:
report_clocks
Note: report_clocks lists only the clock constraints that have been specified for timing.
This command does not list all the clock nets. To find the clock nets in a design, use re-
port_clock_networks.
64-61-46. Click the Maximize icon in the Tcl Console window.

Figure 7-15: Reporting Clocks (KCU105)

Figure 7-16: Reporting Clocks (KC7xx)

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Question 2
In addition to clk_pin_p, there are three more clocks (CLKFBOUT, CLK_OUT2, and CLKOUT1) in
the report. Are these clocks expected?

65-62-47. Click the Restore icon in the Tcl Console window.

Creating a Generated Clock Step 66

In addition to primary clock objects, the clocks can be generated by a variety of
means such as, when a primary clock propagates to a cell like MMCM, PLL, it
generates new clocks, the user-derived clocks can be generated using clock
buffers, and non-clock resources like internal dividers.
The design provided has a clock (clk_samp) that is generated using a clock buffer
(BUFGCE for UltraScale devices and BUFHCE for 7 series devices). You will define
the clock generated by the clock buffer by using the Create Generated Clock
command. The timing engine in the Vivado Design Suite does not automatically
derive the timing for such manually gated clocks and it needs to be specified
(unlike MMCM output clocks). If it is not specified, the same clock constraint at
the input of the buffer will be applied to clk_samp (like an un-gated buffer).

67-63. Launch the Create Generated Clock dialog box and associate the clock name
as clk_samp.
68-64-48. Double-click Clocks (2) > Create Generated Clock in the Timing Constraints
Window.
The Create Generated Clock dialog box opens.
69-65-49. Enter clk_samp in the Clock name field.

70-66. Associate the master pin to clk_samp.

When you are specifying manually created clocks, the source is specified at the
input pin of the clock generating element. In this case, it would be the BUFGCE I
pin/BUFHCE I pin.

71-67-50. Click the icon next to the Master pin (source) field.
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The Specify Master Pin dialog box opens.

72-68-51. Ensure that Cell pins is selected from the Find names of type drop-down list.
73-69-52. Specify the search option as NAME CONTAINS BUF*CE_clk_samp_i0/* to search
for the pins of the clock buffer.
74-70-53. Enable the Search hierarchically option.
75-71-54. Click Find to initiate the search.
76-72-55. Select the input pin of the buffer from the Results > Found section.
KCU105 users: Select clk_gen_i0/BUFGCE_clk_samp_i0/I.
KC7xx users: Select clk_gen_i0/BUFHCE_clk_samp_i0/I.

77-73-56. Click the icon.

Figure 7-17: Specify Master Pin Dialog Box

78-74-57. Click OK.

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Introduction to Clock Constraints Lab Workbook

79-75. Specify clk_samp as a derived waveform with 1/32 frequency of the source
clock.
80-76-58. Select the By clock frequency option under the Derive from Source Clock
Waveform section, if it is not already selected.
81-77-59. Enter 32 as the division factor in the Divide source clock frequency by option.

82-78. Associate the source object to clk_samp.

83-79-60. Click the icon next to the Source objects field.

84-80-61. Ensure Cell Pins is selected from the Find names of type drop-down list.
85-81-62. Specify the search option as NAME CONTAINS BUF*CE_clk_samp_i0/* to search
for the pins of the clock buffer.
86-82-63. Click Find.
87-83-64. Select the output pin of the buffer from the Results > Found section.
KCU105 users: Select clk_gen_i0/BUFGCE_clk_samp_i0/O.
KC7xx users: Select clk_gen_i0/BUFHCE_clk_samp_i0/O.

88-84-65. Click the icon.

89-85-66. Click Set.

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Lab Workbook Introduction to Clock Constraints

90-86. Create a clk_samp object and review the generated clock properties.
The Create Generated Clock dialog box should look like the figure below after
completing the above steps.

Figure 7-18: Create Generated Clock Dialog Box

91-87-67. Click OK to create the generated clock in the design.

92-88-68. Enter the following in the Tcl Console to generate a clock report:
report_clocks
93-89-69. Click the Maximize icon in the Tcl Console window.

Figure 7-19: Clock Report after Generating clk_samp (KCU105)

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Introduction to Clock Constraints Lab Workbook

Question 3
Is the period of clk_samp what you expected? Why or why not?

94-90-70. Click the Restore icon in the Tcl Console window.

95-91. Save the constraints to the XDC file.

96-92-71. Select the Window > Sources tab.
97-93-72. Expand Constraints (1) > constrs_1 using the Hierarchy tab of the Sources view.
98-94-73. Double-click the wave_gen_timing.xdc file to open it in the Sources view.

Question 4
Are there constraints in the XDC file? If not, where are the constraints that you specified?

99-95-74. Close the wave_gen_timing.xdc window.

100-96-75. Select File > Constraints > Save.
101-97-76. Click OK if the Out of Date Design dialog box opens.
The Save Constraints File dialog box opens.
102-98-77. Ensure that the Select an Existing File option is selected.
Note that wave_gen_timing.xdc is the only XDC file in this project; hence, it was selected
by default.
103-99-78. Click OK.
104-100-79. Reopen the wave_gen_timing.xdc file.
Notice that the constraints are now written to the XDC file.

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Implementing the Design Step 105

In this step, you will implement the design and analyze the timing paths and its
properties.

106-101. Implement the design.

107-102-80. Click Run Implementation in the Flow Navigator (under Implementation).
Alternatively, you can select Flow > Run Implementation.

Figure 7-20: Selecting Run Implementation

Note: If needed, click OK to launch synthesis first if prompted.

Notice that the tools run all of the processes required to implement the design. This
means that if the synthesized netlist is not available already, the Vivado Design Suite will
run synthesis before running implementation.
After implementation completes, the Implementation Completed dialog box opens. The
dialog box prompts you to open the implemented design, generate the bitstream, or
view reports.
108-103-81. Click OK again to launch the selected runs.

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109-104-82. Select Open Implemented Design.

Figure 7-21: Implementation Completed Dialog Box

110-105-83. Click OK.

111-106-84. Click Yes if asked to close the Synthesized design before opening the
Implemented design.
Note that the timing for the design is not met since all the constraints are not applied at
this step.
112-107-85. Click OK to close the critical warning dialog box about timing constraints not
met.

113-108. Analyze the Timing Summary Report.

The Timing Summary Report will be open by default in the implemented de-
sign and run as a part of Implementation.
114-109-86. Select the first path in the clk_out1_clk_core under the Intra-Clock paths section
of the Timing Summary window.
Note: There may be timing errors in the setup paths.

Question 5
How many clock paths are constrained in this design?

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Question 6
Are these timing errors expected? Why or why not?

115-110-87. Press <F4> to create the schematic of the first timing path.
Note that the clock path is also visible, along with the data path in the schematic.

If the icon is not selected, the clock path is not shown in the schematic.

Figure 7-22: Schematic of the Timing Path (KCU105) - Example (Your Schematic May Differ)

Figure 7-23: Schematic of the Timing Path (KC7xx) - Example (Your Schematic May Differ)

The clock path and data path have been highlighted in the graphic for better under-
standing.
116-111-88. Double-click the selected path in the Timing Summary window to view the
detailed path report.

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117-112-89. Maximize or float the Path Report to look at the path details.

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Lab Workbook Introduction to Clock Constraints

Note: This is an example timing summary report. Your results may very depends on
which Vivado Design Suite version you are using.

Figure 7-24: Timing Path Report for First Path of clk_out1_clk_core (KCU105)

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Figure 7-25: Timing Path Report for First Path of clk_out1_clk_core (KC7xx)

Note: The timing may vary slightly in the above mentioned timing path reports.
The timing path report provides a detailed summary of the timing path covered by the
specific clock path group. When you click the links in the report, the logic objects are se-
lected in other views.
It provides the detailed information of the logic objects in the path and their associated
delays for the source clock path, data path, and the destination clock path. The details of
the timing path report are as follows.
o Summary: Provides brief information about the timing path and reports slack for the
timing path endpoints. The slack is the difference between the data required time
and the data arrival timing at the path endpoint.
o Source Clock Path: Provides the detailed information of the logic objects in the path
and their associated delays for the source clock path. This source clock path is the
path followed by the source clock from its source point to the clock pin of the
launching flip-flop.
o Data Path: Provides the detailed information of the logic objects in the path and
their associated delays for the internal circuitry, between the launching and capturing
flip-flops. The active clock pin of the launching flip-flop is called the path startpoint.
The data input pin of the capturing flip-flop is called the path endpoint.

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o Destination Clock Path: Provides the detailed information of the logic objects in the
path and their associated delays for the e destination clock path. The destination
clock path is the path followed by the destination clock from its source point,
typically an input port, to the clock pin of the capturing flip-flop.
118-113-90. Extract the information required for the table below.
Hint: Look in the Summary section of the path report.
119-114-91. Repeat the steps to extract information for the path covered by the
clk_out2_clk_core clock group. Make sure you choose the first path.
120-115-92. Examine the timing results. Verify the slowest paths for the two clock groups.

Question 7
Record and verify the startpoint, endpoint, slack, and data path delay of the slowest path for the
following clock groups.

Data Path
Clock Group Source Destination Slack
Delay

clk_out1_clk_core

clk_out2_clk_core

Static Timing Results

The timing analysis at this stage is only for the internal paths of the FPGA, and I/O timing
has not yet been specified for analysis. From the timing summary report, it can be seen
that only some clk_out1_clk_core domain paths under Intra-Clock Paths are failing as of
now. From the source and destination of these paths and an understanding of the
wave_gen design, it can be seen that these long paths are designed as multicycle paths.
You will apply multicycle paths in a later lab to close this timing.
121-116-93. Click the Restore icon or Dock icon in the window banner to restore the Path
Properties window.

122-117. Close the project.

123-118. Close the Vivado Design Suite.

Summary
Through this lab, you have learned how to use the Timing Constraints window to define clocks
in the design. You also learned how to view the clocks in the design by using the
report_clocks command from the Tcl Console and how to generate a timing report through
the GUI.

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Answers
Answers listed represent sample solutions only. Your results may differ depending on the ver-
sion of the software, service pack, or operating system that you are using.

1. Are there any constraints currently in the design?

There are no constraints in the design.

2. In addition to clk_pin_p, there are three more clocks (CLKFBOUT, CLK_OUT2, and CLKOUT1)
in the report. Are these clocks expected?

Yes, they are the MMCM generated clocks for which clock definitions have been
automatically derived.

3. Is the period of clk_samp what you expected? Why or why not?

The reported period of clk_samp is 165, which is expected. The period clk_samp is 32 times
to its source pin, which is nothing but CLKOUT2. The period of CLKOUT2 is 5.161. The
clk_samp reported period is (5.161*32).

4. Are there constraints in the XDC file? If not, where are the constraints that you specified?

There are no constraints in the wave_gen_timing.xdc file because all the constraints created
so far were saved in memory and they have not been saved to file. You need to save the
created constraints to the XDC file before closing the database.

5. How many clock paths are constrained in this design?

From the report_clock command you observed that there are five clocks in the design.
The clk_pin_p clocks and the clkfbout_clk_core clock do not have any timing paths
associated to them. Hence, the Vivado Design Suite has analyzed and generated timing
reports for all three clock paths. The Vivado Design Suite has also reported the timing paths
that are also not covered under these clock paths.

6. Are these timing errors expected? Why or why not?

The timing errors in the design can be expected because the design is not fully constrained. Cur-
rently, the design contains clocking constraints only. Input/output delay constraints, clock group
constraints, and timing exceptions constraints are yet to be specified.

7. Record and verify the startpoint, endpoint, slack, and data path delay for the slowest path for
the following Clock Groups.

Note that there might be differences in the timing values (and hence the timing paths)
based on the OS and Vivado Design Suite version used.

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It can be seen that only clk_out1_clk_core domain paths under the Intra-Clock Paths section
have negative slack.

KCU105 Users
Data Path
Constraint Source Destination Slack
Delay

char_fifo_i0/U0/
inst_fifo_gen/
gconvfifo.rf/gbi.bi/
v8_fifo.fblk/
cmd_parse_i0/
clk_out1_clk_core rst_val_sym.gextw_sym[1 0.336 ns 4.404 ns
send_resp_type_reg[0]/CE
].inst_extd/
gonep.inst_prim/
gf18e2_inst.sngfifo18e2/
WRCLK

clk_gen_i0/clk_div_i0/ clk_gen_i0/
clk_out2_clk_core 0.983 ns 3.187 ns
en_clk_samp_reg/C BUFGCE_clk_samp_i0/CE

Static Timing Results (KCU105)

KC7xx Users
Data Path
Constraint Source Destination Slack
Delay

cmd_parse_i0/
resp_gen_i0/to_bcd_i0/
clk_out1_clk_core send_resp_data_reg[11]/ -1.918 ns 6.791 ns
bcd_out_reg[6]/D
C

dac_spi_i0/
dac_spi_i0/
clk_out2_clk_core out_ddr_flop_spi_clk_i0/ 0.982 ns 1.141 ns
old_old_active_reg/C
ODDR_inst/D2

Static Timing Results (KC7xx)

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