Lab Workbook Introduction to Timing Exceptions

Introduction to Timing Exceptions

2018.3

Abstract
This lab guides you through creating timing exceptions, such as multicycle path and false path
constraints.
This lab should take approximately 45 minutes.

Objectives
After completing this lab, you will be able to:
 Specify multicycle path exceptions
 Specify false path exceptions
 Verify the timing reports to check that an implemented design has met timing

www.xilinx.com 1
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

Introduction
The wave_gen design used in this lab is a programmable waveform generator.

Figure 6-1: wave_gen Design Block Diagram

This design records specific information via the RS-232 serial communication and stores this
data in memory. After data has been stored, it can be retrieved via the RS-232 communications
channel, or played out via a bank of LEDs or a DAC. The wave_gen design implements the RS-
232 communication channel, the waveform generator and connection to the external DAC, and
a simple parser to implement a small number of "commands" to control the waveform genera-
tion.

www.xilinx.com 2
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

This lab starts with a design which does not meet the timing requirements. You will use the Tim-
ing Constraints window for entering timing exceptions in the XDC format and will also use tim-
ing reports for verifying the timing results. In the final stage of timing closure, you will apply
timing exceptions to make all the paths meet timing.

Figure 6-2: Focus in this Lab

www.xilinx.com 3
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

There is additional time required for processing data between the send_resp_data and bcd_out,
thus consuming more than one clock cycle. In this case, multicycle path exceptions can be ap-
plied with both setup and hold checks between the two cell domains.

Figure 6-3: Multicycle Paths

Later in this lab, you will also specify all paths originating from rst_pin as false paths, since they
are synchronized to each of the different clock domains in the design using an instantiation of
the reset_bridge module. This is done by specifying the false path constraints.

General Flow
Step 1: Step 2: Step 3: Step 4:
Opening Defining Defining Implement-
the Multicycle False ing the
Project Path Paths Design

Opening the wave_gen Project Step 1

In this step, you will open the project in the Vivado® IDE and then open the
implemented design database to launch the Timing Constraints window.

2-1. [Linux users]: Launch VirtualBox from the Start menu and start the
Ubuntu_VM virtual machine.

3-2. [Linux users]: Copy the files from the shared Windows folder to your
training directory using the following Linux command:
[host]$ source /media/sf_training/setup_TopicCluster.sh
TimingExceptions_Intro
If you do not recall how to perform these tasks, refer to the "Board, OS, COM,
and IP Address Tasks" section in the Lab Reference Guide.

4 www.xilinx.com
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

4-3. Launch the Vivado Design Suite.

If you do not recall how to perform this task, refer to the "Launching the Vivado
Design Suite" section under Vivado Design Suite Operations in the Lab Reference
Guide.

5-4. Open the Vivado Design Suite project named wave_gen.xpr located in the
directory below.
[Windows users]: Browse to the C:\training\TimingExceptions_Intro\lab\[KCU105
| KC7xx]\netlist directory.
[Linux users]: Browse to the /home/xilinx/training/
TimingExceptions_Intro/lab/[KCU105 | KC7xx]/netlist directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado De-
sign Suite Project" section under Vivado Design Suite Operations in the Lab Ref-
erence Guide.

6-5. Open the implemented design.

If you do not recall how to perform this task, refer to the "Opening the Imple-
mented Design" section under Vivado Design Suite Operations in the Lab Refer-
ence Guide.
7-6-1. Click OK to close the critical message about the design not meeting the timing
requirements.
8-7-2. Select the Edit Timing Constraints option available under Open Implemented Design.
The Timing Constraints window opens in the main workspace area.

Figure 6-4: Timing Constraints Window (KCU105)

www.xilinx.com 5
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

Question 1
What are the different timing constraints defined in this design?

9-8. Review the Design Timing Summary report.

10-9-3. Select the Timing tab at the bottom of the Vivado IDE to review the Design Timing
Summary.

Question 2
What are the constraints that need to be entered to fix the timing errors in the design?

Defining a Multicycle Path Step 11

The clock, input delay, and output delay constraints for the design have already
been specified in the constraints file. The next step is to specify the timing
exceptions in the design. You now will specify the path between
send_resp_data_reg and bcd_out_reg as a multicycle path with a setup
requirement of two clock cycles.

12-10. Define the multicycle path with a setup requirement of two clock cycles
using the Timing Constraints window.
13-11-4. Double-click Set Multicycle Path (0) under the Exceptions category in the Timing
Constraints window.
The Set Multicycle Path dialog box opens.
14-12-5. Select the Options tab.

6 www.xilinx.com
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

15-13-6. Enable the Use path multiplier for setup (maximum delay) calculation option under
the Setup/Hold section.

Figure 6-5: Options Tab in the Set Multicycle Path Dialog Box

16-14-7. Select the Targets tab.

www.xilinx.com 7
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

17-15. Specify the start points for the multicycle path definition.

18-16-8. Click the icon next to the From field in the Start Points section.
The Specify Start Points dialog box opens.
19-17-9. Select Cells from the Find names of type drop-down list (1).
20-18-10. Specify the search options as NAME CONTAINS
*cmd_parse_i0/send_resp_data_reg[*] (2).
21-19-11. Deselect the Search hierarchically option (3).
22-20-12. Click Find.

Figure 6-6: Specify Start Points Tab in the Set Multicycle Path Dialog Box

23-21-13. Click to select all elements from the Find results.

8 www.xilinx.com
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

24-22-14. Click Set.

25-23. Specify the end points for the multicycle path definition.

26-24-15. Click the icon next to the To field in the End Points section.
The Specify End Points dialog box opens.
27-25-16. Select Cells from the Find names of type drop-down list.
28-26-17. Specify the search options as NAME MATCHES
*resp_gen_i0/to_bcd_i0/bcd_out_reg[*].
29-27-18. Deselect the Search hierarchically option.
30-28-19. Click Find.

31-29-20. Click to select all elements from the Find results.

32-30-21. Click Set.

33-31. Complete the multicycle path definition with the setup time requirement.
Specify the number of clock cycles required from the setup requirement for
the multicycle path definition.
34-32-22. Enter 2 in the Specify path multiplier field.
The Set Multicycle Path dialog box (Targets tab) should look like the figure below.
Note the Tcl command at the bottom of the tab.

Figure 6-7: Targets Tab in the Set Multicycle Path Dialog Box
www.xilinx.com 9
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

35-33-23. Click OK in the Set Multicycle Path dialog box.

36-34. Define the multicycle path with a hold requirement of one clock cycle using
the Timing Constraints window.
Now that you have specified the setup requirements for the paths between
send_resp_data* and bcd_out_reg* by using the multicycle path definition,
you will specify the hold time requirement for the same path.
37-35-24. Using the Timing Constraints window, double-click Set Multicycle Path(1) under
the Exceptions category.
38-36-25. Select the Options tab.
39-37-26. Enable the Use path multiplier for hold (minimum delay) calculation option
under the Setup/Hold section.
40-38-27. Select the Targets tab.
If the Set Multicycle Path window does not open with recent data, repeat the steps you
completed in the "Specify the start points for the multicycle path definition" and "Specify
the end points for the multicycle path definition" above to select the start points and end
points.
41-39-28. Enter 1 in the Specify path multiplier field.
42-40-29. Click OK.

Defining False Paths Step 43

rst_pin had been specified as a system-synchronous input with the clk_pin_p
clock, because of which timing analysis is performing recovery/removal analysis
on the flip-flops receiving rst_pin as a CLR/PRE input. The rst_pin input can be
safely considered asynchronous to the design since it is synchronized to each of
the different clock domains in the design using an instantiation of the
reset_bridge module. As a result, the paths from the rst_pin input are false paths.
In this step, you will define all the paths originating from the rst_pin port as false
paths.

44-41. Define the paths starting from rst_pin as false paths.

45-42-30. Double-click Set False Path(0) under the Exceptions category in the Timing
Constraints window.

46-43-31. Click the icon next to the From field in the Start Points section.
The Specify Start Points dialog box opens.

10 www.xilinx.com
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

47-44-32. Select I/O ports from the Find names of type field.
48-45-33. Specify the search options as NAME CONTAINS r*.
49-46-34. Click Find.
50-47-35. Select rst_pin in the Find results section.

51-48-36. Click .
52-49-37. Click Set.
The Set False Path dialog box should look the figure below.
Note the corresponding Tcl command.

Figure 6-8: Set False Path Dialog Box

53-50-38. Click OK.

www.xilinx.com 11
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

The application of this false path should fix the timing failures seen under **asynch_de-
fault**.

Implementing the Design Step 54

55-51. Save the constraints to the XDC file.

All the constraints created so far were saved just in memory, so the created
constraints need to be saved to the XDC file before the database is closed
(in this case, synthesized design database).
56-52-39. Select File > Constraints > Save.
57-53-40. Make sure that the Select an existing file option and wave_gen_timing.xdc are
selected.
58-54-41. Click OK.

59-55. Close the implemented design.

60-56. Run implementation.

Refer to the "Running Implementation" section under Vivado Design Suite Oper-
ations in the Lab Reference Guide if you do not recall how to perform this task.

61-57. Open the implemented design.

If you do not recall how to perform this task, refer to the "Opening the Imple-
mented Design" section under Vivado Design Suite Operations in the Lab Refer-
ence Guide.Review the Timing Summary report.
The Timing Summary report is generated as part of implementation and is
opened in the Console pane when the implemented design is opened.
62-58-42. Select the Timing window near the Console pane if it is not already selected.
63-59-43. Review the Design Timing Summary section.
Note that Worst Negative Slack (WNS) and Worst Hold Slack (WHS) are positive num-
bers. This means that there is no timing failure in the design.

12 www.xilinx.com
© Copyright 2019 Xilinx
 
Lab Workbook Introduction to Timing Exceptions

64-60. Close the implemented design.

65-61. Close the project.

66-62. Close the Vivado Design Suite.

Summary
This lab used the Timing Constraints window to specify path-exception constraints in a design.

www.xilinx.com 13
© Copyright 2019 Xilinx
 
Introduction to Timing Exceptions Lab Workbook

Answers
1. What are the different timing constraints already defined in this design?

Currently there are only the clock constraints, asynchronous clock groups, and the I/O delay
specifications defined in the design.

2. What are the constraints that need to be entered to fix the timing errors in the design?

From the timing tab at the bottom, you can see that timing errors are due to the multicycle
paths between the cmd_parse_i0/send_resp_data_reg[*] and
resp_gen_i0/to_bcd_i0/bcd_out_reg[*] signals that are failing to meet the default single-cycle
timing of clk_out1_clk_core under the Intra-clock Paths section. You have to specify a
multicycle path between the source and destination registers.

There is also a false path on the rst_pin-driven path that also needs to be addressed. An
appropriate false path specification needs to be applied.

14 www.xilinx.com
© Copyright 2019 Xilinx