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The breathing lamp used in VIVADO simulation

------ Based on ZYNQ MINI development board

Writers: Teacher Yang, Teacher Wu

Date of writing final draft: 2022.10.12

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Table of contents

1. Document Implementation Function Introduction................................... ................................................... ..................................3

1. ZYNQ project establishment............ ................................................... ................................................... .............. 3 2.

Realization of the breathing light................................... ................................................... ................................................... ..........

3 3. Create a new verilog testbench file........................... ................................................... .............. 6 4. Verification effect

of integrated layout and routing generation bitstream download...... ................................................... ................... 14

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1. Document Implementation Function Introduction

This document implements the simulation of the design code, using VIVADO's own tools for simulation, and learn how to use it through this tutorial

VIVADO software has its own simulation function. For the method of creating a new project, please refer to the document "Installation and Introduction of Development Software/Introduction to VIVADO and

Create a new ZYNQ Engineering Tutorial under the software".

1. ZYNQ project establishment

Start page (or file->Project->New) Create a new project (CreateNewProject)

Wizard start page Click Next->

ProjectName (project name) Project name: fpga_02_breath_led

Project path: (choose by yourself, do not have a Chinese path)

Check CreateProjectSubdirectory, click Next->

AddSource (add design source file) Click Next->

AddExsixtingIP (add existing IP) Click Next->

AddConstraints (add existing constraint files) Click Next->

DefaultPart (default configuration, chip selection) Family->Zynq-7000

Speed->7010 selection-1,7020

selection-2 7010 version selection target device:

xc7z010clg400-1 7020 version selection target device: xc7z020clg400-2

Click Next->

NewProjectSummary (new project overview) Confirm project information, type selection, etc., click Finish to complete

Second, the realization of the breathing light

For the method of creating a new verilog file, please refer to "01fpga Development: The Simplest LED Flow Lamp". No further details are given here,

The file name we created is: breath_led.v, the module name is breath_led, and the module realizes the breathing light effect of 4 LEDs in turn.

The breath_led.v code is as follows (do not copy the code from here, please copy from the corresponding demo, the format will change when the pdf document is copied

change):

module breath_led #

parameter CLOCK_FRQ=50000000,//input clock

Frequency 50M

parameter PWM_FRQ=1000,//PWM frequency 1K

parameter BREATH_ERIOD=2,//breathing cycle 2S

parameter SET_COMPARE_FRQ=1000,//comparison

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Output frequency 1K

parameter

PWM_COUNTER_MAX=CLOCK_FRQ/PWM_FRQ, //PWM occurrence count maximum value

parameter

BREATH_COUNTER_MAX=CLOCK_FRQ*BREATH_ERIOD,//breath count maximum parameter

SET_COMPARE_COUNTER_MAX=CLOCK_FRQ/SET_COMPARE_FRQ,//Set the maximum value of the comparison

count parameter

COMPARE_VALUE_STEP=PWM_COUNTER_MAX/SET_COMPARE_FRQ//Compare value step size

input wire clk,

input wire rstn,

output wire [3:0]led

);

reg [31:0]counter_pwm; reg

[31:0]counter_breath; reg

[31:0]counter_compare; reg

[31:0]compare_value; reg

pwm_period_clk_view; reg

breath_period_clk_view; reg

compare_period_clk_view; reg

[3:0]led_number;

reg led_breath_view; reg

breath_dir; reg [3:0]led_reg;

assign led=led_reg;

//led value output

always @(posedge clk) begin

if(rstn==0)led_reg<=0; case

(led_number) 8'b000:

led_reg[0]<=led_breath_view;

8'b001: led_reg[1]<=led_breath_view; 8'b010:

led_reg[2]<=led_breath_view; 8'b011:

led_reg[3]<=led_breath_view; default:

led_reg[0]<=led_breath_view; endcase

end

//pwm

always @(posedge clk or negedge rstn) begin

if(rstn==0) begin

counter_pwm<=0;

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pwm_period_clk_view<=0;
end

else

begin

counter_pwm<=counter_pwm+1;

if(counter_pwm<compare_value)led_breath_view<=1; else

led_breath_view<=0; if(counter_pwm>PWM_COUNTER_MAX-1)

begin

counter_pwm<=0;

pwm_period_clk_view<=~pwm_period_clk_view;

end

end

end

//led output logic

reg [3:0]led_number_state;

always @(posedge clk or negedge rstn) begin

if(rstn==0)

begin

led_number=0;

counter_breath<=0;

breath_period_clk_view<=0;

breath_dir<=0; led_number_state<=0;

end

else

begin

counter_breath<=counter_breath+1;

if(counter_breath>BREATH_COUNTER_MAX-1) begin

counter_breath<=0;

breath_period_clk_view<=~breath_period_clk_view;

breath_dir<=~breath_dir; if(breath_dir==1) begin

case (led_number_state)
0:
begin led_number_state=1;led_number=0; end begin
1:
led_number_state=2;led_number=1; end begin
2:
led_number_state=3;led_number=2; end begin
3:
led_number_state=4;led_number=3; end begin
4: led_number_state=5;led_number=2; end begin
5:
led_number_state=6;led_number=1; end begin
6:
led_number_state=0;led_number=0; end default: begin

led_number_state=0; led_number=0;end endcase

end

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end

end

end

//breathing logic and up and down counting logic

always @(posedge clk or negedge rstn) begin

if(rstn==0)

begin

counter_compare<=0;

compare_period_clk_view<=0;

compare_value<=0;
end

else

begin

counter_compare<=counter_compare+1;

if(counter_compare>SET_COMPARE_COUNTER_MAX-1) begin

counter_compare<=0;

if(breath_dir==0) begin

if(compare_value<PWM_COUNTER_MAX)compare_value<=compare_value+COMPARE_VALUE_STEP;
end

else if(breath_dir==1)

begin

if(compare_value>0)compare_value<=compare_value

COMPARE_VALUE_STEP;
end

compare_period_clk_view<=~compare_period_clk_view;
end

end

end

endmodule

In the code, first the top-level parameter list defines some parameters, such as period and PWM count related parameters. Then in the

code, there is the code generated by the breathing cycle, the PWM counting code, and the LED switching code. Our tutorial is mainly to show you how

to use VIVADO's own simulation tool to simulate the design, and the code logic will not be explained. Then we explain

How to emulate.

3. Create a new verilog testbench file

We can see that after creating a new verilog file breath_led.v, under the Sources file column

The breath_led.v file also appears under simulation sources->sim_1. Newly created design files will also be synchronized to the simulation file directory.

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We right-click Add Sources in the simulation soruces, and the interface for adding source files will pop up. Add is checked by default.

or Create simulation sources and click next->:

Then click Create File to pop up a new file window. Here, the default File Type and File location remain

unchanged, and then fill in breath_led_tb for the File name, and then click OK:

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Then click Finish to complete adding the testbench file. Finally, the window for defining the top-level module name of testbench pops up.

Here we do not modify by default, then click OK:

Click YES in the pop-up dialog box:

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Finally, we see that the newly created breath_led_tb.v under sim_1 is newly created.

We double-click breath_led_tb.v to edit it. We first instantiate the breath_led module to be tested, and then write a series of signal initialization,

and clock driver code. Finally, the breath_led_tb.v file code is as follows:

`timescale 1ns / 1ns

module breath_led_tb();

reg clk_reg;

reg rstn_reg;

wire [3:0]led;

wire clk;

wire rstn;

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initial begin

clk_reg=0;

rstn_reg=0;

#10

rstn_reg=1; end

always #1 clk_reg=~clk_reg; assign

rstn=rstn_reg; assign clk=clk_reg;

breath_led #

( .CLOCK_FRQ(1000000) )

breath_led_inst (

.clk(clk), .rst_n(rstn), .led(led)

);

endmodule

In order to improve the simulation verification speed, we changed the clock signal parameter to 100000HZ, and modified it through the form of parameter transfer. The land marked in red above the code

square. This technique can be used during simulation to improve development efficiency and greatly save time.

We set up the simulation. First, we click on Settings in the project management bar. Many settings can be made in the pop-up settings, including project settings,

Model settings, emulation settings, etc.

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We click on simulation to enter, and Vivado Simulator is selected by default. Then click OK to exit.

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After returning to the main interface, right-click Run Simulation under SIMULATION in the project management bar, and select the

A Run Behavioral Simulation:

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Finally, the simulation starts. The simulation can be started by controlling the simulation start and stop button above. Click on the third right in the middle

The corner symbol starts the simulation.

It can be properly rearranged by dragging and dropping. We adjust the window and wait for a while to run. can be seen,

Our LED signal output flows over time, and the breathing light waveform output.

Careful little friends will find that the cycle width of the LED high level is changing when pulling the X axis.

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4. Comprehensive layout and routing to generate bit stream download verification effect

Binding pins and integrated layout and routing to generate bit files, please refer to the document "The Simplest LED Streaming Light for FPGA Development", which is no longer here

Detailed description. We bind the pins as follows:

Finally, the layout and routing generate a bit file and download it to the development board. You can see the gradient brightness effect of our breathing light.

This concludes the tutorial for this section. If you need to use a third-party modelsim simulation, you can change the simulation software selection in the settings.

item, and then install modelsim for simulation. Third-party simulation software is more convenient to use than VIVADO and has higher performance. third party imitation

The real software needs to be studied by yourself, and this tutorial will not discuss it.

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