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General Info

This document provides information about the EE103 Introduction to VLSI Design course. It outlines that the course will use the textbook "Introduction to VLSI Circuits and Systems", and that students will complete labs, quizzes, exams, homework assignments, and a senior project involving designing a VLSI device from specification through testing. The course will utilize Synopsys for synthesis and simulation, Magic for layout, and MOSIS for fabrication of designs using a 0.5 micron CMOS process.

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43 views1 page

General Info

This document provides information about the EE103 Introduction to VLSI Design course. It outlines that the course will use the textbook "Introduction to VLSI Circuits and Systems", and that students will complete labs, quizzes, exams, homework assignments, and a senior project involving designing a VLSI device from specification through testing. The course will utilize Synopsys for synthesis and simulation, Magic for layout, and MOSIS for fabrication of designs using a 0.5 micron CMOS process.

Uploaded by

mcs98e
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE103 Introduction to VLSI Design General Information 1) Introduction

DR. PANETTA, COLOMBO

My background I have 18 years of valuable industry experience. As a hardware designer in both digital and analog. As an undergrad I have taken VLSI Design. In my career I have done two ASICs from coding in VHDL to back-annotation testing. I did synthesis with Synopsys. Simulation with Mentor Graphics Quicksim. 2) Course info Text book is Introduction to VLSI Circuits and Systems ISBN 0-471-12704-3 The pertinent info will be posted on the Class web site at www.eecs.tufts.edu/~karen/EE103 There will be a Midterm and a Final exam, and seniors will also have their senior project. There will be 1 quiz per week (on average) on Tuesdays. I will take the best 6 for the final quiz grade. No make-ups. There will be 1 homework per week (on average) on Thursday. I will take the best 6 for the final homework grade. Late homework penalty is 10% per day. Labs are important. They must be done!!. TA will be available for labs. If you cant do the labs you will not be able to do the project. Its down hill from there! The project grade will be based on completeness. What I want to see is specification, simulation, DRC check all need to be done. In this course we will design a VLSI device. You will do a full specification on thru to testing of your device. This is to be done in teams of 2 to 5 people. Submit projects to me for review first. If you dont have an idea for a project, see me. Weighting LAB 20 % QUIZ 20 % EXAM 30 % PROJECT 20 % HOMEWORK 10%

3) Tools You will be able to code in VHDL or Verilog, we will synthesize and functional simulation with Synopsys or tool of your choice. In this course we will design a VLSI device. You will do a full specification on thru to testing of your device. This is to be done in teams of 2 to 5 people. Submit projects to me for review first. If you dont have an idea for a project, see me. Seniors who want to use this as their senior project can do a Xilinx FPGA in either Verilog (or VHDL). Same rules apply for the course project. 4) Tools cont I have an account setup with MOSIS. We will be using the CMOS 0.5 micron process, which has fabrication start dates almost monthly. We will use the AMI Semiconductor 0.5 Micron CMOS Process. I would like to use thru-hole package to enable us to test our devices on a proto-board that you have been using. DIP packages offered are small. I am trying to get Cell Libraries from AMI Semiconductor. This will make designs easier. Magic will be used for layout. Need to do the tutorials. Learn the tools as fast as possible. IRSIM will be used for simulation. Magic provides an interface for this simulator. Accounts in the SIMLAB on UNIX Workstations. The MAGIC tool downloads are available. See our web site.

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