18BCS37S U1
18BCS37S U1
18BCS37S U1
Accumulator
As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
Program counter
It is a 16-bit register used to store the memory address location of the next
instruction to be executed. Microprocessor increments the program whenever an
instruction is being executed, so that the program counter points to the memory
address of the next instruction that is going to be executed.
Stack pointer
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
Flag register
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
Its bit position is shown in the following table −
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Interrupt control
It controls the serial data communication by using these two instructions: SID
(Serial input data) and SOD (Serial output data).
The content stored in the stack pointer and program counter is loaded into the
address buffer and address-data buffer to communicate with the CPU. The
memory and I/O chips are connected to these buses; the CPU can exchange the
desired data with the memory and I/O chips.
Data bus carries the data to be stored. It is bidirectional, whereas address bus
carries the location to where it should be stored and it is unidirectional. It is used
to transfer the data & Address I/O devices.
8085 Architecture
We have tried to depict the architecture of 8085 with this following image −
Instruction cycle in 8085 Microprocessor
The Program and data which are stored in the memory, are used externally to the
microprocessor for executing the complete instruction cycle. Thus to execute a
complete instruction of the program, the following steps should be performed by the
8085 microprocessor.
• Fetching the opcode from the memory;
• Decoding the opcode to identify the specific set of instructions;
• Fetching the remaining Bytes left for the instruction, if the instruction length is of
2 Bytes or 3 Bytes;
• Executing the complete instruction procedure.
The given steps altogether constitute the complete instruction cycle. These above
mentioned steps are described in detail later. The above instructions are assumed by us
for being in the memory, at the specified locations allocated for the memory.
The points to be noted as without fetching of the opcode from the memory the complete
instruction would remain incomplete. Secondly decoding should be done, thirdly the
fetching process should be done depending on the instruction length. Thirdly the
complete execution process should be carried out to complete the entire process of
execution.
To have a better idea on Instruction Cycle, let us consider the instruction DCX SP and
its instruction cycle into details –
In 8085 Instruction set, DCX SP instruction is used to decrement the SP contents by 1.
DCX SP instruction is a special case of DCX rp instruction which decreases the content
of the register pair. This instruction occupies only 1-Byte in memory.
DCX SP 3B 1
Let us consider that the initial content of SP is 4050H. So after decrement of the content
of SP by using DCX SP instruction, SP would have the value 404FH. Here is the
required tracing table as below –
Before After
Before After
Timing Diagram
Instruction Cycle:
Machine Cycle:
T-State:
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-
state.
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
Opcode fetch cycle (4T)
Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)
The instructions which have more than one byte word size will use the machine
cycle after the opcode fetch machine cycle.
The I/O Read cycle is executed by the processor to read a data byte from I/O
port or from the peripheral, which is I/O, mapped in the system.
Then the lower order memory address is read (6A). - Memory Read Machine
Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.
Instruction Format
The 8085 instruction set is classified into the following three groups
according to word size:
1 One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte.
Operand(s) are internal register and are coded into the instruction
These instructions are 1-byte instructions performing three different tasks. In
the first instruction, both operand registers are specified. In the second instruction,
the operand B is specified and the accumulator is assumed. Similarly, in the third
instruction, the accumulator is assumed to be the implicit operand. These
instructions are stored in 8- bit binary format in memory; each requires one
memory location.
MOV rd, rs
where ddd is a code for one of the 7 general registers which is the destination of
the data, sss is the code of the source register.
ADD r
AA+r
2 Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the
second byte specifies the operand. Source operand is a data byte immediately
following the opcode. For example:
MVI r,data
r data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes.
ADI data
A A + data
OUT port
0011 1110
DATA
Since the byte is not the data but points directly to where it is located this is called
direct addressing.
3 Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the
following two bytes specify the 16-bit address. Note that the second byte is the
low-order address and the third byte is the high-order address.
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data
bytes are 16-bit data in L H order of significance.
rp data16
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate
addressing.
LDA addr
In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand. For example: MVI K, 20F: means 20F is copied into register K.
In this mode, the data is copied from one register to another. For example: MOV K, B:
means data in register B is copied to register K.
In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000K: means the data at address 5000K is copied to register B.
In this mode, the data is transferred from one register to another by using the address
pointed by the register. For example: MOV K, B: means data is transferred from the
memory address pointed by the register to the register K.
This mode doesn’t require any operand; the data is specified by the opcode itself. For
example: CMP.
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,
RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
• Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
• Non-Vector interrupt − In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally by
the device to perform interrupts. For example: INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For example:TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and
RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
TRAP
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When
this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When
this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be
disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
• The microprocessor checks the status of INTR signal during the execution of
each instruction.
• When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
• When instructions are received, then the microprocessor saves the address of
the next instruction on stack and executes the received instruction.
SHLD 16-bit address directly stores from H & L registers SHLD 2050
LXI r.p., 16-bit data loads the specified register pair with data LXI H, 3050
STAX 16-bit address indirectly stores from the accumulator A STAX 2050
OUT 8-bit port address outputs contents of A to the specified port OUT 15
In the table,
R stands for register
M stands for memory
r.p. stands for register pair
Logical instructions are the instructions which perform basic logical operations such as AND, OR,
etc. In 8085 microprocessor, the destination operand is always the accumulator. Here logical
operation works on a bitwise level.
Following is the table showing the list of logical instructions:
ORA R A = A OR R ORA B
CMP M Compares Mc with A and triggers the flag register CMP 2050
CPI 8-bit data Compares 8-bit data with A and triggers the flag register CPI 50
In the table,
R stands for register
M stands for memory
Mc stands for memory contents
Branching instructions refer to the act of switching execution to a different instruction sequence as
a result of executing a branch instruction.
The three types of branching instructions are:
1. Jump Instructions – The jump instruction transfers the program sequence to the memory
address given in the operand based on the specified flag. Jump instructions are 2 types:
Unconditional Jump Instructions and Conditional Jump Instructions.
(a) Unconditional Jump Instructions: Transfers the program sequence to the described memory
address.
(b) Conditional Jump Instructions: Transfers the program sequence to the described memory
address only if the condition in satisfied.
2. Call Instructions – The call instruction transfers the program sequence to the memory address
given in the operand. Before transferring, the address of the next instruction after CALL is pushed
onto the stack. Call instructions are 2 types: Unconditional Call Instructions and Conditional Call
Instructions.
(a) Unconditional Call Instructions: It transfers the program sequence to the memory address
given in the operand.
(b) Conditional Call Instructions: Only if the condition is satisfied, the instructions executes.
3. Return Instructions – The return instruction transfers the program sequence from the
subroutine to the calling program. Return instructions are 2 types: Unconditional Jump Instructions
and Conditional Jump Instructions.
(a) Unconditional Return Instruction: The program sequence is transferred unconditionally from
the subroutine to the calling program.
(b) Conditional Return Instruction: The program sequence is transferred unconditionally from
the subroutine to the calling program only is the condition is satisfied.
HLT - Halt
NOP - No Operation