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Announcements

EE241B : Advanced Digital Circuits • Homework 1 posted, due on February 17

• No class on February 18 (ISSCC)
Lecture 6 – Standard Cells
Borivoje Nikoliü
IEEE International Solid-State Circuits Conference. San Francisco, February 16-21,
2020. Preview in the IEEE Solid-State Circuits Magazine, Winter 2020.

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Outline
• Module 2
• Standard cells
• Gate delay
• Design flows

2.I Delay Revisited

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MOS Transistor as a Switch (EECS251A) MOS Transistor as a Switch (EE241A)

Traversed path
Solving the integral:

with appropriately calculated Idsat

Averaging resistances:

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CMOS Performance Switching Trajectory

6.0E-04

Propagation delay: t pHL ln 2ReqnCL t pLH ln 2ReqpC L

5.0E-04

ln2 = 0.7
4.0E-04

IDS[A]
3.0E-04

2.0E-04

1.0E-04

0.0E+00
0.2 0.4 0.6 0.8 1.0

VDS[V]
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 Effective Current DIBL Matters
• Ion(VDD) is never reached • A. Loke, VLSI’16
FinFET, FDSOI – less DIBL
• Define Ieff = (IH + IL)/2
• IL = IDS(VGS=VDD/2, VDS=VDD); IH=IDS(VGS=VDD, VDS=VDD/2),

Na, IEDM’2002
Von Arnim, IEDM’2007
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Transistor Stacks Effective Current in Stacks

6.0E-04
Add linear current, I3
5.0E-04

4.0E-04

IDS[A]
3.0E-04

2.0E-04

1.0E-04

0.0E+00 Von Arnim, IEDM’2007

0.2 0.4 0.6 0.8 1.0

VDS[V]
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Standard Cell Inverter

• Schematic and layout
N Well
(in a planar bulk process) VDD

VDD PMOS 2O

Contacts
PMOS
2.J Standard Cells In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND
• Pitches are integer multiples of O
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Two Inverters FinFET Standard Cells

ASAP7
Share power and ground

Abut cells

VDD Connect in Metal

Delay is additive
V. Vashishtha, ICCAD’17
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 ASAP7 Standard Cells ASAP7 Standard Cells

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ASAP7 Standard Cells ASAP7 Standard Cells

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ASAP7 Standard Cells ASAP7 Standard Cells

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ASAP7 Standard Cells ASAP7 Standard Cells

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 ASAP7 Standard Cells ASAP7 Standard Cells

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ASAP7 Standard Cells ASAP7 Standard Cells

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ASAP7 Latch FinFET Standard Cells

V. Moroz, Semicon Taiwan, 2016

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Design Kit Components EE241B Technology

• Physical views • ASAP7 7nm predictive technology kit
• Layout and schematic, with abstractions • Also available Synopsys 32/28nm Generic Library
• Netlist • Multi-vth Standard Cell Library 45 IO pads
• Logical view • SRAMs
• Test view • Design rule manual
• Timing, power and noise views
• Documentation

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 Servers to Use
• Please use the instructional servers
• Labs may not be up to date on BWRC machines
• Servers to use:
• c152m-{1-15}.eecs.berkeley.edu
• eda-{1-8}.eecs.berkeley.edu
2.K Class Design Flow
• Other servers may be missing tools / may be using a different version!
• EECS instructional website is helpful!
• http://inst.eecs.berkeley.edu/~inst/iesglabs.html

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Text Editors/Other commands and tools Getting Started: Logging in

• Learn to use vim • From terminal:
• gvim, emacs are some alternatives • ssh –Y <username>@<server>
• You will not be sorry! • Instructional account login
• Gedit can cause some issues • From Windows:
• Use tmux • Can use putty
• Other unix commands • Linux subsystem
• ls, cd, cp, rm, mkdir, tar, grep, … • Can also you x2go to connect to a remote desktop
• Life skills!

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Setting up your environment Instructional Tools and Technology

• Can work in home directory for basic things • Most tools can be found in /share/instww/{cadence or synopsys}
• Move to /scratch/ (local to each machine) for running the labs • ASAP7 technology new for this semester
• Make your own directory here to work in • Open predictive PDK
• Follow the directions in the lab • Can be found in ~ee241/spring20-labs/
• Clone the lab • Lab requires you to look at technology (and maybe some tool manuals)
• Tools are configured as submodules • Manuals are your friend!
• Run git submodule update –init –recursive to initialize the submodules • They can usually be found in a docs/ folder in the tool directory.
• Need to source sourceme.sh every time you reinitialize
• Sets up some Hammer variables
• Sources course .bashrc

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git Lab Preview

• Version control • Update for this semester
• Another important “learn to use” • Converted to use Hammer and ASAP7
• Please post on Piazza and come to office hours if you run into issues
• Shouldn’t need much advanced use for this class but it is a lifeskill! • Baseline overview of a portion of the VLSI flow
• git clone • Simulation, synthesis, P&R
• Initialize • Looking at log files, reports, etc. to understand the design and tools
• git submodule update –init –recursive • It’s about telling the tools what it wants to hear
• Initialize all submodules • What’s missing?
• Only need to run once in this context • Discussed in the summary
• DRC, LVS, more advanced power analysis, much more!
• Pay attention to lecture and think about how you can integrate into the flow
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 Lab Preview (continued) Next Lecture
• Hammer • Library characterization
• https://github.com/ucb-bar/hammer • Static timing
• Python framework for physical design
• Separation of concerns to enable reuse
• What are these hammer-cadence-plugins and hammer-synopsys-plugins?
• Tool specific implementations of APIs
• Not publicly available so do not share!
• So where’s the technology plugin?
• hammer/src/hammer-vlsi/technology/asap7/
• ASAP7
• Take a look at the files!
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