MEENAKSHI SUNDARARAJAN ENGINEERING COLLEGE, CHENNAI-24.

DEPARTMENT OF COMPUTER SCIENCE AND INFORMATION TECHNOLOGY

QUESTION BANK

Subject Code / Subject Name: CS8491/ COMPUTER ARCHITECTURE

Year / Sem : II year / IV Sem
UNIT III-PROCESSOR AND
CONTROL UNIT
Basic MIPS implementation – Building data path – Control Implementation scheme – Pipelining –
Pipelined data path and control – Handling Data hazards & Control hazards – Exceptions.
PART A
Q. QUESTIONS BT COMPE CO PO
No LEVEL TENCE
1 Express the control signals required to perform BTL 2 Understanding C214 PO1
arithmetic operations. .2
2 Define hazard. Give an example for data hazard. BTL 2 Understanding C214 PO1
.2
3 Recall pipeline bubble. BTL 1 Remembering C214 PO1
.2 PO2
4 List the state elements needed to store and access an BTL 1 Remembering C214 PO1
instruction. .2
5 Draw the diagram of portion of data path used for BTL 2 Understanding C214 PO1
fetching instruction. .2 PO2

6 Distinguish Sign Extend and Vector interrupts. BTL 2 Understanding C214 PO1
.2 PO2
PO3
7 Name the R-type instructions. BTL 1 Remembering C214 PO1
.2
8 Evaluate branch taken and branch not taken in BTL 5 Analyzing C214 PO1,
instruction execution. .2 PO2
9 State the two steps that are common to implement BTL 1 Remembering C214 PO1
any type ofinstruction. .2 PO2
10 Design the instruction format for the jump BTL 6 Creating C214 PO1
instruction. .2
11 Classify the different types of hazards with BTL 4 Analyzing C214 PO1
examples. .2 PO2
PO3
12 Illustrate data forwarding method to avoid data BTL 3 Applying C214 PO1
hazards. .2
13 Assess the methods to reduce the pipeline stall. BTL 5 Evaluating C214 PO1
.2
14 Tabulate the use of branch prediction buffer. BTL 1 Remembering C214 PO1
.2 PO2
15 Show the 5 stages pipeline. BTL 3 Applying C214 PO1
.2
16 Point out the concept of exceptions and interrupts. BTL 4 Analyzing C214 PO1
.2
17 What is pipelining? BTL 1 Remembering C214 PO1
.2 PO2
18 Illustrate the various phases in executing an BTL 3 Applying C214 PO1
instruction. .2

19 Classify the types of instruction classes and their BTL 4 Analyzing C214 PO1
instruction formats. .2 PO2
PO3
20 Generalize what is exception. Give one example for BTL 6 Creating C214 PO1
MIPS exception. .2
PART B
Q. QUESTIONS BT COMPE C214 PO
No LEVEL TENCE .2
1 Discuss the basic MIPS implementation of
instruction set. BTL2 Understanding C214 PO1
(13) .2 PO2
PO3

2 State and draw a simple MIPS data path with BTL1 Remembering C214 PO1
control unit and .2
explain the execution of ALU instruction. (13)
3 i) List the types of hazards. (3) BTL 1 Remebering C214 PO1
ii)Describe the methods for dealing with the control .2
hazards.
(10)

4 Design and develop an instruction pipeline BTL 6 Creating C214 PO1

working under various situations of pipeline stall. .2 PO2
(13)

5 i) What is data hazard? How do you overcome it? (8) BTL 1 Remembering C214 PO1
.2
 ii) What are its side effects? (5) PO2

6 i) Summarize control implementation scheme. (9) BTL 2 Understanding C214.2 PO1

ii) Distinguish the data and control path methods in PO2
pipelining. (4) PO3
7 i) Differentiate sequential execution and pipelining. BTL 4 Analyzing C214.2 PO1
(7) PO2
ii) Select the model for building a data path (6)

8 Recommend the techniques for BTL5 Evaluating C214.2 PO1

i) Dynamic branch prediction. (7) PO2
ii) Static branch prediction. (6) PO3
9 Examine the approaches would you use to handle BTL 3 Applying C214.2 PO1
exceptions in MIPS (13) PO2
PO3

10 i) Analyze the hazards caused by BTL 4 Analyzing C214.2 PO1

unconditional branching statements. (7) PO2
ii) Describe operand forwarding in a pipeline
processor with a diagram. (6)
11 Express the modified data path to BTL 2 Understanding C214.2 PO1
accommodate pipelined executions with a diagram. PO2
PO3
12 i) Explain single cycle and pipelined performance with BTL 4 Analyzing C214.2 PO1
examples. (7) PO2
PO3
ii)Point out the advantages of pipeline over single cycle
(6).

13 i) Tabulate the ALU control with suitable truth table.(8) BTL 1 Remembering C214.2 PO1
ii)Differentiate R-type instruction and memory
instruction. (5)

14 With a suitable set of sequence of instructions BTL-3 Applying C214.2 PO1

show what happens when the branch is taken, PO2
assuming the pipeline is optimized for branches
that are not taken and that we moved thebranch
execution to the ID stage.(13)

PART C
1 Assume the following sequence of BTL 6 Creating C214.2 PO1
PO2
instructions are executed on a5 stage
pipelined data path:
add r5,r2,r1 lw r3,4(r5) lw r2,0(r2) or r3,r5,r3 sw
r3,0(r5)
If there is no forwarding or hazard
detection, insert NOPS to ensure correct
execution.
i) If the processor has forwarding, but we forgot to
implement the hazard detection unit, what if
happens when this code executes? (5)
ii) i
If there is forwarding, for the first five cycles,
compose which signals are asserted in each
cycle.(5)
iii) I
If there is no forwarding, what if new inputs and
output signals do we need for the hazard detection
unit.(5)
2 Explain in detail about the laundry process BTL 5 Evaluating C214.2 PO1
through which the pipelining techniques can be PO2
established. (15) PO3

3 Consider the following loop: BTL 5 Evaluating C214.2 PO1

Loop: lw r1,0(r1) PO2
and r1,r1,r2
lw r1,0(r1)
lw r1,0(r1) beq r1,r0,loop
Assume that perfect branch prediction is
used (no stalls) thatthere are no delay slots,
and that the pipeline has full forwarding
support. Also assume that many iterations of
this loop are executed before the loop exits.
i) Assess a pipeline execution diagram for the
third iteration of this loop.(8)
ii) Show all instructions that are in the
pipeline during these
cycles ( for all iterations). (5)

4 Plan the pipelining in MIPS architecture and BTL6 Creating C214.2 PO1
generate the PO2
exceptions handled in MIPS. PO3