Introduction to VLSI Circuits and Systems

積體電路概論
Chapter 09
Advanced Techniques in CMOS Logic Circuits

賴秉樑
Dept. of Electronic Engineering
National Chin-Yi University of Technology
Fall 2007

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Mirror Circuits
ˆ Mirror circuits are based on series-parallel logic gates,
but are usually faster and have a more uniform layout
» Output 0’s imply that an nFET chain is conducting to
ground
» Output 1’s means that a pFET group provides support from
the power supply

(a) Circuit

(b) Layout
Figure 9.1 XOR function table
Figure 9.2 XOR mirror circuit
Introduction to VLSI Circuits and Systems, NCUT 2007
 XOR & XNOR
ˆ The advantages of the mirror circuit are
more symmetric layouts and shorter rise
and fall times

ˆ In Figure 9.3, transient calculations of

XOR
Figure 9.3 Switching mode for
τ x = C out (2 R x ) + C x R x (9.1) transient calculations (XOR)
where x is p or n

t r ≈ 2.2τ p (9.2)

t f ≈ 2.2τ n (9.3)

ˆ In Figure 9.4, a example of XNOR

a ⊕ b = a ⋅b + a ⋅b (9.4) Figure 9.4 Exclusive-NOR (XNOR) circuit

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Pseudo-nMOS
ˆ Adding a single pFET to otherwise nFET-only circuit
produces a logic family that is called pseudo-nMOS
» Less transistor than CMOS
» For N inputs, only requires (N+1) FETs
» Pull-up device: pFET is biased active since the grounded
gate gives VSGp = VDD
» Pull-down device: nFET logic array acts as a large switch
Figure 9.5 General structure
between the output f and ground of a pseudo-nMOS logic gate
» However, since the pFET is always biased on, VOL can
never achieve the ideal value of 0 V
ˆ A simple inverter using pseudo-nMOS as Figure 9.6
βn
2
[2(VDD − VTn )VOL − VOL =
2
] βp
2
(V DD − VTp )
2
(9.4)

βp
VOL = (VDD − VTn ) − (VDD − VTn )2 − (V − VTp
β n DD
)
2
(9.5)
Figure 9.6 Pseudo-nMOS inverter
Introduction to VLSI Circuits and Systems, NCUT 2007
 nFET Array in Pseudo-nMOS
ˆ The design of nFET array of pseudo-nMOS is the
same as in standard CMOS
» Series and parallel logic FETs
» Smaller simpler layouts, and interconnect is much simpler
» However, the sizes need to be adjusted to insure proper
electrical coupling to the next stage
» Resize in physical design (a) General circuit

(a) NOR2 (b) NAND2 (b) Layout

Figure 9.7 Pseudo-nMOS NOR and NAND gates Figure 9.8 AOI gate

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Tri-State Circuits
ˆ A tri-state circuit produces the usual 0 and 1 voltages,
but also has a third high impedance Z (or Hi-Z)
» Useful for isolating circuits from common bus lines
» In Hi-Z case, the output capacitance can hold a voltage
even though n hardwire connection exists

ˆ A non-inverting circuit ( a buffer) can be obtained by

adding a regular static inverter to the input

Figure 9.10 Tri-state layout

(a) Symbol and operation (b) CMOS circuit

Figure 9.9 Tri-state inverter Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Clock-CMOS (C2MOS)
ˆ Static CMOS: the output of a static logic gate is
valid so long as the input value are valid and the
circuit has stabilized

ˆ However, logic delays are due to the “rippling”

through the circuits
» Not reference to any specific time base
» So on, Clock CMOS, or C2MOS is proposed

ˆ C2MOS concept: non-overlapping clock

φ (t ) ⋅ φ (t ) = 0 (9.9) Figure 9.11 Clock signals

⇒ φ (t ) = VDD − φ (t ) (9.10)

» But in physical signal, the clocks may overlap slightly

during a transition

Introduction to VLSI Circuits and Systems, NCUT 2007

 C2MOS Networks
ˆ C2MOS is composed of a static logic circuit with tri-state output network
(made up of FETs M1 and M2) that is controlled by φ and φ
» When φ = 0 , both M1 and M2 are active, and become to a standard static logic gate
» When φ = 1 , both M1 and M2 are cutoff, so the output is a Hi-Z state

Figure 9.12 Structure of a C2MOS gate

Introduction to VLSI Circuits and Systems, NCUT 2007

 Example of C2MOS

(a) NAND2

(a) Inverter (b) NAND2

Figure 9.14 Layout examples of C2MOS circuits

(b) NOR2
Figure 9.13 Example of C2MOS logic gate Introduction to VLSI Circuits and Systems, NCUT 2007
 Leakage in C2MOS (1/2)
ˆ Charge leakage: since the output node cannot hold
the charge on Vout very long
» This places a lower limit on the allowable clock
frequency

ˆ If a voltage is applied to the drain or source, a small

leakage current flows into, or out of, the device
(a) Bulk leakage currents
» One reason is due to the required bulk connections
» The current off of the capacitor by iout
iout = in − i p
dV (9.11)
= −Cout
dt
dV
I L = −Cout
dt
(9.12)

⎛ IL ⎞
V (t )

∫ dV = − ∫ ⎜⎜⎝ C
t
⎟⎟dt (9.13)
out ⎠
0
V1 (b) Logic 1 voltage decay

⎛ I ⎞ Figure 9.15 Charge leakage problem

V (t ) = V1 − ⎜⎜ L ⎟⎟t (9.14)
⎝ Cout ⎠ Introduction to VLSI Circuits and Systems, NCUT 2007
Leakage in C2MOS (2/2)
⎛ I ⎞
V (th ) = V1 − ⎜⎜ L ⎟⎟th = Vx (9.15)
⎝ Cout ⎠
⎛C ⎞
th = ⎜⎜ out ⎟⎟(V1 − Vx ) (9.16)
⎝ IL ⎠
⎛ 50 × 10−15 ⎞
th = ⎜⎜ −13
⎟⎟(1) = 0.5 sec (9.17)
⎝ 10 ⎠
⎛ I ⎞
V (t ) = ⎜⎜ L ⎟⎟t (9.18)
⎝ Cout ⎠
(a) Bulk leakage currents
⎛W ⎞ − (VGS −VT ) /( nVth )
I = I D0 ⎜ ⎟e (9.19)
⎝L ⎠

⎛ 50 × 15−15 ⎞
th = ⎜⎜ −9
⎟⎟(1) = 50 µ sec (9.20)
⎝ 10 ⎠
⎛ 50 × 15−15 ⎞
th = ⎜⎜ −7
⎟⎟(1) = 0.5 µ sec (9.21)
⎝ 10 ⎠

I L (V ) = −Cout (V )
dV (9.22)
dt
t V (t )
(b) Logic 1 voltage decay
∫ dt = ∫
Cout (V )
dV = t (9.23)
0 Vx
I L (V ) Figure 9.15 Charge leakage problem
Introduction to VLSI Circuits and Systems, NCUT 2007
 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Dynamic CMOS Logic Circuits (1/2)

ˆ A dynamic logic gate uses clocking and charge storage

properties of MOSFETs to implement logic operations
» Provide a synchronized data flow
» Result is valid only for a short period of time
» Less transistors, and may be faster than static cascades

ˆ Based on the circuit in Figure 9.17

» The clock φ drives a complementary pair of transistors Mn
and Mp
» An nFET array between the output node and ground to
perform the logic function
» When φ = 0 , it is called precharge phase
» When φ = 1 , it is called evaluation phase

Figure 9.17 Basic dynamic logic gate

Introduction to VLSI Circuits and Systems, NCUT 2007

 Dynamic CMOS Logic Circuits (2/2)

ˆ A dynamic NAND3 is shown in Figure 9.18

f = a ⋅b⋅c (9.24)

ˆ When f = 1, charge leakage reduces the voltages held on the output node

Figure 9.18 Dynamic logic gate example

Introduction to VLSI Circuits and Systems, NCUT 2007

 Charge Sharing Problem
ˆ The origin of the charge sharing problem is the
parasitic node capacitance C1 and C2 between
FETs
» When clock φ → 1 , and the capacitor voltage V1 and V2
are both 0 V at this time, the total charge is
Q = CoutVDD (9.25)
» The worst-case charge sharing condition is when the
inputs are at (a, b, c) = (1, 1, 0)
Vout = V2 = V1 = V f (9.26) (When the current flow ceases) Figure 9.19 Charge sharing circuit

» The principle of conservation of charge

⇒ Q = CoutV f + C1V f + C2V f ⎛ Cout ⎞
(9.27) ⎜⎜ ⎟⎟ < 1 (9.30)
= (Cout + C1 + C2 )V f ⎝ Cout + C1 + C2 ⎠

⇒ Q = (Cout + C1 + C2 )V f = CoutVDD (9.28) V f < VDD (9.31)

⎛ Cout ⎞
⇒ V f = ⎜⎜ ⎟⎟VDD (9.29) Cout >> C1 + C2 (9.32)
⎝ Cout + C1 + C2 ⎠
Introduction to VLSI Circuits and Systems, NCUT 2007
 Domino Logic (1/2)
ˆ Domino logic is a CMOS logic style obtained by
adding a static inverter to the output of the basic
dynamic gate circuit
» Non-inverting
» Cascade operation
» “Domino chain reaction” that must start at the first
stage and then propagate stage by stage to the output Figure 9.20 Domino logic stage

(a) AND gate (b) OR gate

Figure 9.22 Layout for
Figure 9.21 Non-inverting domino logic gates
domino AND gate
Introduction to VLSI Circuits and Systems, NCUT 2007
 Domino Logic (2/2)
ˆ Note that the operation indicates that domino gates are only useful in cascades

(a) Single-FET charge keeper (b) Feedback controlled keeper

Figure 9.23 A domino cascade Figure 9.25 Charge-keeper circuits

f1 = G
(9.33)
f2 = F ⋅ G

(a) Percharge (b) Evaluate

Figure 9.24 Visualization of the domino effect Figure 9.26 Structure of a MODL circuit

Introduction to VLSI Circuits and Systems, NCUT 2007

 Outline
ˆ Mirror Circuits
ˆ Pseudo-nMOS
ˆ Tri-State Circuits
ˆ Clocked CMOS
ˆ Dynamic CMOS Logic Circuits
ˆ Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT 2007

 Dual-Rail Logic Networks
ˆ Single-rail logic: the value of a variable is either a 0 or a 1 only

ˆ Dual-rail logic: both the variable x and its complement x are used to form
the difference

f x = ( x − x) (9.35)

df x ⎛ dx d x ⎞
=⎜ − ⎟ (9.36)
dt ⎜⎝ dt dt ⎟⎠

dx dx
≈− (9.37)
dt dt

df x dx
≈2 (9.38)
dt dt

Introduction to VLSI Circuits and Systems, NCUT 2007

 Differential Cascode Voltage
Switch Logic, DCVS (1/2)
ˆ DCVS or differential CVSL (CVSL) provides for
dual-rail logic gates, and the out results f and f
are held until the inputs induce a change

(a) AND/NAND

Figure 9.27 Structure of a CVSL logic gate (b) OR/NOR

Figure 9.28 CVSL gate example

Introduction to VLSI Circuits and Systems, NCUT 2007

 Complementary Pass-Transistor Logic

ˆ Complementary Pass-Transistor (CPL): an

dual-rail tech. that is based on nFET logic
equations

f = a ⋅b + a ⋅a (9.41)
(a) AND gate (b) AND/NAND array
⇒ a ⋅b + a = a + b = a ⋅b (9.42)
Figure 9.32 CPL AND/NAND circuit

ˆ CPL has several 2-input gates that can be

created by using the same transistor topology
with different input sequences
» Less layout area
» However, threshold will be loss and the fact that
an input variable may have to drive more than one
FET terminal
(a) OR/NOR (b) XOR/XNOR

Figure 9.33 2-input CPL arrays

Introduction to VLSI Circuits and Systems, NCUT 2007