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VLSI Testing & Testability

This 3 credit course covers VLSI testing and testability over 42 hours. The course is divided into 4 modules that cover fundamental VLSI testing concepts, fault modeling and testing techniques, test automation and design verification methods, and functional and timing verification approaches. Some topics discussed include test economy, fault simulation, defects, automatic test pattern generation, design for testability, built-in self-test, scan design, equivalence checking, and hardware emulation. Reference books on digital system testing, formal hardware verification, and principles of CMOS VLSI design are also listed.

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Dr. Lokesh Kumar Bramhane
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281 views1 page

VLSI Testing & Testability

This 3 credit course covers VLSI testing and testability over 42 hours. The course is divided into 4 modules that cover fundamental VLSI testing concepts, fault modeling and testing techniques, test automation and design verification methods, and functional and timing verification approaches. Some topics discussed include test economy, fault simulation, defects, automatic test pattern generation, design for testability, built-in self-test, scan design, equivalence checking, and hardware emulation. Reference books on digital system testing, formal hardware verification, and principles of CMOS VLSI design are also listed.

Uploaded by

Dr. Lokesh Kumar Bramhane
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Subject Code Credits: 3 (3-0-0)

VLSI Testing and Testability


EC650 Total hours: 42

Course Objectives This course covers introduction to the concepts and techniques of VLSI (Very Large
Scale Integration) design verification and testing. Details of test economy, fault
modeling and simulation, defects, Automatic Test Pattern Generation (ATPG), design
for testability, and built-in self-test (BIST) also covered.

Module 1 Fundamental of VLSI testing 12 hours

Basic of VLSI testing, Scope of testing and verification in VLSI design process, Issues in test and verification of
complex chips, embedded cores and SOCs.

Module 2 Fault Modeling and testing 12 hours

Fault models, fault detection and redundancy, fault equivalence and fault location, fault dominance, automatic test
pattern generation, Design for testability, Scan design, Test interface and boundary scan. System testing and test for
SOCs. Delay fault testing.

Module 3 Test automation and Design verification 10 hours

BIST for testing of logic and memories, Test automation, Design verification techniques based on simulation,
analytical and formal approaches.

Module 4 Functional and Timing verification 8 hours

Functional verification, Timing verification, Formal verification, Basics of equivalence checking and model
checking, Hardware emulation.

Reference Books

1. M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Jaico
Publishing House, 1990.
2. T. Kropf, Introduction to Formal Hardware Verification, Springer Verlag, 2000.
3. Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, Second
Edition, 1993.
4. Neil H. E. Weste and David Harris, Principles of CMOS VLSI Design, Addison Wesley, Third Edition,
2004.
5. M. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-
Signal VLSI Circuits, Kluwer Academic Publishers, 2000.

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