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Assignment 2

This document provides instructions for a digital systems design lab assignment to be completed in groups of no more than 4 students. Students are asked to design a 4-bit subtractor using Karnaugh maps, model it using Verilog array instantiation, write a test bench, and interpret the timing results in a report to be submitted during the next lab session.

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57 views

Assignment 2

This document provides instructions for a digital systems design lab assignment to be completed in groups of no more than 4 students. Students are asked to design a 4-bit subtractor using Karnaugh maps, model it using Verilog array instantiation, write a test bench, and interpret the timing results in a report to be submitted during the next lab session.

Uploaded by

Rüstem Eleç
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital System Design

Date: 27/10/2022
Lab Assignment#2
Due Next lab session
Submission hard copy to be tested in lab using Verilog modelling in
groups of no more than 4.

Design a 4-bit subtractor using Karnough Map minimization. You can use
Charlie Coleman tool. Model your design using array instantiation. Write
the test bench and interpret your timing.
Write a full report to be submitted during the lab session

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