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Digital - System - Design Verilog Project

The document describes a 4-bit arithmetic logic unit (ALU) designed in Verilog. It includes the Verilog code for the ALU module which performs addition, AND, OR, XOR logic on 4-bit inputs A and B based on a 2-bit operation code. It also contains a test bench module that initializes test cases to verify the ALU functionality and displays the input, output and result values.

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74 views

Digital - System - Design Verilog Project

The document describes a 4-bit arithmetic logic unit (ALU) designed in Verilog. It includes the Verilog code for the ALU module which performs addition, AND, OR, XOR logic on 4-bit inputs A and B based on a 2-bit operation code. It also contains a test bench module that initializes test cases to verify the ALU functionality and displays the input, output and result values.

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Rüstem Eleç
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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Digital System Design

Verilog Project
Batuhan Kenan EREN – B1805.010034
Rüstem ELEÇ – B1805.010026
Question 1 Answer
Verilog code for a 4-bit ALU:
module ALU (input [3:0] A, B, input [1:0] op, output [3:0] result, output
carry_out, overflow);
// (4-bit adder)
wire [3:0] sum;
wire carry_in;
adder adder_4bit (A, B, carry_in, sum, carry_out);
// (4X1 multiplexer)
wire [3:0] mux_out;
mux4x1 mux_4bit (A, B, sum, op, mux_out);
// (2X1 multiplexer)
wire overflow_temp;
mux2x1 mux_overflow (overflow_temp, carry_out, op[1], overflow);
// (OR gate)
wire [3:0] or_out;
or or_4bit (A, B, or_out);
// (AND gate)
wire [3:0] and_out;
and and_4bit (A, B, and_out);
// (XOR gate)
wire [3:0] xor_out;
xor xor_4bit (A, B, xor_out);
// (Assign result)
assign result = mux_out;
// (Assign overflow_temp)
assign overflow_temp = ((A[3] & B[3] & ~sum[3]) | (~A[3] & ~B[3] &
sum[3]));
endmodule
Just go through tjis.
Here is the Verilog test bench for the above ALU:
module ALU_test;
// (Inputs)
reg [3:0] A;
reg [3:0] B;
reg [1:0] op;
// (Outputs)
wire [3:0] result;
wire carry_out;
wire overflow;
// (Instantiate the ALU)
ALU alu (A, B, op, result, carry_out, overflow);
// (Initialize test case values)
initial begin
A = 4'b0000;
B = 4'b0000;
op = 2'b00;
#1 $display("A: %b, B: %b, op: %b, result: %b, carry_out: %b, overflow: %b",
A, B, op, result, carry_out, overflow);
A = 4'b0000;
B = 4'b1111;
op = 2'b00;
#1 $display("A: %b, B: %b, op: %b, result: %b, carry_out: %b, overflow: %b",
A, B, op, result, carry_out, overflow);
A = 4'b1111;
B = 4'b0000;
op = 2'b00;
#1 $display("A: %b, B: %b, op: %b, result: %b, carry_out: %b, overflow: %b",
A, B, op, result, carry_out, overflow);
A = 4'b1111;
B = 4'b1111;

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