EHB 326E Introduction to Embedded Systems

Homework 4

Rana TİLKİ
040180741
 CALL / RETURN Stack: The CALL/RETURN hardware stack can store up to 31 instruction addresses. It
provides nested CALL sequences up to 31 levels deep. The CALL instruction executes a program counter
manipulation. With this instruction next instruction address is saved to the stack. With return instruction
the most recent address pops from the stack and resumes execution. Stack is also used in interrupt
operation so when interrupst are enable one of these levels should be allocated. If stack is full, oldest
value is overwrited.

Interrupts: Interrupt causes the microprocessor to stop its work and execute a different code instead it is
called ISR (interrupt service routine). So, this way interrupts can solve response problems without
creating new problems themselves. The picoblaze processor provides a single interrupt signal. For
recognition of the interrupt input signal it must be applied at least 2 clock cycle. After the recognition it
stops executing sequence of instructions that was executing and saves address of the next instruction to
be executed on the stack. the Picoblaze processor calls 3FF instruction by the force of interrupt. The CALL
3FF instruction subroutine calls the last memory location of program. 3FF location is an instruction
location that jumps to ISR. Then executes it. After the execution of ISR returns from ISR with a RETIRNI
command. Pops address from stack and continues normal execution of next instruction.

Assembly code of 10 nested interrupts:

#ifDef proc::xPblze6

#set proc::xPblze6::scrpdSize, 64 ; [64, 128, 256]

#set proc::xPblze6::clkFreq, 100000000 ; in Hz

#set IOdev::BRAM0::en, TRUE

#set IOdev::BRAM0::type, mem

#set IOdev::BRAM0::size, 4096

#set instmem::pageSize, 4096

#set instmem::pageCount, 1

#set instmem::sharedMemLocation, loMem ; [ hiMem, loMem ]

#set IOdev::BRAM0::value, instMem

#set IOdev::BRAM0::vhdlEn, TRUE

#set IOdev::BRAM0::vhdlEntityName, "BRAM0"

#set IOdev::BRAM0::vhdlTmplFile, "ROM_form.vhd"

#set IOdev::BRAM0::vhdlTargetFile, "BRAM0.vhd"

#endIf

#ORG ADDR, 0 ;Presets the memory address of the following instruction to 0

LOAD s2, 0 ;s2 is the interrupt counter

load s0, 0 ;initially s0 = 0

main: INT ENABLE ;Enables the interrupt engine

ADD s0, 1 ;increment s0 by 1 until s0 = 255

COMP s0, 255 ;if s0 < 255 C will be set and equals 1

JUMP C, main ;if C = 1, go back to the main

end: JUMP end ;if C != 1, it means s0 = 255, end the main code

;Interrrupt service routine

isr: load s2, 1 ;It is stated that there is an interrupt so, increment interrupt counter equals 1

CALL critical_timing

RETI DISABLE ;Executes a return at the end of an interrupt and disables further interrupts

critical_timing: INT DISABLE ;Disables the interrupt engine

INT ENABLE ;Enables the interrupt engine

ADD s2, 1 ;It is stated that there is an interrupt so, increment interrupt counter by 1

COMP s2, 10 ;Continue with critical_timing loop until there are 10 interrupts

CALL C, critical_timing ;if s2 < 10 go back to the critical_timing loop

RET ;return from call

#ORG ADDR, 4095 ;Presets the memory address of the following instruction to 0

jump isr ;jump to isr

In assembly code, the main code is simple summation code as in homework1. When simulation runs
interrupt is sent with the toggle interrupt button. It stops the execution at address 0x005 when s0 = 11
and goes to ISR. With the CALL critical timing subroutine interrupts enable and disable another nine
times. When s2 which is an interrupt counter is 10 subroutine is ended and go back to the RETI DİSABLE
instruction in ISR. So, this way after 10 nested interrupts go back to the address 0x005 where the
execution stops and normal execution continues.

Below PC can be seen.

Above figure shows that after the interrupts and before the RETI DISABLE instruction pops the address 5
from program counter. And s2 = 10 can be seen from sram.

After the interrupts instructions continue from where they left off.

Below figure shows that main executions end. S0 = 255.

After the fidex simulation BRAM_0 file is generated.

In Vivado top module is modified. The interrupt_0 signal is connected to the top port like below:

entity top is

Port ( clk : in STD_LOGIC;

in_port : in STD_LOGIC_VECTOR (7 downto 0);

interrupt_0 : in STD_LOGIC;

port_id : out STD_LOGIC_VECTOR (7 downto 0)

);

end top;
And also interrupt => interrupt_0 is connected in picoblaze: kcpsm6 port map.

After that, sim_top is modified as in below:

begin

clk <= '0';

wait for 5ns;

clk <= '1';

wait for 5ns;

end process;

process

begin

wait for 2000 ns;

interrupt_0 <= '1';

wait for 30 ns;

interrupt_0 <= '0';

-- wait for 30ns;

end process;

end Behavioral;

In simulation inteerupt is given after 2000ns and with 30ns intervals which is bigger than 2 clock cycle.
Then simulation is run.

When Interrupt (interrupt_0) is given after 2000 ns, 10 interrupt enable signals (interrupt_enable) are
observed as in above figure. s2 also counts the interrupts from 0 to 0A. Through the interrupt routine s0
is stays at 18 which is the value when interrupt is begin.

Above figure shows when interrupt routine begins, pc is at 003.

And below figure shows that after the interrupt routine ends pc returns 003 again.
For 32 Nested Interrupts;

In Fidex code nothing has changed except COMP s2, 32 to count 32 interrupts.

As it can be seen from below, when the interrupt is given s0 = 0E. 31 interrupts is observed and for 32nd
interrupt stack overflow error is given and execution stops. The reason of this error is program counter
stack can store up to 31 instruction addresses.

process

begin

wait for 4000 ns;

In vivado part is all same with the 10 nested loops, just
sim_top is modified like this; interrupt_0 <= '1';

wait for 30 ns;

interrupt_0 <= '0';

-- wait for 30ns;

end process;
When Interrupt (interrupt_0) is given after 4000 ns, 31 interrupt enable signals (interrupt_enable) are
observed as in above figure. 32nd interrupt cannot be observed because of the stack overflow. s2 also
counts the interrupts from 0 to 0e. Through the interrupt routine s0 is stays at 31 which is the value
when interrupt is begin. This can be ovserved from above and below figures.
Above figure shows when interrupt routine begins, pc is at 003.

And below figure shows that after the interrupt routine ends it is observed that pc returns 000 not 003. It
is because of the stack overflow. Therefore, after the interrupt routine ends s0 value will be 0 again
because of returning the address 000.