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Deld Insem QB

This document contains questions from two units related to digital logic design. Unit I questions focus on minimizing logic functions using K-maps and Quine-McClusky method, implementing functions using NAND gates, proving Boolean algebra rules, and converting between SOP and POS forms. Unit II questions cover combinational circuits including adders, subtractors, encoders, decoders, and multiplexers. Example applications include BCD addition, binary to gray code conversion, and designing full adders using multiplexers.

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53 views2 pages

Deld Insem QB

This document contains questions from two units related to digital logic design. Unit I questions focus on minimizing logic functions using K-maps and Quine-McClusky method, implementing functions using NAND gates, proving Boolean algebra rules, and converting between SOP and POS forms. Unit II questions cover combinational circuits including adders, subtractors, encoders, decoders, and multiplexers. Example applications include BCD addition, binary to gray code conversion, and designing full adders using multiplexers.

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SE DELD INSEM Question Bank

UNIT I

1. Minimize the following function using K-map and realize using logic gates:
F(A, B, C, D) = ∑m (1, 5, 7, 13, 15) + d(0, 6, 12, 14)
2. Represent the following signed number in 2's complement method:
i) +25 ii) -25
3. Minimize the following logic function using K-map and realize using logic gates
:F(A,B,C,D) = M(1, 5, 7, 13, 15) + d (0, 6, 12, 14).
4. Simplify the following function using Qunie-McCluskey mini-mization technique :Y(A, B,
C, D) = m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14).
5. Minimize the expression using Quine-Mc-Clusky method :
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD..
6. Represent the following signed number in 2’s complement method
(i) +17 (ii) –17.
7. Implement the following function using NAND only gates.Use K-map to minimize your
circuit
f(A, B, C, D) =(0, 2, 5, 6, 8, 10, 13, 15)
8. Simplify the following Boolean function by using Quine-McClusky method
F(A, B, C, D) = m(0, 1, 3, 7, 8, 9, 11, 15).
9. Implement each expression with NAND logic:
1)ABC+DE
2)ABC+D'+E'
10. Prove the given rules of Boolean algebra
i)A + A' B= A+B
ii)(A+B)(A+C) = A+ BC
11. Convert the SOP function into Canonical or standard form
F = AB + A C + B C
F = ABC + A'B'C + A'BC
12. Exaplain and prove De-Morgan's Law.
13. Convert following SOP form to POS form
F = ∑ x, y, z (0, 2, 3, 5, 7) = x' y' z' + z y' z' + x y' z + xyz' + xyz
14. Convert the POS function into Canonical or standard form
F = (p' + q + r) * (q' + r + s') * (p + q' + r' + s)

UNIT II

1. What is Combinational Circuit? Examples.


2. Design a 3-bit excess 3 to 3-bit BCD code converter using logic gate.
3. Design a 4-bit binary to Gray code converter circuit using logic gates.
4. What are the disadvantages of Half adder over full adder.
5. Implement Full Adder using Half Adder.
6. Implement Full Subtractor using Half subtractor.
7. Explain look ahead carry generator in detail.
8. Dsign full adder circuit using 4 : 1 Multiplexer.
9. Explain rules for BCD addition with suitable example and design a single digit BCD adder
using IC 7483.
10. What is the advantage of encoding a decimal number in BCD as compared with
straight binary ? What is adisadvantage ?
15. Implement full adder using 8:1 Multiplexer and draw the diagram.
16. Write the rules for BCD addition and give example.
17. Implement the expression using a 8 : 1 multiplexer.
f(a,b,c, d)=(0, 2, 3, 6, 8, 9, 12, 14)
18. A certain multiplexer can switch one of 32 data input pins to its output. How many different
input does this MUX have ?
19. Determine the output for the given input states:
D0 = 0,D1 = 1, D3 = 0,S0 = 1, S1 = 0. use 4:1 MUX
20. Implement Full-Adder using suitable De-MUX.
21. Design 2-bit magnitude comparator using logic gates to give output A>B, A=B, A<B inputs
are A(2-bit) and B(2-bit).
22. Design even parity generator circuit for 4-bit input using multiplexer.

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