Floor Planning

1. Tell me about yourself

2. What are the inputs required to start PnR?
PD Inputs include the following files:

a) Netlist File (it's a verilog file containing information related to logical connection between
standard cells)
b) LEF (Physical View of Cell. i.e. its size, area, orientation etc.)
c) Lib (It contains timing and power related information of cells).
d) Upf (It is used in low power design. It contains information related to which power domain being
used, what isolation cells are being used etc.)
e) TF (Technology file, it contains information related to which metal layers are used and what are
their width, resistivity and other parameters.)
f) SDC (It’s a synopsys design constraints file which contains information related to clocks. Which
clocks are being used. What is max trans, max cap. What is clock definition, latency, uncertainty.
What is path exceptions in design, i.e. false path, multi-cycle path etc.)
g) tluplus file: It contains information related to R & C values.
h) IO Assignment File

3. Issues faced in each stages

A. FloorPlan - While placing macros.
Macro count was in hundreds. Non uniform sized macros were there and I had to reserve
enough routing space around macros. I had to check the macro alignment, its orientation and
avoid the crisscross placement. Did multiple iterations to avoid notches.

B. Placement
a. Placed end cap cells, tap cells, IO buffers and then placed, standard cells. Then
used command place_opt to optimize the placement.
b. I got congestion due to Pin density and Cell density.
c. Pin Density – When pins for standard cells were more in a certain part due to use of AOI
and OAI. Used partial blockage and keep-out margin to avoid congestion of pin density.
d. Cell density – When certain standard cells were placed very closely. Used keep out margin
to reduce congestion due to cell density.
C. CTS
a. Timing Issues – setup and hold violation
b. Meeting skew and latency targets
c. Exception pin declaration was not proper
D. Routing
a. After routing I faced congestion which I fixed by detouring the nets.
b. Cross related issues
c. DRC issues
d. Timing issues
e. Antenna violation
4. What are the sanity checks you will do before FP?
Sanity Checks:
i. Netlist Checks – Check_design/ Check_mv_design (Checks the current design for
consistency).
ii. Sanity Checks – Check_timing (Checks for possible timing problems in the
current design).
iii. Library Checks – Check_library (Performs consistency checks between logic and
physical libraries, across logic libraries, and within physical libraries).
iv. Netlist vs SDC – Report_timing (Displays timing information about design).

5. How you will decide whether clk is reaching to flops or not?

With check_timing cmd we can check clk is reaching to flops or not.

6. How you will place if there are 200 macros?

According to hierarchy communication and flyline analysis, we can place macros.

7. How you will decide channel spacing?

Spacing = (no. of pins * pitch of routing layer)/no. of available layers in the preferred direction

8. Other than macros, what are the special cells you placed in FP?
Endcap, Tap cells

9. What is your analysis if timing is violating more before FP?

If timing is violating more then we need to report to synthesis team.

10. What are the checks you will do after placing macros?
I/O overlapping
Macros over lapping
Channel spacing
Notches

11. What are special cells?

Endcap
WellTap cells
Filler cells
Decap cells
Tie-high/Tie-low cells
Spare cells
Antenna diodes

12. What is latchup and how tapcell will avoid latchup violation?
The least resistive path from vdd to gnd due to 2 parasitic transistors npn and pnp is called latchup.
By adding tapcells in nwell & p-substrate in order to decrease resistance in nwell & psubstrate.
13. What is the purpose of endcap cell?
These cells are paced at the end of site rows by satisfying well tie off requirements for the core rows.
These ensures that gaps do not occur btn the well and implant layers i.e well proximity effect and this also
prevents drc violations by satisfying well tie off requirements for the core rows.

14. What will happen if you place macros in the middle of the core?
If macros are placed in the middle of the core it will block few layers and it will do detour routing because of
this type of placement and these causes congestion, timing issues.

15. Diff btw halo and hard blockage?

Halo can be moved along with macros but hard blockage will not move along with macros.

16. How you will decide floorplan is good or bad?

If we are able to meet target congestion and better timing, then we can say our floorplan is good.
Power Planning
17. Which layers you used for power planning and why?
We will do power planning in higher metal layers because metal width varies from lower metal layer to
higher layer. Higher layer consists of more width and resistance will be less in higher layer, so ir drop will
also be less. That is why we will do power planning in higher layer.

18. Checks in pwr planning?

Checks after power planning:
i. Connectivity should be verified.
ii. Any open, floating or dangling nets in the design.
CMDS
check_pg_missing_vias
check_pg_drc
check_pg_connectivity

Placement
19. How tool will place std cells inside the core area?
Two stages- 1. Course placement 2. Detail placement
1. Course placement:
a. First tool will place standard cells based on hierarchy
b. It will do High fanout net synthesis
Adding buffers to the high fanouts
c. Scan chain reordering
d. Logical
optimization Sizing
VT swapping
Buffering
 Logic
restructuring Pin
swapping Cloning
Rebuffering
Trail route
2. Detail placement
a. Area recovery
b. Congestion driven
c. Time driven
PLACEMENT OPTIMIZATION:
In optimization tool will optimize DRV’s and setup
timing Here we will not see hold because clock is ideal.
Checks in placement:
Cells legalization
Utilization
Area
Timing
Congestion

20. What is the cmd to see congestion?

report_congestion

21. In placement what are the congestion types, how to resolve congestion?
We will see congestion where available tracks are less than required tracks.
We may see congestion because of

 Cell density
 Pin density
 Bad floorplan
1. horizontal congestion and
2. vertical congestion

we will see horizontal congestion when horizontal tracks are less and similarly for vertical
congestion if vertical tracks are less

prevention techniques:

 we can avoid congestion by placing blockages.

 Cell padding
 Scan chain reordering.

22. What is the cmd to create placement blockage?

create_placement_blockage –type partial –boundary {} –blocked_percentage 50
 23. What are the types of blockages?
Placement blockages:
1. Hard blockage: It will not allow any cells inside the blockage.
2. Soft blockage: It will not allow std cell but it will allow buffers and inverters during optimization.
3. Partial blockage: It will allow only certain specified percentage of cells.
Routing blockage: It will allow only some specified metal layers inside the
blockage.

What is cloning?

After placing std cells, what are the checks you will do in placement?
Checks:
a. Cells Legalization
b. Congestion
c. Timing (setup)
d. Drv’s
e. HFNS
f. Density

24. Did you check hold timing in placement if not, why?

No, as clk is ideal we will check only setup timing.

25. What is your target congestion in placement and what happens if you do not meet target congestion?
Target congestion: 0.3% (both horizontal & vertical)
If we do not meet target congestion, we will get routing, timing issues & shorts.
Clock Tree Synthesis
26. Checks before cts?
Before CTS we need to check:

1. All cells should be legalized.

2. All power nets are prerouted.

3. All pins should be legalized.

 4. Congestion, timing should be in control.

GOALS OF CTS:

1. To minimize the logical DRCs.

2. Balancing the skew.
3. Minimum Insertion Delay.

27. What are the inputs required for cts?

INPUTS OF CTS:

1. SDC
2. SPEC FILE
3. Placement db
What is CTS?
To distribute a clock from Clock port to Clock pin

Why CTS?
To minimize skew and insertion delay to build the clock tree.
SPEC file contains:
 Clock name
 Clock period
 Max and min delay
 Max skew
 Sink max tran
 Buffer max tran
 Clock buffers and clock inverters information
 Exclude pin
 Through pin
 Information about Metal layers used
 Leaf route type
 NDR’S

28. What is skew and types of skew?

The clock delay diff btn launch clk and capture clk is called skew.
Types:
a. Local skew
b. Global skew
c. Positive skew
d. Negative skew

29. What is useful skew?

If clock skew is added intentionally to meet timing is called useful skew.

30. What are the checks you will do in cts?

i. Timing (setup/hold)
 ii. Utilization numbers
iii. Congestion
iv. All cells should legalize
v. DRV’s

31. What happens if we do not meet target skew?

If we do not meet target skew, timing will violate in further stages.

32. Why we need to minimize insertion delay?

As clk is high transition signal, cells on clk path consumes more power. So if number of clk cells reduces,
power consumption also can be reduced. That is why we need to minimize insertion delay.

33. What are drvs and what happens if drvs are violating?
DRV’S: Max tran, max cap, max fanout

If drvs are violating cell delays cannot be trusted because every cell is characterised with certain range of
targets. So if these exceeds cell delays cannot be trusted.

Routing
34. How tool will do routing?

STEPS INVOLVED IN ROUTING:

1. Global Routing
2. Track Assignment
3. Detailed Routing

GLOBALROUTING:
Router breaks the routing portion of the design into rectangles called gcells and assigns
signalnets to gcells.
The global router attempts to find shortest path through gcells but does not make
actual connection or assign nets to specific nets and to specific track within gcell.
TRACKASSIGNMENT:
In this step the nets are properly assigned on tracks.

DETAILED ROUTING:
Nanoroute follows global routing plan and lays down actual wires that connect
pins to their corresponding nets.
It creates shorts and opens or spacing violations rather than leaving unconnected nets.
We can route detailed routing on entire design, a specified area of design on
selected nets.
Router runs SEARCH AND REPAIR ROUTING during detail routing.
It locates shorts and opens and spacing violations so, it reroutes the effected
area to eliminate violations.

35. Checks in routing?

Timing (setup/hold)
DRVs
Congestion
DRCs
Utilization

36. What are timing optimization techniques?

Buffering
Cell sizing
Vt swapping
Logic restructuring
Layer changing

37. What is timing report? What does it contain?

Startpoint: in1 (input port locked
by clk)
Endpoint: out1 (output port clocked
by clk)
Path Group: clk1
Path Type: max

clock clk (rise edge) 0 0

clock network delay (propagated) 0 0
input external delay 7500 7500.00 f
in1 (in) 142.37 7642.37 f
 i1/INPUT1 (iinvc) 0.33 7642.70 f
i1/OUTPUT1 (iinvc) 1469.09 9111.79 r
out1 (out) 14.66

clock clk (fall edge) 10000 10000

clock network delay (propagated) 0 10000
output external delay -6000 4000
data required time 4000

data required time 4000

data arrival time -9126.45

slack (VIOLATED) -5126.45

38. How you will fix setup/hold violations?

Setup fixing techniques:
 Upsizing
 VT swapping
 Pulling launch clock path
 Pushing capture clock path

Hold fixing techniques:

 Downsizing
 VT swapping
 Pulling capture clock path
 Pushing launch clock path
 Insert buffer in data path

39. What is max tran range?

It is the range given in SDC file, if transition delay crosses that range we will see tran
violations.

40. What type of reasons for Max Tran violations?

The reasons for Max Tran violations

 When long nets are present

 When the driver cell load capacitance is high
 When driver cell drive strength is less

41. Which technique you will apply first to fix setup/hold?

 Vt swapping, sizing, ABOR

42. What is your analysis if timing is violating and how you will fix?
First we need to open timing report and do analysis like which cell is giving more
delay. Based on that need to apply techniques to fix.

43. What is uncertainty & what it contains?

It is used to tight the constraints. It is the extra margin added in the design for future
use.
It contains: Net delay, Skew, Ocv, Jitter, Crosstalk, tool margin.

44. How uncertainty varies from stage to stage?

It varies from stage to stage.
In synthesis we will start with 20% margin but when coming to route stage only jitter
will be left. All other margins will be removed as real delay comes into picture.

45. What is crosstalk & types of crosstalk?

The voltage transition from one net to another net through coupling capacitor
known as Crosstalk.

There are two types:

1. Crosstalk Noise
2. Crosstalk

Delay Crosstalk

Noise:

If aggressor switches and victim is constant is known as Crosstalk noise.

Aggressor net will create spikes on victim net and this effects chip

reliability and causes chip failure.

Crosstalk Delay:

If aggressor and victim net both switches in same direction then delay

decreases and this will effect hold timing.

 If aggressor and victim switches in opposite direction, delay increases

and causes setup timing violation.

46. What if there is crosstalk violation, how it will affect timing?

Crosstalk will effect timing violation. Delay can inc/dec that depends based on
switching direction of nets.

47. What is PVT?

PVT- Process Voltage Temperature
Best case: fast process, highest voltage and lowest temperature
Worst case: slow process, lowest voltage and highest temperature
Normal case: normal process, normal voltage, normal temperature

48. Explain routing which net will you route first ?

Firstly, routing will be done for power domains, then for clock domains and last for
data signals.

49. What is OCV?

When the chip is in operation the variations in pvt is called ocv.
Deratings are used to model ocv effect.

50. Diff btw ocv, aocv and pocv?

OCV:

Minor changes in delays due to the variations in PVT conditions. As cell

delays are varying we will apply a global derating factor then every cell having min and
max delay. All the cells are applying with same derating factor.

AOCV:
Here we r applying a derating factor based on logical depth and distance.
OCV is more pessimistic than AOCV so we r going for AOCV.

POCV [Parametric On Chip Variation]:

It uses a statistical approach, it calculates delay variation by modeling the intrinsic

cell delay and parasitic of load which determines sigma and mean of a logic stage.

Static Timing Analysis (STA)

51. Inputs for STA?
Route db, spef, SDF

52. Inputs for Star rc and inputs for pt shell ?

 Star RC - .v, DEF, Tech file, Output - SPEF file

53. Checks in STA?

Timing, DRVs, min pulse width, Crosstalk

54. What are the diff steps performed in STA ?

3 steps :
Design is broken into set of timing paths
Calculates signal propagation delay along each path.
Checks for violations of timing constraints inside the design and at the input/output
interface.

55. What are diff timing paths ?

Data path
Clock path
Clk gating path
Asynchronous path

56. How you will fix if there are 20k hold violations?

First we should see the WNS, and if it is of same clock or different

clock, if it is of different clock we can fix those violations using pushing
and pulling. If it is of same clock then we should see it is single start
point or multiple start points, if it is single start point then we can
forward trace till the divergent point and fix the violations by
observing the setup margin, if it is multiple start points then we
should analyse the paths individually and fix the
violations by observing the setup margin, if there is no setup margin
then we should get the setup margin and then fix the hold violation.

57. For suppose, if drvs, setup, hold are violating, which one you will try to fix and
why?
I will try to fix drvs first, next setup then hold.

58. What is IR drop and how you will fix?

Each metal layer has some resistance when current flows through metal it consumes
some current nothing but IR drop. Decap cells are used to fix IR issues.

59. What sdc file contains?

Clock definitions:
  Create clock,
 Create generate clock,
 Clock uncertainty
 Input delay
 Output delay
 Virtual clock
DRVs:

 max tran,
 max cap,
 max fanout

Timing exceptions:

 false path,
 multicycle path,
 max delay,
 min delay
 case analysis

60. What is the cmd to create clk and generated clk?

create_clock [get_ports{clk}] –name pclk –period 10 –waveform {4 8}
create_generated_clock –name clk –source PLL –divided_by 2 [get_pins uff0/q]

61. What is antenna effect?

It is a gate damage that can occur due to charge accumulation on metals and
discharge to a gate through gate oxide. These are normally expressed as an
allowable ratio of metal area to gate area greater than allowable area.

62. What is setup/hold?

SETUP: Minimum time required for data stability before the clock edge.

HOLD: Minimum time required for data stability after the clock edge.

63. What are the Setup fixes after Base Tapeout?

Fixes of Setup after Base Tapeout are:
 Metal width is increased.
 Metal jogging from lower metals to higher metals.
 Use of spare cells when net is dominating.
 We can use metal buffers when net is dominant.
 Frequency can be reduced.
64. What are the Hold fixes after Base Tapeout?
 Fixes of Hold after Base Tapeout are:
 Metal width decreases.
 Net deteriorate.
 Using spare cells.

65. What happens if we have setup and hold violations in our design?
setup and hold timings are to be met in order to ensure that data launched
from one flop is captured properly at another and in accordance to the state
machine designed. In other words, no timing violations means that the data
launched by one flip-flop at one clock edge is getting captured by another flip-flop at
the desired clock edge. If the setup check is violated, data will not be captured
properly at the next clock edge. Similarly, if hold check is violated, data intended to
get captured at the next edge will get captured at the same edge. Moreover,
setup/hold violations can lead to data getting captured within the setup/hold
window which can lead to metastability of the capturing flip-flop. So, it is very
important to have setup and hold requirements met for all the registers in the
design and there should not be any setup/hold violations.

66. What is EM?

When high current flows continuously through a metal, due to that high current
metal will break. So we will see opens because of EM violations.

67. What is scan chain reordering?

Rearranging of routing to avoid congestion and timing issues.

68. What is clk gating?

Clk gating is one of the power optimization technique used in design.
It will switch off unwanted clock switching where not in use.

69. What are path exceptions?

False path
Multicycle path
Disable arc

70. What is Multicycle Path?

The path which takes more than one cycle to capture the data is called Multicycle
path.

71. What is Asynchronous Clocks?

The clocks from different sources are called Asynchronous Clocks.

72. What is the cmd to get drv reports?

report_constraints –max_transition –max_capacitance
73. Cmd to dump setup/hold timing reports?
Setup: report_timing –delay_type max –path_type full_clock –max_path 1000 >>
setup.rpt
Hold: report_timing –delay_type min–path_type full_clock –max_path 1000 >>
hold.rpt

74. What is CRPR?

When launch and capture clock share a common path, the common path min delay
and max delay will add additional pessimism to both setup and hold analysis. CRPR
can be used to remove this pessimism.
CRP = latest arrival time to common point – Earliest arrival time to common point.

Explanation:
In the below figure, you can see that there is a common path in the launch clock
path and capture clock path.
When delay is going to calculated based on the min/max delay concept, then the
common path have 2 different values. For example in case of setup analysis, we
calculate the maximum delay for the launch clock path and the minimum delay for the
capture clock path. But practically same set of cells can't behave different for
different clock path.
In a physical design, however, the cells along the common portion of the clock tree
cannot simultaneously achieve their maximum and minimum delay values. Thus
there will be a single value of delay of the common path that will be propagated to
both the launching and capturing clock paths.

Therefore our timing report contains artificially introduced pessimism that is derived
from our usage of max and min delay for the launching and capturing paths along
this common portion of the clock network. The value of this pessimism is the
difference between max and min delay at the common point in the clock network.

We can remove this pessimism with the help of CRPR (an automated concept of
removing in the EDA tools).
In general, it’s not recommended to enable CRPR (automated way to correct CRP)
mode by default during the analysis of timing violations because it takes a lot of
time (Tool run time increases a lot). Without enabling CRPR, we calculate the slack
 or say timing violations. If everything is good then no need to enable CRPR analysis
mode but if there are violations in certain paths, we can enable CRPR mode in the
tool for those selective paths.
Tool automatically removes the pessimism (as per its algorithm) and then checks
the violations. Now if number of violations decrease (which should be), then the
final number of violations are considered as real violations because the remaining
violations are practically possible violation (at least not considering non-practical
situation of having min and max delay simultaneously in few cells in clock path).

75. Diff btw normal cell and clk cell?

Clk cells are specially built with equal rise and equal fall time.
Gives less delay when compared to normal cells.

76. Diff btw technologies?

Lower Technologies < 28nm Higher Technologies > 28nm

1. Transistor sizes are very small Transistor sizes are big.

2. Num of transistors increases. Less num of transistors.
3. More drc issues. Less drc issues.
4. More rc values. Less rc values.
5. More timing violations. Less timing violations.

77. Diff btw vt flavours?

LVT SVT HVT

Less delay Moderate delay More delay

More leakage power Moderate leakage power Negligible leakage power

78. Timing is good in cts but violating in routing, what could be the reason?
Need to check constraints.
Crosstalk issue.

79. In which stage you will apply deratings?

Placement

80. What is the use of filler/Decap/spare/tie-high, tie-low cells?

Filler cell
Filler cells are used to provide power rail and nwell continuity.
Decap cell
Decap cells are used to avoid ir drop issues.
Spare cell
Spare cells are extra cells added in design, used in eco stage.
Tie-high/Tie-low cell
 Some cells constantly require logic high and logic low instead of tying gate to vdd &
gnd, these cells are used in order to avoid cell damages.

81. In which stage you will place filler cells?

After post route

82. What are the techniques to fix crosstalk?

Shielding
Buffering on victim net
Downsizing driver on aggressor net
Applying NDRs

83. What is STA?

STA is a method of validating the timing performance of a design by checking all
possible paths for timing violations under worst case conditions.

84. Is SDC mandatory in floorplan?

No, because SDC contains clock definitions, delays, DRV’s and exceptional paths so in
floorplan we don’t need all this information.

85. Write setup and hold equations?

Setup = Required Time – Arrival Time
Where Required Time= clock period+capture clock path latency – library setup –
setup uncertainty
Arrival time= launch clock path latency + clock to Q delay + comb delay

Hold = Arrival Time – Required Time

Where Required Time= capture clock path latency+library hold +hold uncertainty
Arrival Time = launch clock path latency + clock to Q delay + comb delay
86. What is the time period of the clock with 500MHZ frequency and draw a clock
waveform?
87. Create a clock with 10ps period and rise edge 4ps and fall edge 8ps

create_clock [get_ports{clk}] –name pclk –period 10 –waveform {4 8}

88. What is the cmd to know total number of macros in design?
sizeof_collection [get_cells * -hier –filter “is_hard_macro==true”]

89. Cmd used to select macros?

change_selection [get_cells * -hier –filter “is_hard_macro==true”]

90. What are mandatory things for generate clock

Source master pin

Divided by /multiple by factor

91. Command to create generated clock

create_generated_clock –name clk –source PLL –divided_by 2 [get_pins uff0/q]

92. What is LVS?

Layout vs Schematic

Inputs: lvs.v, GDS II and rule deck file.

 Source netlist(physical) and reference netlist(logical) are converted

in spice netlist
 LAYOUT: It takes source netlist into spice netlist
 SCHEMATIC: It takes reference netlist into spice netlist.
 LVS means comparison of layout and schematic spice netlist
 Spice netlist will count transistors and connectivity
 If layout and schematic netlist are equal, we can
proceed otherwise it will give below violations
o Shorts
o Opens
o Floating nets
o Pin mismatches
o Component mismatch
CMOS inverter

CMOS transistor explanation

The main advantage of CMOS over NMOS and BIPOLAR technology is

the much smaller power dissipation. Unlike NMOS or BIPOLAR
circuits, a Complementary MOS circuit has almost no static power
dissipation. Power is only dissipated in case the circuit actually switches.
This allows integrating more CMOS gates on an IC than in NMOS or
bipolar technology, resulting in much better performance.
Complementary Metal Oxide Semiconductor transistor consists P-
channel MOS (PMOS) and N-channel MOS (NMOS).
NMOS

NMOS is built on a p-type substrate with n-type source and drain

diffused on it. In NMOS, the majority carriers are electrons. When a
high voltage is applied to the gate, the NMOS will conduct. Similarly,
when a low voltage is applied to the gate, NMOS will not conduct.
NMOS are considered to be faster than PMOS, since the carriers in
NMOS, which are electrons, travel twice as fast as the holes.

PMOS

P- channel MOSFET consists P-type Source and Drain diffused on an N-

type substrate. Majority carriers are holes. When a high voltage is
applied to the gate, the PMOS will not conduct. When a low voltage is
applied to the gate, the PMOS will conduct. The PMOS devices are
more immune to noise than NMOS devices.CMOS Working Principle

In CMOS technology, both N-type and P-type transistors are used to

design logic functions. The same signal which turns ON a transistor of
one type is used to turn OFF a transistor of the other type. This
characteristic allows the design of logic devices using only simple
switches, without the need for a pull- up resistor.

In CMOS logic gates a collection of n-type MOSFETs is arranged in a

pull-down network between the output and the low voltage power
supply rail (Vss or quite often ground). Instead of the load resistor of
NMOS logic gates, CMOS logic gates have a collection of p-type
MOSFETs in a pull-up network between the output and the higher-
voltage rail (often named Vdd).

Thus, if both a p-type and n-type transistor have their gates connected to
the same input, the p-type MOSFET will be ON when the n-type
MOSFET is OFF, and vice-versa. The networks are arranged such that
one is ON and the other OFF for any input pattern as shown in the figure
below.

CMOS offers relatively high speed, low power dissipation, high noise
margins in both states, and will operate over a wide range of source and
input voltages (provided the source voltage is fixed).