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Decoupling capacitor optimization by spectral current-based power delivery

network impedance formulation for SSD/eMMC/uSD card

Article · January 2014

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DesignCon 2014

Decoupling Capacitor
Optimization by Spectral
Current-based Power Delivery
Network Impedance Formulation
for SSD/eMMC/uSD Card

Jongjoo Lee, Samsung Electronics

[email protected] / [email protected]

Joon Ki Paek, Samsung Electronics

[email protected] / [email protected]

Kwangsoo Park, Samsung Electronics

Juhwan Lim, Samsung Electronics

Jongyun Yun, Samsung Electronics

Joonhee Lee, Samsung Electronics

Abstract
New target impedance of a power delivery network (PDN) for memory cores is
formulated with rigorous experiments and analyses for optimal design of memory-
incorporated digital systems, which is based on the current spectra of mobile DRAM and
NAND-Flash memory. We also extended the new target PDN-Z equation to include the
power noise coupling from the I/O power to the core power using the self and the transfer
impedances and current profiles. The new target PDN-Z specification was applied to
optimize the PCB design and the decoupling capacitors of Flash solution products such as
SSD, eMMC, eMCP, and uSD memory card. We have successfully achieved the world-
best competitiveness particularly in SSD design with minimal number of decoupling
capacitors.

Author(s) Biography

Jongjoo Lee (S’99 - M’02) received the B.S. degree in electronics from Kyungpook
National University, Daegu, Korea, in 1994, and the M.S. and Ph.D. degrees in electrical
engineering from the Korea Advanced Institute of Science and Technology (KAIST),
Daejeon, Korea, in 1997 and 2001, respectively. His doctorial dissertation concerned the
development of photoconductive vectorial electric near-field probes using
micromachining for transient mapping of picosecond electric-pulse propagation
phenomena. In 2002, he joined the Package team, Memory division, Samsung Electronics,
Hwasung, Korea, where he led SI/PI group developing SI/PI co-simulation and high-
performance distinguished packages and standardizing memory packages, as a senior
engineer. After leading EMI TF at the DRAM design team from 2009 to 2010, he
appointed to the Flash solution development team, where he is currently a Principal
engineer leading SSD design and Mobile ecosystem. His recent interests cover from
device-level SI/PI/EMI to set-level co-design. He is a listee of international biographical
reference books from 2008.

Joon Ki Paek received the B.S. degree in electronics and electrical engineering from
Yonsei University, Seoul, Korea, in 2003 and the M.S. and Ph. D. degree in electrical and
computer engineering from KAIST, Daejeon, Korea in 2005 and 2009, respectively.
Since 2009, he is working in Samsung electronics and his research interests are
SI/PI/EMI and PCB design of package and set board.

Kwangsoo Park received the B.S. degree in electronics from University of Seoul, Korea,
in 2000 and the M.S. degree in electrical engineering from Seoul National University,
Korea, in 2002. In 2002, he joined the DRAM-Module Development team, Samsung
Electronics, Hwasung, Korea, where he worked as an SI/PI engineer from 2002 to 2007,
and has been working at the Flash Development team as an SI/PI senior engineer for SSD
since 2008.
JuHwan Lim received the B.S., M.S., and Ph.D. degrees in electronics from Korea
University, Seoul, Korea, in 2001, 2003, and 2008, respectively. Since 2008, he has been
a senior engineer at Samsung Electronics.
His research interests are signal/power integrity and RF interference for high speed
mobile DRAM/NAND product and its applications.

Jongyun Yun received the B.S. degree in electronics from Kyungpook National
University, Daegu, Korea, in 1988, and is studying MBA from the SungKyunkwan
University, Seoul, Korea, in 2013. He joined the HDD Development, Samsung
Electronics, Hwasung, Korea, where he led signal processing and read/write channel
design for high-performance magnetic storage device as a vice president by 2011. He
joined the Flash Solution Development team in 2011 where he is currently a Vice
President leading SSD development team. His recent interests are server and data center
storage systems.

Joonhee Lee received B.S. degree in electronics from Hongik University, Seoul, Korea,
in 1985, and the MBA from SungKyunKwan University, Seoul, Korea, in 2010. He
joined Samsung Semiconductor, Giheung, Korea, in 1984, and he had worked at the
DRAM PE team, the Application Engineering team, and the Module Development team.
He is a Vice President since 2008, and currently the leader of ‘Solution Development
team’ which develops eMMC, eMCP, UFS, uSD card, SSD and other flash storage
solutions.
Introduction

One of the most important objectives of an electronic system’s power delivery is to

supply every IC with enough charges for proper operation of the IC up to target speed.
Therefore, the power delivery network (PDN) as a real path for the power delivery must
be designed carefully to secure the required properties that was generally low impedance
up to high frequency, because a poor PDN can induce large supply voltage fluctuations
and then invoke malfunction of the logical circuits of an IC as well as jitter/timing issues
[1], electromagnetic interference problems [2], and electrostatic discharge issues. On the
other hand, excessive PDN design using many passives such as decoupling capacitors
and assigning separately isolated power planes will lead to increase of BOM cost and
failure possibility during manufacturing, making impractical especially at a form-factor
limited mobile product. The PCB real estate of a mobile product is generally very small
and dense, and a large number of passives such as decoupling capacitors can increase the
defective rates of a system during manufacturing-process and user-field, because the
failure at a passive also leads to a system failure. Therefore, the adequate PDN design for
a system will be a key in success of a practical high-performance system. Actually, the
power-fluctuation noise within a certain level has negligible effects on most of digital
systems so that the design target of a PDN is to make the maximum voltage drop seen by
an IC smaller than the certain level, which is the allowable limit. Although the certain
level was usually specified as the 5 ~ 10% fluctuation of a supply voltage level thus far,
the 10% is really double of the 5% and the time-domain value is difficult to clarify due to
the intrinsic irregular superposition effect of time-domain waveforms. Therefore, the
definition of the certain level becomes most important in attaining an effective PDN
design, and the PDN impedance (PDN-Z) has been used as an indicator of a PDN
performance where the target PDN-Z becomes the certain level.

The target PDN-Z defined in time domain as the allowable voltage fluctuation divided by
the amount of total IC current consumption [1] [3] has been a constant for a long time so
that many decoupling capacitors have been used to maintain the PDN-Z below the
constant target PDN-Z. However, the constant target PDN-Z could result in an over-
design, since the actual PDN-Z is frequency-dependent and the operating current of an IC
is also frequency-dependent and decreases as frequency increases, in general. Recently,
some literatures [4] [5] started to reflect the frequency-dependent current spectrum
property to define a frequency-varying target PDN-Z. Nevertheless, the basis is still the 5
~ 10% fluctuation of supply voltage in time domain making the target PDN-Z value
ambiguous in frequency domain. Because the immunity of a circuit on power supply
noise is dependent on a company’s micro-fabrication and circuit design methods, the
allowable limit must be determined with experiments on real products. In this paper, we
performed rigorous experiments on memory devices to secure the allowable limit of the
voltage fluctuation and more specifically the target PDN-Z in frequency domain, and
then we succeeded in formulating the new target PDN-Z for memory devices’ core
powers for the first time.

In defining the target PDN-Z’s of memory devices, we focused only on the core powers
because the PDN property is the most important off-chip factor affecting to the
performance of a device’s core blocks. For I/O powers, on the other hand, the PDN is one
of the factors affecting to the I/O signal quality so that the performance of an I/O-PDN
must be analyzed as the impact to the I/O signal integrity by using such as SI/PI co-
simulation [6][7]. In this paper, we firstly introduce the experimental method we used
and the resulting formulation of the memory core’s target PDN-Z. And then we verify the
new target PDN-Z formula by applying it to the design of Flash memory-incorporated
solution products such as SSD, eMMC, micro-SD card for the optimization of their PDN
design with minimal number of decoupling capacitors.

Target PDN-Z Criterion

To setup the target PDN-Z criterion, we designed an experiment with a special test board.
Using the current profile of a CPM (chip power model: composed of current spectrum
and on chip PDN) of a LPDDR2 DRAM core power and the PDN-Z profiles of many test
cases (we find the border of pass/fail condition), we found the target PDN-Z. Following
is the detailed illustration.

The Test Board and Experiment setup

Because the PDN for I/O power must be analyzed with signal integrity using such SI/PI
co-simulation method, we focused on core PDN. Figure-1 shows the schematic of power
networks for the test board. Power nets of the memories and the accompanying
components are isolated by using dedicated voltage regulators (VRs) and ground-shielded
power planes with a 16-layer PCB to prohibit noise cross-coupling. Each power net of the
memories in a package is separated. The core power of a LPDDR2 DRAM (VDD2 net)
was selected for PDN-Z experiment.

Figure-1: Power Network Architecture of Test Board

Figure-2 shows the test board and vehicle. The vehicle is an eMCP which consists of an
LPDDR2 DRAM, 4 NAND-flash memories and an eMMC controller. Each power net of
the eMCP substrate was designed to be separated and the chips were arranged the all chip
pads to be exposed from the top-side as shown in the inset of Figure-2.
A PDN-Z for a chip power is desirable to be defined at the chip pad to evaluate the PDN-
Z effects on a device performance. So, we de-capsulated the EMC of the package
chemically to expose the chip pads of each device for VNA micro-probing for exactness,
although a matrix transformation from a board to a chip pad can be used [5]. Figure-3
shows the measurement method. The de-capsulated package was put into a specially
designed socket which has thin 4-corner pressing-nodes, and then VNA micro-probes
was used to measure the PDN-Z at the power-ground chip pads. The board operation was
monitored through an application processor control program on a PC, whether at normal
status or at failed status.

Figure-2: Test Board and Test Vehicle (eMCP: LPDDR2 DRAM + eMMC)
The colored ballmap of LPDDR2 portion of the eMCP indicates the Power and the Ground balls.

Figure-3: Measurement method

Experiment Results

For reliable testing of many cases, we checked the reproducibility and the repeatability of
the measurement at first, and the test method and environment were reliable enough to
ensure the results.

The original test board operated well. We changed the PDN-Z of the LPDDR2 DRAM
core power (VDD2) by varying the number of package power/ground balls and
decoupling capacitors on the test board. As we reduce the number of decoupling
capacitors and package balls, the system PDN-Z measured at chip pad increases as shown
in Figure-4, where reducing the package power/ground balls shown in Figure-4(a) was
more effective than the decoupling capacitors in Figure-4(b) in affecting the system
PDN-Z.

(a) (b)
Figure-4: PDN-Z plots measured at chip pad of VDD2, reducing the number of
package balls (a) and on-board decoupling capacitors (b).

(a) (b)
Figure-5: (a) PDN-Z plots of the VDD2 net where the bold reds represent failed ones.
(b) Core current spectrum of the DRAM (Burst Write mode)

To find out the border of PDN-Z between the pass and the fail, the VDD2 PDN-Z of the
LPDDR2 DRAM was measured at chip pad in many cases. Figure-5(a) plots the
measured PDN-Z’s, where the bold red graphs are measured ones when the DRAM
operation was failed and the blue graphs are for normal DRAM operations. Figure-5(b) is
the current spectrum of the DRAM VDD2 when it is in the write burst operation which
uses most core current meaning the worst power noise condition.

Figure-6: PDN-Z plots vs. target PDN-Z definition for LPDDR2 DRAM core power

The resulting VDD2 PDN-Z graphs shown in Figure-5(a) were re-plotted to categorize
into a safe group (lower blue ones) and a fail group (upper red ones) as shown Figure-6
by removing the safe PDN-Z plots in the fail group for analysis convenience. The green
graph is the inverse of the DRAM core current spectrum scaled to touching the top PDN-
Z graph in the lower safe group, meaning the target PDN-Z. That is, the scaling factor
0.05 in the y-axis becomes the allowable voltage fluctuation limit in frequency region,
leading to 4% ripple criterion for the 1.2V DRAM core VDD2 supply voltage at the peak
current frequency.

Figure-7: Experimental setup for specifying target PDN-Z of NAND core power
The same experiment was performed for the core power of a NAND-Flash memory. In
the NAND core power, however, there was no fail condition at the test board. As shown
in Figure-7, therefore, we fed NAND core power with a long twisted-cable from an
external DC power supply instead of the VR on the test board.

Figure-8 shows the similar graphs with the ones in Figure-6 validating the target PDN-Z
criterion also on the NAND-Flash memory core power. In Figure-8, the blue graph is the
inverse spectral current-based target PDN-Z of the NAND core power with the 4% in-
frequency criterion. The black graph is the PDN-Z of NAND core power with the on-
board VR feeding and the green graph is the PDN-Z for the feeding with the twisted
cable through an external power supply shown in Figure-7. The NAND with the twisted
cable feeding still operated well. On the other hand, The NAND was failed when the
cable was untwisted and widened making the loop inductance of the cable large.
Therefore, Figure-8 indicates that the target PDN-Z specification defined with the 4% in-
frequency criterion can also be used effectively for the NAND core power design.

Figure-8: Resulting PDN-Z plot for a NAND core power

Formulation of New target PDN-Z

In applying the target PDN-Z specification to real products, however, the noise coupling
from other powers to the memory core power must be additionally considered, because
cost-effective real packages and system boards cannot be designed like the test board
which used a sufficient metal-layered PCB and separately dedicated VRs. In the case of
SSD, for example, a DRAM I/O power and a controller DDR IP power as well as a
DRAM core power all share the same VR with an on-board PDN. So, we adopted the
transfer impedance to include the noise coupling effect from the I/O power to the core
power as follows:
 ∆ %
(1)

where , , , and are the self impedance which was considered as the PDN-Z
thus far, the transfer impedance between the two power domains, and the I/O and the core
current spectra, respectively. The effectiveness of this newly derived target PDN-Z
formulation was validated though applying to real products. Followings are the detail.

Product Application Results

SSD

In designing an SSD with a smaller-sized PCB than a conventional one for 2.5” to save
cost, we applied the new target PDN-Z specification equally to all I/O powers and a
controller core power as well as memory core powers except host/SATA-related powers
to optimize the PCB design and the number of decoupling capacitors on each PDN. The
number and the size of decoupling capacitor are important to save and secure a PCB real
estate. Figure-9(b) is the small-sized PCB designed with the analyses formulated in this
paper.

Figure-9: (a) SSD in a conventional 2.5” size,

(b) SSD with a small-sized PCB designed using the techniques of this paper.

Figure-10 shows the simple power connections of the SSD in test. The SSD consisted of
a controller package, a DRAM package, and multiple NAND packages supporting 8 I/O
channels and up to 8 ways for high density. Actually, a PMIC integrating every VR into a
chip was used and each output channel of the PMIC is in SMPS type for high power
efficiency so that inductor(s) and capacitor(s) are accompanied for regulating the
switching pulses to DC-like power supply. Simple description of the target vehicle’s
power connections in interest is as follows.

- 3.3V NAND power: only for NAND core, but all NANDs share a PDN.
- 1.2V DRAM power: DRAM core, DRAM I/O, and controller DDR IP share a PDN.
- 1.8V NAND power: NAND I/O and controller FMC share a PDN.
 Figure-10: PDN architecture of an SSD

The graphs in Figure-11 are the PDN-Z plots showing the relationship in equation (1) for
the DRAM interface of the SSD, where the green graph is the target PDN-Z of the SSD’s
DRAM core power specified from spectral core current spectrum of the DRAM. The blue
one is the self impedance of the designed real SSD-PCB, and the red one is the PDN-Z
calculated by equation (1) to include the power noise coupling from I/O to core. The
PDN design in Figure-10 meets the specification with a lower PDN-Z (red one) than the
target PDN-Z (green one).
Actually I/O PDN-Z can also be pre-evaluated using the same method only with the
exchange of I and I in equation (1), where the self impedance is defined at the chip
pad of I/O power instead of core power.

Figure-11: PDN-Z
Figure-10: relationship
PDN-Z in equation
relationship (1) for for
in equation(1) the an
DRAM in the
DRAM test SSD.
in SSD
The green graph is the target PDN-Z of the DRAM core power,
the red one is the PDN-Z calculated by equation (1) for that of the SSD-PCB.
Figure-12 shows the simulated PDN-Z graph of the SSD NAND. There are 8 NAND I/O
channels. Because the I/O current effect on the target PDN-Z {the second term in
equation (1)} generally occurs at high frequencies above MHz and the margin from
specification to real PCB PDN-Z is very large as can be seen in Figure-12, we consider
only the self and transfer impedances. In Figure-12, the black graph is the PDN-Z at a
NAND core power chip pads and the red one is the sum of that and the 7 transfer
impedances from other 7 NAND I/O channel powers, without any decoupling capacitors.

Black graph: | | 
Red Graph: | | 

Though the red graph violates the target PDN-Z specification (green graph in Figure-12)
at low frequencies below 40 kHz, it moves to the dotted blue graph with the regulating
inductor and capacitors of VR, meaning the satisfaction of the target PDN-Z specification.
With the VR inductor and capacitors, therefore, the NAND core PDN can be designed
with no decoupling capacitors satisfying the target PDN-Z criterion defined in this paper.

Figure-12: NAND Core PDN-Z’s of the SSD vs. the target PDN-Z (green graph).
Black graph is self impedance, red one is the sum of self and transfer impedances,
and dotted blue one is the real PDN-Z including the transfer impedances and the VR-
regulating inductor and capacitors.

The resulting SSD shown in Figure-9(b) was designed having about 43% reduced
decoupling capacitors which led to around 37% reduction of total capacitors in the SSD
compared to the previous one. Figure-13 is the resulting shmoo’s on the NAND interface
speed measured during the real operation of the SSD, showing the same performance
with the previous one having many decoupling capacitors. Therefore, we can say the
target PDN-Z specification can be effectively used for the optimization of PDN design
and decoupling capacitors at a real product such as SSD.
 Figure-13: NAND operating speed shmoo.
Left: previous SSD with many decoupling capacitors,
Right: small-size SSD with optimized decoupling capacitors.

eMMC & micro-SD memory card

An eMMC is actually mounted on a system board as a package and a micro-SD (uSD)

memory card is inserted to a uSD socket mounted on a system board so that they don’t
need on-package/card decoupling capacitors for NAND core powers as it can be inferred
from Figure-8 and Figure-12. In case of uSD card, NAND I/O circuits use the same
external power with the core due to the low-speed operation. Actually, the SI/PI co-
simulation [6] [7] showed the NAND interface didn’t need any decoupling capacitors
also due to the relatively low I/O speed. As operating speed increases, however, the need
for a decoupling capacitor is increasing to isolate noise coupling between I/O and core in
accordance with real PCB design. To support the UHS-I specification of uSD and to
operate the I/O circuits of the Toggle 2.0 NAND-Flash memory in 1.8V high-speed
SSTL signaling [8], low-dropout (LDO) voltage regulation circuits were implemented on
eMMC and Card controllers. Figure-14 depicts the power networks of an eMMC (a) and
a uSD card (b), where the LDO18 at the eMMC is the power for the internal NAND
interface between NAND and controller. To check the need of decoupling capacitors on
the I/O PDN, we used the SI/PI co-simulation method, in this case, including the LDO
circuitry to optimize the LDO output capacitance.

Figure-14: Power network architecture of an eMMC (a) and a uSD memory card (b)
 Figure-15: Eye-diagrams of NAND I/F of an eMMC obtained by SI/PI co-simulation
(a) with an ideal power source, (b) with a LDO circuitry,
and (c) with package design improvement

Figure-16: Power droops of NAND I/O-PDN obtained by SI/PI co-simulation.

Upper blue for an ideal power source, lower red for LDO output power source

Although there are supply voltage droops on the NAND I/O PDN as shown in Figure-16,
the eye-diagrams became good as shown in Figure-15(c), with an on-package PDN
design improved by reducing the PDN-L along with chip-placement optimization. As a
result, the eMMC and the uSD card could operate well only with the LDO output
capacitors, resulting in the reduction of on-package decoupling capacitors from 4~5ea to
less than 2ea. That is, the decoupling capacitors circled in Figure-14 can be removed.

Conclusion

We specified a new PDN-Z design criterion experimentally based on the inverse of

spectral currents of an LPDDR2 DRAM core power for the first time. To perform the
experiment, we designed and made a test board to have independently and separately
ground-shielded power planes. To measure the proper PDN properties directly, we de-
capsulated a portion of EMC on a species of eMCP and micro-probed a pair of
power/ground chip pads using a VNA. And then we upgraded the new target PDN-Z
specification to apply to real PCB/products, including noise couplings among power
domains by adopting transfer impedance in addition to the self impedance-based PDN-Z.
The derived target PDN-Z formula was successfully applied to optimize the decoupling
capacitors resulting in overwhelming competitiveness on the quantity of the capacitors
especially in SSD design. In case of eMMC and uSD card, the technique was applied
with an SI/PI co-simulation method including a LDO circuitry and decoupling capacitors
were also optimized in size and number.
 References

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[2] T. H. Hubing et al., “Power bus decoupling on multilayer printed circuit boards,”
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[3] M. Swaminathan et al., “Power distribution networks for system-on-package: status

and challenges,” IEEE Trans. Advanced Packaging, vol. 27(2), pp. 286-300, 2004.

[4] Jingook Kim et al., “Closed-form expressions for the maximum transient noise
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[5] Seungbae Lee et al., “Noble PDN Design of Maximum Allowable Target Impedance
for Multi-GHz Mobile Application Processor Platforms,” DesignCon 2013.

[6] Jongjoo Lee et al, “Split-ground effect of electronic package on the input-level of
high-speed DRAM,” Proc. 53rd ECTC, pp. 1440-1444, 2003.

[7] Jongjoo Lee, "Effects of Package on the Signal Integrity & Power Integrity of
DRAM," 2nd EDAPS, 2003.

[8] http://www.samsung.com/global/business/semiconductor/support

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