2022 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES) | 978-1-6654-4940-3/22/$31.

00 ©2022 IEEE | DOI: 10.1109/SPICES52834.2022.9774131

Design and Performance Analysis of Various 32-bit

Hybrid Adders using Verilog
Renjith R Benson Biju Ancy Joy
Department of Electronics and Department of Electronics and Department of Electronics and
Communication, Mar Baselios College of Communication, Mar Baselios College of Communication, Mar Baselios College of
Engineering and Technology Engineering and Technology Engineering and Technology
APJ Abdul Kalam Technological University APJ Abdul Kalam Technological University APJ Abdul Kalam Technological University
Kerala, India Kerala, India Kerala,India
[email protected] [email protected] [email protected]

Vaishnavi Ganeshan Sivasankar R

Department of Electronics and Communication, Department of Electronics and Communication,
Mar Baselios College of Engineering and Mar Baselios College of Engineering and
Technology Technology
APJ Abdul Kalam Technological University APJ Abdul Kalam Technological University
Kerala, India Kerala, India
[email protected] [email protected]

Abstract—Area, Power and Delay optimizations are the affected. Optimizing area, delay and power of VLSI systems
challenges in current digital IC design. Processors which have always been a challenge. The thing as a designer can do is
are being currently used require adder units. In this work, to bring about any change in the performance parameters of any
different type of 32-bit VLSI adders will be studied and individual component the digital system comprises so that it can
their design implementation will be done. Some of the have an overall improvement in performance. One such
adders were designed using 3-2 compressor. Some of the 32- individual component is the adders which are used in digital
bit hybrid adders is proposed by using differing types of system which can be used to perform complex addition.
combination of adders and logic. The combination includes Multiplication, subtraction and division which can be done with
parallel prefix adders like Kogge-Stone adder (KSA), the help of a simple adder unit. Hybrid adders are combination
Brent-Kung adder (BKA), Ladner-Fischer adder (LFA) of two or more adders of same or different type, a hybrid adder
and Han-Carlson adder (HCA). Two 64-bit hybrid adders can be designed in such a way that the individual adder
is designed by analyzing the performance of the 32-bit comprised within the adder overcomes the limitation of the
designed hybrid adders and by selecting the best 32-bit other adder used, say, a combination of two adders such that
adders. Analysis of the adder performance can be done in one adder overcomes the limitation of other adder and prove to
terms of Area (Number of LUT s), Delay (nS) and Power be advantageous in complex computations. Another type of
(W) analysis is performed with the help of Xilinx ISE 14.7, high-speed adders is the parallel prefix adders, they can perform
a Verilog synthesis software and implementation of the addition in a parallel fashion (compute the bits parallelly)
same using Verilog HDL family Spartan-6 selecting device making them one among the high-speed adders. A combination
XC6SLX16 choosing grade speed -3. of these highspeed adders can bring about an unimaginable
improvement in the performance of digital systems in terms of
Keywords— 3-2 compressor, Brent-Kung adder (BKA), Han- operating speed, frequency of operation, delay etc.
Carlson adder (HCA), Hybrid adders, Kogge-Stone adder (KSA), Investigating combinations of different adders and comparing
Ladner-Fischer adder (LFA) and Parallel prefix adders. their performance parameters is the main goal of this research
work.
I. INTRODUCTION
The structure of this research paper is as follows: Section I is
VLSI systems are constantly developing and a greater number about the research work's introduction, Section II is about the
of transistors are being incorporated in a single IC every two literature review in brief, Section III is about different adder
years so that they can perform better and fast. As the number of topologies, Section IV is mostly about hybrid adders, Section V
bits a system can handle increases, delay increases and is about simulation results, and Section VI is about the research
performance parameters like area and power are in turn work's conclusion.

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 II. LITERATURE REVIEW the proper carry in is known, the correct sum and carry out are
selected with the help of the multiplexer once the calculation is
There have been several researches on adders to minimize completed. The adder's computation process is speed up as a
their delay, which are mentioned in [1],[4],[3],[5],[15],[16] result of this. As a result, the carry select adder achieves faster
which focuses on a comparative study of the performance of operation at the expense of a larger number of devices in the
various types of parallel adders and proposes a hybrid adder circuit. As a result, the area and power utilized by the circuits
circuit to reduce propagation delay. Proposed a design of 1-bit
increases. For a -bit carry select adder; the delay time is:
full adder which utilizes static CMOS logic and Swing
restoration pass transistor logic (SRPL) [2]. The research work = + + + (1)
[6] focusses on the Gate Diffusion Input (GDI), which is a new
technique for designing low-power digital circuits. Proposed a B. Carry Save Adder (CSA)
method based on domino logic, The technique incorporates a
power-delay tradeoff using Tanner EDA Tool [7]. An efficient Another kind of parallel RCA is the Carry Save Adder, which
BCD adder is constructed using a low power synthesis does not compute the carry during the stages but instead stores
technique. Pipelining and parallelism are two alternative or saves it and then calculates it later. Let us pretend we have to
approaches that have been considered [8]. figure out A, B, and C. As a consequence, CSA separates this
The study on [9],[10] shows a reversible logic synthesis for into the following equation:
a one-bit adder, the new proposed hybrid approach uses
traditional QCA cells and decreases cell numbers and area, + + = + (2)
includes a technique and system implementation for reducing
energy consumption in ripple carry adder blocks. SPICE and
Verilog-A are used to simulate the system [11]. The Carry Look
Ahead Adder is compared to the circuit of a fast RBSD adder
cell, The comparison of alternative adder topologies with the
RBSD based adder is the basis for this research [12]. Proposed
a unique approximate adder structure for LUT-based FPGA
technology [13]. Proposed an attempt to optimize adder design
in terms of hardware (Area) consumption and operation speed
[14], It's clear that the Ling adder design outperforms the hybrid
carry skip adder in terms of area usage, but at the expense of
speed of operation.
Fig. 2. Carry save adder block diagram.
III. ADDERS The CSA has a number of full adders, each of which performs
A. Carry Select Adder (CSELA) a single summation and generates the carry separately. After
shifting the carry to the left, the total sum may be determined.
A carry select adder (CSELA) is a parallel adder that can The carry save technique is best known for its application in
simultaneously add two -bit values. Carry select adder is multiplier architecture. The Sum at any i’th stage is given by:
thought to be more efficient than carry look ahead adder, and it
= ⊕ ⊕ (3)
also operates quickly.
The Carry out,

!" = + + (4)

C. Kogge Stone Adder (KSA)

KSA is a parallel prefix version of a carry look ahead adder.

It is widely recognized as the fastest adder and is widely used
in high-speed arithmetic circuits. Carry is generated in O(log n)
time. Carries are computed faster in KSA since they are
parallelized, albeit at the cost of greater space. The following
explanations can make you understand how KSA works.
KSA's entire operation may be easily appreciated by
breaking it down into three main parts:
Fig. 1. Carry select adder block adder.
1. Pre processing
A CSELA is made up of ripple carry adders and multiplexers. This stage entails computing the signals to generate and
The addition of two bits is done with the help of two adders in propagate for each pair of bits in A and B. The logic equations
both circumstances, when the carry is 0 and when it is 1. When below provide these signals:

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# = ⊕ (5) The figure shown above (Fig. 4) is nothing but an 8-bit Ladner
$ = %&' (6) Fischer adder, the base components used in the adder are black
cell, gp block (generate and propagate) blocks and buffers.
Figure 3 below represents a 4-bit KSA. Black cell is used for computing the generate the propagate
signals. Buffer used for balancing loading effect. To generate
carry signal O(logN) time complexity is required. The
performance of this adder depends on the minimum logic depth
and fanout. Based on the prefix graph of LFA adder, we can
generate the prefix terms necessary and finally sum can be
obtained by xor-ing ( and !" .

E. Brent Kung Adder (BKA)

BKA is a type of parallel prefix adder that consists of a BKA
pre-processing stage, a BKA parallel prefix network, and a
BKA post-processing stage for computing summation and
output carry of input bits. The 16-bit BKA prefix graph is
shown in the diagram below:

Fig. 3. 4-bit KSA Illustration.

2. Carry look ahead network

This block sets KSA apart from other adders and is
responsible for its outstanding performance. Calculating the
carriers that correspond to each bit is part of this phase. As
intermediary signals, it uses group propagate and generate, as
stated by the logic equations below:
( :* = ( :+," %&' (+:* - :* = - :+," ./ ( :+," %&' -+:* (7)

Fig. 5. Prefix graph for 16-bit BKA.

3. Post processing
1. BKA Pre-Processing stage
This is the final stage, which all adders in this family go
through (carry look ahead). It entails bits being added. The sum Two signals, Generate and Propagate, are computed for the
bits are computed using the formula below: inputs A and B. The equations below are used to calculate the
above signals.
=( ⊕ !" (8)
$ = %&' (9)
D. Ladner Fischer Adder (LFA)
# = ⊕ (10)
for i = 0,1,2,...n-1 where n is no. of bits.
Ladner Fischer adder which is also a type of parallel prefix
adder. It is considered as the fastest adder. it is widely used in 2. BKA parallel prefix network
industry because of its high performance. Since its a type of
parallel prefix adder it has reduced delay as well as it consumes In order to compute carry equivalents for each input bit,
less area. intermediate signals such as carry generate and propagate
signals are generated at this stage. They can be given in the
equations below:
-1 = -" ./ (" %&' -1 (11)
(1 = (" %&' (1 (12)
-2 = - ./ ( %&' - !" (13)
(2 = ( %&' ( !" (14)
for i = 2,3...n-1 where n is no. of bits.
Carries of each input bit are given by equations:
0 = -1 (15)
2=- (16)
for i = 1,2...n-1 where n is no. of input bits.
Fig. 4. Prefix carry tree of 8-bit Ladner-Fischer adder.

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 3. BKA Post-Processing stage separately. The hybrid adder module takes two N bit inputs and
performs binary addition between the N bits to produce the N
At this point, the following equations are used to calculate bit Sum and Cout. The figure below can be illustrated with an
the final sum bits and output carry: example. Consider two 32-bit inputs (N=32):
0 = (1 (17) A= 10010010 10001101 11011010 11011010
1 = (" ⊕ -1 (18) B= 10000000 01000001 00010101 01100101
2 = ( ⊕ - !" (19)
4 = -5!" (20) Let us now understand the addition of the two 32-bit inputs with
for i = 2,3,...n-1 where n is no. of input bits. the help of hybrid adder.

F. Han-Carlson Adder (HCA)

Fan out, number of logic levels, and number of black cells
are all well-balanced in the Han-Carlson adder. As a result, the
Han-Carlson adder can match the speed of the Kogge-Stone
adder while consuming less power and covering less space. To
create a Han Carlson prefix tree, simply modify the pseudo code
for Kogge Stone's structure. The figure below (Fig. 6) depicts
an 8-bit HCA with buffers with thick lines indicating the critical
route.

Fig. 7. Calculations in a Hybrid Adder System.

Assuming that Adder 1 and 2 are 8-bit adders and Adder 3 is

a 16-bit adder, Bits from 0-7 will be processed by Adder 1 and
Cout coming from the Adder 1 will be given as Cin for the
Adder2, the Adder 2 will process the bits from 8-15 and will
produce Sum[15:8] and Cout2, The Cout2 will be given as Cin
for the Adder3, Adder 3 will process the remaining bits from
16-31 to produce Sum[31:16] and final Cout which is the
Cout3. The overall Sum can be taken from all the three adders
Fig. 6. Prefix graph for 8-bit HCA.
and carry out from Adder3. Adder 1 and Adder 2 forms 16-bit
The main distinction is that the Han Carlson prefix tree places module1, Adder 2 forms the 16-bit Module 2. The combination
cells every other bit in each logic level, and the final logic level of two 16-bit Module to form a 32-bit hybrid adder module, The
adjusts for any missing carry. Han Carlson proposes a good addition result can be obtained as:
trade-off between fanout, number of logic levels, and number
of black cells. Brent Kung graphs make up the outer rows of the Sum= 00010010 11001110 11110000 01111111 with
Han Carlson topology, while Kogge Stone graphs make up the Cout= 1.
inside rows. The Han Carlson adder employs a single Brent
V. SIMULATION AND RESULTS
kung level at the start and end of the graph, with a total of
1+log2(n) levels. The prefix is represented by black dots, while
Different 16-bit adders were implemented like Carry elect
the white dots are simply placeholders.
adder, carry save adder, Kogge stone adder and Brent kung
IV. HYBRID ADDER adder, Ladner fischer adder and Han Carlson adder and with the
help of these adders 32-bit hybrid adders were designed using
A combination of two or more adders is called as a hybrid Xilinx ISE 14.7 and implemented using Verilog HDL family
adder combination. The combination should be chosen in such Spartan -6 choosing device XC6SLX16 selecting grade speed
a way that the one adder overcomes the limitation of another
of -3. The Hybrid adder structures designed were of
adder within the hybrid adder system and prove to be
heterogeneous fashion, performance analysis of all the designed
advantageous. There can be two different types of the
hybrid adders was observed in terms of Area (in LUTs), Delay
combinations of adders. A combination of two or more adders
of the same type is called as a homogeneous hybrid adder and (in nS) and Power (in W). The modified adders can be discussed
the combination of two or more adder of different type is called below:
as a heterogeneous adder. 1. CSELA_KSA Hybrid adder
The figure below (Fig. 7) shows an example of an N bit
hybrid adder, it comprises of three different adders which can 32-bit hybrid adder from the combination of 16-bit CSELA
be used for computing internal carry’s, sum and carryout and 16-bit KSA. The RTL view is shown in the figure below:

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 Fig. 11. RTL Schematic View of BKA_KSA Hybrid adder.

Fig. 8. RTL Schematic View of CSELA_KSA Hybrid adder. 5. LFA_KSA hybrid adder
2. CSELA_KSA_KSA Hybrid adder
32-bit LFA_KSA hybrid adder formed by the combination of
32-bit hybrid adder from the combination of 16-bit hybrid 16-bit LFA and 16-bit KSA. The figure below is the RTL
adder comprising of 8-bit CSELA and 8-bit KSA and 16-bit schematic view of the Proposed LFA_KSA Parallel prefix
KSA. The RTL view is shown in the figure below: hybrid adder:

Fig. 9. RTL Schematic view of CSELA_KSA_KSA. Fig. 12. RTL Schematic View of LFA_KSA Hybrid adder.

3. CSA_KSA_CSELA Hybrid adder 6. HCA_KSA hybrid adder

16-bit CSA is merged with 8-bit KSA and 8-bit CSELA
32-bit HCA_KSA hybrid adder formed by the combination
Hybrid adder combination to form 32- bit CSA_CSELA_KSA
of 16-bit HCA and 16-bit KSA. The figure below is the RTL
Hybrid adder. RTL view is shown in figure below:
schematic view of the Proposed HCA_KSA Parallel prefix
hybrid adder:

Fig.10. RTL Schematic view of CSA_CSELA_KSA Hybrid adder.

Fig. 13. RTL Schematic view of HCA_KSA Hybrid adder.
4. BKA_KSA Hybrid adder
7. BKA_LFA Hybrid adder
Hybrid adder formed by combining 16-bit Brent-Kung adder
and 16-bit Kogge stone adder. RTL view is shown in the figure 32-bit BKA_LFA hybrid adder formed by the combination
below: of 16-bit BKA and 16-bit LFA. The figure below is the RTL

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schematic view of the Proposed BKA_LFA Parallel prefix 10. Proposed 64-bit hybrid adder-1
hybrid adder:
Here Proposed_64_bit_adder_1 is the top module, 32-bit
HCA_KSA is combined with 32-bit LFA_KSA to form 64-bit
hybrid adder-1. The figure below is nothing but the RTL
schematic view of the Proposed 64-bit hybrid adder-1 designed:

Fig. 14. RTL Schematic View of BKA_LFA Hybrid adder.

8. BKA-HCA
Fig. 17. RTL Schematic View of Proposed_64_bit_adder_1.
32-bit BKA_HCA hybrid adder formed by the combination 11. Proposed 64-bit hybrid adder-2
of 16-bit BKA and 16-bit HCA. The figure below is the RTL
schematic view of the Proposed BKA_HCA Parallel prefix Here Proposed_64_bit_adder_2 is the top module, 32-bit
hybrid adder: CSELA_KSA_KSA is combined with 32-bit LFA_KSA to
form 64-bit hybrid adder-1. The figure below is nothing but the
RTL schematic view of the Proposed 64-bit hybrid adder-2:

Fig. 15. RTL Schematic View of BKA_KCA Hybrid adder.

Fig. 18. RTL Schematic View of Proposed 64_bit_adder_2.
9. HCA-LFA hybrid adder
The simulation waveform (behavioral model) results of
various designed Hybrid adders are shown below. The modified
32-bit HCA_LFA hybrid adder formed by the combination
adders can be extended by placing different adders in module,
of 16-bit HCA and 16-bit LFA. The figure below is the RTL
a test bench can be created corresponding to inputs (A, B, Cin)
schematic view of the Proposed HCA_LFA Parallel prefix
can be provided to produce outputs, and a test bench can be
hybrid adder:
created corresponding to inputs (A, B, Cin) can be provided to
produce outputs (Sum, Cout).

Fig. 19. Behavioral model of CSELA_KSA.

Fig. 16. RTL Schematic View of HCA_LFA Hybrid adder. Fig. 20. Behavioral model of CSELA_KSA_KSA.

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 TABLE I. Table for Comparison.

ADDER DESIGN AREA (in DELAY (in POWER (in W)

LUTs) nS)
Kogge stone adder-16 16 5.590 0.031
Carry select adder-16 32 12.845 0.029
Fig. 21. Behavioral model of CSA_CSELA_KSA. Carry save adder-16 31 13.656 0.029
Brent kung adder-16 14 12.043 0.020
Ladner-Fischer adder- 13 7.548 0.029
16
Han-Carlson adder-16 18 7.670 0.029
CSELA-8 13 8.324 0.029
Fig. 22. Behavioral model of BKA_KSA.
KSA-8 8 5.590 0.029
Modified hybrid adder- 31 13.999 0.031
1
(CSELA_KSA)
Modified hybrid adder- 35 9.827 0.031
2
(CSELA_KSA_KSA)
Fig. 23. Behavioral model of LFA_KSA. Modified adder-3 48 16.666 0.031
(CSA_CSELA_KSA)
Proposed adder-4 33 11.301 0.029
(BKA_KSA)
Proposed adder-5 34 7.548 0.029
(LFA_KSA)
Proposed adder-6 33 7.670 0.029
Fig. 24. Behavioral model of HCA_KSA. (HCA_KSA)
Proposed adder-7 38 11.301 0.029
(BKA_LFA)
Proposed adder-8 36 11.301 0.029
BKA_HCA)
Proposed adder-9 37 7.670 0.029
(HCA_LFA)
Fig. 25. Behavioral model of BKA_LFA. Proposed 64-bit hybrid 67 7.670 0.029
adder-1
(LFA_KSA +
HCA_KSA)
Proposed 64-bit hybrid 63 8.658 0.029
adder-2
(LFA_KSA +
Fig. 26. Behavioral model of BKA_HCA. CSELA_KSA_KSA)

The table on top shows the performance analysis of different

designed hybrid adders in terms of performance parameters like
Area, Delay and power. The performance analysis is necessary
as we can compare the performance of different adders and find
Fig. 27. Behavioral model of HCA_LFA. which adder perform better and which adder suits for which
application etc., From table-2 it is clear that power value is
almost same for all the adders, The modified KSA occupy less
area than other adders, for KSA-16 it is occupying only 16
LUTs and for KSA-8 only 8 LUTs, if we look at their delay
values, they are both same, hence KSA can be designed for
utilizing less space in ICs. Modified adder-2 has the least delay
Fig. 28. Behavioral model of LFA_KSA + HCA_KSA. among hybrid adders and occupy very less Area around 35
LUTs, and can be used as High-speed adders. By selecting
proper adder combination, we can design adders with better
delay performances. Adder combination with CSA has the most
delay. BKA occupy less area (14 LUTs) and utilize less power
than KSA, but in terms of delay performance KSA is the best
Fig. 29. Behavioral model of LFA_KSA + CSELA_KSA_KSA.
option. The next best option among parallel prefix adder is LFA

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which has the next less delay in nS. The combination of LFA REFERENCES
and KSA showed less delay and better area performances.
Below it comes the HCA_KSA with delay around 7.670 nS, [1] S. Sarkar and J. Mehedi, "Design of hybrid (CSA-CSkA) adder for
improvement of propagation delay," 2017 Third International Conference
therefore these two fast adders can be used for proposing a 64- on Research in Computational Intelligence and Communication Networks
bit hybrid adder. The combination of CSELA_KSA_KSA has (ICRCICN), Kolkata, India, 2017, pp. 332-336, doi:
the least delay in the modified hybrid adders around 9.827 nS 10.1109/ICRCICN.2017.8234530.
which is used to design proposed 64-bit-hybrid adder-1 along [2] S. Janwadkar and S. Das, "Design and Performance Evaluation of Hybrid
Full Adder for Extensive PDP Reduction," 2018 3rd International
with LFA_KSA these three-hybrid adder can be used for Conference for Convergence in Technology (I2CT), Pune, India, 2018,
application which require less delay and less area applications, pp. 1-6, doi: 10.1109/I2CT.2018.8529780.
all the designed adders occupy less area in FPGAs can be used [3] K. A. K. Maurya, Y. R. Lakshmanna, K. B. Sindhuri and N. U. Kumar,
for such applications. The proposed 64-bit hybrid adder-1 "Design and execution of 32-bit adders using various full adders," 2017
Innovations in Power and Advanced Computing Technologies (i-PACT),
utilized 6.35% more Area and 12.8% less Delay than Proposed Vellore, India, 2017, pp. 1-6, doi: 10.1109/IPACT.2017.8245176.
64-bit hybrid adder-2. Proper selection or combination of [4] V. Shah, U. Fatak and J. Makwana, "Design and Performance Analysis of
individual adders used in hybrid adders can lead to adders with 32-Bit VLSI Hybrid adder," 2019 3rd International Conference on Trends
less delay, less delay means high speed, also utilizing less space in Electronics and Informatics (ICOEI), Tirunelveli, India, 2019, pp.
1070-1075, doi: 10.1109/ICOEI.2019.8862522.
in ICs and lesser power consumption, however when Speed [5] M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam, "Design
increases, delay reduces and decreasing in delay means more of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation,"
area requirement and more area means more power. in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67,
no. 8, pp. 1464-1468, Aug. 2020, doi: 10.1109/TCSII.2019.2940558.
VI CONCLUSION [6] Arkadiy Morgenshtein, Alexander fish and Israel Wagner “Gate Diffusion
input (GDI) – a technique for low power. Design of Digital circuits
Analysis and characterization IEEE International symposium on
The proposed system uses hybrid adders, which are powerful circuit and system February2012.
high-speed adders that can perform complex computations and [7] Sentamilselvi M, Mahendran P “High performance Adder Circuit in VLSI
give better processing power to the digital systems the system” International journal of Technology Enhancements and
comparison between different 32-bit VLSI hybrid adders and emerging engineering Research IJTEEE VOL 2 Issue3.
[8] Shambhavi Mishra, Gaurav Verma “Low power and Area efficient
individual adders is done with the help of parameters like Area, implementation of BCD Adder of FPGA” IEEE 2013.
Power and Delay. The logic can be expanded for wide word [9] Rashmi Chawla, Prashant Kumar, Priya Yadav “Adde Circuit Design
length adders including 64-bit, 128-bit etc. which can be used using advanced quantum dot cellular Automata (AQCA)” National
as the fundamental building block in modern ICs, also the Conference on Recent Advances in electronics and Computer
engineering RAECE 2015.
adders can be used to execute other operations like [10] Wei wang, Konrad Walus and G.A. Jullien “Quantum Dot Cellular
multiplication, subtraction, complementing bits etc., Different automata adder” IEEE2003.
types of combination of modified adders (both heterogeneous [11] Mohammad Fawaz, Nader kobrosli, Jessica Rizakallah “Energy
minimization feedback loop for ripple carry Adders” 97814244-82740 /10
and homogeneous) can be done. Future scope of this work lies
@ 2010IEEE.
in design and implementation of higher bit versions of adder [12] Smita Sharma, Akansha Singh, Krashnkant Gupta “Addition Of
using hybrid adders, the designed hybrid adders can be used to redundant binary signed digits using RBSD Adder” 2015 1st International
implement multipliers like Baugh Wooley, booth multipliers Conference On futuristic trend in Computational analysis and
Knowledge management (ABLAZE2015).
etc. which are high speed multipliers. The hybrid adders can [13] Andreas Becher, Jorge Echavarria, Danie Ziener, Stefan Wildermann
also be used as a functional element in high speed ALUs, the and Jurgen Teich “A LUT-Based Approximate adder” 2016 24th
adders can be modified to implement add/subtract logic circuit Annual international Symposium on field Programmable custom
and can be used in high-speed VLSI systems. Computing Machine.
[14] Alisha, Tilak raj “Tracing of Delay Estimation in Heterogeneous adders
with FPGA” IEEE 2017.
ACKNOWLEDGEMENT [15] Shubham Sarkar, Sujan Sarkar, Jishan Mehedi “Comparison of
Various adders and their VLSI Implementation” IEEE2018 International
The success and final outcome of this work necessitated a Conference on computer communication And Informatics (ICCCI-2018).
great deal of guidance and assistance from a lot of people, and [16] K.Anirudhkumar Maurya, K.Bala Sindhuri, Y.Ramalakshmanna,
N.Udaya Kumar “Design and implementation of 32 bit adder using
we are really fortunate to have received this during the course various Full adders” IEEE (i-PACT2017) International Conference
of our research work. We owe everything we've accomplished on innovations in power and Advanced computing technology.
to their guidance and aid, and we'll never forget to thank them.
We gratefully acknowledge Ms. Ancy Joy, Assistant Professor,
our research work guide for her guidance and suggestions
during this study. We are grateful for and lucky to have received
consistent encouragement, support, and advice from all
teaching staff members of the Department of Electronics and
Communication, MBCET which enabled us to complete our
research work on time.

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