Chapter - 1 Vlsi
Chapter - 1 Vlsi
2.7 2-20
Lithography.
Mask Generation.
2-24
2.7.1
*****
2.8 2-26
Process to Pattern SiO
Jenil Thakkar
Introduction to VLSI
Syllabus
Overview of VLSI design methodology, VLSI design flow, Design hierarchy, Concept
Package
of regularity, Modularity and Locality, VLSI design style, Design quality,
technology, Computer aided design technology.
Page No.
Content
1-2
1.1 Historical Perspective
1-5
1.2 Design Methodology
Circuits 1-7
1.3 Abstraction Levels in digital
1-8
1.4 Concepts of Regularity, Modularity and Locality
1-8
1.5 VLSI Design Flow Y- Chart Representation
-
1-11
1.6 Package Technology
Simulation 1-12
1.7 Use of CAD Tools for Layout and
1-14
1.8 University Questions and Answers
Jenil Thakkar
1-2
Introduction to VLa Spee
Technology& Design
(GTU) hast
4PVLSI
1 . 1H i s t o r i c a lP e r s p e c t i v e :
IC is the
abbreviated
components
are inseparably remely pro
Jenil Thakkar
42VLSI Technology &Design (GTU 1-4
Introduction to VLSI
Silicon 1C Technology
Bipolar MOS
4M
Pentium
1M DEC Alpha
1M
80486 68040
250K 80860
68030
80386
880200
100K
64K**** 80286
32A
68000
16K
8086
4K
8048
10K
8085
K1K 8080
8008 Source: Intel Corp.
4004
1K
70 75 80 85 90 95 2000
Year
Fig. 1.1.2: Level of integration versus time for memory chips and logic cnips
It can be observed
(Fig. 1.1.2) that in terms of transistor count, logic
significantly fewer transistors in any cnp
given year mainly due to large consumption of chip
for complex interconnects. Memory circuits be
are highly regular, and thus more celd
a
integrated with much less area of
interconnects. This has also been one of the ua easo
why the rate of increase of chip complexity (transistor count Is consistently higher
for memory circuits.
per chip) 1s CoO
design time, cost and the functionality of the circuit. The basic options available to any
designer are: standard cells based design, full custom design and semi custom design.
low-typically a few tens of transistors per day per design. The entire mask is produced without
use of any library. Thus the development cost of such a design style is becoming prohibitively
high. Also time to market is more Thus, the concept of design reuse is becoming popular in
order to reduce design cycle time and development cost.
Advantages:
1. High performance
Disadvantages
1. High cost
2 Larger time to market
er
logic devices
PLI
SPLD CPLD FPGA
Vss- 2
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4VLSITechnology &Design (GTU) 1-7 Introduction to VLSI*
Advantages
Reduces mask since fewer custom masks need to be
cost
produced.
Less time to market. Fastest logic implementation compared to full custom approach and
standard ccll approach.
Disadvantages
Size is fixed.
Number of transistors are fixed.
Metalheight is fixed (Supply and ground lines are fixed).
2 Metal layers are possible.
Low efficiency. Most of the transistors may not be in use.
Suitable for low production volumes.
Time to market is of prime concern to every designer and this has lead to the rapid
evolution in the design technology. Designers need to cope up with time to market by being
adhered to rigid design methodologies and strategics that are friendlier to design automation.
The hierarchical design approach is adopted allowing reuse of cells thereby reducing design
effort and increasing the chances for first time working implementation. This is possible as
digital systems can be represented in different levels of abstraction. At each design level, the
internal details for complex module can be abstracted away and replaced by a black box view
or model. This model contains virtually all the information needed to deal with the block at the
next level of hierarchy. For example, once a designer has implemented for an adder module,
itS performance can be defined very accurately and can be captured in model. For all purpose,
can be considered a black box with known characterises. As it is not required for
the system
itdesigner to look inside this box; hence design complex is substantially reduced.
Jenil Thakkar
PVLSI Technology &Design (GTU) 1-8
Introduction to VLS
Typically used abstraction levels in digital circuit design are in
order of increasin
abstraction, the device, the circuit, gate, functional module
(example adder) and svstem le
(example processor). The circuit designer will never seriously consider
increasin
the solid state level
equation (device level) governing the behaviour phvsi
devices when of the designing a digital gate
1.4 Concepts of Regularity, Modularity and Locality
Jenil Thakkar
VLSI Technology& Design(GTU) 1-9 Introduction to VLSI
Structural
domain Behavioral
domain
9 System
Algorithm /program
FTEDT Finite
state machine Fm
Register/
adder Modula
descripon PA
Logic gate
Boolean
equation
FM
Transistopr
Masks
Cell
placement
Modules
placement
C m c
PM Cmn PhysicalChip
domain floor plan
Fig. 1.5.1 shows the design flow for most logic chips, using design activities on three
different axes (domains) which resemble the letter Y.
The design flow begins with the specifications that describe the behaviour of the target
chip. The architecture of the system is correspondingly than dcfined and is henceforth mapped
onto the chip surface by floor planning.
In the, next lower level of abstraction the design in the behavioural domain can be
defined using finite state machines (FSMs) which are structurally implemented with functional
modules such as registers and combinational logic units. Using automatic module placement
Jenil Thakkar
2VLSI Technology& Design (GTU 1-10
Introductition to
feature of CAD tools these modules then
Vis
are
geometrically placed onto the chip
chip
followed by routing. surface. It i
The next evolution starts with module description. Individual modules are then
implemented using logical gates, which are placed and interconnected by usina
a
placement and routing program. The last evolution involves description of gates using hool.cel
equations that is
implemented by employing transistors at transistor level olea
gates and finally mask is generated which is implementation
required by the various processing steps. in t
fabrication process. A simplified view of this h
design flow is shown in Fig. 1.5.2.
Design
Specification
Architecture design/
System level design
HDLcoding
Simulation
Verification
Meets
No Specification?
Yes
Fabrication
Jenil Thakkar
Introduction to VLSI
4VLSITechnology& Design (GTU) 1-11
packages.
1.6.1 Through Hole Package:
In through hole package one or more rows of leads or pins are available that are
designed to go through the holes of printed circuit board (PCB) and are soldered underneath.
Body of through hole packages are made from either plastic or ceramic. The number of leads
on a through hole package may vary from 3 to 64. IC package having single row of leads is
called single in line package (SIP), while with two rows of leads is called dual in line package
(DIP). DIP's are mostly encountered in educational institutes. IC having grid arrangement of
lead is called as pin grid aray (PGA). They offer more number of pin counts (more than
400 pins ) and are better than DIP's in terms of thermal conductivity and power dissipation
characteristics.
Celeron
pGA
uP
socket. The leads of surface mount packages except ball grid array (BGA) are bent at an angle
near the foot to aid soldering to the surface of the circuit board. Ball grid array packages on the
other hand do not have solderable leads instead their leads are ball shaped and are arranged in
a grid pattern underneath the package. BGA IC's are held against contacts on the board with
pressure. They are constructed from either plastic or ceramic and have leads varying from 56
to 1312.
Jenil Thakkar
4PVLSITechnology &Design (GTU) 1-12
Introduction to V
Surface mount package are made up of ceramic,
plastic, metals or combination off
three and has leads ranging from I to 1312. Small outline
package (SO) with a single rowa
leads and flat package (FP), which has leads on 2 or 4 sides of
the
ow
package are common tvoe
of surface mount
packages.
ContactlesS packages do not come into direct physical contact with a circuit board. They
are scanned to provide information to other devices wirelessly. They have no leads and are
made only with plastic bodies.
Design verification
DRC, Simulation etc. Produce masks
Package
Test
IC fabrication process
Fig. 1.7.1: IC design and fabrication process
Jenil Thakkar
Introduction to VLSI
4VLSI Technology &Design(GTU) 1-13
human ability requires computer to check layout, circuit performance, process design etc.
and
VLSI circuit
So, computers are used extensively to aid in the design and optimization process.
designers are normally given a set of design rules based on a particular technology and a
technology files in order to do their work.
Thedesign phase involves
Design capture:
The behaviour and/ or siructure of a system may be captured in a hardware description
language such as VHDL, verilog etc. The system could also be entered through schematic
capture using schematic editors.
Synthesis
Synthesis is the process of converting the high level description of the system into lower
gate level circuit. ie. Once the system specification is entered designer need not bother for
selecting and interconnecting at the gate level. Only the library and optimization criteria
power or speed) need to be specified and the synthesis tool does the remaining. Most
synthesis tools support a large range of FPGA and CPLD device vendors.
Layout
The physical layout may be generated either automatically from a high level description
or may be hand edited using a layout editor (MAGIC or MICROWIND).
Design verification:
To verify the design simulation is done. Simulation tool is a software timing program
used to verify the functionality or timing of the circuit. Various simulators may be used at the
logic, circuit or layout level (SPICE, IRSIM etc.). These simulators perform functional, timing
and other tests. Layout needs to run through get another type of verification tool called Design
Rule Checker (DRC) which checks for design rule violations. Design rules specify various
layout rules such as the optimum width and spacing between various layers.
Pattern generation
It generates the database suitable for manufacturer. Translators are available to translate
the design from a standard layout format like Callech Intermediae Format (CIF) to the pattern
generation format. That is, on completion of design and layout, the system design is contained
in system layout files in intermediate form. These files are converted to pattern generator files,
to be sent to the mask making facility. Once the masks are manufactured, the semi conductor
Jenil Thakkar
1-14
VLSI Technology &Design(GTU) Introduction to VLS
device fabrication starts which after several processing steps becomes a fully phveia
component.
ysical 1C
Based on a typical VLSI design work flow, a good VLSI CAD tool must sn
pport the
followingfeatures
1) Physical design layout editor, circuit schematics design.
2) Physical verification Must contain DRC, circuit extractor, capability to plot ut
and /or display for visual checking.
3) Behavioural verification.
Oral Questions
Q. 1 Why MOS technology has become dominant technology in IC market. (Section 1.1)
Q.2 Differentiate full custom and semicustom design approach. (Section 1.2)
Q.3 Explain VLSI design flow. (Section 1.5)
Q. 4 What is importance of CAD tools in VLSI. (Section 1.7)
a.5 Differentiate between LSI, MSI and VLSI circuit. (Section 1.1)
Q.6 State Moore's law. (Section 1.1)
1.8 University Questions and Answers
May 2011
Q. 1 Discuss VLSI design flow in detail. (Section 1.5)
(4 Marks)
Dec. 2011
Q. 2 Explain VLSI design flow using Y-chart. (Section 1.5) (7 Marks)
May 2012
Q. 3 Answer the following : Compare Semi-custom and
Full custom VLSI design style
(Section 1.2.1 and 1.2.2)
(3% Marks)
Dec. 2012
Q. 2 Discuss following approaches (with examples) used to reduce complexity of
design: 1. Hierarchy, 3. Modularity, and 4. Locality. (7 Marks)
(Section 1.4)
O00
Jenil Thakkar