CS8382 – DIGITAL SYSTEMS LAB

LAB MANUAL

THIRD SEMESTER CSE/IT

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 SYLLABUS

1. Design and implementation of Adder and Subtractor using logic gates.

2. Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa

(ii) Binary to gray and vice-versa

3. Design and implementation of 4 bit binary Adder/ subtractor and BCD

adder using IC 7483

4. Design and implementation of 2 bit Magnitude Comparator using logic

gates 8 Bit Magnitude Comparator using IC 7485

5. Design and implementation of 16 bit odd/even parity checker generator

using IC74180.

6. Design and implementation of Multiplexer and De-multiplexer using logic

gates and study of IC74150 and IC 74154

7. Design and implementation of encoder and decoder using logic gates and
study of IC7445 and IC74147

8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12

Ripple counters

9. Design and implementation of 3-bit synchronous up/down counter

10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip-
flops

11. Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description

Language

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 LIST OF EXPERIMENTS

Title
S. No
1. Design of Adders using logic gates and Verilog HDL
2. Design of Subtractor using logic gates and Verilog HDL
3. Design of BCD to excess-3 code converter and vice versa using logic gates
4. Design of Binary to Gray code converter and vice-versa using logic gates
5. Design of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
Design of 2 bit Magnitude Comparator using logic gates and 8 Bit Magnitude
6.
Comparator using IC 7485
7. Design of Encoder and decoder using logic gates and study of IC7445, IC74147
8. Design of 16-bit odd/even parity checker/ generator using IC74180
9. Design of Mux using logic gates, Verilog HDL and study of IC74150
10. Design of De-Mux using logic gates, Verilog HDL and study of IC 74154
11. Design of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
12. Design of 3-bit synchronous up/down counter
13. Design of SISO, SIPO, PISO and PIPO Shift Registers using Flip-flops
14. Design of Counters and Shift Registers using Verilog HDL

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EXPT NO. : STUDY OF LOGIC GATES
DATE :

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT -  1

9. PATCH CORD  - 14
THEORY:

Circuit that takes the logical decision and the process are called logic
gates. Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as
AND function. The output is high when both the inputs are high. The output
is low level when any one of the inputs is low.

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OR GATE:

The OR gate performs a logical addition commonly known as OR function.

The output is high when any one of the inputs is high. The output is low
level when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the
input is low. The output is low when the input is high.
NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high

when both inputs are low and any one of the input is low .The output is low
level when both inputs are high.
NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when

both inputs are low. The output is low when one or both inputs are high.
X-OR GATE:

The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:

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AND GATE:

SYMBOL: PIN DIAGRAM:

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OR GATE:

NOT GATE:

SYMBOL: PIN DIAGRAM:

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X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

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3-INPUT NAND GATE :

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NOR GATE:

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EXPT NO. : DESIGN OF ADDER AND SUBTRACTOR
DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two
outputs one from the sum ‘ S’ and other from the carry ‘ c’ into the higher
adder position. Above circuit is called as a carry signal from the addition of
the less significant bits sum from the X-OR Gate the carry out from the
AND gate.

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FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum

of input; it consists of three inputs and two outputs. A full adder is useful to
add three bits at a time but a half adder cannot do so. In full adder sum
output will be taken from X-OR Gate, carry output will be taken from OR
Gate.
HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The
half subtractor has two input and two outputs. The outputs are difference and
borrow. The difference can be applied using X-OR Gate, borrow output can
be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates.

In a full subtractor the logic circuit should have three inputs and two outputs.
The two half subtractor put together gives a full subtractor .The first half
subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half
subtractor and the second term is the inverted difference output of first X-
OR.
PROCEEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

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RESULT:
HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

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FULL ADDER
TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for CARRY:

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 CARRY = AB + BC + AC

LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDERS

HALF SUBTRACTOR
TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

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K-Map for BORROW:

BORROW = A’B
LOGIC DIAGRAM:

FULL SUBTRACTOR
TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

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K-Map for Borrow:

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

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EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete
elements of information results in the use of different codes by different
systems. A conversion circuit must be inserted between the two systems if
each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses
different binary code.
The bit combination assigned to binary code to gray code. Since each
code uses four bits to represent a decimal digit. There are four inputs and
four outputs. Gray code is a non-weighted code.

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 The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from
K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible
even though each uses a different binary code. To convert from binary code
to Excess-3 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

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BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE:
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3:

G3 = B3

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K-Map for G2:

K-Map for G1:

K-Map for G0:

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LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

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K-Map for B3:

B3 = G3

K-Map for B2:

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K-Map for B1:

K-Map for B0:

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LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTER

TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

E2=B2B1+B2B1B0+B2B1B0
E2=B2B1+B1(B2B0+B2B0) = B2B1+B1(B2 B0)

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K-Map for E1:

= B1 О B0
K-Map for E0:

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LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

x3 x2 X3 X4 A B C D

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

2
K-Map for C:

K-Map for D:

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LOGIC DIAGRAM:

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EXPT NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR
DATE :

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers. It can be constructed with full adders connected in
cascade, with the output carry from each full adder connected to the input
carry of next full adder in chain. The augends bits of ‘A’ and the addend bits
of ‘B’ are designated by subscript numbers from right to left, with subscript
0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C 0 and it ripples
through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters,
placed between each data input ‘B’ and the corresponding input of full
adder. The input carry C0 must be equal to 1 when performing subtraction.

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4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one
circuit with one common binary adder. The mode input M controls the
operation. When M=0, the circuit is adder circuit. When M=1, it becomes
subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD,
together with an input carry from a previous stage. Since each input digit
does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum
being an input carry. The output of two decimal digits must be represented
in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD.
The 2 decimal digits, together with the input carry, are first added in the top
4 bit adder to produce the binary sum.
PROCEDURE:

12. Connections were given as per circuit diagram.

13. Logical inputs were given as per truth table

14. Observe the logical output and verify with the truth tables.

RESULT:

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PIN DIAGRAM FOR IC 7483:

Input Data A Input Data B Addition Subtraction

A A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
4
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

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4-BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:

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BCD ADDER:

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

K MAP

C = S4 (S3 + S2)

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LOGIC DIAGRAM:

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EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF MAGNITUDE

COMPARATOR

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operator that determine one

number is greater than, less than (or) equal to the other number. A
magnitude comparator is a combinational circuit that compares two numbers
A and B and determine their relative magnitude. The outcome of the

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comparator is specified by three binary variables that indicate whether A>B,
A=B (or) A<B.

A = A3 A2 A1 A0
B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a

combinational circuit designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of

pairs of significant digits starting from most significant position. A is 0 and
that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0

The same circuit can be used to compare the relative magnitude of

two BCD digits.
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

   
x3 x2 x1 x0

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PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

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2 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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K MAP :

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LOGIC DIAGRAM:

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PIN DIAGRAM FOR IC 7485:

8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

LOGIC DIAGRAM:

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4
EXPT NO. :
DATE :

16 BIT ODD/EVEN PARITY CHECKER /GENERATOR

AIM:
To design and implement 16 bit odd/even parity checker generator
using IC 74180.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. NOT GATE IC 7404 1
1. IC 74180 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:

A parity bit is used for detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to
make the number is either even or odd. The message including the parity bit
is transmitted and then checked at the receiver ends for errors. An error is
detected if the checked parity bit doesn’t correspond to the one transmitted.
The circuit that generates the parity bit in the transmitter is called a ‘parity
generator’ and the circuit that checks the parity in the receiver is called a
‘parity checker’.
In even parity, the added parity bit will make the total number is even
amount. In odd parity, the added parity bit will make the total number is odd

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amount. The parity checker circuit checks for possible errors in the
transmission. If the information is passed in even parity, then the bits
required must have an even number of 1’s. An error occur during
transmission, if the received bits have an odd number of 1’s indicating that
one bit has changed in value during transmission.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

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PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS OUTPUTS
Number of High Data PE PO E O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1

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16 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:

16 BIT ODD/EVEN PARITY GENERATOR

TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 I7’ I6’ I5’ I4’ I3’ I2’ I1’ I0’ Active ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

LOGIC DIAGRAM:

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EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic
gates and study of IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units
over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally there are 2 n input line
and n selection lines whose bit combination determine which input is
selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It
takes information from one line and distributes it to a given number of

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output lines. For this reason, the demultiplexer is also known as a data
distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the
AND gates. The data select lines enable only one gate at a time and the data
on the data input line will pass through the selected gate to the associated
data output line.
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

5
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

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CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

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5
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

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LOGIC DIAGRAM FOR DEMULTIPLEXER:

5
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150: MUX

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5
PIN DIAGRAM FOR IC 74154:DEMUX

IC74155-DEMUX-8X1,16X1

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EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates and
study of IC 7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a
decoder. An encoder has 2n input lines and n output lines. In encoder the
output lines generates the binary code corresponding to the input value. In
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is assumed
that only one input has a value of one at any given time otherwise the circuit

6
is meaningless. It has an ambiguila that when all inputs are zero the outputs
are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which
converts coded input into coded output where input and output codes are
different. The input code generally has fewer bits than the output code. Each
input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2 n possible
outputs. 2n output values are from 0 through out 2n – 1.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

6
BCD TO DECIMAL DECODER:
PIN DIAGRAM FOR IC 74155:2x4 Decoder

PIN DIAGRAM FOR IC 74147(Encoder)

6
LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

6
6
LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

6
6
EXPT NO. :
DATE :
CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE
COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple
counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse

arriving at its clock input. Counter represents the number of clock pulses
arrived. A specified sequence of states appears as counter output. This is the
main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external
pulse and then each successive flip flop is clocked by Q or Q output of
previous stage. A soon the clock of second stage is triggered by output of
first stage. Because of inherent propagation delay time all flip flops are not
activated at same time which results in asynchronous operation.

6
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

6
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

6
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

7
MOD - 10 RIPPLE COUNTER
TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

LOGIC DIAGRAM:

7
7
MOD - 12 RIPPLE COUNTER
TRUTH TABLE:
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0

LOGIC DIAGRAM:

7
7
EXPT NO. :
DATE :
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS
UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse

arriving at its clock input. Counter represents the number of clock pulses
arrived. An up/down counter is one that is capable of progressing in
increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of
the counter is controlled by up/down signal. When this signal is high counter
goes through up sequence and when up/down signal is low counter follows
reverse sequence.

7
7
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

7
STATE DIAGRAM:

CHARACTERISTIC TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

7
 TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

K MAP

7
LOGIC DIAGRAM:

8
EXPT NO. :
DATE :
DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both

directions is known as shift register. The logical configuration of shift
register consist of a D-Flip flop cascaded with output of one flip flop
connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest
possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.

8
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

8
PIN DIAGRAM:

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

8
SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:

TRUTH TABLE:
OUTPUT
Q3 Q2 Q1 Q0
CLK DATA
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1
PARALLEL IN SERIAL OUT:
LOGIC DIAGRAM:

8
TRUTH TABLE:
CLK D3 D2 D1 D0 OUTPUT
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
DATA INPUT OUTPUT
D3 D2 D1 D0 Q3 Q2 Q1 Q0
CLK
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

8
EXPT NO. :
DATE :

ADDER SIMULATION USING VERILOG PROGRAMMING

Aim
To realize the operation of Half-adder and Full-Adder circuits using
Verilog programming.
Software Required
Xilinx 9.1i

Half-Adder
A combinational circuit that performs the arithmetic addition of two
bits is called a Half Adder. The input variables of a half adder are called
augend and addend bits. The output variables are called the sum and carry.
It is implemented by using AND and XOR gates.
Full-Adder
A combinational circuit that performs the arithmetic addition of three
bits is called a Full Adder. The input variables of a Full adder are called
augend and addend bits. The output variables are called the sum and carry.
It is implemented by using AND, OR and XOR gates.

Program – Half Adder

input a;
input b;
output s;
output c;
xor(s,a,b);
and(c,a,b);
endmodule

module testbench();
reg a,b;
wire s,c;
ha test(a,b,s,c);
initial
begin

8
a=0;b=0;
#5 a=0;b=1;
#5 a=1; b=0;
#5 a=1;b=1;
#5 $finish;
end
endmodule

Output Waveform

Procedure
1. Xilinx ISE software environment is opened and a new project is
created.

2. New source file in Verilog programming using XILINX editor is

created.

3. The project created is synthesized and checked for any errors by

clicking synthesis command in the process window.

4. Setting changed to behavioral simulation of sources window.

5. A new source file of test bench waveform is created for simulation.

8
 6. The input binary values for test bench waveform are configured.

7. Simulate behavioral model in the process winow is run.

8. XILINX ISE simulates the verilog HDL program and displays the
output waveform.

Program - Full Adder

module ful(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;

wire w1,w2,w3;

xor(w1,a,b);

xor(sum,w1,cin);

and(w2,a,b);

and(w3,w1,cin);

or(cout,w2,w3);

endmodule

8
RTL Schematic

Output Waveform –Full Adder

8
Result:
Thus the program for Half adder and Full adder was written using
HDL and simulated successfully using XILINX 9.1i ISE simulator.

EXP NO.
4x1 MUX

Aim: To implement a 4x1 MUX using structural simulation in Xilinx ISE.

Program:
module mux(y,s0,s1,i0,i1,i2,i3,clk);
input s0;
input s1;
input i0;
input i1;
input i2;
input i3;
output y;
begin
assign y=(i0 & ~s0 & ~s1 )|(i1 & ~s0 & s1 )|(i2 & s0 & ~s1 )|(i3 & s0 & s1 );
endmodule

module testbench();
reg s0,s1,i0, i1, i2, i3 ;
wire y;
mux a1(y, s0, s1, i0, i1, i2, i3);
initial
begin
s0=0;s1=0;i0=1;i1=0;i2=0;i3=0;
#10 s0=0;s1=1;i0=0;i1=1;i2=0;i3=0;
#10 s0=1;s1=0;i0=0;i1=0;i2=1;i3=0;
#10 s0=1;s1=1;i0=0;i1=0;i2=0;i3=1;
#10 $finish;
end
endmodule

9
RTL Schematic:

Waveform:

Result:
Thus a 4x1 MUX was implemented using structural simulation in Xilinx ISE.

9
EXP NO.
1X4 DEMUX

Aim: To implement a 1X4 DEMUX using structural simulation in Xilinx ISE.

Program:
module demux(o1,o2,o3,o4,s0,s1,i,clk);
input i,s0,s1,clk;
output o1,o2,o3,o4;
assign o1=(s0 & s1 & i);
assign o2=(~s0 & s1 & i);
assign o3=(s0 & ~s1 & i);
assign o4=(~s0 & ~s1 & i);
end
assign o1=x1;
assign o2=x2;
assign o3=x3;
assign o4=x4;
endmodule

module testbench();
reg s0,s1,i;
wire o1,o2,o3,o4;
demux a1(o1,o2,o3,o4,s0,s1,i);
initial
begin
s0=0;s1=0;i=1;
#10 s0=0;s1=1;i=1;
#10 s0=1;s1=0;i=1;
#10 s0=1;s1=1;i=1;
end
endmodule

9
RTL Schematic:

Waveform:

Result:
Thus a 1X4 DEMUX was implemented using structural simulation in Xilinx ISE.

9
EXP NO.
Flip-Flops

Aim: To implement the following flip-flops using structural simulation in Xilinx ISE
1. T

2. D

T Flip-flop:

Program:
module tff(t,clk,q);
output q;
input t,clk;
reg q=0;
always@(posedge clk) begin
if (t==0)
q <= q;
else
q <= ~q;
end
endmodule

module testbench();
reg t,clk;
wire q;
tff test(t,clk,q);
initial
begin
$monitor($time,"t=%b,clk=%b,q=%b",t,clk,q);
end
initial
begin
clk=1'
forever #50 clk=~clk;
end
initial
begin
t=1
forever #500 t=~t;
end
endmodule

9
RTL Schematic:

Waveform:

D Flip-flop:
Program:
module DFF1(Q,D, CLK);
output Q;
input D;
input CLK;
reg Q;
always @(posedge CLK)
begin
Q <=D;
end
endmodule

module testbench();
reg D,CLK;
wire Q;
DFF1 one(Q,D,CLK);
initial
begin
$monitor ($time,"Q=%b,D=%b,CLK=%b", Q,D,CLK);
end
initial
begin
D=0;CLK=1;

9
#5 D=0;CLK=0;
#5 D=0;CLK=1;
#5 D=1;CLK=0;
#5 D=1;CLK=1;
#5 D=0;CLK=0;
#5 D=1;CLK=1;
#5 D=1;CLK=0;
#5 D=0;CLK=1;
#5 D=1;CLK=0;
#5 D=1;CLK=1;
$finish;
end
endmodule

RTL Schematic:

Waveform:

Result:
Thus the flip-flops were implemented using structural simulation in Xilinx ISE.

9
EXP NO.
2 bit counters

Aim: To implement the following counters using structural simulation in Xilinx ISE:
Program:
module counter(clk,c0);
input clk;
output [1:0]c0;
reg c0=0;
always @(posedge clk)
c0=c0+1;
endmodule

module testbench();
reg clk;
wire [1:0]c0;
counter c1(clk,c0);
initial
begin
clk=0;
forever #100 clk=~clk;
end
initial
begin
$monitor($time,"c0=%b,clk=%b",c0,clk);
end
endmodule

RTL Schematic:

9
Waveform:

Result:
Thus the counters were implemented using structural simulation in Xilinx ISE

9
Expt No.

SERIAL IN SERIAL OUT SHIFT REGISTER

Aim:
To Implement a serial in serial out shift register in Xilinx ISE

Program:
module taja(d,clk,q);
input d,clk;
output q;
reg [3:0]q1;
dff t1(d,clk,q1[0]);
dff t2(q[0],clk,q1[1]);
dff t3(q[1],clk,q1[2]);
dff t4(q[2],clk,q);
endmodule

module dff(d,clk,q);
input d,clk;
output q;
reg q=0;
always@(posedge clk)
begin
case(d)
0:q=0;
1:q=1;
endcase
end
endmodule

module testbench();
reg d,clk;
wire [3:0]q;
taja a1(d,clk,q);
initial
begin
clk=1;
forever #10
clk=~clk;
end
initial
begin
d=1;
#20 d=0;
#20 d=1;

9
#20 d=0;
#200 $finish;
end
endmodule

Result:
Thus a serial in serial out shift register was implemented in Xilinx ISE