Midas M8000
Midas M8000
Midas M8000
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M8000
2. Block Diagram and Pin Description
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M8000
2.3 Pin Description
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M8000
Pin No. Pin Name Description
Overflow (Output, open drain) - Detects an overflow condition on both left and
36 OVFL
right channels.
41 RST Reset (Input) - The device enters a low power mode when low.
Stand-Alone Mode
CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the
34 CLKMODE
MCLK path to the core device circuitry.
37 DIF1
DIF1, DIF0 (Input) - Inputs of the audio interface format.
38 DIF0
39 M1
Mode Selection (Input) - Determines the operational mode of the device.
40 M0
MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the
42 MDIV
MCLK path to the core device circuitry.
Control Port Mode
CLKMODE (Input) - This pin is ignored in Control Port Mode and the
same functionality is obtained from the corresponding bit in the Global
34 CLKMODE
Control Register.
Note: Should be connected to GND when using the part in Control Port Mode.
I²C Format, AD1 (Input) - Forms the device address input AD [1].
37 AD1/CDIN
SPI Format, CDIN (Input) - Becomes the input data pin.
I²C Format, AD0 (Input) - Forms the device address input AD [0].
38 AD0/ CS
SPI Format, CS (Input) - Acts as the active low chip select input.
I²C Format, SCL (Input) – Serial clock for the serial control port. An external
39 SCL/CCLK pull-up resistor is required for I²C control port operation.
SPI Format, CCLK (Input) – Serial clock for the serial control port.
I²C Format SDA (Input/ Output) - Acts as an input/output data pin. An external
40 SDA/CDOUT pull-up resistor is required for I²C control port operation.
SPI Format CDOUT (Output) - Acts as an output only data pin.
MCLK Divider (Input) - This pin is ignored in Control Port Mode and the
same functionality is obtained from the corresponding bit in the Global
42 MDIV
Control Register.
Note: Should be connected to GND when using the part in Control Port Mode.
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M8000
3. Electrical Parameter
3.4 DC Power
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M8000
3.5 Logic levels
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M8000
3.7 ANALOG CHARACTERISTICS (COMMERCIAL)
Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full-scale input sine
wave. Measurement Bandwidth is 10 Hz to 20 kHz.
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M8000
3.8 DIGITAL FILTER CHARACTERISTICS
Notes:
1. The filter frequency response scales precisely with Fs.
2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
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M8000
3.10 SERIAL AUDIO INTERFACE - I²S/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic “0” = GND = 0 V; Logic “1” = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Notes:
1. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System Clocking”
on page 6.
2. CLKMODE functionality described in Section 4.6.3 “Master Mode Clock Dividers” on page 18.
3. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance is
guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 20.
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M8000
3.11 SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic “0” = GND = 0 V; Logic “1” = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Notes:
1. TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.
2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System Clocking”
on page 6.
3. CLKMODE functionality described in Section 4.6.3 “Master Mode Clock Dividers” on page 18.
4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaranteed only
when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 20.
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M8000
3.12 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF
Notes:
1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
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M8000
3.13 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF
Notes:
1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. For fsck <1 MHz
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M8000
4. APPLICATIONS
4.1 Power
The M8000 features five independent power pins that power various functional blocks within the device and allow
for convenient interfacing to other devices. Table 1 shows what portion of the device is powered from each supply
pin. Please refer to “Recommended Operating Conditions” on page 6 for the valid range of each power supply pin.
The power supplied to each power pin can be independent of the power supplied to any other pin.
To meet full performance specifications, the M8000 requires normal low-noise board layout. The “Typical
Connection Diagram” on page 36 shows the recommended power arrangements, with the VA pins connected to a
clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be powered from
the analog supply via a single-pole decoupling filter.
Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high-frequency
capacitors placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ pins in order
to avoid unwanted coupling of these signals into the device. The FILT+ and VQ decoupling capacitors must be
positioned to minimize the electrical path to ground.
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M8000
4.3 Master Clock Source
The M8000 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillator driver or an
externally generated clock.
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M8000
4.4.1 Synchronization of Multiple Devices
To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must be the
same for all M8000 devices in the system. If only one master clock source is needed, one solution is to place one
M8000 in Master Mode, and slave all of the other devices to the one master, as illustrated in Figure 8. If multiple
master clock sources are needed, one solution is to supply all clocks from the same external source and time the
M8000 reset de-assertion with the falling edge of MCLK. This will ensure that all converters begin sampling on the
same clock edge.
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M8000
4.5.1 I²S and LJ Format
The I²S and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are
transmitted, odd channels first, then even. The MSB is always clocked out first.
In Slave Mode, the number of SCLK cycles per channel is fixed as described under “Serial Audio Interface - I²S/LJ
Timing” on page 10. In Slave Mode, if more than 32 SCLK cycles per channel are received from a master controller,
the M8000 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per channel are received from a
master, the M8000 will truncate the serial data output to the number of SCLK cycles received.
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M8000
4.5.3 Configuring Serial Audio Interface Format
The serial audio interface format of the data is controlled by the configuration of the DIF1 and DIF0 pins in Stand-
Alone Mode or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control Port Mode, as shown in
Table 2.
M1 M0 Mode Frequency
0 0 Single-Speed Master Mode (SSM) 2 kHz - 54 kHz
0 1 Double-Speed Master Mode (DSM) 54 kHz - 108 kHz
1 0 Quadruple-Speed Master Mode (QSM) 108 kHz - 216 kHz
1 1 Auto-Detected Speed Slave Mode 2 kHz - 216 kHz
Table 3. M1 and M0 Settings
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M8000
4.6.3 Master Mode Clock Dividers
Figure 12 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, including the
significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
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M8000
4.7 Master and Slave Clock Frequencies
Tables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The MCLK/LRCK ratio
should be kept at a constant value during each mode. In Master Mode, the device outputs the frequencies shown.
In Slave Mode, the SCLK/LRCK ratio can be set according to design preference. However, device performance is
guaranteed only when using the ratios shown in the tables.
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M8000
Table 11. Frequencies for 192 kHz Sample Rate using TDM
Table 12. Frequencies for 192 kHz Sample Rate using TDM
4.8 Reset
The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon
de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device starts
sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When changing between
mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface format, master/slave,
or speed modes, it is recommended to reset the device following the change by holding the RST pin low for a
minimum of one MCLK cycle and then restoring the pin to a logic-high condition.
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M8000
4.9 Overflow Detection
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M8000
4.11 Optimizing Performance in TDM Mode
Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise management
is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital activity with
the analog sampling processes to ensure that the noise generated by the digital activity is minimized (ideally
non-existent) when the analog sampling occurs. Noise management, when implemented properly, minimizes the
on-chip interference between the analog and digital sections of the device. This technique has proven to be very
effective and has simplified the process of implementing an A/D converter into a systems design. The dominant
source of interference (and most difficult to control) is the activity on the serial audio interface (SAI). However, noise
management becomes more difficult to implement as audio sample rates increase simply due to the fact that there
is less time between transitions on the SAI.
The M8000 A/D converter supports a multi-channel Time-Division-Multiplexed interface for Single, Double and
Quad-Speed sampling modes. In Single-Speed Mode, sample rates below 50 kHz, the required frequencies of
the audio serial ports are sufficiently low that it is possible to implement noise-management. In this mode, the
performance of the device is relatively immune to activity on the audio ports.
However, in Double-Speed and Quad-Speed modes there is insufficient time to implement noise management due
to the required frequencies of the audio ports. Therefore, analog performance, both dynamic range and THD+N,
can be degraded if the serial port transitions occur concurrently with the analog sampling. The magnitude of the
interference is not only related to the timing of the transition but also the di/dt or transient currents associated with
the activity on the serial ports. Even though there is insufficient time to properly implement noise management, the
interference effects can be minimized by controlling the transient currents required of the serial ports in Double-
and Quad-Speed TDM Modes.
In addition to standard mixed-signal design techniques, system performance can be maximized by following several
guidelines during design.
–– Operate the serial audio port at 3.3 V and not 5 V. The lower serial port voltage lowers transient currents.
–– Operate the A/D converter as a system clock Slave. The serial clock and Left/Right clock become high-impedance
inputs in this mode and do not generate significant transient currents.
–– Place a buffer on the serial data output very near the A/D converter. Minimizing the stray capacitance of the
printed circuit board trace and the loading presented by other devices on the serial data line will minimize the
transient current.
–– Place a resistor, near the converter, between the A/D serial data output and the buffer. This resistor will reduce the
instantaneous switching currents into the capacitive loads on the nets, resulting in a slower edge rate. The value
of the resistor should be as high as possible without causing timing problems elsewhere in the system.
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M8000
4.13.1 SPI Mode
In SPI Mode, CS is the M8000 chip select signal; CCLK is the control port bit clock (input into the M8000 from a
controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller. Data is clocked
in on the rising edge of CCLK and is supplied on the falling edge of CCLK.
To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The
eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address
Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data that
will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It
may be externally pulled high or low with a 47 kΩ resistor, if desired.
There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte
is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle that finishes
( CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as desired. To
begin a read, bring CS low, send out the chip address and set the read/write bit (R/ W ) high. The next falling edge of
CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto-
increment bit is set to 1, the data for successive registers will appear consecutively
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M8000
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
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M8000
5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All
registers above 0Ah are RESERVED.
Default: 0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data format and
the Master clock dividers for all channels. It also contains a Control Port enable bit.
Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone Mode.
When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding register values
become functional.
Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit invokes 256X
mode (divide XTI by 1.0 - pass through).
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is selected.
When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divided by 4.
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M8000
The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
CLKMODE,MDIV[1],MDIV[0] DESCRIPTION
0 Divide-by-1
100 Divide-by-1.5
001 or 010 Divide-by-2
101 or 110 Divide-by-3
11 Divide-by-4
111 Reserved
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data.
DIF[1:0]
0x00 Left-Justified format
0x01 I²S format
0x02 TDM
0x03 Reserved
Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as an audio
clocking Master or Slave.
MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds
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M8000
5.6 04h ( HPF ) High-Pass Filter Register
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M8000
5.11 09h Reserved
6. FILTER PLOTS
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M8000
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M8000
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M8000
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60
dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This technique ensures
that the distortion components are below the noise level and do not affect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-199, and the Electronic Industries Association
of Japan, EIAJ CP-307. Expressed in decibels. The dynamic range is specified with and without an A-weighting filter.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz.
Units in decibels.
Interchannel Isolation
A measure of crosstalk between one channel and all remaining channels, measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to all other channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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M8000
Intra-Channel Phase Deviation
The deviation from linear phase within a given channel.
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M8000
9. Package Information
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