Scribd
Upload
57 views20 pages

Lecture-14 CH-04 2

This document discusses pipelining in computer processors. It describes how pipelining works by overlapping the execution of instructions across multiple stages to improve performance. It discusses different types of hazards that can occur in pipelines like structural hazards from competing for resources, data hazards from instructions depending on previous results, and control hazards from branches. Various techniques are presented to mitigate hazards like forwarding, stalling, code scheduling, and branch prediction. The goal of pipelining is to increase the processor's throughput by executing multiple instructions simultaneously while keeping individual instruction latency the same.

Uploaded by

Osama Rousan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
57 views20 pages

Lecture-14 CH-04 2

This document discusses pipelining in computer processors. It describes how pipelining works by overlapping the execution of instructions across multiple stages to improve performance. It discusses different types of hazards that can occur in pipelines like structural hazards from competing for resources, data hazards from instructions depending on previous results, and control hazards from branches. Various techniques are presented to mitigate hazards like forwarding, stalling, code scheduling, and branch prediction. The goal of pipelining is to increase the processor's throughput by executing multiple instructions simultaneously while keeping individual instruction latency the same.

Uploaded by

Osama Rousan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 20

COMPUTER ORGANIZATION AND DESIGN 6th

Edition
The Hardware/Software Interface

Chapter 4
The Processor
Performance Issues
◼ Longest delay determines clock period
◼ Critical path: load instruction
◼ Instruction memory → register file → ALU →
data memory → register file
◼ Not feasible to vary period for different
instructions
◼ Violates design principle
◼ Making the common case fast
◼ We will improve performance by pipelining

Chapter 4 — The Processor — 2


Datapath With Control

Chapter 4 — The Processor — 3


§4.6 An Overview of Pipelining
Pipelining Analogy
◼ Pipelined laundry: overlapping execution
◼ Parallelism improves performance

◼ Four loads:
◼ Speedup
= 8/3.5 = 2.3
◼ Non-stop:
◼ Speedup
= 2n/(0.5n + 1.5) ≈ 4
n is the number of
stages

Chapter 4 — The Processor — 4


MIPS Pipeline
◼ Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 5


Pipeline Performance
◼ Assume time for stages is
◼ 100ps for register read or write
◼ 200ps for other stages
◼ Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register ALU op Memory Register Total time


read access write
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 6


Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 7


Pipeline Speedup
◼ If all stages are balanced
◼ i.e., all take the same time
◼ Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
◼ If not balanced, speedup is less
◼ Speedup due to increased throughput
◼ Latency (time for each instruction) does not
decrease

Chapter 4 — The Processor — 8


Pipelining and ISA Design
◼ MIPS ISA designed for pipelining
◼ All instructions are 32-bits
◼ Easier to fetch and decode in one cycle
◼ c.f. x86: 1- to 17-byte instructions
◼ Few and regular instruction formats
◼ Can decode and read registers in one step
◼ Load/store addressing
◼ Can calculate address in 3rd stage, access memory
in 4th stage
◼ Alignment of memory operands
◼ Memory access takes only one cycle

Chapter 4 — The Processor — 9


Hazards
◼ Situations that prevent starting the next
instruction in the next cycle
◼ Structure hazards
◼ A required resource is busy
◼ Data hazard
◼ Need to wait for previous instruction to
complete its data read/write
◼ Control hazard
◼ Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 10


Structural Hazards
◼ Conflict for use of a resource
◼ In MIPS pipeline with a single memory
◼ Load/store requires data access
◼ Instruction fetch would have to stall for that
cycle
◼ Would cause a pipeline “bubble”
◼ Hence, pipelined datapaths require
separate instruction/data memories
◼ Or separate instruction/data caches

Chapter 4 — The Processor — 11


Data Hazards
◼ An instruction depends on completion of
data access by a previous instruction
◼ add $s0, $t0, $t1
sub $t2, $s0, $t3

Chapter 4 — The Processor — 12


Forwarding (aka Bypassing)
◼ Use result when it is computed
◼ Don’t wait for it to be stored in a register
◼ Requires extra connections in the datapath

Chapter 4 — The Processor — 13


Load-Use Data Hazard
◼ Can’t always avoid stalls by forwarding
◼ If value not computed when needed
◼ Can’t forward backward in time!

Chapter 4 — The Processor — 14


Code Scheduling to Avoid Stalls
◼ Reorder code to avoid use of load result in
the next instruction
◼ C code for A = B + E; C = B + F;

lw $t1, 0($t0) lw $t1, 0($t0)


lw $t2, 4($t0) lw $t2, 4($t0)
stall add $t3, $t1, $t2 lw $t4, 8($t0)
sw $t3, 12($t0) add $t3, $t1, $t2
lw $t4, 8($t0) sw $t3, 12($t0)
stall add $t5, $t1, $t4 add $t5, $t1, $t4
sw $t5, 16($t0) sw $t5, 16($t0)
13 cycles 11 cycles

Chapter 4 — The Processor — 15


Control Hazards
◼ Branch determines flow of control
◼ Fetching next instruction depends on branch
outcome
◼ Pipeline can’t always fetch correct instruction
◼ Still working on ID stage of branch
◼ In MIPS pipeline
◼ Need to compare registers and compute
target early in the pipeline
◼ Add hardware to do it in ID stage

Chapter 4 — The Processor — 16


Stall on Branch
◼ Wait until branch outcome determined
before fetching next instruction

Chapter 4 — The Processor — 17


Branch Prediction
◼ Longer pipelines can’t readily determine
branch outcome early
◼ Stall penalty becomes unacceptable
◼ Predict outcome of branch
◼ Only stall if prediction is wrong
◼ In MIPS pipeline
◼ Can predict branches not taken
◼ Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 18


MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

Chapter 4 — The Processor — 19


Pipeline Summary
The BIG Picture

◼ Pipelining improves performance by


increasing instruction throughput
◼ Executes multiple instructions in parallel
◼ Each instruction has the same latency
◼ Subject to hazards
◼ Structure, data, control
◼ Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 20

You might also like