Issue.

: 1 Revision: 26

HIGH DATA RATE RECEIVER

CORTEX Series

HDR-XXL USER’S MANUAL

DTU 100355
EVOLUTIONS

Is. Rev. Date Description

1 0 September 1, 2006 Document created

1 1 March 1, 2007 General update

1 2 June 1, 2007 General update

1 3 August 29, 2007 Software upgrade e6r7

1 4 October 1, 2007 Software upgrade e7r0

1 5 November 30, 2007 General update

1 6 February 26, 2008 Software upgrade e7r2

1 7 May 30, 2008 Software upgrade e7r3

1 8 December 15, 2008 Software upgrade e8r0

1 9 February 15, 2009 Software upgrade e8r1

1 10 May 2, 2009 16QAM performances

1 11 July 1, 2009 Software upgrade e8r3

1 12 September 24, 2009 Software upgrade e8r4

1 13 December 15, 2009 Software upgrade e8r5

1 14 February 15, 2010 Software upgrade e8r6

 Issue.: 1 Revision: 26

EVOLUTIONS

Is. Rev. Date Description

1 15 August 20, 2010 Software upgrade e8r7

1 16 December 14, 2010 Software upgrade e8r8 and e8r9

1 17 April 15, 2011 Software upgrade e8r10

1 18 June 30, 2011 Software upgrade e8r11

1 19 September 9, 2011 Software upgrade e8r12

1 20 April 16, 2012 Software upgrade e8r13 (Multi-DPU processing update) and e8r14

1 21 May 14, 2012 Software upgrade e9r0 (Support for Windows 7 Operating System and Diversity combining)

1 22 September 15, 2012 Software upgrade e9r1

1 23 January 15, 2013 Software upgrade e9r3

1 24 February 5, 2013 Marking and Security update

1 25 March 29, 2013 Software upgrade e9r4

1 26 June 28, 2013 Software upgrade e9r4.1

COPYRIGHT

THIS DOCUMENT IS THE PROPERTY OF ZODIAC DATA SYSTEMS

UNDER THE COPYRIGHT LAWS, IT MUST NOT BE REPRODUCED OR TRANSMITTED IN ANY

FORM, ELECTRONIC OR MECHANICAL, INCLUDING PHOTOCOPYING, RECORDING, STORING

IN AN INFORMATION RETRIEVAL SYSTEM, OR TRANSLATING, IN WHOLE OR IN PART,

WITHOUT THE PRIOR WRITTEN APPROVAL OF ZODIAC DATA SYSTEMS.

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

CONTENTS

1. CORTEX HDR OVERVIEW ................................................................................................. 5

1.1 SCOPE ..................................................................................................................................................................... 6

1.2 CORTEX HDR MAIN FEATURES ........................................................................................................................... 7

1.3 MISSION OF THE CORTEX HDR ............................................................................................................................ 8

1.3.1 Introduction ............................................................................................................................................ 8
1.3.2 Operating Modes .................................................................................................................................... 8
1.3.3 Telemetry Demodulation ........................................................................................................................ 9
1.3.4 Telemetry Processing ............................................................................................................................. 9
1.3.5 Polarization Combining ....................................................................................................................... 10
1.3.6 Simulation & Self-testing ...................................................................................................................... 11

1.4 CORTEX HDR ARCHITECTURE ........................................................................................................................... 12

1.4.1 Functional Block Diagram of a Demodulation Channel ...................................................................... 12
1.4.2 Test Modulator Functional Block Diagram ......................................................................................... 13
1.4.3 CORTEX HDR Hardware Architecture................................................................................................ 14
1.4.3.1 PC-compatible Workstation ......................................................................................................................................... 15
1.4.3.2 Test Modulator Board .................................................................................................................................................. 16
1.4.3.3 Demodulator Board ...................................................................................................................................................... 17
1.4.3.4 I/O Connectors ............................................................................................................................................................. 17
1.4.4 CORTEX HDR Software ....................................................................................................................... 18
1.4.4.1 Local or Remote M&C ................................................................................................................................................. 18
1.4.4.2 Password Protection ..................................................................................................................................................... 18
1.4.4.3 Software Version .......................................................................................................................................................... 19

1.5 CORTEX HDR INTERFACES ................................................................................................................................ 20

1.5.1 Mechanical & Electrical Interfaces...................................................................................................... 20
1.5.2 TCP-IP Interface .................................................................................................................................. 20
1.5.3 FTP Interface ....................................................................................................................................... 21

1.6 CORTEX HDR PERFORMANCES .......................................................................................................................... 22

1.6.1 Demodulation Unit ............................................................................................................................... 22
1.6.1.1 IF Reception ................................................................................................................................................................. 22
1.6.1.2 Demodulation ............................................................................................................................................................... 23
1.6.1.3 Bit Synchronization ...................................................................................................................................................... 24
1.6.1.4 Filtering ........................................................................................................................................................................ 25
1.6.1.5 Viterbi Convolutional Decoding .................................................................................................................................. 25
1.6.1.6 De-scrambler ................................................................................................................................................................ 26
1.6.1.7 Transport Layer (RS-DVB or asynchronous LDPC layer) ........................................................................................... 27
1.6.1.8 BEM 4D 8PSK TCM DVB-S R-S ............................................................................................................................... 27
1.6.1.9 VHR-DVB-S2 and CCSDS-SCCC standard ................................................................................................................ 28
1.6.1.10 OQPSK/8PSK variable modulation............................................................................................................................ 28
1.6.2 Diversity Combining Unit..................................................................................................................... 29
1.6.3 Data Processing Unit ........................................................................................................................... 30
1.6.3.1 Frame Synchronization ................................................................................................................................................ 30
1.6.3.2 Data Time-tagging ....................................................................................................................................................... 30
1.6.3.3 CRC Frame checking ................................................................................................................................................... 30
1.6.3.4 CCSDS and ECSS Decoding ....................................................................................................................................... 30
1.6.3.5 LDPC Decoding ........................................................................................................................................................... 31
1.6.3.6 Data Output .................................................................................................................................................................. 32
1.6.4 Data Storage......................................................................................................................................... 33

ZODIAC DATA SYSTEMS PROPRIETARY Page i

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

1.6.5 Playback ............................................................................................................................................... 35

1.6.6 Test Modulator ..................................................................................................................................... 36
1.6.6.1 IF Modulation............................................................................................................................................................... 36
1.6.6.2 Noise Source ................................................................................................................................................................ 36
1.6.6.3 Modulation ................................................................................................................................................................... 36
1.6.6.4 PCM Simulation ........................................................................................................................................................... 37
1.6.6.5 Doppler Simulation ...................................................................................................................................................... 37
1.6.7 Start-up Menus ..................................................................................................................................... 38
1.6.8 Frequency Reference ............................................................................................................................ 38
1.6.8.1 External Reference ....................................................................................................................................................... 38
1.6.8.2 Internal Reference ........................................................................................................................................................ 38
1.6.9 Time Code Reference ............................................................................................................................ 38
1.6.10 Mechanical - Environment ................................................................................................................... 39
1.6.11 Supply ................................................................................................................................................... 39

2. HARDWARE DESCRIPTION ............................................................................................ 41

2.1 CORTEX HDR INTEGRATION ........................................................................................................................ 42

2.1.1 Hardware Configuration ...................................................................................................................... 42
2.1.2 PC-compatible Workstation ................................................................................................................. 43
2.1.3 Demodulator board .............................................................................................................................. 44
2.1.3.1 Overview ...................................................................................................................................................................... 44
2.1.3.2 First generation board: single IF input ......................................................................................................................... 44
2.1.3.3 Second generation board: separate IF inputs ................................................................................................................ 45
2.1.4 Test Modulator Board .......................................................................................................................... 46
2.1.5 Extension Board ................................................................................................................................... 46
2.1.6 Specific I/O Board ................................................................................................................................ 46

2.2 I/O CONNECTORS DEFINITION ..................................................................................................................... 47

2.2.1 CPU Board I/Os ................................................................................................................................... 47
2.2.2 Demodulator & Test Modulator I/Os ................................................................................................... 47
2.2.2.1 HDR I/O with single IF input and optional SCSI interface for RAID-5 DR2912 storage device................................ 47
2.2.2.2 HDR I/Os with single IF input and optional LVDS / TTL interfaces ........................................................................... 48
2.2.2.3 HDR I/Os with separate IF inputs ................................................................................................................................ 49
2.2.2.4 HDR I/Os with separate IF inputs and optional optical fibre interface for RAID-5 ER2912 storage device ............... 50
2.2.2.5 HDR I/Os Demodulator with with separate IF inputs and output extension................................................................. 51
2.2.2.6 Demodulator I/Os ......................................................................................................................................................... 52
2.2.2.7 Test Modulator I/Os ..................................................................................................................................................... 65
2.2.3 Output Data Definition and Timing ...................................................................................................... 67
2.2.3.1 Timing for all output types ........................................................................................................................................... 67
2.2.3.2 I/Q merged output ........................................................................................................................................................ 68
2.2.3.3 Split 2 output (I and Q normal output) ......................................................................................................................... 68
2.2.3.4 Split 4 output ................................................................................................................................................................ 69
2.2.3.5 CADU output formats .................................................................................................................................................. 70
2.2.4 Specific I/Os (Customers requirements) ............................................................................................... 70

3. FUNCTIONAL DESCRIPTION ......................................................................................... 71

3.1 MONITORING & CONTROL .................................................................................................................................... 72

3.1.1 Monitoring ............................................................................................................................................ 72
3.1.2 Control ................................................................................................................................................. 72

3.2 LOGGING ................................................................................................................................................................ 72

3.3 DEMODULATION ..................................................................................................................................................... 73

3.3.1 IF Processing ....................................................................................................................................... 73
3.3.2 Bit Synchronization .............................................................................................................................. 73
3.3.2.1 Signal Processing ......................................................................................................................................................... 73

ZODIAC DATA SYSTEMS PROPRIETARY Page ii

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

3.3.2.2 Customized FIR Filters ................................................................................................................................................ 74

3.3.2.3 DEAF Filtering............................................................................................................................................................. 76
3.3.2.4 XDEAF for reception of dual polarization data transmission ....................................................................................... 79
3.3.2.5 Adjacent channel rejection ........................................................................................................................................... 82
3.3.3 Viterbi Convolutional Decoding ........................................................................................................... 83
3.3.3.1 General ......................................................................................................................................................................... 83
3.3.3.2 Single or Dual Viterbi Decoder .................................................................................................................................... 84
3.3.3.3 Parallel Viterbi decoders .............................................................................................................................................. 85
3.3.3.4 Punctured Viterbi ......................................................................................................................................................... 86
3.3.4 PCM Decoding ..................................................................................................................................... 88
3.3.4.1 DNRZ, QPSK Decoding (DQPSK) .............................................................................................................................. 88
3.3.4.2 DNRZ, OQPSK Decoding ........................................................................................................................................... 90
3.3.5 I/Q Shift Compensation in OQPSK Mode ............................................................................................ 92
3.3.6 CCITT V.35 De-scrambler ................................................................................................................... 92
3.3.7 BEM : 4D-8PSK-TCM-DVB-S Reed Solomon Decoding ..................................................................... 93
3.3.7.1 Introduction .................................................................................................................................................................. 93
3.3.7.2 4D-8PSK-TCM Coder.................................................................................................................................................. 93
3.3.7.3 DVB-S Transport Layer : Reed Solomon Code ......................................................................................................... 101
3.3.8 PRN-BER Computation ...................................................................................................................... 105
3.3.8.1 BER on Separate I & Q Channels .............................................................................................................................. 105
3.3.8.2 BER on Merged I & Q Channels ................................................................................................................................ 105
3.3.9 Digital Outputs ................................................................................................................................... 107
3.3.10 Doppler and Integrated Phase Measurement ..................................................................................... 107
3.3.10.1 Introduction .............................................................................................................................................................. 107
3.3.10.2 Required setup for optimal performance .................................................................................................................. 107
3.3.10.3 Sampling rate ........................................................................................................................................................... 108
3.3.10.4 Accumulated Phase Format ...................................................................................................................................... 108
3.3.10.5 Displaying the carrier offset of the Doppler port in the DMU window .................................................................... 112
3.3.10.6 Interpolation Process ................................................................................................................................................ 113
3.3.10.7 Doppler Computing .................................................................................................................................................. 113
3.3.10.8 Impact of Phase Errors on Doppler Computing........................................................................................................ 114
3.3.10.9 Sampling Period Resolution ..................................................................................................................................... 114

3.4 DATA PROCESSING ............................................................................................................................................... 116

3.4.1 Functional Breakdown of the Data Processing Unit .......................................................................... 116
3.4.2 Frame Synchronization & Ambiguity Resolution ............................................................................... 117
3.4.2.1 Frame Synchronization Strategy ................................................................................................................................ 117
3.4.2.2 Frame Synchronizer Input .......................................................................................................................................... 118
3.4.2.3 Automatic PSK Ambiguity Resolution ...................................................................................................................... 119
3.4.3 CCSDS Data De-randomizer.............................................................................................................. 120
3.4.4 Customized Data De-randomization .................................................................................................. 121
3.4.5 CRC Frame Checking......................................................................................................................... 122
3.4.6 (255,223) Reed-Solomon Decoding .................................................................................................... 122
3.4.7 (255,239) Reed-Solomon Decoding .................................................................................................... 123
3.4.8 (10,6) Reed-Solomon Frame Header Decoding ................................................................................. 123
3.4.9 Specific Decoding ............................................................................................................................... 123
3.4.10 LDPC Decoding ................................................................................................................................. 124
3.4.10.1 Introduction .............................................................................................................................................................. 124
3.4.10.2 LDPC 7/8 for near-earth applications ....................................................................................................................... 124
3.4.10.3 LDPC 1/2 and 2/3 codes for deep space applications .............................................................................................. 124
3.4.10.4 Implementation ........................................................................................................................................................ 125
3.4.10.5 Performances ............................................................................................................................................................ 126
3.4.11 Recording and Data Transmission over Ethernet .............................................................................. 130
3.4.11.1 Data Storage ............................................................................................................................................................. 130
3.4.11.2 TCP-IP Data Recovery ............................................................................................................................................. 131
3.4.11.3 Archiving and FTP Recovery ................................................................................................................................... 132
3.4.12 Playback function ............................................................................................................................... 138
3.4.12.1 Operating Modes ...................................................................................................................................................... 138
3.4.12.2 Sources of the data to replay .................................................................................................................................... 139
3.4.13 Multi-DPU processing........................................................................................................................ 140
3.4.13.1 Generality ................................................................................................................................................................. 140
3.4.13.2 Ambiguity resolution by the DPUs .......................................................................................................................... 145

ZODIAC DATA SYSTEMS PROPRIETARY Page iii

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

3.4.13.3 BER measurements .................................................................................................................................................. 147

3.4.13.4 Data output ............................................................................................................................................................... 147
3.4.13.5 Guide for multi DPU Operation ............................................................................................................................... 148

3.5 POLARIZATION COMBINING ................................................................................................................................ 159

3.5.1 General ............................................................................................................................................... 159
3.5.2 Data Path ........................................................................................................................................... 159
3.5.3 Signal Processing ............................................................................................................................... 160

3.6 TEST MODULATION............................................................................................................................................... 162

3.6.1 IF Signal Generation .......................................................................................................................... 162
3.6.2 PCM Generation ................................................................................................................................ 163
3.6.2.1 Pseudo Random Data ................................................................................................................................................. 163
3.6.2.2 PCM Simulation from File ......................................................................................................................................... 165
3.6.2.3 PCM Simulation from External Data & Clock ........................................................................................................... 165
3.6.2.4 Constellation Mapping ............................................................................................................................................... 166

3.7 SYSTEM BER VS EB/NO ......................................................................................................................................... 170

3.7.1 Theoretical Probability of Bit Error ................................................................................................... 170
3.7.2 Eb/No vs C/No at Demodulator Input ................................................................................................ 175
3.7.3 Some System Examples ....................................................................................................................... 175
3.7.4 Examples ............................................................................................................................................ 176

3.8 CABLE EQUALIZER FILTER .................................................................................................................................. 178

3.9 DATA LOGGING..................................................................................................................................................... 180

4. OPERATING MANUAL ..................................................................................................... 181

4.1 STARTING AND CONFIGURING THE CORTEX HDR ........................................................................................... 182

4.1.1 First Steps ........................................................................................................................................... 182
4.1.1.1 Starting the PC Workstation ....................................................................................................................................... 182
4.1.1.2 Signal Processing Software. Start-up Menu ............................................................................................................... 182
4.1.1.3 Starting the Monitoring & Control Software .............................................................................................................. 182
4.1.2 Factory Configuration ........................................................................................................................ 183
4.1.3 Software Exit & CORTEX HDR Shutdown ........................................................................................ 183
4.1.3.1 Exiting the Monitoring & Control Software ............................................................................................................... 183
4.1.3.2 Exiting the Signal Processing Software ...................................................................................................................... 183
4.1.3.3 Restarting the SPS & MCS ........................................................................................................................................ 183
4.1.3.4 CORTEX HDR Shutdown ......................................................................................................................................... 184
4.1.4 Screen Saver ....................................................................................................................................... 184

4.2 SIGNAL PROCESSING SOFTWARE (SPS) ............................................................................................................... 185

4.2.1 CTX Documents .................................................................................................................................. 185
4.2.2 SPS Start Sequence ............................................................................................................................. 185
4.2.3 Configuring the CORTEX from CTX Documents ............................................................................... 186
4.2.3.1 CTX Document Name Table ...................................................................................................................................... 186
4.2.3.2 CTX Document Storage and Loading ........................................................................................................................ 186
4.2.4 Start-up Menu Selection by Remote Access Control (RAC) ............................................................... 187
4.2.4.1 General ....................................................................................................................................................................... 187
4.2.4.2 MCS Graphical User Interface ................................................................................................................................... 188
4.2.4.3 Menus Description File .............................................................................................................................................. 189
4.2.5 SPS Version Identification .................................................................................................................. 190
4.2.5.1 Common Data ............................................................................................................................................................ 190
4.2.5.2 CORTEX HDR Specific Data .................................................................................................................................... 190
4.2.6 CORTEX HDR System Parameters in Registry .................................................................................. 191
4.2.6.1 CORTEX Station ....................................................................................................................................................... 191

ZODIAC DATA SYSTEMS PROPRIETARY Page iv

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

4.2.6.2 Demodulation Unit ..................................................................................................................................................... 191

4.2.6.3 Transport Layer : Frame Synchronizer Setting........................................................................................................... 193
4.2.6.4 Test Modulation Unit ................................................................................................................................................. 196
4.2.6.5 Global HDR ............................................................................................................................................................... 197

4.3 MONITORING & CONTROL SOFTWARE (MCS) ................................................................................................... 198

4.3.1 General ............................................................................................................................................... 198
4.3.2 MCS Documents ................................................................................................................................. 199
4.3.3 MCS Start Sequence. MCS Control Status ......................................................................................... 200
4.3.4 M&C Session. MCS Documents Management ................................................................................... 202
4.3.4.1 Close the Active M&C Session .................................................................................................................................. 202
4.3.4.2 Open an M&C session with a CORTEX .................................................................................................................... 202
4.3.4.3 Save the CORTEX Configuration to an MCS Document on the Disk ....................................................................... 202
4.3.4.4 Reconfigure the CORTEX from an Existing MCS Document ................................................................................... 202
4.3.5 Graphical User Interface ................................................................................................................... 203
4.3.5.1 MCS Login Window .................................................................................................................................................. 203
4.3.5.2 MTDI (Multiple Tabbed Document Interface) ........................................................................................................... 204
4.3.5.3 Upper Toolbar ............................................................................................................................................................ 205
4.3.5.4 Lower Toolbar ............................................................................................................................................................ 208
4.3.5.5 Bottom Status Toolbar ............................................................................................................................................... 210
4.3.6 CORTEX Monitoring & Configuration .............................................................................................. 211
4.3.6.1 Default Operating Mode............................................................................................................................................. 211
4.3.6.2 CORTEX Configuration ............................................................................................................................................ 211
4.3.6.3 Forced Connection to the Control Port (Pseudo Local Mode) ................................................................................... 212
4.3.6.4 OK/DIFFER Management Mode ............................................................................................................................... 212
4.3.7 MCS Version Identification ................................................................................................................ 213
4.3.8 Changing a Password......................................................................................................................... 214
4.3.9 MCS Interface for CTX document management ................................................................................. 215
4.3.10 MCS Interface for User MCS files loading......................................................................................... 216
4.3.11 MCS File System Architecture ............................................................................................................ 217
4.3.12 MCS System Parameters in Registry .................................................................................................. 218
4.3.12.1 Monitoring ............................................................................................................................................................... 218
4.3.12.2 MCS Auto-Connect .................................................................................................................................................. 218
4.3.12.3 MCS Preferences ...................................................................................................................................................... 219

4.4 OPERATING SYSTEM AND FILES ARCHITECTURE ................................................................................................ 220

4.4.1 Introduction ........................................................................................................................................ 220
4.4.2 Files Architecture ............................................................................................................................... 220
4.4.2.1 Files associated with Monitoring & Control Software ............................................................................................... 220
4.4.2.2 Files associated with the Signal Processing Software ................................................................................................ 220
4.4.2.3 Files associated with the Cortex HDR Hardware ....................................................................................................... 221
4.4.2.4 Other Files .................................................................................................................................................................. 221
4.4.3 Windows 7 Tools & Functionnalities ................................................................................................. 222

4.5 CORTEX HDR GUI ............................................................................................................................................ 223

4.5.1 Conventions &Warnings .................................................................................................................... 223
4.5.2 Graphical User Interface. Windows Breakdown ................................................................................ 224
4.5.3 CORTEX HDR Top-level Windows .................................................................................................... 225
4.5.3.1 “Global” Window....................................................................................................................................................... 225
4.5.3.2 “Time” Window ......................................................................................................................................................... 230
4.5.3.3 Time Management Procedures ................................................................................................................................... 232
4.5.3.4 “Config.” Window ..................................................................................................................................................... 236
4.5.3.5 “Project” Window ...................................................................................................................................................... 241
4.5.3.6 “Information” Window .............................................................................................................................................. 242
4.5.4 Demodulator Windows ....................................................................................................................... 243
4.5.4.1 “Global” Window....................................................................................................................................................... 243
4.5.4.2 “Physical layer” Window ........................................................................................................................................... 260
4.5.4.3 “BER” Window .......................................................................................................................................................... 263
4.5.4.4 “Decoding” Window .................................................................................................................................................. 266
4.5.4.5 “Spectrum” Window .................................................................................................................................................. 272

ZODIAC DATA SYSTEMS PROPRIETARY Page v

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

4.5.4.6 “Vector” Window....................................................................................................................................................... 274

4.5.4.7 “Filter” Window ......................................................................................................................................................... 278
4.5.5 Data Processing Unit Windows .......................................................................................................... 280
4.5.5.1 “CADU” Window ...................................................................................................................................................... 280
4.5.5.2 “Transport Layer” Windows ...................................................................................................................................... 288
4.5.5.3 “BER” Windows ........................................................................................................................................................ 290
4.5.5.4 “Real Time Frame” Window ...................................................................................................................................... 292
4.5.5.5 “Quick Look” Window .............................................................................................................................................. 294
4.5.6 Polarization Combining Windows ...................................................................................................... 297
4.5.6.1 “Global” Window....................................................................................................................................................... 297
4.5.6.2 “BER” Window .......................................................................................................................................................... 299
4.5.6.3 “Decoding” Window .................................................................................................................................................. 299
4.5.6.4 “Vector” Window....................................................................................................................................................... 299
4.5.7 Data Recording Unit Windows ........................................................................................................... 300
4.5.7.1 “Global Disk and Memory Management” Window ................................................................................................... 300
4.5.7.2 “Recording Global” Window ..................................................................................................................................... 305
4.5.7.3 “FTP” window ........................................................................................................................................................... 310
4.5.7.4 “Virtual Channels” Window ...................................................................................................................................... 314
4.5.8 Test modulator Windows .................................................................................................................... 315
4.5.8.1 “Modulation” Window ............................................................................................................................................... 315
4.5.8.2 “PCM” Window ......................................................................................................................................................... 321
4.5.8.3 “Encoding” Window .................................................................................................................................................. 324
4.5.8.4 “Physical Layer” Window .......................................................................................................................................... 328
4.5.9 Playback Windows.............................................................................................................................. 330
4.5.9.1 “Global” Window....................................................................................................................................................... 330
4.5.9.2 “File” Window ........................................................................................................................................................... 332
4.5.10 Logging Windows ............................................................................................................................... 338
4.5.10.1 “Data Logging Control” Window............................................................................................................................. 338
4.5.10.2 “Data Logging Editor” Window ............................................................................................................................... 340
4.5.11 Licenses and Basic Menus .................................................................................................................. 342

5. MAINTENANCE PROCEDURES ..................................................................................... 353

5.1 GENERAL .............................................................................................................................................................. 354

5.1.1 Mechanical Inspection and Cleaning ................................................................................................. 354
5.1.2 Handling Precautions ......................................................................................................................... 354
5.1.3 CPU Load Considerations ................................................................................................................. 355
5.1.4 Software Loading ............................................................................................................................... 355

5.2 FUNCTIONAL INVESTIGATION.............................................................................................................................. 355

5.2.1 Demodulator Check ............................................................................................................................ 355
5.2.2 Viterbi Check ...................................................................................................................................... 356
5.2.3 Demodulator Output Ports ................................................................................................................. 356
5.2.4 Interpretation of the Vector Display ................................................................................................... 357

5.3 HARDWARE INVESTIGATION & REPAIR .............................................................................................................. 362

5.3.1 LED Indicators ................................................................................................................................... 362
5.3.1.1 Test Modulator Board ................................................................................................................................................ 362
5.3.1.2 Demodulator Board .................................................................................................................................................... 362
5.3.1.3 CPU Board ................................................................................................................................................................. 362
5.3.2 IPMIMonitor Tool. Temperature Alarm ............................................................................................. 362
5.3.3 PC Workstation Maintenance ............................................................................................................. 363

5.4 SOFTWARE UPGRADE & INSTALLATION ............................................................................................................. 364

5.4.1 Loading or Upgrading the IN-SNEC Software ................................................................................... 364
5.4.2 Complete Software Re-installation ..................................................................................................... 364

6. SATELLITES CONFIGURATION EXAMPLES ............................................................ 365

ZODIAC DATA SYSTEMS PROPRIETARY Page vi

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

7. ANNEX 1: CORTEX HDR ETHERNET INTERFACE..................................................... A

8. ANNEX 2: DEMODULATOR BOARD ............................................................................... B

9. ANNEX 3: TEST MODULATOR BOARD .......................................................................... C

10. ANNEX 4: PC-COMPATIBLE WORKSTATION ............................................................. D

11. ANNEX 5: PROJECT-SPECIFIC DATA ............................................................................ E

ZODIAC DATA SYSTEMS PROPRIETARY Page vii

 HIGH DATA RATE RECEIVER HDR-XXL ZDS Ref : DTU 100355 Issue : 1 Rev.: 26
CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

LIST OF FIGURES

FIGURE 1 : CORTEX HDR DEMODULATION AND INGESTION FUNCTIONAL BLOCK DIAGRAM ......................................... 12
FIGURE 2 : CORTEX HDR TEST MODULATOR FUNCTIONAL BLOCK DIAGRAM ............................................................... 13
FIGURE 3 : CORTEX HDR HARDWARE BLOCK DIAGRAM ................................................................................................ 14
FIGURE 4 : EXMPLE OF CORTEX HDR WORKSTATION .................................................................................................... 15
FIGURE 5 : TEST MODULATOR. FUNCTIONAL BLOCK DIAGRAM ........................................................................................ 16
FIGURE 6 : MCS SOFTWARE VERSION ............................................................................................................................... 19
FIGURE 7 : CORTEX HDR TCP-IP INTERFACES ............................................................................................................... 21
FIGURE 8 : DEMODULATOR STAGE WITH SINGLE IF INPUT ................................................................................................. 44
FIGURE 9 : DEMODULATOR STAGE WITH SEPARATE IF INPUTS ........................................................................................... 45
FIGURE 10 : CORTEX HDR I/OS WITH SINGLE IF INPUT AND OPTIONAL SCSI STORAGE.................................................. 47
FIGURE 11 : CORTEX HDR I/OS WITH SINGLE IF INPUT AND OPTIONAL LVDS / TTL INTERFACES ................................. 48
FIGURE 12 : CORTEX HDR I/OS WITH SEPARATE IF INPUTS ............................................................................................ 49
FIGURE 13 : CORTEX HDR I/OS WITH ECL OUTPUT EXTENSION ..................................................................................... 51
FIGURE 14 : SOFT DECISION CODING VS I/Q CONSTELLATION (NORMAL SOFT OUTPUT) .................................................. 63
FIGURE 15 : SOFT DECISION CODING VS I/Q CONSTELLATION (MERGE SOFT OUTPUT) .................................................... 64
FIGURE 16 : EFFECT OF THE DEAF. ................................................................................................................................... 78
FIGURE 17 : EFFECT OF THE XDEAF. ................................................................................................................................ 81
FIGURE 18 : VITERBI DECODING MODULE. SINGLE & DUAL OPERATING MODES ............................................................. 84
FIGURE 19 : PARALLEL VITERBI DECODING MODULE. ...................................................................................................... 85
FIGURE 20 : VITERBI DE-PUNCTURING PROCESS................................................................................................................ 86
FIGURE 21 : PUNCTURED VITERBI BER PERFORMANCES. .................................................................................................. 88
FIGURE 22 : STRUCTURE OF THE 4D 8PSK-TCM CODER/MAPPER .................................................................................... 94
FIGURE 23 : DIFFERENTIAL CODER AND MODULO-8 ADDER PRINCIPLE ............................................................................ 95
FIGURE 24 : CONVOLUTIONAL CODER RECOMMENDED FOR HIGH DATA RATES ............................................................... 96
FIGURE 25: CONSTELLATION MAPPER FOR 2 BITS/CHANNEL-SYMBOL ............................................................................... 97
FIGURE 26 : CONSTELLATION MAPPER FOR 2.25 BITS/CHANNEL-SYMBOL ......................................................................... 97
FIGURE 27 : CONSTELLATION MAPPER FOR 2.5 BITS/CHANNEL-SYMBOL ............................................................................ 98
FIGURE 28 : CONSTELLATION MAPPER FOR 2.75 BITS/CHANNEL-SYMBOL ......................................................................... 99
FIGURE 29: CODER AND MAPPER IMPLEMENTATION AT 2 BITS/CHANNEL-SYMBOL EFFICIENCY ....................................... 99
FIGURE 30 : CODER AND MAPPER IMPLEMENTATION AT 2.25 BITS/CHANNEL-SYMBOL EFFICIENCY................................ 100
FIGURE 31: CODER AND MAPPER IMPLEMENTATION AT 2.5 BITS/CHANNEL-SYMBOL EFFICIENCY .................................. 100
FIGURE 32 : CODER AND MAPPER IMPLEMENTATION AT 2.75 BITS/CHANNEL-SYMBOL EFFICIENCY................................ 100
FIGURE 33 : CONCATENATION PRINCIPLE ........................................................................................................................ 101
FIGURE 34 : RANDOMIZATION PRINCIPLE ........................................................................................................................ 102
FIGURE 35 : DATA ARRANGEMENT IN TCM 2.5 BITS/CHANNEL_SYMBOL ....................................................................... 104
FIGURE 36 : BER MEASUREMENT METHODS : TESTED AMBIGUITIES AND GUI DISPLAY ................................................ 106
FIGURE 37 : DATA PROCESSING UNIT BLOCK DIAGRAM ................................................................................................. 116
FIGURE 38 : FRAME SYNCHRONIZATION PROCESS ........................................................................................................... 118
FIGURE 39 : DATA TRANSMISSION OVER TCP-IP. MESSAGE FORMATTING ..................................................................... 131
FIGURE 40 : RECORDED DATA FILE STRUCTURE ............................................................................................................. 133
FIGURE 41 : CCSDS FTP MODE STORAGE DIRECTORIES ................................................................................................ 135
FIGURE 42 : PLAYBACK FUNCTION : TEST MODULATOR OPERATING MODE ..................................................................... 138
FIGURE 43 : PLAYBACK FUNCTION : TEST MODULATOR DATA + CLOCK MODE ............................................................... 138
FIGURE 44 : QPSK DEMODULATION WITH 2 DPU ............................................................................................................ 141
FIGURE 45 : QPSK OR 16QAM DEMODULATION WITH 4 DPU......................................................................................... 142
FIGURE 46 : 16QAM DEMODULATION WITH 8 DPU......................................................................................................... 143
FIGURE 47 : QPSK OR 16QAM DEMODULATION WITH 1 DPU......................................................................................... 144
FIGURE 48 : QPSK DEMODULATION WITH 2 DPU ............................................................................................................ 144
FIGURE 49 : 8 DPU DATA FLOW FOR AUTOMATIC AMBIGUITY RESOLUTION ................................................................... 145
FIGURE 50 : PROBABILITY OF BIT ERROR VS EB/NO FOR DIFFERENT PCM CODES ......................................................... 170
FIGURE 51 : PROBABILITY OF BIT ERROR VS EB/NO WITH CONVOLUTIONAL CODING (RATE: 1/2) .................................. 171
FIGURE 52 : PROBABILITY OF BIT ERROR VS EB/NO WITH REED-SOLOMON CODING ...................................................... 171
FIGURE 53 : PROBABILITY OF BIT ERROR VS EB/NO IN 8PSK MODE WITH OR AT 2,5 BIT/SYMBOL.................................. 172

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FIGURE 54: PROBABILITY OF BIT ERROR VS EB/NO WITH GMSK ................................................................................... 173
FIGURE 55: PROBABILITY OF BIT ERROR VS EB/NO WITH 16QAM AND RS DECODING (800 MBPS) ............................... 174
FIGURE 56 : EXAMPLE OF NON-LINEARITY IN A RG188A/U CABLE ................................................................................ 178
FIGURE 57 : EXAMPLE OF COMPENSATION - SYMBOL RATE = 150 MBPS......................................................................... 179
FIGURE 58 : SPS START SEQUENCE ................................................................................................................................. 185
FIGURE 59: CTX DOCUMENT MANAGEMENT .................................................................................................................. 187
FIGURE 60 : MCS MENU MANAGEMENT WINDOW .......................................................................................................... 188
FIGURE 61 : ABOUT CORTEX SPS VERSION .................................................................................................................. 190
FIGURE 62 : MCS START SEQUENCE................................................................................................................................ 200
FIGURE 63 : MCS TOP-LEVEL WINDOW .......................................................................................................................... 203
FIGURE 64 : MCS LOGIN WINDOW .................................................................................................................................. 203
FIGURE 65 : MULTIPLE TABBED DOCUMENT INTERFACE ................................................................................................. 204
FIGURE 66 : CORTEX MCS ABOUT : SOFTWARE VERSION ............................................................................................... 213
FIGURE 67 : CHANGING A PASSWORD .............................................................................................................................. 214
FIGURE 68 : GRAPHICAL USER INTERFACE: WINDOWS BREAKDOWN .............................................................................. 224
FIGURE 69 : CORTEX HDR : GLOBAL WINDOW............................................................................................................ 225
FIGURE 70 : GLOBAL ENGINEERING WINDOW ................................................................................................................. 228
FIGURE 71 : TCP-IP SECONDARY WINDOW ..................................................................................................................... 229
FIGURE 72 : CORTEXXL « TIME » WINDOW ................................................................................................................... 230
FIGURE 73 : LEAP SECOND MANAGEMENT ...................................................................................................................... 233
FIGURE 74 : CORTEX HDR : CONFIG. WINDOW............................................................................................................. 236
FIGURE 75 : CORTEX HDR : CONFIG. WINDOW WITH EXTENSION BOARD .................................................................... 237
FIGURE 76 : CONFIGURATION HELP WINDOW FOR THE DEMODULATOR .......................................................................... 239
FIGURE 77 : CONFIGURATION HELP WINDOW FOR THE TEST MODULATOR ...................................................................... 239
FIGURE 78 : CORTEX HDR : PROJECT WINDOW ............................................................................................................ 241
FIGURE 79 : CORTEX HDR : INFORMATION WINDOW ................................................................................................... 242
FIGURE 80 : DEMODULATOR : GLOBAL WINDOW FOR QPSK MODULATION + I & D FILTER ........................................... 243
FIGURE 81 : DEMODULATOR : GLOBAL WINDOW FOR QPSK MODULATION + RAISED COSINE FILTER ........................... 243
FIGURE 82 : DEMODULATOR : GLOBAL WINDOW FOR QPSK MODULATION + CUSTOM FILTER ...................................... 244
FIGURE 83 : DEMODULATOR : GLOBAL WINDOW FOR OQPSK MODULATION................................................................. 244
FIGURE 84 : DEMODULATOR : GLOBAL WINDOW FOR GMSK MODULATION .................................................................. 245
FIGURE 85 : DEMODULATOR : GLOBAL WINDOW FOR SOQPSK MODULATION .............................................................. 245
FIGURE 86 : DEMODULATOR : GLOBAL WINDOW FOR UQPSK MODULATION................................................................. 246
FIGURE 87 : DEMODULATOR: GLOBAL WINDOW FOR 8PSK MODULATION ..................................................................... 246
FIGURE 88 : DEMODULATOR: GLOBAL WINDOW FOR 16QAM MODULATION ................................................................. 247
FIGURE 89 : DEMODULATOR: GLOBAL WINDOW FOR 16APSK MODULATION ................................................................ 247
FIGURE 90 : DEMODULATOR: GLOBAL WINDOW FOR 32APSK MODULATION ................................................................ 248
FIGURE 91 : DEMODULATOR: GLOBAL WINDOW FOR 64APSK MODULATION ................................................................ 248
FIGURE 92 : DEMODULATOR: GLOBAL WINDOW FOR VCM QPSK / 8PSK ..................................................................... 249
FIGURE 93 : DEMODULATOR: GLOBAL WINDOW FOR DVB-S2 /SCC .............................................................................. 249
FIGURE 94 : DEMODULATOR: GLOBAL WINDOW FOR MULTI-DPU OPERATION .............................................................. 250
FIGURE 95: DEMODULATOR : PHYSICAL LAYER WINDOW FOR SCCC AND DVB-S2 STANDARD...................................... 260
FIGURE 96: DEMODULATOR : BER WINDOW PRN MODE ................................................................................................ 263
FIGURE 97: DEMODULATOR : BER WINDOW FILE MODE ................................................................................................. 263
FIGURE 98 : DEMODULATOR : DECODING WINDOW FOR BPSK MODULATION ................................................................ 266
FIGURE 99 : DEMODULATOR : DECODING WINDOW FOR QPSK & OQPSK MODULATION (VITERBI SINGLE) ................. 266
FIGURE 100 : DEMODULATOR : DECODING WINDOW FOR QPSK & OQPSK MODULATION (VITERBI DUAL) ................. 267
FIGURE 101 : DEMODULATOR : DECODING WINDOW FOR UQPSK MODULATION ........................................................... 267
FIGURE 102 : DEMODULATOR : DECODING WINDOW FOR 8PSK MODULATION ............................................................... 268
FIGURE 103 : DEMODULATOR : SPECTRUM WINDOW....................................................................................................... 272
FIGURE 104 : DEMODULATOR : BPSK VECTOR WINDOW ................................................................................................ 274
FIGURE 105 : DEMODULATOR : QPSK(OQPSK) VECTOR WINDOW ................................................................................ 274
FIGURE 106 : DEMODULATOR : 8PSK VECTOR WINDOW ................................................................................................ 275
FIGURE 107 : DEMODULATOR : 16QAM VECTOR WINDOW ............................................................................................ 275
FIGURE 108 : DEMODULATOR : 16APSK VECTOR WINDOW............................................................................................ 276
FIGURE 109 : DEMODULATOR : 32APSK VECTOR WINDOW............................................................................................ 276
FIGURE 110 : FILTER: TIME DISPLAY SELECTION ............................................................................................................ 278
FIGURE 111 : FILTER: FREQUENCY DISPLAY SELECTION ................................................................................................. 278

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FIGURE 112 : DPU : CADU WINDOW .............................................................................................................................. 280

FIGURE 113 : DPU : TRANSPORT LAYER WINDOW (R-S DVB MODE) ............................................................................ 288
FIGURE 114 : DPU : BER WINDOW ................................................................................................................................. 290
FIGURE 115 : DATA PROCESSING UNIT : REAL TIME FRAME WINDOW ............................................................................ 292
FIGURE 116 : DATA PROCESSING UNIT : QUICK LOOK WINDOW ..................................................................................... 294
FIGURE 117 : TELEMETRY BLOCK DESCRIPTION.............................................................................................................. 295
FIGURE 118 : POLARIZATION COMBINING: GLOBAL WINDOW ......................................................................................... 297
FIGURE 119 : GLOBAL DISK & MEMORY MANAGEMENT WINDOW (CONFIGURATION) ................................................... 300
FIGURE 120 : GLOBAL DISK & MEMORY MANAGEMENT WINDOW (STATUS) ................................................................. 300
FIGURE 121 : DRU : RECORDING GLOBAL WINDOW ....................................................................................................... 305
FIGURE 122 : DRU : FTP WINDOW (GENERIC) ................................................................................................................ 310
FIGURE 123 : DRU : FTP WINDOW (CCSDS STANDARD)................................................................................................ 310
FIGURE 124 : DRU : VIRTUAL CHANNELS WINDOW ........................................................................................................ 314
FIGURE 125 : TEST MODULATOR : MODULATION WINDOW FOR BPSK, QPSK AND UQPSK .......................................... 315
FIGURE 126 : TEST MODULATOR : MODULATION WINDOW FOR OQPSK ........................................................................ 315
FIGURE 127 : TEST MODULATOR : MODULATION WINDOW FOR 8PSK ............................................................................ 316
FIGURE 128 : TEST MODULATOR : MODULATION WINDOW FOR 16QAM ........................................................................ 316
FIGURE 129 : TEST MODULATOR : MODULATION WINDOW FOR 16APSK ....................................................................... 317
FIGURE 130 : TEST MODULATOR : MODULATION WINDOW FOR 32APSK ....................................................................... 317
FIGURE 131 : TEST MODULATOR : MODULATION WINDOW FOR 64APSK ....................................................................... 318
FIGURE 132 : TEST MODULATOR : SCCC DVBS2 MODULATION STANDARD ................................................................... 318
FIGURE 133 : TEST MODULATOR : PCM WINDOW FOR BPSK, QPSK, OQPSK, 8PSK, 16QAM AND N-APSK .............. 321
FIGURE 134 : TEST MODULATOR : PCM WINDOW FOR UQPSK ...................................................................................... 321
FIGURE 135 : TEST MODULATOR : ENCODING WINDOW FOR BPSK, QPSK, OQPSK, UQPSK AND 16QAM ................. 324
FIGURE 136 : TEST MODULATOR : ENCODING WINDOW FOR 8PSK ................................................................................. 324
FIGURE 137 : TEST MODULATOR : PHYSICAL LAYER WINDOW FOR SCCC AND DVB-S2 STANDARD ............................. 328
FIGURE 138 : PLAYBACK : GLOBAL WINDOW .................................................................................................................. 330
FIGURE 139 : PLAYBACK : FILE WINDOW IN REPORT TM MODE (BY DATE) ................................................................... 332
FIGURE 139 : PLAYBACK : FILE WINDOW IN REPORT TM MODE (BY NUMBER) .............................................................. 332
FIGURE 140 : PLAYBACK : FILE WINDOW IN PLAYBACK DATA FILE MODE..................................................................... 333
FIGURE 141 : PLAYBACK : FILE WINDOW IN BER FILE MODE ......................................................................................... 333
FIGURE 141 : PLAYBACK : FILE WINDOW IN RECORDED FRAMES MODE ......................................................................... 334
FIGURE 142 : LOGGING STATUS WINDOW ........................................................................................................................ 338
FIGURE 143 : LOGGING EDITOR WINDOW ........................................................................................................................ 340

ZODIAC DATA SYSTEMS PROPRIETARY Page x

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ACRONYMS & ABBREVIATIONS

SYMBOLS:
% Percent
 Plus or minus
 Greater than or equal
 Less than or equal
 And
 Approximately

PREFIXES:
n Nano-
 Micro-
m Milli-
k Kilo-
M Mega-
G Giga-
T Tera-

UNITS:
A Ampere
b Byte
bps Bit per second
C Celsius
dB Decibel
F Farad
Hz Hertz
mm Millimeter
rpm revolutions per minute
 Ohms
s Second
sps Symbol per second
s/s Sample per second (ks/s, Ms/s,...)
V Volt

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ABBREVIATIONS:
AD Applicable Document
AGC Automatic Gain Control
AIT Assembly Integration and Test
APSK Amplitude and Phase Shift Keying
AQPSK Asynchronous Quadrature Phase Shift Keying
ASB Anti Side Band
ASCII American Standard Code for Information Interchange
BR Bit Rate
BER Bit Error Rate
BEM Bandwidth Efficient Modulation
BP-L Bi-Phase-L
BP-M Bi-Phase-M
BP-S Bi-Phase-S
BPSK Binary Phase Shift Keying
BW Band Width
CADU Channel Access Data Unit
CCITT Consultative Committee on International Telegraphy and Telephony
CFDP CCSDS File Delivery Protocol
CCSDS Consultative Committee for Space Data Systems
CLK Clock
CMA Constant Modulus Algorithm
CPU Central Processing Unit
DAS Direct Attachment Storage
dBc dB with respect to the un-modulated carrier
DC Direct Current
DEAF Digital Equalization Automatic Filter
DEM / DMU Demodulation Unit
DNRZ Differential Non Return to Zero (NRZ-L with differential encoding in QPSK modulation)
DPU Data Processing Unit
DRG Data Recording Global
DRU Data Recording Unit
DSP Digital Signal Processor
DVB Digital Video Broadcasting (DVB-S / DVB-S2 standards)
D/C frequency Down Converter
ECL Emitter Coupled Logic

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ECSS European Cooperation for Space Standardization

EMC Electro Magnetic Compatibility
FIR Finite Impulse Response
FFT Fast Fourrier Transform
FM Frequency Modulation
FPGA Field Programmable Gate Array
FTP File Transfer Protocol
GMSK Gaussian Minimum Shift Keying
GM/Ksps Giga, Mega, Kilo Symbols Per Second
GUI Graphical User Interface
HDR High Data rate Receiver
HBW High Band Width
IF Intermediate Frequency
I/F Interface
I/O Input/Output
I&D Integral & Dump
LAN Local Area Network
LDPC Low Density Parity Check code
LED Light Emitting Diode
LMS Least Mean Square algorithm
LO Local Oscillator
LPF Low Pass Filter
HBF High Band Filter
LSB Least Significant Byte (Bit)
LVDS Low Voltage Differential Signal
MCS Monitoring & Control Software
MMI Man Machine Interface
MSB Most Significant Byte (Bit)
MTBF Mean Time Between Failure
MTTR Mean Time To Replace
M&C Monitoring & Control
NA Not Applicable
NRZ-L Non Return to Zero Level
NRZ-M Non Return to Zero Mark
NRZ-S Non Return to Zero S
OQPSK Offset Quadrature Phase Shift Keying

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PC Personal Computer
PLL Phase Locked Loop
PM Phase Modulation
pp Peak to peak
PS Power Supply
PSK Phase Shift Keying
QPSK Quadrature Phase Shift Keying
RAID Redundant Array of Independent Disks
RF Radio Frequency
RMS Root Mean Square
RRC Root Raised Cosine
R-S (RS) Reed-Solomon
SAN Storage Array Network
SNUG (NASA) Space Network User’s Guide
SCSI Small Computer System Interface
SOQPSK Shaped Offset Quadrature Phase Shift Keying
SPS Signal Processing Software
SR Symbol Rate
SQPSK Staggered Quadrature Phase Shift Keying
TBC To Be Confirmed
TBD To Be Defined
TCM Trellis Coded Modulation
TCP/IP Transport Control Protocol / Internet Protocol
TM TeleMetry
UQPSK Unbalanced Quadrature Phase Shift Keying
UTC Universal Time, Coordinated
U/C frequency Up Converter
VC Virtual Channel
VCDU Virtual channel Data Unit
VCID Virtual Channel Identifier
VCM Variable Coding Modulation
VSWR Voltage Standing Wave Ratio
WAN Wide Area Network
ZDS Zodiac Data Systems
16QAM 16 states Quadrature Amplitude Modulation

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CAUTION

CAUTION
RISK OF ELECTRICAL SHOCK
DO NOT OPEN
!
CAUTION : TO REDUCE THE RISK OF ELECTRIC SHOCK,
DO NOT REMOVE COVER (OR BACK).
REFER SERVICING TO QUALIFIED PERSONNEL.

LEGEND

The exclamation point within an equilateral triangle is intended to alert the user
to the presence of important operating and maintenance (servicing) instructions
in the literature accompanying the product.

The lightning flash with an arrowhead symbol within an equilateral triangle, is

intended to alert the user to the presence of uninsulated ‘dangerous voltage’
within the product’s enclosure that may be of sufficient magnitude to constitute
a risk of electric shock to persons.

ZODIAC DATA SYSTEMS PROPRIETARY Page 1

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IMPORTANT SAFETY INSTRUCTIONS

This product is designed and manufactured to meet strict quality and safety standards (conformity to “EN
60950:2002 standard: Safety of information technology equipment.

However, you should be aware of the following installation and operation precautions:

Take heed of warning and instructions

You should read all the safety and operating instructions before operating this apparatus.
Retain this handbook for future reference and adhere to all warnings in the handbook or on the
apparatus

Water and moisture

To reduce the risk of fire or electric shock, do not expose this apparatus to rain or moisture.
The presence of electricity near water can be dangerous. Do not use the apparatus near water.

Object or liquid entry

Take care that objects do not fall and liquids are not spilled into the product chassis through
any openings.

Installation

Ensure that the product chassis ventilation is not impeded.

Do not block any ventilation openings. Install in accordance with the manufacturer’s
instructions.

Only use attachments and accessories specified by the manufacturer.

This unit must should be used in a 19” rack mount cabinet only

Cleaning

Unplug the unit before cleaning.

Clean only with dry cloth.
This product should normally only require a wipe with a soft, damp, lint-free cloth.
Do not use paint thinner or other chemical solvents for cleaning.

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Opening of the product chassis

To reduce the risk of electric shock, do not remove cover (or back).
No user serviceable parts inside ; the product chassis should only be opened by
qualified personnel for maintenance purpose ( except for opposite instructions in the
user’s manual ).

Technical Maintenance

Refer all servicing to qualified maintenance personnel. Servicing is required when apparatus
has been damaged in any way, such as power supply cord is damaged, liquid has been spilled
or objects have fallen into the apparatus, the apparatus has been exposed to rain or moisture,
does not operate normally, or has been dropped.

The qualified maintenance personnel must take reasonable precautions to face the
obvious DANGERS.

Powers sources

Only connect the apparatus to a power supply of the described in the operating instructions or
as marked on the apparatus.

Turning off the power switch does not completely isolate this product from the power line so
remove the plug from the socket if not using it for extended period of time.

Unplug this apparatus during lightning storms.

Power cord protection

Power supply cords should be routed so that they are not likely to be walked on or pinched by
items placed upon or against them, paying particular attention to cords and plugs, and the
point where they exit from the appliance

Grounding

WARNING : this apparatus shall be connected to a mains socket outlet with a

protective earthing connection.
The appliance must be connected to an electrical ground and the power cord is
designed for that.

Power supply cable and socket

This apparatus must be used with a power supply cable of 1 mm2 section minimum
The power supply socket must be located at a distance of less than 1.5 m from the
equipment

ZODIAC DATA SYSTEMS PROPRIETARY Page 3

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Lifting the unit

If this apparatus weighs over 25kgs, so take extreme care when lifting or moving this
unit. We recommend that two people are available to lift this unit.

Battery replacement and disposal

CAUTION: Risk of explosion if battery is replaced by an incorrect type. Dispose of

used batteries according the instructions.

CE MARKING

Markings are placed at the rear of the unit, regarding the power ratings and compliance.

The symbol on the PC chassis indicates that it is in compliance with the Electromagnetic
Compatibility directive (2006/95/EC) and the low Voltage directive (IEC60950-1/A1:200973/23/CEE) . A
certificate of compliance is available by contacting technical support. This equipment is a:
 Group 1 Class A product
Recommendation concerning the cabling :

CE certification has been carried out with 3-meter interconnecting cables with remote equipment.

ZODIAC DATA SYSTEMS recommends the use of high quality interconnecting cables type. The high
quality recommended user interconnecting cables are “shield twisted pair” or “coaxial cable” industrial type
with cable shield. The cable shield will provide the necessary mechanical protection.

Not using this high quality designed cable could result in unexpected intersystem/extrasystem
electromagnetic emission and susceptibility.

INTERNATIONAL SECURITY STATEMENT

France, Canada: L’appareil doit être connecté à une prise de terre

Suomi: Laite on liitettävä suojamaadoituskoskettimilla varustettuun pistorasiaan

Norge: Apparatet ma tilkoples jordet stikkontakt

Sverige: Apparaten skall anslutas till jordat uttag

ZODIAC DATA SYSTEMS PROPRIETARY Page 4

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CORTEX SERIES - USER’s MANUAL Customer Ref : Date : June 28, 2013

1. CORTEX HDR
OVERVIEW

ZODIAC DATA SYSTEMS PROPRIETARY Page 5

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1.1 SCOPE
This manual contains the information necessary to install, configure, operate and maintain the ZDS PC-based
High Data Rate Receiver XXL (CORTEX HDR XXL).

The document is divided into six main sections:

 Section 1 : CORTEX HDR overview and performances,

 Section 2 : Hardware description and I/O connections,

 Section 3 : Functional description,

 Section 4 : Operating procedures and description of the Graphical User Interface,

 Section 5 : Hardware and software maintenance procedures,

 Section 6 : Configuration examples for different satellites.

Project-specific information (if any) and additional data on the CORTEX HDR are annexed to the document :

 Annex 1 : Description of the TCP-IP Ethernet interface.

 Annexes 2 & 3 : Layout of the Test Modulator board and Demodulator board.

 Annex 4 : Description of the PC compatible workstation.

 Annex 5 : Hardware and software configuration of the CORTEX HDR at delivery. Project-specific data if any.

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1.2 CORTEX HDR MAIN FEATURES

High Data Rate Telemetry Processing

Dual-demodulator capability with fully tunable IF @ 720 MHz and/or Mono-demodulator

capability with fully tunable IF @ 1.2 GHz (Hardware dependent)

Supported demodulations : BPSK, QPSK, OQPSK (SQPSK), UQPSK (AQPSK, AUQPSK,

AUSQPSK), 8PSK, GMSK, SOQPSK, 16QAM, 16APSK, 32APSK, 64 APSK

Digital filtering : RRC, GMSK, SOQPSK, User defined, Equalizer, static or auto-adaptive mode
(DEAF)

Viterbi decoding : CCSDS, single or dual mode, ½ (+ puncture) or ¼ rate, single or parallel
processing

4D-TCM (Multi-Trellis Coded Modulation) decoding : CCSDS BEM

Data processing : frame synchronization, time-tagging, De-randomization, R-S decoding, CCSDS,

DVB, ECSS, CRC, CCSDS Packet reconstruction and CFDP

Low Density Parity Check Code decoding (CCSDS LDPC 7/8, 2/3 and 1/2 )

Data ingestion : data storage with programmable filtering and sorting for further transmission to
remote clients or/and real-time data transmission to remote Clients

Data replay: capability to replay the recorded data (Playback mode)

High Integration with Drastically Reduced Hardware for Increased Availability

Extensive Use of Digital Signal Processing Techniques for Enhanced Performance, Upgradability
and Flexibility

PC-based Architecture

Built-in Test & Simulation Capability

User-friendly and Intuitive Graphic User Interface

Wide Range of Configuration Parameters and Status

No Tuning, no Preventive Maintenance

ZODIAC DATA SYSTEMS PROPRIETARY Page 7

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1.3 MISSION OF THE CORTEX HDR

1.3.1 Introduction
The Cortex High Data rate Receiver is dedicated to the reception of the high rate telemetry of the remote sensor
satellites.

The Cortex HDR is part of the Cortex family products, all using the same architecture: a board with FPGA chips
plugged into the 4U-high Cortex chassis (equipped with Intel Server Board).

The Cortex HDR fulfills :

 Telemetry demodulation,

 Telemetry processing,

 Telemetry simulation for test purposes (optional),

Following to 4 possible operating modes.

1.3.2 Operating Modes

The HDR XXL is available with two generations of demodulator boards.

The first generation of demodulator board provides a single 720 MHz IF input. The second generation provides
two independent 720 MHz IF inputs and one independent 1.2 GHz IF input. Each input is dubbed with an alternate
connector.

Depending on the delivered hardware configuration (first or second generation of demodulator board), the
delivered operational configuration (licenses dependent) and the selected start-up menu, the HDR can be
operated in one of the following four operating modes:

 Mode 1: Mono demodulator on single 720 MHz IF input

 Mode 2: Dual demodulators on single 720 MHz IF input

 Mode 3: Dual demodulators on two independent 720 MHz IF inputs

 Mode 4: Mono demodulator on single 1.2 GHz IF input

The 4 modes are supported by the second generation of demodulator board. Only modes 1 and 2 are supported
by the first generation.

Performances and particularly the supported maximum bit rates are dependent on the operating mode.

Depending on the delivered configuration (licenses dependent) and the selected start-up menu, one or two data
processing units can be connected at the output of two parallel demodulator units, or up to heigh processing units
can be connected at the output of one demodulator unit.

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1.3.3 Telemetry Demodulation

 Input frequency : 720 MHz nominal, tunable between 530 and 910 MHz

or

1.2 GHz nominal, tunable between 910 MHz and 1490 MHz

 Automatic carrier acquisition

 BPSK, QPSK, OQPSK (SQPSK), UQPSK (AQPSK, AUQPSK, AUSQPSK), 8PSK, GMSK, SOQPSK, 16QAM,
16APSK, 32APSK, 64APSK demodulation

 Equalization filter: static or auto-adaptive (DEAF)

 Automatic compensation for cross-polarization perturbations(XDEAF)

 Adjacent channel rejection filters

 Bit synchronization

 Fully digital matched and shaped filters: Raised Cosine, Root Raised Cosine, GMSK, SOQPSK shaping filter
(CCSDS and IRIG standard), User defined

 Viterbi decoding : single or dual mode, ½ (+ puncture) or ¼ rate, single or parallel processing (stacked Viterbi)

 De-scrambler: CCITT V.35 and Intelsat V.35

 4D-TCM (Trellis Coded Modulation) decoding

 DVB-S2 and SCCC standard supported

1.3.4 Telemetry Processing

 Multi-channel architecture (up to 8 parallel channels – Multi DPU processing)

 Transport Layer for RS DVB or LDPC decoders (Asynchronous decoding layer)

 CADU Frame synchronization (CCSDS Transfer layer)

 Data time-tagging (internal, external IRIG B signal or external NTP server)

 De-randomization, De-interleaving, Virtual filling, Reed-Solomon decoding (supported standard: CCSDS, DVB-
S, ECSS)

 CRC frame checking

 CCSDS Low Density Parity Check decoding (LDPC 7/8, 2/3 and 1/2)

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 Programmable data filtering and sorting with dynamical creation of directories and files for recovery by remote
clients using FTP

 Data output : Raw data or frames (CADU / VCDU)

Real-time data or stored data

Data files

 Data interface :

 Standard PCM outputs (differential Data plus Clock outputs): multi format provided:

- output of the demodulator unit (DMU) or output of the data processing unit (DPU)

- merged or split at the output of the DMU (2, 4 or 8 streams)

- possibility of Soft Decision at the output of the demodulator(separate I and Q 3 bits or merged
I/Q 6 bits)

 Ethernet Network: TCP-IP. FTP server

 Data storage: internal or on external DAS (hardware dependant – consult ZDS)

 Raw data, CADU, VCDU or Packet

 CFDP protocol

 Replay of recorded data

1.3.5 Polarization Combining

 Modes: Selection of the best channel or combining of two channels.

 Maximum combining gain: 3 dB (identical Eb/No on both channels)

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1.3.6 Simulation & Self-testing

The CORTEX HDR incorporates powerful simulation & testing capabilities for functional and performance test
purposes :

 Telemetry simulation

 Noise generation.

 IF Modulation.

 Doppler simulation

 Automatic BER measurement.

 Real time IF spectrum analysis.

 Real time vector analysis.

 Unit self-testing at boot.

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1.4 CORTEX HDR ARCHITECTURE

1.4.1 Functional Block Diagram of a Demodulation Channel

Digital Outputs

Data + Clock

Vector Demodulation Generation

(1 or 2 demod )

Analog Processing BPSK, QPSK,

IF Inputs (1 or 2 IF inputs) O/S/U/A/QPSK
SOQPSK 8PSK Optional Optional
Bit
16QAM Viterbi CADU
Sync
A/D Conversion Rejection & Matched filter or TCM RS or LDCP
PCM
decoding Decoding
I&D Decoding
RRC /GMSK / SOQPSK filters Descrambling
EQUALIZATION Transport layer
DEAF

Optional ingestion: SCSI output

Frame Synchronization
Time Tagging
5/10 MHz Input
Real Time TCP/IP
Time & Frequency
Data Storage
Distribution Internal or external SCSI DAS
Time Code Input

BER Measurement

Vector Analysis

Spectrum Analysis

Automatic filter display Ethernet LAN

Monitoring & Control

Monitoring & Control

Software Package (MCS)

Graphical User Interface

(Free Copyright)

Figure 1 : CORTEX HDR Demodulation and Ingestion Functional Block Diagram

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1.4.2 Test Modulator Functional Block Diagram

Noise Generation

IF Output

IF Modulation Telemetry Simulation

BPSK, QPSK, O/UQPSK Pseudo-random or File
8PSK, 16QAM RS DVB transport layer
TCM / VITERBI CADU
RS or LDPC encoding

Ext. LO Input Digital Input

Figure 2 : CORTEX HDR Test Modulator Functional Block Diagram

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1.4.3 CORTEX HDR Hardware Architecture

The CORTEX HDR comprises the following elements:

 A PC-compatible workstation,

 A Demodulator board (ZDS),

 An optional Test Modulator board, including a noise generator and a telemetry simulator (ZDS).

PC-compatible Workstation

1G Base T
ETHERNET PORT

Dual-Pentium CPU Board

PCI BUS

Monitoring TM Data DC Supply Monitoring DC Supply

& Control & Control

Demodulator Board Test Modulator Board

(Option)

IF PCM + CLOCK 10M + IRIG+AGC IF TEST

INPUTS I/Os I/Os OUTPUT I/Os

Figure 3 : CORTEX HDR Hardware Block Diagram

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1.4.3.1 PC-compatible Workstation

The PC-compatible workstation includes :

 A rack-mountable industrial PC chassis (19-inch width, 4 rack-space).

 A dual-Pentium CPU board.

 An integrated 8-inch color display (800x600 SVGA).

 An extractable keyboard / pointing device for local operation.

 A hard disk for the operating system and application software.

 A set of hard disks for data recording (last generations).

 A CD drive.

Refer to Annex 4 for more detail on the PC-compatible workstation.

Figure 4 : Example of CORTEX HDR Workstation

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1.4.3.2 Test Modulator Board

Test Modulator is an optional board for test purposes :

 PCM generation : internal data (pseudo-random or pattern from files) or external data (+ associated clock).

 PCM encoding

 Frame encoding (CADU size)

 Randomization

 Error code encoding (exclusive functions):

RS DVB transport layer,

CCSDS RS,

LDPC.

 Convolutional encoding.

 Carrier generation & modulation (programmable Bit rate and IF frequency) :

BPSK, QPSK, OQPSK, UQPSK, (TCM) 8PSK, 16QAM, 16APSK, 32 APSK, 64 APSK

 Baseband pulse shape filtering (RRC, GMSK)

 Modulated signal output with programmable power level.

 Noise generation with programmable power level.

 Doppler simulation

 DVB-S2 and SCCC modulation sequences simulation

Carrier ON/OFF
External OL Carrier Generation

External I & Q
Data + Clock Modulation ON/OFF Vector Modulation
PCM & Viterbi BPSK/QPSK
Encoding OQPSK/UQPSK
Internal PCM 8PSK
Generation
PRN or File

Output Level
Setting

Level Setting
Noise ON/OFF
Noise Source
-93 to –132 dBm/Hz +

IF Output

Figure 5 : Test Modulator. Functional Block Diagram

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1.4.3.3 Demodulator Board

Main features of the Demodulator board are :

 Amplification, filtering and analog-to-digital conversion of the IF signal.

 Digital vector demodulation.

 Bit synchronization.

 Viterbi (or TCM) decoding.

 PCM decoding

 Frame synchronization

 Time tagging
 De-randomization, RS or LDPC decoding

 Data and Clock output.

 BER measurement.

 Vector analysis.

The Demodulator board is monitored and controlled by the Pentium CPU board via the PCI bus.

1.4.3.4 I/O Connectors

SMA-type I/O connectors are located at the rear panel of the chassis (Demodulator I/Os and Test Modulator I/Os).
The HDR can be delivered with LVDS outputs (option) or other.

See Section 2 for a detailed description of the I/O ports.

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1.4.4 CORTEX HDR Software

The CORTEX HDR is supplied with two separate software packages :

 Signal Processing Software package (SPS)

 Monitoring & Control Software package (MCS)

These software are executed under the control of the Operating System. Software configuration at delivery is
described in Annex 5.

1.4.4.1 Local or Remote M&C

The Signal Processing Software and Monitoring & Control Software communicate by means of connected sockets
under TCP-IP protocol. As a result, the notion of local or remote M&C no longer applies to the CORTEX HDR :
since the MCS software package can be installed (free copyright) into any PC-based computer(s), there is no
difference between operating the equipment locally (front panel keyboard and screen) or remotely, provided that
the CORTEX HDR and the PC-based computer(s) are connected to the same Ethernet network.

1.4.4.2 Password Protection

The following functions are password-protected :

 Cortex user login.

 CORTEX HDR configuration.

 Reset of TCP-IP connections.

Default setting at delivery: cortex (login function). Other functions: no password.

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1.4.4.3 Software Version

The software version at delivery is described in Annex 5 and, in more details, in the CORTEX HDR Acceptance
Test Report (document reference: CRE100135).

 PROMed software (Demodulator and Test Modulator boards) : see the factory acceptance test results
(CRE100135).

 Disk resident software (SPS & MCS) :

 Signal Processing Software (FPGA & DSP software downloaded to the Demodulator board at boot-up) :
open the CONFIG window (see Section 4.5.3.2 for more details).

 Signal Processing Software (Pentium software) : click on at the bottom of the screen. Then select
About Cortex... to display the software version.

 Monitoring & Control Software : click on or on Help in the top-level window, then select About
CrtxMcs... :

Figure 6 : MCS Software Version

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1.5 CORTEX HDR INTERFACES

1.5.1 Mechanical & Electrical Interfaces
Refer to Section 1.6 and 2.2 for signal characteristics (bit rate, carrier frequency, modulation, PCM code, level,
impedance, test points, etc…) and I/O connections.

1.5.2 TCP-IP Interface

Monitoring & Control data are exchanged between the Signal Processing Software (SPS) and remote M&C clients
over a single Ethernet port. The CORTEX HDR acts as a data server. Data are exchanged using the connected-
sockets communication protocol.

Some data flows accept multiple clients at a time (monitoring, logging, spectrum analysis, vector analysis data),
while other flows accept only one client at a time (equipment configuration and reset).

Each type of transfer flow is allocated a specific port number which the clients use for connecting to the
equipment. Port numbers are listed below :

MAXIMUM NUMBER OF
DATA FLOW PORT NUMBER
CONNECTIONS

CORTEX HDR Monitoring Data (MON) 3000 24

CORTEX HDR Control Data (CTRL) 3001 1

CORTEX HDR Remote Access Control (RAC) 3003 1

TCP-IP Reset (RST) 3002 1

Logging Data (LOG) 3040 5

Telemetry Data (TM) 3075 (Option) 6

Spectrum Analysis Data (SPA) 3050 3

Vector Analysis Data (VEC) 3055 3

Doppler or Analysis Data (DOP) 3060 3

Table 1 : CORTEX HDR TCP-IP Port Addresses

A detailed description of this interface is available in Annex 1 (Documents reference : STI 100013 and STI
100013_HDR).

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Next figure shows data flows between CORTEX HDR software components and between the CORTEX HDR and
the outside world :

Single-client Connections
M&C SOFTWARE

Multi-client Connections

CLIENTS

SIGNAL PROCESSING
SOFTWARE
Spectrum Analysis Data (SPA)
3050

Control Data (CTRL)

REMOTE TCP-IP CLIENTS

3001

Monitoring Data (MON)

3000
Telemetry Data (Option)
3075

Reset Commands (RST) DATA SERVER

3002

Logging Data (LOG)

3040

Vector Analysis Data (VEC)

3055
RAC Commands (RAC)
3003

Figure 7 : CORTEX HDR TCP-IP Interfaces

1.5.3 FTP Interface

Received data frames can be filtered and sorted, depending on the selected TM flow, the result of the Reed-
Solomon decoding, the virtual channels, or User defined. The resulted data frames are embedded inside specified-
names files and can be store in dedicated directories on an archiving system.

In order to recover the constructed data files through the network by external Clients, the CORTEX HDR is fitted
with a powerful FTP server. External Clients can connect this server at the standard dedicated FTP port number.

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1.6 CORTEX HDR PERFORMANCES

WARNING :

PERFORMANCE DATA IN THIS SECTION ARE TYPICAL VALUES MEASURED IN BEST CASE CONDITIONS.

SOME FUNCTIONALITIES MAY STILL BE IN THE DEVELOPMENT PHASE.

PLEASE CONTACT ZDS FOR MORE INFORMATION.

PROGRAMMING RESOLUTION: REFER TO ANNEX 1. CONFIGURATION PARAMETERS ARE SPECIFIED OVER

32-BIT INTEGERS OR SINGLE-PRECISION FLOAT (8-BIT EXPONENT AND TWO’s COMPLEMENT 24-BIT

MANTISSA). HOWEVER, RESOLUTION CAN BE LIMITED BY THE HARDWARE DESIGN. LIMITATIONS ARE

DESCRIBED IN THE GRAPHICAL USER INTERFACE .

1.6.1 Demodulation Unit

1.6.1.1 IF Reception
Dual-demodulator capability Operating mode 1: Mono demodulator on single 720 MHz IF input

Operating mode 2: Dual demodulators on single 720 MHz IF input

Operating mode 3: Dual demodulators on 2 independent 720 MHz IF

Operating mode 4: Single demodulator on single 1.2 GHz IF input

Input frequency 720 MHz  190 MHz or 1.2 GHz  290 MHz (hardware dependent)

Frequency setting step Single precision float

Input ports 2 (selectable) per IF inputs (Normal and Alternate)

Input stages 1 or 2 depending on the operating mode

Input impedance 50 

VSWR < 1.3

AGC range -10 dBm to -50 dBm

AGC time constant 1 ms

AGC test 0 Volt (IF level  -60 dBm) to 3 Volts (IF level -10 dBm)
Minimum termination : 1000 

Carrier acquisition range ± 10 kHz to ± 1 MHz

IF bandwidth Automatically adjusted from the symbol rate

IF level variation  10 dB/sec

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1.6.1.2 Demodulation
Demodulation (notes 1) BSPK , QPSK , OQPSK (SQPSK)

UQPSK (AQPSK, AUQPSK, AUSQPSK), 8PSK, GMSK, 16QAM, 16APSK,

32APSK, 64APSK

SOQPSK (MIL standard filter, IRIG TG filter, CCSDS A-type or B-type filters)
Bit rates (notes 1, 2 & 3)
Operating mode 1 (mono demodulator @ 720 MHz IF input)::

Maximum actual symbol rate 320 Msps

Maximum Bit rate in BPSK mode 320 Mbps

Maximum Bit rate in QPSK modes 640 Mbps

Maximum bit rate in 8PSK mode 960 Mbps

Maximum bit rate in 16QAM / 16APSK mode 960 Mbps

Maximum bit rate in 32APSK mode 1200 Mbps

Maximum bit rate in 64APSK mode 1400 Mbps

Operating modes 2 and 3 (dual demodulator @ 720 MHz IF input):

Maximum actual symbol rate per channel 240 Msps

Maximum Bit rate in BPSK mode per channel 240 Mbps

Maximum Bit rate in QPSK modes per channel 480 Mbps (600 Mbps
without any decoder)

Maximum bit rate in 8PSK mode per channel 720 Mbps

Maximum bit rate in 16QAM mode per channel 720 Mbps

Operating mode 4 (mono demodulator @ 1.2 GHz IF input):

Maximum actual symbol rate 500 Msps

Maximum Bit rate in BPSK mode 500 Mbps

Maximum Bit rate in QPSK modes 1000 Mbps

Maximum bit rate in 8PSK mode 1500 Mbps

Maximum bit rate in 16QAM / 16APSK, 32APSK, 2000 Mbps

64APSK mode

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Synchronization threshold  1dB (Eb/No) in QPSK,  3,5dB (Eb/No) in 8PSK

Acquisition time  0.25 second

Doppler measurement Yes

Doppler rate  10 kHz/s

IF level measurement accuracy  2 dB

Cable Equalizer (note 1) Yes. Amplitude equalization : 0 to 12 dB between 570 & 870 MHz

1.6.1.3 Bit Synchronization

Acquisition range  0.1 % of the symbol rate

BER degradation vs theory, measured @ BER = 10-6 :

Bit Rate QPSK modes 8PSK mode*

200 Mbps < 0.3 dB < 0.3 dB
300 Mbps < 0.3 dB < 0.3 dB
400 Mbps < 0.4 dB < 0.4 dB
600 Mbps < 0.7 dB < 0.6 dB
1000 Mbps < 0.9 dB < 0.8 dB
1500 Mbps - < 1.0 dB

* with TCM + Reed Solomon encoding

PCM code NRZ-L/M/S, BP-L/M/S

Differential decoder DNRZ for QPSK and OQPSK

Eb/No measurement Resolution : 0.1 dB

Accuracy : 1 dB

Symbol clock display Yes

Output ports I Channel : Data & Clock

Q Channel : Data & Clock

Merged I+Q : Data & Clock

Output (electrical) ECL Differential or LVDS (optional)

Output clock polarity Normal or inverted

Output data polarity Normal or inverted (+ swap I/Q)

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1.6.1.4 Filtering
(notes 1)

Filter type Finite Impulse Response

Symmetrical (even or odd): 52 taps (even) or 51 taps (odd)

Asymmetrical: 25 taps on direct path I and Q, plus 8 complex taps (Q to I and I to

Q)

Sampling rate 2 or 4 time the symbol rate

Maximum symbol rate 120 Msps for sampling rate at 4 times the symbol rate
(720 MHz input, dual demodulator)
240 Msps for sampling rate at 2 times the symbol rate
(720 MHz input, dual demodulator menus)
360 Msps for sampling rate at 2 times the symbol rate
(720 MHz input, mono demodulator menus)
600 Msps for sampling rate at 2 times the symbol rate
(1.2 GHz input, mono demodulator menus)

FIR response Characteristics defined in ASCII file

Raised Cosine

Root Raised Cosine (roll-off factor programmable)

GMSK (BT factor programmable)

Shaped filter for SOQPSK

Additional filters Rejection filter HBF (sampling rate at 4 time the symbol rate with decimation by 2
at the output)

Rejection low pass filter LPF +/- 128 MHz bandwidth

Auto-adaptability Static or Auto-adaptive: “Digital Equalization Automatic Filter”, with learn and
save mode.

1.6.1.5 Viterbi Convolutional Decoding

(notes 1)
1.6.1.5.1 VITERBI ½
Convolutional decoding and error-correction comply to CCSDS recommendations 101.0-B-3 (Blue Book, 05/1992).

Code rate 0.5 information bit per encoded bit

Constraint length 7 bits

Code generators G1 = 1111001 ; G2 = 1011011

Phase relationship Programmable association of G1 or G2 with first symbol :

Programmable inversion on output path of G2 :
G1 - G2 Inverted (CCSDS) (G1 is associated with first symbol)
G1 - G2
G2 Inverted - G1 (G2 is associated with first symbol)

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G2 – G1

Decoding mode Single decoder or separate decoders on I & Q (dual mode)

2
Puncturing /3 3/4 4/5 5/6 6/7 7/8 or programmable in the registry.
Parallel processing 1 to 16 parallel rate ½ Viterbi decoders on each I & Q with symbol
sequence compliant with NASA Space Network User’s Guide (450-
SNUG)

Maximum (encoded) bit rate In single Viterbi mode : up to 240 Mbps or 1160 Mbps with the high rate
menus
In dual Viterbi mode : up to 480 Mbps or 1160 Mbps with the high rate
menus (for Viterbi ½. else puncturing rate dependent).
In parallel processing mode (> 4xI / 4xQ) : > 600 Mbps

Decoder status Locked/unlocked. Symbol error rate (obtained by comparing the input
data to the re-encoded decoded data).

1.6.1.5.2 VITERBI ¼
Application example : ERS-2 low bit rate satellite.

Code rate 0.25 information bit per encoded bit

Constraint length 4 bits

Code generators G1 = 1000 ; G2 = 1100 ; G3 = 1010 ; G4 = 1001

Maximum (encoded) bit rate 240 Mbps

1.6.1.6 De-scrambler
The cortex HDR supports several types of auto-synchronized de-scrambler (before frame synchronisation):

- Specific satellite de-scrambler (consult ZDS for details)

- CCITT V.35 de-scrambler (standard and Intelsat modes selectable)

Note 1 : License dependent (delivered licenses are listed in Annex 5)

Note 2 : Software version dependent
Note 3 : Bit rates are given at the input of the demodulator. Bit rates can be limited by the used decoder,
refer to the Maximum bit rates tables given in the chapter “Licenses and Start-up Menus” or consult ZDS

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1.6.1.7 Transport Layer (RS-DVB or asynchronous LDPC layer)

The Cortex HDR supports the “Transport layer” processing.

The Transport layer is implemented between the demodulator output and the input of the CADU frame
synchronizer (CCSDS Transfer Frame layer).

The Transport layer can be used (enable or disable by programmation) with:

 the RS-DVB decoding process

 the LDPC decoding (7/8,1/2, 2/3) process

The Transport layer acts as a first specific frame synchronizer. The parameters of this synchronizer can be set in
Windows Registries (refer to the paragraph “Cortex HDR System Parameters in Registry”).

The following figure gives an example of the transport layer used with LDPC.

1.6.1.8 BEM 4D 8PSK TCM DVB-S R-S

This mode is compatible with the CCSDS report on BANDWIDTH-EFFICIENT MODULATIONS (CCSDS 413.0-G-
1, GREEN BOOK, March 31, 2003) with completion for updating ECSS RF & Modulation standard ECSS E-50-
05A and ECSS Telemetry channel coding ECSS E-50-01 draft 0.5.

This modulation is compatible with Pleiades, SMOS, Sentinel satellites.

 8PSK - 4D TCM trellis : output rate 2.0, 2.5 or 2.75 bits/symbol (rate 2.25 is available on request)

 Decoder status : lock/unlock, BER estimation on corrected errors

 DVB-S Transport layer : synchronisation, randomization, DVB-S RS or RS(239,255) decoding ,

Interleaving

 Transport layer control parameter : ON/OFF, discard idle frames ON/OFF

 Transport layer status : lock/unlock, number of R-S correction, idle frames counter, corrected R-S CADU
counter (good/bad CADU), dropout events.

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1.6.1.9 VHR-DVB-S2 and CCSDS-SCCC standard

The Cortex HDR supports the future variable modulation and coding standards for high rate telemetry:

 DVB-S2 standard : ETSI EN 302 307 V1.1.2, Digital Video Broadcasting, second generation framing
structure, channel coding and modulation systems for Broadcasting, Interactive Services, New Gathering
and other Broad band satellite applications.

 CCSDS SCCC standard : CCSDS 131.2-R-1, Flexible advanced coding and modulation scheme for high
rate telemetry applications.

1.6.1.10 OQPSK/8PSK variable modulation

The Cortex HDR supports variable QPSK/8PSK modulation scheme used by specific satellites.

The on line switching between the following modulation modes is supported:

- OQPSK with differential NRZ-M coding on each I and Q branches

- 8PSK with specific differential coding on the symbols.

It has to be noted that the input symbol rate is constant. The demodulator of the HDR recognizes the current
modulation mode and switch automatically in the corresponding configuration (demodulation mode and differential
decoding).

Whatever the current modulation can be at a given time, the demoduated data are output on the same two parallel
ECL ports (Output mode = Split 2). The output clock rate is adjusted consequently.

This variable modulation mode is supported with the demodulator menu number 11.

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1.6.2 Diversity Combining Unit

The Cortex HDR allows to combine two IF signals from different polarizations in post-detection mode. Two
combining modes are available:

- Automatic selection of the best channel

- Combining of the two channels, through optimal weighting. In this case up to 3 dB gain can be
achieved when both signals have the same Eb/No.

The combining system, also named Diversity Combining Unit (DCU), receives the data from two demodulators. It
resolves phase ambiguity between both channels, and deals with the different locking states possible. Its output
feeds a FEC device, followed by a Format Output.

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1.6.3 Data Processing Unit

1.6.3.1 Frame Synchronization
Synchronization word size 8, 16, 24, 32, 40, 48, 56, 64 or 128 bits

Frame size 16 to 1,048,580 bytes

Synchronization strategy Error threshold on the synchronization word : SYN = 0 to 15 errors

Check to Lock threshold : CTL = 0 to 15 frames

Lock to Search threshold : LTS = 0 to 15 frames

Bit slippage (0, 1 or 2 bits)

Automatic ambiguity resolution with feed-back on I & Q digital outputs

1.6.3.2 Data Time-tagging

Time code input IRIG-B or External NTP server

Default time-tag format 64 bits (second of the year + s of the current second)

Time tagging accuracy  50 s (IRIG B)

1.6.3.3 CRC Frame checking

Polynomial Programmable on 16 bits (CCITT compliant)

Preset value Programmable on 16 bits

1.6.3.4 CCSDS and ECSS Decoding

Reed-Solomon decoding CCSDS RS(255, 223) or RS(255, 239)

Interleave factor automatically programmed (1 to 8)

Virtual filling

R-S counters (good and bad frames, BER)

Frame Header R-S decoding CCSDS RS(10,6)

De-randomization Polynomial, initialization and offset programmable

CRC verification Frame by frame

CCSDS decommutation Yes (CADU, VCDU and Packet)

CFDP protocol Yes

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1.6.3.5 LDPC Decoding

The LDPC (Low Density Parity Check code) decoders implemented inside the HDR are compatible with the LPDC
codes recommended by CCSDS (CCSDS 131.1-O-2, September 2007). Are available:

- LDPC 7/8 (mono mode after I/Q merged or dual mode on separate I and Q outputs)

- LDPC 1/2 1K, 4K and 16K

- LDPC 2/3 1K and 4K

The LDPC decoding is an iterative process with parity decoding. In this implementation, after the last iteration, the
parity control is processed one more time. This control is able to detect bit error before and after decoding, and
elaborates a quality “Good/Bad” status of the decoding CADU.

Bit rates supported by the LDPC decoderd depends on the rate of the decoder (7/8, ½ or 2/3) and on the use or
not of the Demodulator Extension board (hardware option). The Following table gives the maiximum bit rates.

Without Extension Board With Extension Board

LDPC 7/8 800 Mbps 2000 Mbps

LDPC 1/2 50 Mbps 500 Mbps

LDPC 2/3 (1K) N.A. 500 Mbps

LDPC 2/3 (4K) N.A. 300 Mbps

The performance of the LDPC depends on the number of iterations, the following table gives as example the
obtained performances in terms of BER for BPSK and QPSK modulations: BER versus Eb/N0 performance @
BER = 10-6, with LDPC 7/8 (HDR XXL without the Extension Board).

ITERATIONS EB/N0 @ BER = 10-6 HDR MAX. OUTPUT RATE

10 3.75 210 Mbps
7 4.1 390 Mbps
5 4.6 550 Mbps
4 5.1 700 Mbps

LDPC coding can be used with or without the Transport layer (refer to the paragraph: Transport Layer).

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1.6.3.6 Data Output

Type of data Raw data (frame synchronizer OFF) or frames (VC extraction capability)

Real-time data or stored data

Data interface 1-Gbyte Ethernet

TCP-IP

FTP (Integrated FTP server)

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1.6.4 Data Storage

Associated Hardware:
Internal storage Internal hard disks

Up to 2 Tbyte (available capacity)

External Recorder (note 1) External Direct Attachment Storage (DAS) system (DR2912 or ER2912)

SCSI or Optical fibre interface

Up to 12 Tbyte (note 2)

RAID 5

Read/Write Performance:
Input data rate Up to 2 Gbps aggregate

Stored data Raw data or frames (CADU) or virtual channels (VCDU) or Packet or
files set (CFDP)

Record sequence Start / Stop manual commands

Auto-start at programmed date

Read data Raw Data

CADU frame

VCDU virtual channel

Read sequence Immediate or according IRIG Time or using FTP

Read Data Rate Bandwidth Up to 600 Mbps (with 1 Gbyte Ethernet interface)

Note 1: For any other recorders models, please consult ZDS.

Note 2: Raw capacity depending on the recorder configuration.

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File Associated Process for FTP access:

Files architecture and construction Destination directories programmable

Destination files names programmable

Decommutation, filtering and sorting up to 5 fields in CADU

Up to 64 destination files

File size defined by the number of frames from 20 Mbytes to 4 Gbytes

Data recovery FTP Read and Delete commands supported

Disk space management Warning level programmable

Alarm level for auto-erase programmable

Delete of the oldest files (date programmable)

Auto tests Auto test of directories and files

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1.6.5 Playback
Operating Modes: Test Modulator mode: replay at IF level using the Test Modulator
board

Data + Clock mode: Replay at the demodulator(s) PCM data outputs

(Data + Clock outputs)

Data sources: Recorded files from a previous satellite pass

User files

Replay data rate : Programmable up to 800 Mbps

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1.6.6 Test Modulator

1.6.6.1 IF Modulation
IF carrier frequency 720 MHz +/- 140 MHz or 1.2 GHz +/- 50 MHz (hardware dependent)

IF output port 1

Output level -10 dBm to -40 dBm (0.05 dB steps)

Output level setting accuracy  2 dBm

Output impedance / VSWR 50  / 1.3

IF stability As per reference clock (internal or external)

Unwanted emissions Better than -40 dBc @ -10 dBm output level

1.6.6.2 Noise Source

Noise source ON/OFF

Noise density -93 dBm/Hz to -130 dBm/Hz (1 dB steps)

Noise bandwidth 2 GHz

1.6.6.3 Modulation
Modulation BSPK , QPSK , OQPSK (SQPSK)

UQPSK (AQPSK, AUQPSK, AUSQPSK)

8PSK, 16QAM, 16APSK, 32APSK, 64APSK

Symbol rate Same as demodulators

Convolutional coding Compliant to CCSDS recommendation (See characteristics in 1.6.1.5)

Single or Dual encoding mode, rate ½, parallel mode (stacked Viterbi)

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1.6.6.4 PCM Simulation

Operating mode Fixed pattern :

ASCII-coded file on hard disk (32768 bytes)

Separate or merged I and Q data flows

Programmable pseudo-random pattern : 210, 211, 215, 223

External Data + CLK (serial mode)

PCM coding NRZ-L/M/S, DNRZ, BP-L/M/S

Convolutional code (Viterbi)

TCM

CCSDS Reed-Solomon

DVB Reed-Solomon

LDPC 7/8

PCM modulation ON or OFF

Polarity of transmitted NRZ-L Normal or inverted

BER test capability Yes (by the Demodulator)

BER measurement from recorded data on external Data+Clock inputs

TM test ports Data and Clock (I & Q)

Level : ECL differential (hard-wired at delivery)

Data : NRZ-L

Clock phase : 0°

External Data & Clock Level : ECL differential (hard-wired at delivery)

Data : NRZ-L (serial mode)

Clock phase : 180°

Clock jitter : as per input clock jitter

Modulator board termination must be either voltage terminated

(unbalanced) or not (balanced). Factory setting : as per Customer

1.6.6.5 Doppler Simulation

Frequency range 0 to +/- 1MHz

Rate 0 to 100 KHz/s

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1.6.7 Start-up Menus

The CORTEX HDR supports multiple start-up menus. See section 4.4.9 for more details on the
functionalities supported by each menu.

1.6.8 Frequency Reference

1.6.8.1 External Reference
Input port 1 port

Frequency 10 MHz sine or square

Impedance 50 

Level 0.5 to 10 Vpp (if DC = 0)

DC max. =  4 V

1.6.8.2 Internal Reference

Frequency 10 MHz

Frequency stability   5 ppm ageing first year

  2 ppm ageing following years

  15 ppm vs temperature variations (10° to 40°)

1.6.9 Time Code Reference

Time code IRIG-B or NASA 36

Input port 1

Amplitude 0.8 to 8 Vpp

Impedance 100 k

Time tagging accuracy  50 s

Flywheel mode Yes

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1.6.10 Mechanical - Environment

Industrial PC chassis 19-inch rack-mountable (4 rack space)

Depth : 550 mm

Test Modulator board PCI, 1 slot (+ 1 I/O slot)

Demodulator board PCI, 1 slot (+ 3 I/O slots)

Weight  25 kg

Operating temperature + 10°C to + 40°C

Storage temperature - 20°C to + 60°C

Relative humidity 5% to 95% noncondensing

1.6.11 Supply
Supply (last generation) 90 - 264 VAC

47 – 63 Hz

Maximum consumption 3.3 A – 1.4 A

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2. HARDWARE
DESCRIPTION

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2.1 CORTEX HDR INTEGRATION

2.1.1 Hardware Configuration
In its minimum hardware configuration, the HDR XXL unit consists in:

- one 4U-high PC-compatible workstation

- one demodulator board with its I/O interfaces (ECL interfaces)

Depending on the delivered configuration, optional hardware parts can be added to the unit and consist in:

- a test modulator board

- a LVDS I/O interface board

- a SCSI interface board for data storage on a DAS recording system

- the extension board for very high rates LDPC decoders

Moreover, 3 different configurations of the demodulator board are available today:

- first generation demodulator board with single 720 MHz IF input

- second generation demodulator board with 2 x 720 MHz IF inputs

- second generation demodulator board with 2 x 720 MHz plus 1.2 GHz IF inputs

The main operational difference between the first and second generations of demodulator boards is detailed in the
paragraph 2.1.3.

The following table lists the HDR XXL available models and their reference number depending on the different
selected options:

Model Without LVDS I/O With LVDS I/O

HDR XXL 1 x 720 without test modulator SM 01009212 SM 01016055

HDR XXL 1 x 720 with test modulator SM 01009211 SM 01016054

HDR XXL 2 x 720 without test modulator SM 01022660 SM 01022662

HDR XXL 2 x 720 with test modulator SM 01022661 SM 01022663

HDR XXL 2 x 720 + 1200 without test modulator SM 01022664 SM 01022666

HDR XXL 2 x 720 + 1200 with test modulator SM 01022665 SM 01022667

HDR XXL 2 x 720 + 1200 with test modulator and SM 01030046 -

with the extension board

The position of the boards inside the chassis must not be changed. A sticker at the rear panel of the equipment
shows how the boards must be mounted in the chassis. Do not change this setting.

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2.1.2 PC-compatible Workstation

The PC-compatible workstation cabling is described in Annex 4.

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2.1.3 Demodulator board

2.1.3.1 Overview
The HDR XXL is available with two kinds of demodulator boards.

The first generation of demodulator board provides a single 720 MHz IF input.

The second generation provides two independent 720 MHz IF inputs and one independent 1.2 GHz IF input. This
last board is configured in factory and delivered with 2 x 720 MHz IF inputs or 2 x 720 MHz plus 1 x 1.2 GHz IF
inputs.

The demodulator assembly consists in (refer to Annex 2):

- the mother board: PCI board with FPGA

- the IF input mezzanine

- the synthesizer mezzanine

- the I/O mezzanine

- the set of cables and I/O connectors

The I/O mezzanine in its standard version provides only the ECL I/O. In option the mezzanine provides ECL plus
LVDS I/O.

2.1.3.2 First generation board: single IF input

The following figure gives the diagram of the input stage when the unit is mounted with the single 720 MHz IF input
demodulator board.

Demodulator A

Nom. A
Analogue D
720 MHz
C
input
Alter.

Demodulator B

Figure 8 : Demodulator stage with single IF input

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The incoming 720 MHz IF signal is distributed in parallel towards both digital demodulators after analogue filtering,
amplification and digital conversion.

2.1.3.3 Second generation board: separate IF inputs

The following figure gives the diagram of the input stage when the unit is mounted with the separate IF inputs
demodulator board (second generation of demodulator board).

Nom. IF 1
Analogue
1.2 GHz input
Ater. IF 1
2
A
D Demodulator A
C
1
Nom. IF 2
Analogue
720 MHz
Ater. IF 2 input

2
Nom. IF 3
A
Analogue
D Demodulator B
720 MHz
Ater. IF 3 input 1 C

Figure 9 : Demodulator stage with separate IF inputs

1. D
The demodulator board provides double 720 MHz IF inputs (configuration 1) or single 1.2 GHz IF input
(configuration 2). Both configurations are exclusive. The selection between configurations is done by basic menu
selection.
EM
With configuration 1 (720 MHz inputs) both demodulators A and B are available. The 1.2 GHz IF inputs 1 are not
used, the 720 MHz IF inputs 2 and 3 (nominal and alternate) are available and can be selected from the GUI.

With configuration 2 the demodulator B is not available. Only the IF input 1 (nominal and alternate) is used.

OD
UL
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2.1.4 Test Modulator Board

Today, two generations of test modulator boards are available. The main difference between the boards is the
capacity to generate the IF output frequency:

The first generation board generates a 720 MHz IF frequency programmable within a few MHz range. The ZDS
reference of the board is : SM 01008857.

The second generation board generates a 720 MHz IF frequency or a 1.2 GHz IF frequency programmable within
a larger range (720 MHz ± 140 MHz and 1.2 GHz ± 50 MHz). The ZDS reference of the board is : SM 01019647.

The test modulator assembly consists in (refer to Annex 3):

- the mother board: PCI board with FPGA

- the IF output mezzanine

- the synthesizer mezzanine

- the I/O mezzanine (option)

2.1.5 Extension Board

The extension board is an optional board used to obtain full performances of the decoders. Today this board is
essentially used to achieve high bit rates with the LDPC decoders and to support high rate SCCC and DVB-S2
standards.

This board is a PCI board fitted with a set of high performance FPGA. It is connected with the demodulator board.

2.1.6 Specific I/O Board

Specific I/O board can be installed inside the chassis for AIT or test purpose. These specific interfaces are
described inside the specific user manual. Please refer to the Annex 5 of the delivered documents folder.

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2.2 I/O CONNECTORS DEFINITION

2.2.1 CPU Board I/Os
The only operational I/O ports on the CPU board are the two RJ45 10/100 Base-T Ethernet ports, used for
connection to the Ethernet network(s).

See Annex 4 for more details on the CPU board.

2.2.2 Demodulator & Test Modulator I/Os

2.2.2.1 HDR I/O with single IF input and optional SCSI interface for RAID-5
DR2912 storage device

J20 J10 J1 J60 J50

CLK+ CLK+ NOM IF CLK IN+ IF OUT

H/B

J21 J11 J2 J61 J51

CLK- CLK- ALT IF CLK IN- EXT LO

J22 J12 J62 J52

OUT1+ OUT1+ IN1+ CLK OUT+

J23 J13 J3 J63 J53

OUT1- OUT1- AGC OUT IN1- IN1 +

J24 J14 J4 J64 J54

OUT2+ OUT2+ IRIG IN IN2+ IN1 -

J25 J15 J5 J65 J55

OUT2- J40 OUT2- 10MHz IN IN2- CLK I+
DATA I/O

H/B
J26 J16 J66 J56
HW CLK I-
OUT3+ OUT3+ IN3+
FAIL

J27 J17 J67 J57

OUT3- OUT3- IN3- 10 MHz IN

DEMODULATOR DATA DEMODULATOR DEMODULATOR DEMODULATOR TEST

CHANNEL B STORAGE CHANNEL A INPUT MODULATOR

1.1.1.1.1.1.1.1.3
STORAGE
1.1.1.1.1.1.1.1.1 C 1.1.1.1.1.1.1.1.2
HA
NN
EL
A

Figure 10 : CORTEX HDR I/Os with single IF input and optional SCSI storage

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2.2.2.2 HDR I/Os with single IF input and optional LVDS / TTL interfaces

J20 J10 J1 J60 J50

CLK+ CLK+ NOM IF CLK IN+ IF OUT

H/B

J21 J11 J2 J61 J51

CLK- CLK- ALT IF CLK IN- EXT LO
J70
LVDS
DEMOD
OUT A
J22 J12 J62 J52
OUT1+ OUT1+ IN1+ CLK OUT+

J71
LVDS
DEMOD
J23 J13 OUT B J3 J63 J53
OUT1- OUT1- AGC OUT IN1- IN1 +

1.1.1.1.1.1.1.1.7 D
J24 J14
J72
LVDS
E J4 J64 J54
IRIG IN IN1 -
OUT2+ OUT2+ DEMOD
IN M IN2+

O
J25
OUT2-
J15
OUT2-
D J5
10MHz IN
J65
IN2-
J55
CLK I+

OUT B
H/B

J26 J16 J66 J56

J73 HW
OUT3+ OUT3+ IN3+ CLK I-
TTL I/O FAIL

J27 J17 J67 J57

OUT3- OUT3- IN3- 10 MHz IN

DEMODULATOR DEMODULATOR LVDS & TTL DEMODULATOR DEMODULATOR TEST

CHANNEL B CHANNEL A I/Os INPUT MODULATOR

1.1.1.1.1.1.1.1.6
1.1.1.1.1.1.1.1.4 C IN
HA PU
NN T
EL 1.1.1.1.1.1.1.1.5
A

Figure 11 : CORTEX HDR I/Os with single IF input and optional LVDS / TTL interfaces

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2.2.2.3 HDR I/Os with separate IF inputs

J20 J21 J22 J23 J24 J25 J26 J27 J10 J1 J50
CLK+ NOM IF1 IF OUT
J80 ALT-IF1
H/B

CLK+ CLK- OUT1+ OUT1- OUT2+ OUT2- OUT3+ OUT3-

J11 J2 J51
CLK- NOM IF2 EXT LO
DEMODULATOR CHANNEL B J81 ALT-IF2

J60 J61 J62 J63 J64 J65 J66 J67 J12 J3 J52
OUT1+ NOM IF3 CLK OUT+

J82 ALT-IF3

CLK IN+ CLK IN- IN1+ IN1- IN2+ IN2- IN3+ IN3- J53
J13 J4
OUT1- AGC OUT IN1 +
DEMODULATOR INPUT INPUT IF

J14 J5 J54
OUT2+ IRIG IN IN1 -

J15 J6 J55
OUT2- 10MHz IN CLK I+

H/B

J16 J56
HW CLK I-
OUT3+
FAIL

J17 J57
OUT3- 10 MHz IN

DEMODULATOR DEMODULATOR TEST

CHANNEL A MODULATOR

1.1.1.1.1.1.1.1.
1.1.1.1.1.1.1.1.8 C
HA
NN
EL
A

Figure 12 : CORTEX HDR I/Os with separate IF inputs

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2.2.2.4 HDR I/Os with separate IF inputs and optional optical fibre interface for
RAID-5 ER2912 storage device

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2.2.2.5 HDR I/Os Demodulator with separate IF inputs and outputs extension

Figure 13 : CORTEX HDR I/Os with ECL output extension

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2.2.2.6 Demodulator I/Os

2.2.2.6.1 STANDARD VERSION SINGLE IF INPUT
Unless otherwise specified, all I/Os are ECL with SMA connectors :

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

DEMODULATOR NOM IF J1 Nominal IF input

-10 to -50 dBm
ALT IF J2 Alternate IF input

AGC OUT J3 AGC voltage output Between 0 and 3 V.

-10 dBm ->3 V +/- 200 mV
-50 dBm -> 0.6 V +/- 200 mV

IRIG IN J4 IRIG-B time code input 0.8 to 8 Vpp, 100 k

10 MHz IN J5 Input Reference Clock 10 MHz, sine or square, 50 

0.5 to 10 Vpp (if DC = 0)
DC max =  4 V

DEMODULATOR CLK + J10 Refer to paragraph

CHANNEL A CLK - J11 (2.2.2.6.5) ECL differential
+ -
OUT1 + J12 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J13 (2.2.2.6.5)
Adapted Termination required
OUT2 + J14 Refer to paragraph (note 1)
OUT2 - J15 (2.2.2.6.5)

OUT3 + J16 Refer to paragraph

OUT3 - J17 (2.2.2.6.5)

DEMODULATOR CLK + J20 Refer to paragraph

CHANNEL B CLK - J21 (2.2.2.6.5) ECL differential
+ -
OUT1 + J22 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J23 (2.2.2.6.5)
Adapted Termination required
OUT2 + J24 Refer to paragraph (note 1)
OUT2 - J25 (2.2.2.6.5)

OUT3 + J26 Refer to paragraph

OUT3 - J27 (2.2.2.6.5)

DEMODULATOR CLK IN + J60 Clock input

INPUT CLK IN - J61

IN1 + J62 Data input ECL differential

IN1 - J63 for BER measurement or
data post-processing

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+ -
IN2 + J64 Data input V > -1 Volt, V < -1.7 Volt
IN2 - J65 for BER measurement or
data post-processing 50  termination required (note 2)

IN3 + J66 Data input

IN3 - J67 for BER measurement or
data post-processing

Table 2 : Demodulator Single IF I/Os Definition

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2.2.2.6.2 STANDARD VERSION DOUBLE IF INPUTS

Unless otherwise specified, all I/Os are ECL with SMA connectors :

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

DEMODULATOR NOM IF 1 J1 Nominal IF input 1.2 GHz

-10 to -50 dBm

NOM IF2 J2 Nominal IF 1 input 720 MHz

-10 to -50 dBm

NOM IF 3 J3 Nominal IF 2 input 720 MHz

-10 to -50 dBm

AGC OUT J4 AGC voltage output Between 0 and 3 V.

-10 dBm ->3 V +/- 200 mV
-50 dBm -> 0.6 V +/- 200 mV

IRIG IN J5 IRIG-B time code input 0.8 to 8 Vpp, 100 k

10 MHz IN J6 Input Reference Clock 10 MHz, sine or square, 50 

0.5 to 10 Vpp (if DC = 0)
DC max =  4 V

INPUT IF ALT IF 1 J80 Alternate IF input 1.2 GHz

-10 to -50 dBm

ALT IF2 J81 Alternate IF 1 input 720 MHz

-10 to -50 dBm

ALT IF 3 J82 Alternate IF 2 input 720 MHz

-10 to -50 dBm

DEMODULATOR CLK + J10 Refer to paragraph

CHANNEL A CLK - J11 (2.2.2.6.5) ECL differential
+ -
OUT1 + J12 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J13 (2.2.2.6.5)
Adapted Termination required
OUT2 + J14 Refer to paragraph (note 1)
OUT2 - J15 (2.2.2.6.5)

OUT3 + J16 Refer to paragraph

OUT3 - J17 (2.2.2.6.5)

DEMODULATOR CLK + J20 Refer to paragraph

CHANNEL B CLK - J21 (2.2.2.6.5) ECL differential
+ -
OUT1 + J22 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J23 (2.2.2.6.5)
Adapted Termination required
OUT2 + J24 Refer to paragraph (note 1)
OUT2 - J25 (2.2.2.6.5)

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OUT3 + J26 Refer to paragraph

OUT3 - J27 (2.2.2.6.5)

DEMODULATOR CLK IN + J60 Clock input for DPU 1

INPUT CLK IN - J61

IN1 + J62 Data input for DPU 2 ECL differential

IN1 - J63 + -
V > -1 Volt, V < -1.7 Volt
IN2 + J64 Clock input for DPU 2
IN2 - J65 50  termination required
(note 2)
IN3 + J66 Data input for DPU 1
IN3 - J67

Table 3 : Demodulator Double IF I/Os Definition

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

DEMODULATOR CLK + J30 Refer to paragraph

OUTPUT Ext CLK - J31 (2.2.2.6.5) ECL differential
(note 3) + -
OUT1 + J32 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J33 (2.2.2.6.5)
Adapted Termination required
OUT2 + J34 Refer to paragraph (note 1)
OUT2 - J35 (2.2.2.6.5)

OUT3 + J36 Refer to paragraph

OUT3 - J37 (2.2.2.6.5)

CLK + J40 Refer to paragraph

CLK - J41 (2.2.2.6.5) ECL differential
+ -
OUT1 + J42 Refer to paragraph V > -1 Volt, V < -1.7 Volt
OUT1 - J43 (2.2.2.6.5)
Adapted Termination required
OUT2 + J44 Refer to paragraph (note 1)
OUT2 - J45 (2.2.2.6.5)

OUT3 + J46 Refer to paragraph

OUT3 - J47 (2.2.2.6.5)

Table 4 : Demodulator Output Extension

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Note 1 : ECL differential outputs must have this termination :

External termination :

Balanced ECL : Unbalanced ECL :

+ +
R = Z0
R = 2.Z0
-2 V

_ _
R = Z0

Z0 : Characteristic Impedance of the line -2 V

Note 2 : ECL differential inputs have a 50  termination :

External 50  termination :

Unbalanced ECL :

+
50 

-VT

_
50 

-VT

Note 3 : Only available with the demodulator with Output Extension option

2.2.2.6.3 SCSI STORAGE INTERFACE (OPTION)

For the data storage option on an external DAS system, an SCSI connector is added.

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

DATA STORAGE DATA I/O J40 Data for storage on Ultra 320 SCSI LVD
external Hard Disk
68 pin LVD SCSI connector

Table 5 : SCSI Data Storage Interface

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2.2.2.6.4 OPTIONAL LVDS INTERFACE (OPTION)

For the LVDS I/Os option, the following connectors are added.

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

LVDS & TTL I/Os LVDS DEMOD J70 Data and clock outputs
LVDS standard characteristics
OUT A for demodulator A

LVDS DEMOD J71 Data and clock outputs

OUT B for demodulator B

LVDS DEMOD J72 Data and clock inputs

IN

TTL/IO J73 Data and clock I/Os TTL standard characteristics

The TTL I/Os are disable for bit
rates above 50 Mbps

Table 6 : LVDS and TTL Interface

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LVDS Interface:

SH2
GND
CHA_OUT1 + 1
CHA_OUT1 – 2
CHA_OUT2 + 3
CHA_OUT2 –
DEMOD OUT A
4
CHA_OUT3 + 5
CHA_OUT3 - 6
CHA_CLK + 7
CHA_CLK – 8
SH1
GND

J70

SH2
GND
CHB_OUT1 + 1
CHB_OUT1 – 2
CHB_OUT2 + 3
CHB_OUT2 –
CHB_OUT3 +
4
5 DEMOD OUT B
CHB_OUT3 - 6
CHB_CLK + 7
CHB_CLK – 8
SH1
GND

J71

SH2
GND
CHA_IN1 + 1
CHA_IN1 – 2
CHA_IN2 + 3
CHA_IN2 –
DEMOD IN
4
CHA_IN3 + 5
CHA_IN3 - 6
CHA_CLK + 7
CHA_CLK – 8
SH1
GND

J72

LVDS Connector : EMBASE RJ45 CAT. 6

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Note : LVDS differential outputs must be terminated as follows :

ZT = Termination impedance = 100 

The output level is adjusted around the typical 1.2 V offset, with a peak-to-peak amplitude varying from 250 mV to
450 mV.

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TTL I/O Interface:

CLKA_OUT 6
GROUND 1 11 CHA_OUT1
CHA_OUT2 7
CHA_OUT3 2 12 CHB_OUT1
CHB_OUT2 8
CHB_OUT3 3 13 CLKB_OUT
GROUND 9
DATA_IN2 4 14 DATA_IN1
DATA_IN3 10
GROUND 5 15 CLK_IN

J73

TTL I/O Connector: SUB HD 15 female

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2.2.2.6.5 CHANNEL A & CHANNEL B I/OS DESCRIPTION

The Outputs of the demodulators depend on :

 the selected option

 the demodulation mode

 the selected soft decision output

 the selected Data format output (CADU)

 and the setting of the Output Mode parameter

The following table shows the different configurations for both Demodulator A and Demodulator B (standard
outputs).

CONNECTO BPSK QPSK QPSK QPSK A/UQPSK CADU CADU CADU

R 8PSK 8PSK 8PSK +SYNC +SYNC SPLIT 2
16QAM 16QAM 16QAM +USER +GOOD +SYNC

SPLIT 2 I/QMERGE SPLIT 4

DEMODULATOR CHANNEL A OUTPUTS 1
J10 Clock @ BR Clock @ BR/2 Clock @ BR Clock @ BR Clock @ Clock @ BR Clock @ Clock @ BR /
CLK + / Demod A Demod A Demod A /4 BR I Demod A BR 2 Demod A
CLK - J11 Demod A Demod A
J12
OUT1 + / Data Data I Data Data I -1 Data I Data Data Data I
OUT1 - J13
J14
OUT2 + / Reserved Data Q Data Data Q -1 Data Q Sync pulse 2 Sync pulse Data Q
OUT2 - J15 2
J16 Clock @ BR Clock @ BR/2 Clock @ BR Clock @ Clock @ Clock for Status Sync pulse 2
OUT3 + / Demod A Demod A Demod A BR/4 BR Q User data 1 = good
OUT3 - J17 Demod A Demod A 0 = bad
DEMODULATOR CHANNEL B OUTPUTS 1
J20 Clock @ BR Clock @ BR/2 Clock @ BR reserved Clock @ Clock @ BR Clock @ Clock @ BR /
CLK + / Demod B Demod B Demod B BR I Demod B BR 2 Demod B
CLK - J21 Demod B Demod B
J22
OUT1 + / Data Data I Data Data I - 2 Data I Data Data Data I
OUT1 - J23
J24
OUT2 + / Reserved Data Q Data Data Q - 2 Data Q Sync pulse Sync pulse Data Q
OUT2 - J25 2
J26 Clock @ BR Clock @ BR/2 Clock @ BR Reserved Clock @ Clock for Status Sync pulse 2
OUT3 + / Demod B Demod B Demod B BR Q User data 1 = good
OUT3 - J27 Demod B Demod B 0 = bad

Table 7 : Data & Clock Outputs vs Demodulation

* BPSK demodulation can be set to SPLIT2 mode with high rates hardware menus (single demodulator). In this case
the data stream is split on the two outputs J12/ J13 and J22/J23.

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The following table shows the available configurations with the demodulator hardawre menu 16
(multi-DPU process) and with the demodulator fitted with the Output Extension option.

CADUS + CLOCK CADUS + CLOCK SPLIT 4 SPLIT 8

4 DPU 8 DPU

J10 / J11 Clock @ output of DPU A Clock @ output of DPU A Clock @ BR / 4 Clock @ BR / 8
CLK +
CLK -
J12 / J13
OUT1 + Data of DPU A Data of DPU A Data I 1 Data I 1
OUT1 -
J14 / J15
OUT2 + Data of DPU C Data of DPU C Data Q 1 Data I 2
OUT2 -
J16 / J17 Clock @ output of DPU C Clock @ output of DPU C Clock @ BR / 4 Clock @ BR / 8
OUT3 +
OUT3 -
J20 / J21 Clock @ output of DPU E Clock @ output of DPU E Clock @ BR / 4 Clock @ BR / 8
CLK +
CLK -
J22 / J23
OUT1 + Data of DPU E Data of DPU E Data I 2 Data I 3
OUT1 -
J24 / J25
OUT2 + Data of DPU G Data of DPU G Data Q 2 Data I 4
OUT2 -
J26 / J27 Clock @ output of DPU G Clock @ output of DPU G Clock @ BR / 4 Clock @ BR / 8
OUT3 +
OUT3 -
J30 / J31 Reserved Clock @ output of DPU B Reserved Clock @ BR / 8
CLK +
CLK -
J32 / J33 Reserved Reserved
OUT1 + Data of DPU B Data Q 1
OUT1 -
J34 / J35 Reserved Reserved
OUT2 + Data of DPU D Data Q 2
OUT2 -
J36 / J37 Reserved Clock @ output of DPU D Reserved Clock @ BR / 8
OUT3 +
OUT3 -
J40 / J41 Reserved Clock @ output of DPU F Reserved Clock @ BR / 8
CLK +
CLK -
J42 / J43 Reserved Reserved
OUT1 + Data of DPU F Data Q 3
OUT1 -
J44 / J45 Reserved Reserved
OUT2 + Data of DPU H Data Q 4
OUT2 -
J46 / J47 Reserved Clock @ output of DPU H Reserved Clock @ BR / 8
OUT3 +
OUT3 -

Table 8 : Data & Clock Outputs with Demodulator Menu 16 (Multi DPU)

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QPSK QPSK
NORMAL SOFT 3 MERGE SOFT
DEMODULATOR CHANNEL A
CLK + Clock @ BR/2 Clock @ BR
CLK - Demod A Demod A

OUT1 + I bit 2 I/Q bit 5

OUT1 - (MSB) (MSB)

OUT2 + I bit 1 I/Q bit 4

OUT2 -
OUT3 + I bit 0 I/Q bit 3
OUT3 -
DEMODULATOR CHANNEL B
CLK + _ 0 = indicates I
CLK - 1 = indicates Q
OUT1 + Q bit 2 I/Q bit 2
OUT1 - (MSB)
OUT2 + Q bit 1 I/Q bit 1
OUT2 -
OUT3 + Q bit 0 I/Q bit 0
OUT3 - (LSB)

Table 9 : Data & Clock Outputs vs Demodulation (soft outputs) Hardware menu dependent

Note 1: Except for the QPSK mode with soft decision output, which involves only the demodulator A, the output
configuration setting for each demodulator is done from the corresponding GUI windows (Demodulator Global
Window: Output mode selection).

Note 2: Pulse corresponding to the first bit of the frame synchronizer.

Note 3: The coding of In and Qn used for the soft decision outputs is given in the following representation of the
I/Q constellation.
011
Q

010

001

000

100 101 110 111 000 001 010 011

111

110

Exact constellation
position depends
101
on AGC settings

100

2. Q

Figure 14 : Soft Decision Coding vs I/Q Constellation (Normal Soft Output)

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011111

I
000000
111111
100000

111111
000000

011111
100000

Figure 15 : Soft Decision Coding vs I/Q Constellation (Merge Soft Output)

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2.2.2.7 Test Modulator I/Os

All I/O connectors are SMA :

I/O SECTION LABEL ID SIGNAL DEFINITION ELECTRICAL

-10 to –40 dBm
IF OUT J50 IF output

EXT LO J51 External Local Nominal freq. Range = 720 MHz  190 MHz
Oscillator input
Nominal input level = 0 dBm  1 dBm
Zin = 50 
VSWR < 1.3
Destructive level ≥ +13 dBm

CLK OUT + J52 Clock output of the

modulating data ECL differential
+ -
V > -1 Volt, V < -1.7 Volt
Adapted Termination required
(note 1)

IN1 + J53 Data input (note 1)

IN1 - J54
ECL differential
CLK_I+ J55 Clock input (note 1) + -
CLK_I - J56 V > -1 Volt, V < -1.7 Volt

50  termination required (see above)

10 MHz IN J57 Input Reference Clock 10 MHz, sine or square, 50 

0.5 to 10 Vpp (if DC = 0) DC
max =  4 V

Table 10 : Modulator I/Os Definition

Note 1 : Depending on the modulation mode (BPSK, QPSK, OQPSK, UQPSK) and the setting of the Input Mode
parameter, data and clock input to the Test Modulator are :

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MODULATION INPUT MODE MODULATOR INPUTS

SETTING
CLK_I+/CLK_I- IN1+ / IN1-

BPSK Clock Data

External
QPSK, OQPSK (SQPSK) Clock Merged I & Q

UQPSK (AQPSK, AUQPSK, AUSQPSK) External I I Clock I Data

All modes Internal No external inputs

Table 11 : Data & Clock Inputs vs Modulation

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2.2.3 Output Data Definition and Timing

2.2.3.1 Timing for all output types

1 / Bit Rate

CLK+ *

ts th

OUTX +/- ** DATA

For I/Q merged output, RS CADU output and LDPC CADU output:

t s = 1/2BR - 500 ps

t h = 1/2BR - 500 ps

For normal I and Q outputs:

t s = 1/BR - 500 ps

t h = 1/BR - 500 ps

* Clock polarity : Normal Output Clock

** Except when OUT3 = CLK

Remark: For data output after specific decoding process (example: TCM + RS-DVB, punctured Viterbi), “holes”
inside the output data and clock signals can be present. These “holes” are due to the delayed check symbols and /
or synchronization words. Nevertheless it has to be considered that for each data corresponds an edge of the
clock.

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2.2.3.2 I/Q merged output

1 / Bit Rate

CLK +/-

I Data Q Data I Data

DATA

2.2.3.3 Split 2 output (I and Q normal output)

2 / Bit Rate

CLK +/-

DATA I I Data I Data

DATA Q Q Data Q Data

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2.2.3.4 Split 4 output

4 / Bit Rate

CLCK +/-

DATA I-1 I Data n I Data n+2

DATA Q-1 Q Data n Q Data n+2

DATA I-2
I Data n+1 I Data n+3

DATA Q-2 Q Data n+1 Q Data n+3

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2.2.3.5 CADU output formats

1 / Bit Rate

CLK +/-

Data

Frame
Synchronization User Data Parity Data
Word

User Data
Clock

Quality of the CADU

Status 1: Good
0: Bad (errors)

Synchro Pulse

CADU

2.2.4 Specific I/Os (Customers requirements)

The Cortex HDR can be delivered with specific I/O for AIT or test purpose. These specific interfaces are
described inside the specific DTU document. Please refer to the Annex 5 of the delivered documents folder.

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3. FUNCTIONAL
DESCRIPTION

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3.1 MONITORING & CONTROL

3.1.1 Monitoring
The CORTEX HDR supplies its status on request from a Monitoring Client. On reception of a monitoring request,
the CORTEX HDR checks its validity. If the request is correct, it returns a monitoring message embedded in an
Ethernet packet. In the case of an invalid request, the CORTEX HDR returns a negative acknowledgment
message.

A monitoring message contains the current configuration of the unit (expected frequency, operating mode, etc.),
dynamic status (IF level, Eb/No, frequency offset, etc.) and alarms (hardware alarm, etc.).

The Monitoring Client can request:

 the high-level monitoring table of the CORTEX HDR,

 the Demodulator monitoring table,

 the Test Modulator monitoring table (if available),

 the Data Processing Unit table,

 the Data Recording Global table (if available),

 the Data Recording Unit table (if available),

 the project-specific monitoring table,

 the whole set of here above monitoring tables.

Up to eight Monitoring Clients can be simultaneously connected to the Monitoring port. For more detail on the
monitoring messages, refer to Annex 1.

3.1.2 Control
Configuration commands received from a Control Client allow configuration of the equipment (example : change
the uplink carrier frequency on the Test Modulator) or triggering and action (example : restart the carrier
acquisition process on the Demodulator).

A detailed description of the Graphical User Interface is available in Section 4.

Simultaneous connection of several Control Clients to the Control port is not allowed for security reasons. For
more detail on the configuration commands, refer to Annex 1.

3.2 LOGGING
The CORTEX HDR reports on the Logging port all changes in its configuration.

Up to five Logging Clients can be simultaneously connected to the Logging port. For more detail on the logging
messages, refer to Annex 1.

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3.3 DEMODULATION
3.3.1 IF Processing
 Signal Processing :

 IF signal selection (Nominal or Alternate input).

 Automatic gain control : the signal level must be in the range –10 dBm to –50 dBm.

 Analog-to-Digital conversion of the received signal.

 IF acquisition : the programmed acquisition range must be compatible with the maximum frequency
uncertainty (Doppler shift, oscillators drift,…).

 Cable equalizer filter (see Section 3.8) : cable loss equalizer with programmable attenuation.

 IF filtering : matched filter, adjacent canal rejection or custom FIR filters (option).

Test & Monitoring :

 A number of status enable to monitor the demodulation process at IF : IF signal level, PLL status, carrier
offset, etc…

 Spectrum analysis : allow to visualize the received signal spectrum.

 Vector analysis : check that the displayed constellation is correct and corresponds to the noise and signal
characteristics.

 Filter analysis : display in real time the pulse and frequency responses of the digital filtering.

3.3.2 Bit Synchronization

3.3.2.1 Signal Processing
 Matched filters : basic supply : Integral & Dump. Optional : Root Raised, Raised filters with programmable
roll-off factor, GMSK, user-programmable FIR filters (see next section).

 Symbol phase recovery : see demodulation de-mapping scheme in section 3.6.2.4.

Test & Monitoring : a number of status enable to monitor the bit synchronization process : PLL status, signal to
noise ratio (Eb/No), etc…

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3.3.2.2 Customized FIR Filters

3.3.2.2.1 GENERAL

The filtering is based on one FIR for I channel and one FIR for Q channel.

The FIR sampling rate is either :

 twice the symbol rate (symbol rate < 480 Msps)

 or four time the symbol rate (only if symbol rate < 240 Msps)

Example : for a QPSK / 100 Mbps (50 Msps) data stream, the FIR filter sampling rate can be set to 100 MHz or
200 MHz.

Two types of filters are available :

 symmetrical filter: 52 taps (even symmetrical FIR) or 51 taps (odd symmetrical FIR)

 asymmetrical filter: 26 taps on direct path I and Q plus 8 complex taps (Q to I and I to Q)

The I & D filter design is usually the best answer to matched filtering needs. However, custom filters may improve
the performances in some circumstances, like :

 reduction of adjacent channel interferences

 phase/amplitude equalization

3.3.2.2.2 CUSTOM FILTERS PROGRAMMING

Filter coefficients can be programmed from files on the hard disk. Up to 1000 files can be loaded to the disk. Files
are ASCII-coded and can be edited using Notepad or any other text editor.

Each file contains 16-bit data (in hexadecimal format):

Line 1: FIR type selection:

0000 for asymmetrical filter

0001 for even symmetrical filter

0002 for odd symmetrical filter

Bit 2 set to 1 enables the complex filter

Bit 3 set to 1 enables the complex filter

Line 2: Sampling rate selection:

0000 for 2 time the symbol rate

0001 for 4 time the symbol rate

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Line 3: Direct FIR length

Line 4: Cross FIR length

Line 5: Cross FIR delay

Line 6: Reserved line

Line 7 to line 32 : Direct coefficients (16 bit) on I

Line 33: Reserved line

Line 34 to line 41 : Crossed coefficients Q to I for complex filter

Line 42: Reserved line

Line 43 to line 68 : Direct coefficients (16 bit) on Q

Line 69: Reserved line

Line 70 to line 77 : Crossed coefficients I to Q for complex filter

Access path to the filter files is : C:\Program Files\In-snec\crtxnt\FIR. Files are named fir_cust1 to
fir_cust1000.

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3.3.2.3 DEAF Filtering

3.3.2.3.1 GENERAL
The equivalent channel of a satellite communication system is constituted of :

1. the emitter filter : for frequency division multiplexing (FDM), the pass-band emitter filter is generally a cavity
filter. Base-band filtering depends on the application.

2. the channel : the channel could be considered as an amplitude fading channel with additive White Gaussian
Noise. Amplitude fading is resolved by automatic gain control. One can add the possibility of multi-paths
created by the structure of the satellite that can be modeled by a Finite Impulse Response filter.

3. the receiver filter : they are many possibilities, commonly used filters are Integral & Dump and Root Raised
Cosine (RRC) filters.

In order to get perfect recovery of transmitted pulses or symbols, the equivalent channel must verify the well-
known Nyquist criterion (for a symbol rate R = 2*fc where fc is the physical channel bandwidth, the impulse
response of the equivalent channel should be equal to 0 for each multiple of 1/R). This property is verified for a
chain made of a RRC emitter filter and a RRC receiver filter, as RRC are well-known Nyquist filters. However,
emitter filters at RF frequencies are very often cavity filter design to meet the regulatory rejection specifications,
they are able to work with the signal coming from the high-power amplifier and they have a non-linear phase
response. Moreover, changes of emitter filter characteristics (magnitude and phase) could not be avoided when
there are large variations of temperature like those which take place in space. So, the equivalent channel seldom
verify the Nyquist criterion and this induces inter-symbol interferences (ISI) that are harmful for performances.

A second aspect that is harmful for performances is noise. Two types of noises are present : the thermal noise and
the interference noise, coming from close channels.

In order to reduce the ISI and the influence of noise, two types of receiver could be used :

- The Matched Filter

- The Wiener Filter

As they are, these filters are not useful because the equivalent channel is changing. So, they are implemented
through conventional equalizer which are adaptive filters, but these filters need a training sequence which causes
a payload loss.

A better solution for equalizing the incoming signal is to use an automatic adaptive equalizer.

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3.3.2.3.2 PRINCIPLE OF THE DEAF

The DEAF feature (DEAF stands for “Digital Equalization Automatic Filtering”) is a digital signal processing
technique based on the adaptive filters theory. It performs a blind equalization for satellite communications of the
incoming signal from the estimated statistics. It does not require additional knowledge of the desired response :
whereas conventional equalization techniques requires a training period where a known data sequence is sent to
the receiver in order to initialize the equalization device then switches to a standard transmission mode, a blind
equalizer switches automatically and smoothly from the startup period to a standard transmission mode without
training sequence.

The algorithm behind DEAF is a “Bussgang-like” algorithm implemented on a fractionally-spaced equalizer for
better performances :

Y is a vector of samples.

Z is a the output vector of the equalizer.

C is the equalizer’s taps vector.

First step : initialization / C is initialized at C(0).

Second step : start-up / C is iteratively calculated / C(n1)C(n) f(Y,Z) where  is the step-size and f a
non-linear and zero-memory function of Z.

Third step : standard transmission mode / C() is used to filter Y.

The algorithm used by the DEAF device has a convergence time lower than 100 ms.

3.3.2.3.3 USE OF THE DEAF

The automatic digital equalization function is particularly efficient in the following operations:

- satellite filter equalization (transmission channel)

- compensation of perturbations due to multi-path signal

The main result of the DEAF operation is an important improvement of the measured Eb/No for high data rates
telemetry.

The following screen shot of the constellation display of the HDR shows the advantage of the DEAF for filter
equalization. The screen shot has been done during reception tests through an actual transmission filter. The
demodulator #1 is set without the DEAF and demodulator #2 is set with the DEAF.

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Figure 16 : Effect of the DEAF.

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3.3.2.4 XDEAF for reception of dual polarization data transmission

In order to increase the data transmission rate in a given bandwidth, some satellites use the polarization diversity.
Two radio waves are then transmitted using orthogonal polarizations in the same frequency channel (typically
RHCP and LHCP).

If we consider one channel (one polarization), we can see that this channel has a high probability to be perturbed
by the other channel. And we can defined a cross polarization discrimination coefficient as:

XPD = 20 log (Co-polar component / Cross-polar component)

In the transmission channel, several different sources of cross-polarization can occur:

- on-board antenna cross-polarization

- on-board antenna depointing

- propagation effect (rain, bad weather)

- ground antenna low elevation

- ground antenna depointing

- ground antenna cross-polarization

Typically and in case of bad conditions of transmission, XPD can be down to < 14 dB for X-band systems and < 8
dB for K-band systems.

In order to compensate for the impact of the cross polarization effects on the data reception, the Cortex HDR
provides the XDEAF function.

The XDEAF function is a real time and automatic digital filtering which takes into account the reception of both
polarizations.

The XDEAF function can compensate for XPD down to 5 dB.

The following BER curves have been measured for a QPSK transmission at 200 Mbps using dual polarization. The
XPD coefficient is 12 dB. The gain for a BER = 10-6 is 4 dB between the green curve (XDEAF disabled) and the
red one (XDEAF enabled).

The following figure gives the effect of the XDEAF on the received constellation in the same previous conditions.

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Figure 17 : Effect of the XDEAF.

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3.3.2.5 Adjacent channel rejection

In case of multi-channel transmission, the combination of successive filtering processes implemented inside the
HDR:

- LPF rejection filter,

- HBF rejection filter,

- matched filter: RRC or customized equalizer filter for channel equalization,

Allows an efficient rejection of adjacent channels.

An interesting method offered by the HDR to customize the matched filter on the received signal is to use the
combination of the rejection filters and the DEAF process. In a first time a standard filter is selected (example RRC
filter) and the DEAF process is activated. When the frequency response of the filter is stabilized, it is possible to
store the parameters of the filter inside a specific file. Then, the matched filter can be set up with the customized
filter (file) constructed by the DEAF process. Refer to $ 4.4.4.1 “Global” Window and § 4.4.4.6 “Filter” Window.

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3.3.3 Viterbi Convolutional Decoding

3.3.3.1 General
Convolutional coding technique is well suited for telemetry channels with predominant Gaussian noise.
Convolutional decoding and error-correction by the CORTEX HDR complies to the CCSDS recommendation
101.0-B-3 (Blue Book - May 1992) and to the NASA Space Network User’s Guide (450-SNUG, June 2002):

 Viterbi decoding of the data received from the bit synchronizer.

 Viterbi de-puncturing if required.

 Operating mode : single or dual Viterbi mode.

 Processing mode: single decoder or parallel decoders (up to 16 decoders on each I & Q).

 BER estimate by re-encoding the Viterbi decoded data and comparing the re-encoded data to the data fed
to the Viterbi decoder. Note : if the Viterbi decoder(s) fails to lock (BER too high), check the Viterbi
characteristics (Normal or inverted G2, single or dual Viterbi, G1G2 or G2G1 sequencing) and verify
the setting of the I & Q output mode parameter (Demodulator output to the Viterbi decoder(s) input).

Test & Monitoring : a number of status enable to monitor the Viterbi decoding process : decoder lock status, BER
(in %), etc…

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3.3.3.2 Single or Dual Viterbi Decoder

The Viterbi decoding module can operate either in single mode or in dual mode :

 In the single mode, there is only one Viterbi decoder connected to the Demodulator module (I & Q output
channels of the demodulator are connected to G1 & G2 inputs of the Viterbi decoder).

 In the dual mode, the Viterbi decoding module has two separate Viterbi decoders on I and Q Channels.

Vector Demodulator Viterbi Decoding Module

I channel
G1
IF input Data
QPSK, OQPSK Viterbi
Q channel decoder
G2

Viterbi Decoding Module

Vector Demodulator
Z-1 G1
I channel Viterbi I channel
decoder
IF input QPSK, OQPSK G2
UQPSK,
BPSK (I only) Z-1 G1
Q channel Q channel
Viterbi
decoder
G2

Figure 18 : Viterbi Decoding Module. Single & Dual Operating Modes

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3.3.3.3 Parallel Viterbi decoders

The HDR supports the rate ½ Viterbi parallel processing as specified in the NASA SNUG (450-SNUG). The
number of decoders can be set between N = 1 and 16 on I and Q channels. Dual Viterbi decoding as
described in the previous paragraph can be seen as a particular case of the parallel processing with N = 1.

The supported symbols sequence is given in the following figure.

S11
Z-1 G1
D1
Viterbi
decoder
S12 #1
G2

S21
Z-1 G1
I or Q channel Viterbi D2
decoder
S22
G2
#2 …,DN,…,D2,D1,…
…, SN2,...S22,S12,SN1,….S21,S11

2 x Data rate Data rate

SN1
Z-1 G1 DN
Viterbi
decoder
SN2 #N
G2

Figure 19 : Parallel Viterbi Decoding Module.

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3.3.3.4 Punctured Viterbi

Punctured Viterbi is supported for most puncturing rates : 2/3 3/4 4/5 5/6 6/7 7/8

Puncturing codes (Code 0 and Code 1) and swap sequence must be programmed in the registry (see section
4.2.6.2.2).

De-puncturing & swapping

Code 0
1
I1 FIFO 1
0
Vector 0
Viterbi
NULL 1
0
Demodulator Decoder
I2 1 0
FIFO 2

Code 1 Swap seque nce

Example : ¾ Punctured Dual Viterbi :

3/4 Viterbi (2,1,7)

QPSK Punctured decoder
demodulation DNRZ
3/4 Viterbi (2,1,7) (option)
Punctured decoder

C0(1) C1(2) C0(4) C1(5) C0(1) NULL C0(3) C0(4) NULL C0(6)

De-puncture
C1(1) C0(3) C1(4) C0(6) 3/4 C1(1) C1(2) NULL C1(4) C1(5) NULL

Registry keys : VitPunctCode0 : 1 1 0 1 1 0

VitPunctCode1 : 1 0 1 1 0 1
VitPunctSwap : 0 1 1 0 1 1

G1 Viterbi input = C0
G2 Viterbi input = C1
Viterbi decoder setting : “ G1-G2”

Figure 20 : Viterbi De-puncturing Process.

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There are two conventions for Viterbi puncturing codes. The first is the one which is defined by CCSDS
recommendation and the second can be found on certain commercial encoders. The second convention only
exists for puncturing ratios with an even denominator.

Example : 7/8 punctured Viterbi

Cod0 : 1000101
Cod1 : 1111010

Conv. 1 pattern : C0(1) C1(1) C1(2) C1(3) C1(4) C0(5) C1(6) C0(7) ...
Conv. 2 pattern : C0(1) C1(1) C1(3) C1(2) C1(5) C0(4) C1(7) C0(6) ...

Convention 2 pattern is convention 1 pattern with each pair of bit swapped apart from the first pair.

The convention can be defined with the registry key VitPunctConv.

The following table shows the effect of the different values of VitPunctConv registry key.

0 : depuncturing is defined by the VitPunctSwap registry key as described in the previous chapter

1 : VitPunctSwap registry key is ignored. VitPunctCode0 and VitPunctCode1 can be defined

asymetricaly. convention is 1.
2 : VitPunctSwap registry key is ignored. VitPunctCode0 and VitPunctCode1 can be defined
asymetricaly. convention is 2.

Next figure shows the BER performances of ¾ punctured Viterbi :

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1,E-01

1,E-02

1,E-03
NRZ-L
1,E-04 DNRZ
Viterbi 1/2
1,E-05 viterbi 3/4
Viterbi 3/4 DNRZ
1,E-06

1,E-07

1,E-08
2,0 3,0 4,0 5,0 6,0 7,0 8,0

Figure 21 : Punctured Viterbi BER Performances.

3.3.4 PCM Decoding

The following codes are supported : NRZ-L/M/S, DNRZ, Bi-P-L/M/S.

When Viterbi decoding is not used, DNRZ is required for ambiguity resolution in QPSK and OQPSK mode.
Several possible DNRZ schemes can be defined, according to the demodulation (QPSK, or OQPSK).

3.3.4.1 DNRZ, QPSK Decoding (DQPSK)

Several DNRZ algorithms are possible for ambiguity resolution in QPSK mode. The DNRZ code (algorithm) value
can be programmed via a registry key (see section 4.2.6.2.6) using examples in next two sections (CCSDS
recommended code and non-CCSDS codes).

3.3.4.1.1 CCSDS RECOMMENDED DNRZ CODE IN QPSK MODE

CCSDS recommendation for DQPSK is :

Iout IinQinIout 1IinQinQout 1IinQinIout 1IinQinQout 1

QoutIinQinQout1IinQinIout1IinQinQout1IinQinIout1
This is equivalent to the following DQPSK decoding look-up table :

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Idl[n-1] Qdl[n-1] Idl[n] Qdl[n] Îin[n] Q̂in[n]

0 0 0 0 1 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 1 0 0
0 1 0 0 0 1
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 1 1
1 0 1 1 0 1
1 1 0 0 0 0
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 1 1

3.3.4.1.2 OTHER POSSIBILITIES FOR DNRZ CODES IN QPSK MODE

Next table summarizes the 24 possibilities for DNRZ codes in QPSK Mode :

In Qn Feature
code 1 11 10 01 00 C5A3 AC35 CCDSDS DNRZ
code 2 11 01 10 00 AC35 C5A3 CCDSDS DNRZ + Q;I
code 3 01 10 11 00 6996 AC35
code 4 10 01 11 00 AC35 6996
code 5 10 11 01 00 C5A3 6996
code 6 01 11 10 00 6996 C5A3
code 7 11 10 00 01 C5A3 9669
code 8 11 00 10 01 AC35 9669
code 9 00 10 11 01 6996 3A5C
code 10 10 00 11 01 AC35 3A5C CCDSDS DNRZ + Q;/I
code 11 10 11 00 01 C5A3 53CA CCDSDS DNRZ + I;/Q
code 12 00 11 10 01 6996 53CA
code 13 11 00 01 10 9669 AC35
code 14 11 01 00 10 9669 C5A3
code 15 01 00 11 10 3A5C AC35 CCDSDS DNRZ + /I;Q
code 16 00 01 11 10 3A5C 6996
code 17 00 11 01 10 53CA 6996
code 18 01 11 00 10 53CA C5A3 CCDSDS DNRZ + /Q;I
code 19 00 10 01 11 53CA 3A5C CCDSDS DNRZ + /Q;/I
code 20 00 01 10 11 3A5C 53CA CCDSDS DNRZ + /I;/Q
code 21 01 10 00 11 53CA 9669
code 22 10 01 00 11 9669 53CA
code 23 10 00 01 11 9669 3A5C
code 24 01 00 10 11 3A5C 9669

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3.3.4.1.3 DQPSK CONFIGURATION IN REGISTRY

Using the CCSDS DNRZ code and its decoding look-up table :

In 1 1 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0xC5A3
Qn 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0xAC35

To select this code in the registry, set the registry key to 1 (code number in the left-hand column of the above
table) or enter the DNRZ code value (0xC5A3AC35) as defined in the above decoding table).

Selection of the other codes follows the same rule.

3.3.4.2 DNRZ, OQPSK Decoding

Several DNRZ algorithms are possible for ambiguity resolution in OQPSK mode. The DNRZ code (algorithm)
value can be programmed via a registry key (see section 4.2.6.2.6) using examples in next two sections (Most
commonly used and Other possibilities).

3.3.4.2.1 MOST COMMONLY USED DNRZ CODE IN OQPSK MODE

Idl[n-1] Qdl[n-1] Idl[n] Qdl[n] Îin[n] Q̂in[n]

0 0 0 0 0 1
0 0 0 1 0 0
0 0 1 0 1 0
0 0 1 1 1 1
0 1 0 0 1 1
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 0 0
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 0
1 1 1 0 0 0
1 1 1 1 0 1

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3.3.4.2.2 OTHER POSSIBILITIES FOR DNRZ CODES IN OQPSK MODE

Next table summarizes the 24 possibilities for DNRZ codes in OQPSK Mode :

In Qn Feature
code 1 0 1 1 0 3C3C 9999 Most common
code 2 1 0 0 1 C3C3 6666
code 3 0 0 1 1 0FF0 C3C3
code 4 1 1 0 0 F00F 3C3C
code 5 1 0 1 0 CC33 A5A5 NRZ-S
code 6 0 1 0 1 33CC 5A5A NRZ-M
code 7 0 1 1 0 3C3C 6666
code 8 1 0 0 1 C3C3 9999
code 9 0 0 1 1 0FF0 3C3C
code 10 1 1 0 0 F00F C3C3
code 11 1 0 1 0 CC33 5A5A
code 12 0 1 0 1 33CC A5A5
code 13 0 1 1 0 9999 3C3C
code 14 1 0 0 1 6666 C3C3
code 15 0 0 1 1 C3C3 0FF0
code 16 1 1 0 0 3C3C F00F
code 17 1 0 1 0 A5A5 CC33
code 18 0 1 0 1 5A5A 33CC
code 19 0 1 1 0 6666 3C3C
code 20 1 0 0 1 9999 C3C3
code 21 0 0 1 1 3C3C 0FF0
code 22 1 1 0 0 C3C3 F00F
code 23 1 0 1 0 5A5A CC33
code 24 0 1 0 1 A5A5 33CC

3.3.4.2.3 DOQPSK CONFIGURATION

Using the example of the most common DOQPSK code, and its decoding look-up table :

In 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0x3C3C
Qn 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0x9999

To select this code in the registry, set the registry key to 1 (code number in the left-hand column of the above
table) or enter the DNRZ code value (0x3C3C9999) as defined in the above decoding table).

Selection of the other codes follows the same rule.

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3.3.5 I/Q Shift Compensation in OQPSK Mode

In OQPSK mode, I and Q symbols are ideally shifted by half symbol.

BER degradation is expected if the I-to-Q phase offset is not exactly half symbol.

For optimum BER performances, the HDR demodulator software is able to compensate, in real-time, for incorrect
phase offset. The maximum adjustment range is half-symbol  ¼ symbol.

Parameter OQPSK I/Q delay allows enabling or disabling the compensation mechanism :

 OFF : Compensation is disabled.

 ON(auto) : Compensation is enabled. The phase offset error is automatically compensated.

 ON(static) : Compensation is enabled. The expected phase offset error must be manually programmed
(from +0.25 to –0.25 symbol).

The I/Q shift status indicates the measured phase offset error.

On the Test Modulator, the I/Q phase offset in OQPSK mode can be set in the range [half-symbol  0.5 symbol].

The phase offset adjust is disabled if the programmed bit rate is below 200 Mbps.

3.3.6 CCITT V.35 De-scrambler

The Cortex HDR XXL supports the V.35 descrambler.

In the demodulation channel, this descrambler is implemented after the Viterbi decoder and the differential
decoder if used and before the frame synchronizer.

The V.35 descrambler is basically a 20-stages shift register with XORED specific outputs. In addition, a specific
operation is used inside the process to guarantee an output transition once every 32 bits for long sequences of 0
or 1.

Two standards are implemented inside the Cortex HDR XXL:

 the CCITT V.35 standard

 the INTELSAT V.35 standard

The descrambler can be enabled or disabled by set-up (from the Cortex HDR GUI or by TCP/IP remote control).
The selection of the standard is done also by set-up.

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3.3.7 BEM : 4D-8PSK-TCM-DVB-S Reed Solomon Decoding

This mode is compatible with the CCSDS REPORT ON BANDWIDTH-EFFICIENT MODULATIONS (CCSDS
413.0-G-1, GREEN BOOK, 31 March 2003) with completion for updating ECSS RF & Modulation standard ECSS
E-50-05A and ECSS Telemetry channel coding ECSS E-50-01 draft 0.5

This modulation is compatible with the PLEIADES satellites.

3.3.7.1 Introduction
The L-dimensional MPSK-TCM (LD-MPSK-TCM) belongs to a family of modulations first introduced by G.
Ungerboeck and improved by S. Pietrobon with the introduction of the multidimensional techniques. The MPSK-
TCM are based on MPSK modulations with the use of convolutional coding to introduce “authorized sequences”
between signal points linked by the trellis of the code. Note that single constellation MPSK modulations may also
be referred to as "bi-dimensional" in reference to the representation of the MPSK constellation points in a signal
space defined by orthogonal I and Q vectors.

In any case, the application of this procedure to several parallel constellations of the same size is referred to as L-
dimensional TCM, denoted LD-MPSK-TCM (with L > 1 and M = 8). The trellis is constructed to maximize the
minimum Euclidian distance between different paths originating and merging to the same state. The construction
of the optimum trellis code and partitioning for the M points in the constellation is based on heuristic rules
proposed in G. Ungerboeck. "Channel Coding with Multilevel/Phase Signals", IEEE Transactions on Information
Theory, vol. IT-28, no. 1, pp.55-67, January 1982 and S. Pietrobon et al. "Trellis-Coded Multidimensional Phase
Modulation", IEEE Transaction on Information Theory, vol. 36, no. 1, pp.63-89, January 1990.

With 4D-8PSK-TCM, the combination of convolutional coding, multiphase modulation and multidimensional
techniques offers a substantial power gain together with bandwidth conservation or reduction, in comparison to
their separate utilization as it is done frequently with binary or quaternary modulations (i.e., sequential
implementation of convolutional coding). The result is an improvement of the performances in terms of BER versus
signal to noise ratio for the same or better bandwidth efficiency, compared with the uncoded (or even
convolutionally coded) OQPSK or QPSK modulations.

Example: Assuming the bit rate of input data equal to 100 Mbps, the 4D-8PSK-TCM channel symbol rate is 50
Msps for 2 bits/channel-symbol or 40 Msps for 2.5 bits/channel-symbol.

The performances of 4D-8PSK-TCM scheme can be substantially improved when concatenated with Reed
Solomon (R-S) on bytes block coding with a proper interleaving so as to ensure a good word error splitting (at the
output of the convolutional trellis decoder) and then good working conditions for the R-S decoder.

3.3.7.2 4D-8PSK-TCM Coder

The 4D-8PSK Trellis-Coded Modulator consists of a serial to parallel converter, a differential coder, a trellis
encoder (convolutional coder), a constellation mapper and an 8PSK modulator (see Figure 22).

Note that in this figure, wi (with index i = 1, … , m) represent the uncoded bits and xj (with index j = 0, … , m) are
the coded bits. The trellis encoder is based on a 64 state systematic convolutional coder and can be considered as
the inner code if an outer block code is introduced. Carrier phase ambiguity is resolved by the use of a differential
coder located prior to the trellis encoder. Spectral efficiencies of 2, 2.25, 2.5, and 2.75 bits/channel-symbol are
achieved with four possible architectures of the constellation mapper. The output switch addresses successively

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one of the four symbols ( Z(0) – Z(3) ) from the constellation mapper to the 8PSK modulator (which is in fact a
QPSK modulator for the 2 first efficiencies values).

The present standard is based on the use of a 4D-8PSK-TCM characterized by the following parameters:

 Size of the constellation : M = 8 phase states (8PSK)

 Number of signal set constituents : L = 4 (shown as Z(0) … Z(3) in Figure 22)

 Number of states for the trellis encoder : 64

 Rate of the convolutional coder used for the construction of the trellis : R = 3/4

 Rate of the modulation: Rm = m/(m+1) selectable to 8/9, 9/10, 10/11, or 11/12

 Efficiency of the modulation :

 Reff = 2 bits per channel-symbol (for Rm = 8/9)

 Reff = 2.25 bits per channel-symbol (for Rm = 9/10)

 Reff = 2.5 bits per channel-symbol (for Rm = 10/11)

 Reff = 2.75 bits per channel-symbol (for Rm = 11/12)

In fact, the serial to parallel conversion is a byte (8 bits) to symbol (8 to 11 bits) conversion that will be described
later.

Figure 22 : Structure of the 4D 8PSK-TCM Coder/Mapper

3.3.7.2.1 DIFFERENTIAL CODER

The differential coder depicted in Figure 23 is used to eliminate phase ambiguity on carrier synchronization for
each modulation efficiency. Table 12 gives the bit reference at input and output of the differential coder in each
case.

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Table 12 : Bit Mapping for Differential Coder

An example of differential encoder connections is given in Figure 23 for the 2 bits/channel-symbol case. The
structure of the modulo 8 adder is also shown; it is applicable to both the coder mapper and differential coder.

OUT

Figure 23 : Differential Coder and Modulo-8 Adder Principle

For all the bits non concerned by the differential encoding, we have then :
xk  wk k  m 1

3.3.7.2.2 CONVOLUTIONAL CODER

The convolutional coder used to implement the trellis is depicted in Figure 24. This code corresponds to one of the
“best” codes for phase transparency.

The systematic coder is implemented with the following characteristics :

 number of states : 64 states,

 constraint length : K = 7

The convolutional encoder is specified by the following polynomial in octal: h 3 = 050, h2 = 024, h1 = 006, h0 = 103.
Figure 24 shows the recommended convolutional encoder. The shift registers of the encoder are clocked at the
rate of RChS/4.

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Figure 24 : Convolutional Coder Recommended for High Data Rates

The number of coded bits is the same for the four modulation efficiencies (i.e., the same structure is used for 2,
2.25, 2.5, and 2.75 bits/channel-symbol), only the number of uncoded bits is changed. The advantage of this coder
is its optimized performance and the reduced internal rate which is equal to 1/8, 1/9, 1/10, or 1/11 of the
information rate.

3.3.7.2.3 CONSTELLATION MAPPER FOR 4D-8PSK-TCM

The constellation mapper principles are given in next figures for the four possible efficiencies of this modulation
(i.e., 2 bits/channel-symbol, 2.25 bits/channel-symbol, 2.5 bits/channel-symbol and 2.75 bits/channel-symbol).
These mappers implement the straightforward logical mapping described in the equations below. The
correspondence between the signals Z(i) at the input of the modular and the 8PSK phase states of the
constellations follows a natural mapping (i.e., 0, 1, 2 …, 7).

If Z(i) represents the signals (three lines) at the input of the modulator with Z(0) being the signal set of the first
constellation and Z(3) being the signal set of the fourth constellation, the signal set Z (i) is represented by the
following equation. This representation shows that the bits which are common to each vector set (shown in the first
part of right-hand side of each equation) are sensitive to a phase rotation of /4 and will be differentially encoded.

(i) Equation for 2 bits/channel symbol efficiency :

 Z (0)   1  0   0 
 (1)        
 Z   4 x  2 x  x    4
1 x 7  
 2
x 3 
Z ( 2)   8 5 1 1  x6   x2  mod 8
 ( 3)        
     
 Z   1  x 7  x 6  x 4   x 3  x 2  x 0 

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x0
x1
x2
x3
x4 0
x5 0
x6
x7
x8 0
(1) (1) (1) 210 210
0 Z2 Z1 Z0
+
2 1 0
21 0 2 1 0 2 1 0 2 1 0 210 210
+ + +
2 1 0 2 1 0 2 1 0

(0) (0) (0) (1) (1) (1)

Z2 Z1 Z0 Z2 Z1 Z0 (2) (2) (2) (3) (3) (3)
Z2 Z1 Z0 Z2 Z1 Z0

Figure 25: Constellation Mapper for 2 bits/channel-symbol

(ii) Equation for 2.25 bits/channel symbol efficiency :

 Z ( 0)   1  0   0   0 
 (1)          
 Z  1
  4 x  2 x  x   4  x   x   x 0 
1 
8

  2 4
   0  mod 8
Z ( 2)   9 6 2
x7 x3
 ( 3)          
1  x  x  x   x  x  x   x 
 Z      8 7 5  4 3 1   0  

Figure 26 : Constellation Mapper for 2.25 bits/channel-symbol

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(iii) Equation for 2.5 bits/channel symbol efficiency

 Z ( 0)   1  0   0   0 
 (1)          
 Z  1
  4 x  2 x  x   4  x   x   x 

9
  2 5
  1
mod 8
x 0 
3  
Z  
( 2 ) 10 7
1 x8 x4
 ( 3)          
            
 Z      9
1 x x 8 x 6  5
x x 4 x 2  1x x 0 

Figure 27 : Constellation mapper for 2.5 bits/channel-symbol

(iv) Equation for 2.75 bits/channel symbol efficiency

 Z ( 0)   1  0   0   0 
 (1)          
 Z   4 x  2 x  x 1  4 x10  
 2
x6  

x2 
 Z ( 2)   11 8 4  
1  x9  x5  x1  mod 8
 ( 3)          
1  x  x  x   x  x  x   x  x  x 
 Z      10 9 7  6 5 3  2 1 0 

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Figure 28 : Constellation Mapper for 2.75 bits/channel-symbol

3.3.7.2.4 CODER/MAPPER IMPLEMENTATION AT 2, 2.25, 2.5 & 2.75 BITS/CHANNEL-SYMBOL EFFICIENCY

The principle of the coder-mapper for 2, 2.25, 2.5, and 2.75 bits/channel-symbol efficiency is given in next figures :
Data In(0:7)

Z(0) Modulated
Carrier
Constellation mapper
Byte to Symbol

w8 x8 Z(1)
conversion

x7 x7
x6 x6
w5 x5
x4 x4 Z(2)
x3 x3
x2 x2
w1 x1 Z(3)
Differential Convolutional x0
coder Carrier
Coder R=3/4 Generator
Figure 29: Coder and Mapper Implementation at 2 bits/channel-symbol Efficiency

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Data In(0:7) Z(0) Modulated

Carrier

Constellation mapper
Byte to Symbol
w9 x9
x8 x8 Z(1)
conversion
x7 x7
w6 x6
x5 x5
x4 x4 Z(2)
x3 x3
w2 x2
x1 x1 Z(3)
Differential Convolutional x0
coder Carrier
Coder R=3/4 Generator
Figure 30 : Coder and Mapper Implementation at 2.25 bits/channel-symbol Efficiency
Data In(0:7)

Z(0) Modulated
w10 x10 Carrier

Constellation mapper
Byte to Symbol

x9 x9
x8 x8 Z(1)
conversion

w7 x7
x6 x6
x5 x5
x4 x4 Z(2)
w3 x3
x2 x2
x1 x1 Z(3)
Differential Convolutional x0
coder Carrier
Coder R=3/4 Generator
Figure 31: Coder and Mapper Implementation at 2.5 bits/channel-symbol Efficiency
Data In(0:7)

Z(0) Modulated
w11 x11
x10 x10 Carrier
Constellation mapper
Byte to Symbol

x9 x9
w8 x8 Z(1)
conversion

x7 x7
x6 x6
x5 x5
w4 x4 Z(2)
x3 x3
x2 x2
x1 x1 Z(3)
Differential Convolutional x0
coder Carrier
Coder R=3/4 Generator
Figure 32 : Coder and Mapper Implementation at 2.75 bits/channel-symbol Efficiency

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3.3.7.3 DVB-S Transport Layer : Reed Solomon Code

As defined in § 4.7 of ECSS-E50-01 draft 0.5, the concatenation principle correspond to the following processes
but with some interaction between them as depicted in next figure :

Randomized Codeblocks Transport frames MTCM symbols

Transfer frames
Row/column
Scrambler R-S encoder interleaving with Bytes to Symb. MTCM encoding
(DVB-S type) (DVB-S type) sync. Bytes transformation 8PSK modulation
insertion
Channel_symbol
Synchronization for
frame/RS and scrambler

hronisation
Transfer frames Randomized Codeblocks Transport frames MTCM symbols
Symb. to bytes
Descrambler R-S decoder MTCM 8PSK
transformation
(DVB-S type) (DVB-S type) decoding demodulation
/deinterleaving

Sync bytes
search/global sync.

Figure 33 : Concatenation Principle

3.3.7.3.1 SYNCHRONIZED RANDOMIZATION

Within the transmitter, the input digital data is randomized with a PRBS whose characteristics are :

 Generating polynomial : 1+x14+x15

 Initialization sequence : 100101010000000

This sequence is loaded at the beginning of each transport frame. Due to the chosen polynomial, it is possible to
output the data by bytes with the help of a shifted calculation , i.e. out bit1 or MSB of byte = reg15 EX-OR reg14,
out bit2 = reg14 EX-OR reg13, out bit3 = reg13 EX-OR reg12, out bit4 = reg12 EX-OR reg11, out bit5 = reg11 EX-
OR reg10, out bit6 = reg10 EX-OR reg9, out bit7 = reg9 EX-OR reg8 and out bit8 or LSB of byte = reg8 EX-OR
reg7 and then shift by 8 bits the contents of the register before calculating the PRBS sequence for the next byte.

It should be noticed that in order to avoid tedious rate changes, the data have to be captured at the interface by
group of 238 bytes with one blank byte in front and 16 blank bytes at the rear. During the blank bytes, the
randomization is shifting but the enable bit must be downed to zero.

The randomization processing is described on next figure.

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B 8

Figure 34 : Randomization Principle

3.3.7.3.2 REED-SOLOMON ENCODING

Then, the data shall be encoded by using a shortened Reed-Solomon encoder (238,254) type

The encoding process is the following :

 first, one byte (00 hexa.) is added in front of the 238 data bytes

 then a standard (239,255) R-S code (from DVB-S standard) is applied by computing 16 redundancy
bytes.

 finally the 00 extra-byte is removed

The code generation polynomial is : g(x) = (x+0)(x+1)(x+2)...(x+15) with =02 (hexa.)

The primitive polynomial is : p(x) = 1+x2+x3+x4+x8

3.3.7.3.3 PACKETS INTERLEAVING AND SYNCHRONISATION BYTE INSERTION

After R-S encoding, the data shall be interleaved (depth 8 or 16) and formatted in transport frames.

The interleaving is performed by using a matrix of (8)16 rows and 254 columns. The 254-bytes packets are writen
row by row, the first byte being put in the first cell. When filled, the matrix is read column by column by packets of
254 bytes separated by synchronization markers. The process goes on with the following group of 16(8)*254 data
bytes creating then a complete frame of 16(8)*255 bytes.

The 16 (8) blocks of 255 bytes (254 data bytes plus one synchro. byte) form the transport frame. This frame
accounts for 4080 (2040) bytes or 32640 (16320) bits.

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The synchronization marker of the frame (corresponding to the first block of 254 bytes) is B8 (in hexadecimal) and
the separation between the other 15 (7) blocks of the frame is made by a marker whose value in hexadecimal is
47 when the medium data rate is used.

For high data rates interface, the equipment has the capacity for inserting filling frames. The synchronization
marker for those filling frame are specific. 96 (in hexadecimal) for the first block and 69 for the 15 (7) following
blocks.

It should be noticed that at the receiver side, those filling packets have to be removed.

The succession of the three processes described here above give the way to :

PRBS trunc. Period = 2023 (I=8) or 4063 (I=16) bytes

17 17 R2a 17 R8a or 16a 17 R1b

blank R1a blank
blank blank
bytes 238 bytes bytes 238 bytes bytes 238 bytes bytes 238 bytes

Source information in packets : Blank bytes and randomized block Ri

254 bytes

Sync Ri RS redund.
or sync i 238 bytes 16 bytes

Reed Solomon RS (254,238, t=8) error protected packet

2040 (I=8) or 3824 (I=16) bytes

IR1a Sync IR2a Sync IR8a or 16a IR1b

Sync Sync
238 bytes 2 238 bytes 8/16 238 bytes 238 bytes

Randomized transport packets : Sync bytes and interleaved randomized block IRi

3.3.7.3.4 INTERFACE BETWEEN TRELLIS CODED SYMBOLS AND BYTES

As the size of trellis coded symbol can vary from 8 to 11 bits, there must be a definition of the arrangement that
gives the bytes (8 bits fixed) for the R-S concatenated part.

The convention is the following, depicted for 4D-8PSK-TCM 2.5 with the arrangement of the 10 bits with regard to
the 8 input bits is described on next figure.

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A B C D E
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w10 w9 w8 w7 w6 w5 w4 w3 w2 w1 w10 w9 w8 w7 w6 w5 w4 w3 w2 w1

Decuplet 1 = Decuplet 2 = Decuplet 3 = Decuplet 4 =

MTCM symbol 1 MTCM symbol 2 MTCM symbol 3 MTCM symbol 4

Notes : * Byte 1 is the first byte transmitted on the Air interface,

* The UW will be every time positioned on the byte 1.

Figure 35 : Data Arrangement in TCM 2.5 bits/channel_symbol

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3.3.8 PRN-BER Computation

Depending on the mission, BER measurement in PRN mode can be done either on separate or merged I and Q
channels (see 4.2.6.2.3).

3.3.8.1 BER on Separate I & Q Channels

This method is based on PRN codes property : The splitting of a PRN data flow into I and Q provides two PRN
data flows (same PRN).

When restarting BER measurement (see 4.5.4.2), each ambiguity is tested (~1s), before selecting the ambiguity
which provides with the lower BER. The BER is then measured applying this ambiguity. This method is particularly
interesting when the ambiguity is not resolved by the demodulation (example : Metop satellite configuration).

Example 1 : QPSK, NRZ-L demodulation. Demodulation remaining ambiguities :

If natural QPSK de-mapping is used : IQ, /QI, Q/I,/I/Q.

If inverse QPSK de-mapping is used : QI, I/Q, /IQ,/Q/I.

Even with these ambiguities, BER measure can be done in this mode.

Using this method, BER I and BER Q can be separately displayed (see 4.2.6.2.3, value 1), or averaged (see
4.2.6.2.3, value 0).

Example 2 : 8PSK, NRZ-L demodulation, using a PRN code for each 3 8PSK data flows.

Demodulation remaining ambiguities :

If natural 8PSK de-mapping is used : 8 phase ambiguities.

If inverse 8PSK de-mapping is used : 8 other phase ambiguities.

Providing that the right 8PSK de-mapping (normal or inverse, natural or Gray) has been selected, BER measure
can be done in this mode.

3.3.8.2 BER on Merged I & Q Channels

This method applies to merged I and Q data in QPSK or OQPSK mode, or single I data in BPSK mode, or single I
+ Single Q in UQPSK mode, or single1 + single2 + single3 in 8PSK mode.

In this mode, no ambiguity tests are done. Data which are used for BER measure are an image of output data
(channel A for Demodulation Unit # 1, channel B for Demodulation Unit # 2, see 2.2.2). Ambiguities can then be
manually tested, using the 8 first values of OUTPUT MODE parameter (see 4.5.4.1).

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REGISTRY QPSK QPSK & OQPSK BPSK UQPSK AQPSK 8PSK

SELECTION OQPSK
+ SINGLE VITERBI
4.2.6.2.3

0 Method 1 :
IQ,/IQ,I/Q,/I/Q,
QI,/QI, Q/I,/Q/I
GUI : 1 BER value Method 1 : Method 1 : Method 1 : Method 1 :
(I,Q average)
IQ,/I/Q I,/I I,/I, on I 8 phase
(IQ merged before GUI : 1 BER value Q,/Q on Q ambiguities
Viterbi decoding)
1 Method 1 : GUI : 2 BER values GUI : 1 BER value
GUI : 1 BER value (BER I & BER Q) (averaged BER)
IQ,/IQ,I/Q,/I/Q,
QI,/QI, Q/I,/Q/I
GUI : 2 BER values
(BER I & BER Q)

2 Method 2 : Method 2 : Method 2 : Method 2 : Method 2 :

GUI : 1 BER value GUI : 1 BER value GUI : 1 BER value GUI : 2 BER values GUI : 1 BER value
(BER IQ) (BER I) (BER I &BER Q) (averaged BER)

Figure 36 : BER Measurement Methods : Tested ambiguities and GUI display

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3.3.9 Digital Outputs

Digital outputs characteristics can be configured :

 Clock polarity : normal or inverted.

 Data (I/Q) polarity : normal or inverted.

 Data swap : Normal I & Q, I inverted & Q, I & Q inverted, I inverted & Q inverted
+ Swap : Q & I, Q inverted & I, Q & I inverted, Q inverted & I inverted

 Output mode : Normal or split (separate I & Q output) or I/Q merged or CADU output (refer to the
Hardware Description chapter)

3.3.10 Doppler and Integrated Phase Measurement

3.3.10.1 Introduction
The HDR provides Doppler measurements (measurements of the offset between the set up IF value and the
actual one) and integrated phase measurements. These measurements are available for the user through a
specific TC/IP port (refer to the STI 100013 HDR document).

The elementary Doppler measurements (IF offset measurements) are generated every 13.1072 ms. They are
sampled at the rate specified by the parameter « Doppler measurement sampling rate » (every 100 ms to every 10
seconds). As the sampling rate and the generation rate are asynchronous, a linear interpolation is applied for
improved measurement accuracy. Samples are stored, for further transmission, in a measurement block which
size is programmable between 1 and 1000 elementary measurement(s).

The Elementary integrated phase measurements are generated every 13.1072 ms. They are sampled at the rate
specified by the parameter « Doppler measurement sampling rate » (every 100 ms to every 10 seconds). As the
sampling rate and the generation rate are asynchronous, a linear interpolation is applied for improved
measurement accuracy. Samples are stored, for further transmission, in a measurement block which size is
32-N
programmable between 1 and 1000 elementary measurement(s). The integrated phase resolution is 2π/2
radian, with N tunable (see user’s manual for more information). The 64-bit phase counter capacity is 232+N/IF
seconds. As an example, N = 15 gives a counter capacity of 1 day 8 hours and 46 minutes at 1.2GHz.
The following demodulator menus support advanced Doppler measurements, integrating the phase of the
carrier oscillator: Menus # 6, 7, 9, 10, 12, 13, 17, 18, 27, 28, 36, 38, 39, 50.

A single Doppler port is used for transmitting IF offset measurements or integrated phase measurements.(refer to
the STI 100013 HDR document).

3.3.10.2 Required setup for optimal performance

Accurate phase and Doppler measurements need a very precise and stable sampling period. Moreover, the
internal oscillators must also run at a very stable frequency. Even though it is possible to get rough Doppler and
phase measurements without any external reference, it is strongly recommended to connect the demodulator to a
10MHz reference to obtain accurate results.

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Doppler and phase measurements are time-tagged. For precise datation of Doppler and phase measurements, it
is strongly recommended to connect the demodulator to an IRIG-B generator. In such case, the precision of the
time tag is 1µs.

3.3.10.3 Sampling rate

Elementary accumulated phases are sampled at the rate specified by the parameter « Doppler measurement
sampling rate » (every 100 ms to every 10 seconds, see STI). Phase generation period depends on the sampling
rate value.
If the sampling rate is a multiple of 10 ms, the accumulated phases are generated each 10 ms in order to take
advantage from raw data. Thus, Doppler measurement is based on exact values of phase.
If the sampling rate is not a multiple of 10 ms, the raw accumulated phases are sampled every 10 ms. To obtain
the accumulated phase at the desired date, an interpolation process is used. The following figure shows how to
set sampling rate for the Doppler port:

3.3.10.4 Accumulated Phase Format

Elementary 32-bit phase values are accumulated in a 96-bit internal counter. The phase resolution of this counter
is 2-32 cycle, or 2π/232 radian = 8.4e-8°. The 32 LSB can thus be seen as a measurement of the phase, modulo 2π,
while the 64 LSB count the number of cycles since the Doppler port started to emit:

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64 bits 32 bits
Cycle counter 2π rad

A 64 bit counter, using 32 bits for the modulo part, and 32 bits for the cycle counting part, has a revolution period
of 5s for an IF at 720 MHz. The overall 96 bits counter has a revolution period of more than 800 years. The
Doppler port thus discards some of the MSBs and LSBs to output 64 bits phase measurements. The truncature
operates as follows. The registry value:

HKEY_LOCAL_MACHINE\SOFTWARE\IN-SNEC\CrtxHdr\SetDefault\Signal Processing\DmuX\Integ_Phase_BinShift

sets the number of LSBs that are discarded. Let N be the value of Integ_Phase_BinShift:

Internal 96 bits counter : Cycle counter 2π rad

Doppler port phase Cycle counter 2π rad

measurement :
32+N 32-N N

The phase resolution thus becomes 2π/232-N radian. The revolution period of this counter is 232+N/IF where IF is the
input IF frequency. The default value for the registry key is 15 (decimal), 0xE (hex).

Table 13 and Table 14 give phase resolution and revolution period for different settings of N, with an IF of
720MHz, and 1.2 GHz.

Samples are stored for further transmission, in a measurement block which size is programmable between 1 and
1000 elementary measurement(s). The first measurement in the block is time-tagged. The figure below shows how
to set the block size in the DMU window.

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Phase Doppler
Truncature 64-bits phase
resolution resolution
(N) revolution time
in deg over 1s in Hz

26 5.6E+00 12 y 253 d 7 h 59 m 26 s 1.6E-02

25 2.8E+00 6 y 126 d 15 h 59 m 43 s 7.8E-03
24 1.4E+00 3 y 63 d 7 h 59 m 51 s 3.9E-03
23 7.0E-01 1 y 214 d 3 h 59 m 55 s 2.0E-03
22 3.5E-01 289 d 13 h 59 m 57 s 9.8E-04
21 1.8E-01 144 d 18 h 59 m 58 s 4.9E-04
20 8.8E-02 72 d 9 h 29 m 59 s 2.4E-04
19 4.4E-02 36 d 4 h 44 m 59 s 1.2E-04
18 2.2E-02 18 d 2 h 22 m 29 s 6.1E-05
17 1.1E-02 9 d 1 h 11 m 14 s 3.1E-05
16 5.5E-03 4 d 12 h 35 m 37 s 1.5E-05
Default registry
value for N 15 2.7E-03 2 d 6 h 17 m 48 s 7.6E-06
14 1.4E-03 1 d 3 h 8 m 54 s 3.8E-06
13 6.9E-04 13 h 34 m 27 s 1.9E-06
12 3.4E-04 6 h 47 m 13 s 9.5E-07
11 1.7E-04 3 h 23 m 36 s 4.8E-07
10 8.6E-05 1 h 41 m 48 s 2.4E-07
9 4.3E-05 50 m 54 s 1.2E-07
8 2.1E-05 25 m 27 s 6.0E-08
7 1.1E-05 12 m 43 s 3.0E-08
6 5.4E-06 6 m 21 s 1.5E-08
5 2.7E-06 3 m 10 s 7.5E-09
4 1.3E-06 1 m 35 s 3.7E-09
3 6.7E-07 47.7 s 1.9E-09
2 3.4E-07 23.8 s 9.3E-10
1 1.7E-07 11.9 s 4.7E-10
0 8.4E-08 5.9 s 2.3E-10

Table 13: counter capacity and resolution at 720 MHz

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Phase Doppler
Truncature 64-bits Phase
resolution resolution
(N) revolution time
in deg over 1s (in Hz)

26 5.6E+00 7 y 241 d 4 h 51 m 50 s 1.6E-02

25 2.8E+00 3 y 303 d 2 h 25 m 55 s 7.8E-03
24 1.4E+00 1 y 334 d 1 h 12 m 57 s 3.9E-03
23 7.0E-01 349 d 12 h 36 m 28 s 2.0E-03
22 3.5E-01 174 d 18 h 18 m 14 s 9.8E-04
21 1.8E-01 87 d 9 h 9 m 7 s 4.9E-04
20 8.8E-02 43 d 16 h 34 m 33 s 2.4E-04
19 4.4E-02 21 d 20 h 17 m 16 s 1.2E-04
18 2.2E-02 10 d 22 h 8 m 38 s 6.1E-05
17 1.1E-02 5 d 11 h 4 m 19 s 3.1E-05
16 5.5E-03 2 d 17 h 32 m 9 s 1.5E-05
Default registry
15 2.7E-03 1 d 8 h 46 m 4 s 7.6E-06
value for N
14 1.4E-03 16 h 23 m 2 s 3.8E-06
13 6.9E-04 8 h 11 m 31 s 1.9E-06
12 3.4E-04 4 h 5 m 45 s 9.5E-07
11 1.7E-04 2 h 2 m 52 s 4.8E-07
10 8.6E-05 1 h 1 m 26 s 2.4E-07
9 4.3E-05 30 m 43 s 1.2E-07
8 2.1E-05 15 m 21 s 6.0E-08
7 1.1E-05 7 m 40 s 3.0E-08
6 5.4E-06 3 m 50 s 1.5E-08
5 2.7E-06 1 m 55 s 7.5E-09
4 1.3E-06 57.6 s 3.7E-09
3 6.7E-07 28.8 s 1.9E-09
2 3.4E-07 14.4 s 9.3E-10
1 1.7E-07 7.2 s 4.7E-10
0 8.4E-08 3.6s 2.3E-10

Table 14: counter capacity and resolution at 1.2 GHz

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3.3.10.5 Displaying the carrier offset of the Doppler port in the DMU window

When using menu 6 or 7, the display of the carrier offset in the DMU window (see figure below) is modified to take
advantage of the accurate estimate of the Doppler port.

By default, in these two menus the carrier offset is computed using the integrated phase of the Doppler
measurement feature, with a fixed sampling period of 10ms.

The sampling period of the integrated phase offset can be modified through the Windows registry key:

HKEY_LOCAL_MACHINE\SOFTWARE\IN-SNEC\CrtxHdr\SetDefault\Signal Processing\DMUX\Integ_Phase_Freq_Offset

With the following possible values:

0: Default estimator
1: Integrated phase estimator over 10ms period
2: Integrated phase estimator over programmable period (same as the Doppler port)

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3.3.10.6 Interpolation Process

In some cases, when the sampling rate and the generation rate are asynchronous, a linear interpolation is applied
to provide the accumulated phases at the required sampling frequency.

Such an interpolation generates an error. Let’s call inter the interpolated phase, err the phase error, T the 10-ms
period and  the time between 0 and T when the phase is interpolated.

inter(t)(t)  (tT)(t)
T
The Taylor expression of the phase at t+ is :

2
(t)(t)F D(t) D'(t) R2(t) , where D(t) is the input Doppler and R2(t) the rest such
2
that :
3
R2(t )  sup D''(x) (Lagrange overestimation).
3! xt,t  
err(t )inter (t )(t )  (t T)(t)(t )(t) T    R2(t T)R2(t )
D'(t)
T 2 T
T2 T3
so err(t )   sup D'(t)   sup D''(x)
8 xt,t T  3 xt,t T 
For instance, a Doppler rate of 1000 Hz/s with a second-order Doppler variation of 10 Hz.s-2 give a phase error
lower than (0.0125 + 3.3310-6) cycle.
IN MOST CASES, USER WOULD NOT USE CRANKY VALUES FOR THE SAMPLING RATE. THUS, NO INTERPOLATION WOULD BE
APPLIED, BECAUSE ACCUMULATED PHASE ARE GENERATED SYNCHRONOUSLY WITH THE SAMPLING RATE DATES.

3.3.10.7 Doppler Computing

The Doppler measurements are computed owing to the accumulated phase interpolated every Ts seconds

according to the formula  2 2


f t Ts  132 
(t Ts)(t)
Ts
 f IFR , where f is the computed Doppler, fIFR is the IF

Receiver center frequency and  the accumulated phase with a resolution of 2-32 cycle.

ferr t Ts 
The Doppler error is
2

(t Ts)(t)
Ts
 ' t Ts
2
 
Ts 2 Ts 3
With (t Ts)(t)Ts'(t) ''(t)  (3)(t) R3(t Ts)
2 6
Ts 4
where R3(t Ts)   sup  (4)(x) ,
4! xt,t Ts
Ts2 2

and  2

' t Ts2 '(t) Ts''(t)
2
 (3)(t) R'2 t Ts
2
 
Ts
3
 
where R'2 t Ts 
2
 2

 sup  (4)(x) .
3! xt,t Ts


So ferr t Ts 
Ts2
 Ts3
 sup D(2)(x)   sup D(3)(x) where D(t) is the input Doppler.
2 24 xt,t Ts 16 xt,t Ts

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A typical second-order Doppler variation of 10 Hz.s-2and third-order Doppler variation of 10-4 Hz.s-3 give a phase
error lower than (4.1610-3 + 6.2510-9) Hz for a sampling period Ts of 0.1 s, and lower than (41.6 + 6.2510-3)
Hz for a sampling period Ts of 10 s.

3.3.10.8 Impact of Phase Errors on Doppler Computing

If err is the error on the accumulated phase, the error on the computed Doppler is lower than 1  2err , where
232 Ts
Ts is the sampling period.

So, the maximum error on the Doppler computing due to the linear interpolation on the second-order phase

variation is 
Ts 2

DR T
2
.

For example, with a Doppler rate of 1000 Hz/s, the maximum error will be 0.43 Hz for a sampling period of 0.1 s
and 0.0043 Hz for a sampling period of 10 s.

f 2vr
The relation between range rate and Doppler is :  , where f is the satellite carrier frequency, vr the radial
f c
velocity (range rate) and c the light celerity.

For a 2.2-GHz beacon, the corresponding range rate error will be 2.93 cm/s for a sampling period of 0.1 s and
0.293 mm/s for a sampling period of 10s.

3.3.10.9 Sampling Period Resolution

3.3.10.9.1 ERROR DUE TO COMPUTING
The accumulated phase and Doppler sampling is processed owing to an internal 64 bits- NCO running at T =
264
10 ms. The effective sampling period is : Tseff  T where incr is the NCO phase increment. So the
incr
resolution on the period is 
264T  1  1 e
incr incr e
 264T eTs2

incr 2 264T
where e is the error made on the phase

increment computing (in this computing Tseff is approximated by Ts, and e is consided as <<< incr).

Due to double-float format limitations, e = 214 is higher than the possible error (11 bits come from the difference
between the 64 bits and the 53 bits mantissa of the double-float representation, on which up to 3 bits may be lost
in the computing process).

When Ts = 10 s (worst case), the resolution is 6.810-12 s.

This resolution is effective when the programmed sampling period is a value for which the floating representation
does not generate any error (examples : 10 s, 1 s or 0.125 s).
An error  made on the sampling period generates an error on the Doppler estimation :

(t)(t Ts) (t)(t Ts)

Ts

Ts
(t)(t Ts) 
Ts(Ts)

(t)(t Ts) 
Ts
  f t Ts   ,
Ts 2 Ts
 
where f is the current IF frequency.

With a typical value of 720 MHz, the Doppler computing error will be 39 mHz with Ts = 0.125 s.

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3.3.10.9.2 ERROR DUE TO FLOATING REPRESENTATION

The floating representation may generate an error in Ts  Ts2-23 (for example, 0.1 + 1.4910-9 s in the case of 0.1
s programming), which could have generated an error on Doppler estimation of  
f t Ts 223 .
2
But this floating representation is converted into double, owing to rounding processing, so that this error is not
added to the previous one (provided that the programmed sampling period does not have more than 5 digits in its
fractional part).

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3.4 DATA PROCESSING

3.4.1 Functional Breakdown of the Data Processing Unit

IF Input
Digital Outputs
Demodulatio
Demodulation n Data + Clock
Bit synchronization Generation
PCM decoding

Frame synchronization
Demodulatio n
R-S decoding/descrambling
Time Code Input
LDPC decoding
Virtual Channel extraction
Time Distribution
Time tagging

1-G bps Ethernet LAN

Demodulatio n
Demodulatio Data output
Real Time n
Buffer TCP/IP

Monitoring & Control

SCSI

Data output
FTP

DAS
Up to 3 Tbytes
RAID 5

Figure 37 : Data Processing Unit Block Diagram

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3.4.2 Frame Synchronization & Ambiguity Resolution

Frame synchronization is performed only if parameter Frame Synchronizer is set to on. If Frame
Synchronizer is set to off, raw data mode is activated (used with ingestion capability).

3.4.2.1 Frame Synchronization Strategy

The frame synchronizer strategy consists in finding the synchronization word which marks the beginning of the
frame in the signals (I in BPSK, I or Q or I & Q in QPSK, 1 & 2 &3 in 8PSK…) output by the bit synchronizer and in
reacting correctly to a loss of lock. This process is illustrated by next figure :

 SEARCH phase (S) :

In this mode, the frame synchronizer compares the signal bit by bit, until it matches the expected
synchronization word to within n bits where « n » is a programmable error factor, referred to as the
synchronization threshold (SYN). The synchronization threshold can vary from 0 to 15 (inclusive).

A programmable mask can also be applied to the synchronization word to ignore corrupted bits in the
synchronization word resulting from a spacecraft failure.

 CHECK phase (C) :

Before moving onto the LOCK mode, the frame synchronizer will check « i » consecutive occurrences of the
synchronization word (to within n errors). The contents of the telemetry block between two synchronization
words is not checked. During this phase, any occurrence of an incorrect synchronization word returns the
frame synchronizer to the SEARCH mode. « i » is programmable between 0 and 15 (inclusive) and referred as
the CTL (Check-To-Lock) threshold. To switch from SEARCH to LOCK, the frame synchronizer must receive
i+1 correct synchronization words except when i = 0 (in that case, the frame synchronizer will transmit frames
starting from the frame containing the first occurrence of a correct synchronization word).

 LOCK phase (L) :

In the LOCK mode, the frame synchronizer merely checks the occurrence of a new synchronization word (to
within n errors) every frame. The window in which the synchronization word should be found is enlarged by  N
bits (N = bit slip parameter = 0, 1 or 2 bits) to cope with potential bit slip in the telemetry demodulation process.

 FLYWHEEL phase (F) :

Transmission errors (signal heavily affected by noise) or loss of PSK demodulator lock may occur : the frame
synchronizer will then only return to SEARCH mode after « j » consecutive occurrences of incorrect
synchronization words (number of errors greater than the synchronization threshold). « j » is programmable
between 0 and 15 (inclusive) referred to as the LTS (Lock-To-Search) threshold.

The frame synchronizer synchronizes the frame in accordance with the SYN, CTL, LTS and Bit Slip parameters
provided to it :

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SW 1,9

SW 0,8
C correct

NT
correct
NT C SW 2,A
correct
(1) NT (2)
NT T
S (1)
NT L
SW 7,F incorrect
NT (3)

S: SEARCH T (3) T SW 3,B

(3)
C: CHECK SW 6,E T incorrect
L: LOCK incorrect T
F: FLYWHEEL NT
SW 4,C
F
SW: Synchronisation Word incorrect
NT : frame not transmitted
T : frame transmitted
F SW 5,D
incorrect F T

T
Scenario: CTL = 2, LTS = 3
Received telemetry:
Dotted lines: alternate scenario (different frame contents)
Frames 0 to 2: SW correct
Frames 3 to 7: SW incorrect (1): return to search mode if SW incorrect
Frames 8 to A: SW correct (2): stay in lock mode while SWs are correct
Frames B to F: SW incorrect (3): return to lock mode if SW correct

Figure 38 : Frame Synchronization Process

3.4.2.2 Frame Synchronizer Input

Frame synchronizer input can be either I or Q or merged I & Q. Depending on the demodulation and decoding
scheme, the following setting must be programmed (refer to parameter Input Selection in the Data Processing
Unit. Section 4) .

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3.4.2.3 Automatic PSK Ambiguity Resolution

Automatic PSK Ambiguity Resolution is performed only if parameter IQ output polarity in the Demodulator Unit
Monitoring Table is set to Ambiguity solved by DPU (see section 4.5.4.1.1.1). Should the data at the bit
synchronizer output be ambiguous, good data can be obtained by using this Ambiguity Resolution Mode.

Phase or channel ambiguity resolution is then automatically performed by the frame synchronizer during the
SEARCH phase (and only during this phase). If the comparison between the expected synchronization word and
a given window on the received data stream fails, another phase & channel configuration is checked and the
process is repeated until the frame synchronization word is identified. The frame synchronizer switches then to the
CHECK phase.

When the synchronization input is set to I ( respectively Q) (see section above)., the frame synchronizer
searches the synchronization word on I and Q channels (at Frame synchronizer input) and automatically
route the selected channel to the I (respectively Q) ECL output.

MODULATION & NRZ-L, BP-L DNRZ NRZ-M/S

DECODING
BP-M/S

QPSK Specification (note 2) Ambiguity resolved

OQPSK Specification (note 2)

BPSK Specification (note 2)

Not Applicable
AQPSK (note 1) Ambiguity resolved Ambiguity resolved

UQPSK Specification (note 2)

QPSK + Viterbi single Specification (note 2)

BPSK + Viterbi Specification (note 2)

QPSK + Dual Viterbi Ambiguity resolved Ambiguity resolved

OQPSK + Dual Viterbi Not Applicable Specification (note 2)

8PSK Ambiguity resolved (note 3)

Not Applicable
8PSK + TCM Specification (note 2)

Note 1 : Same bit rate but asynchronous I and Q clocks.

Note 2 : Allows to retrieve the original data stream even if the on-board data process is unknown to the operator.

Note 3 : Providing that correct 8PSK de-mapping (normal or Gray) has been selected.

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3.4.3 CCSDS Data De-randomizer

Randomization technique can be used:

- to maintain bit or symbol synchronization on the telemetry processing chain, by always having a minimum bit
transition density on the received telemetry signal,

- to avoid a false carrier lock that can occur on a modulated signal with periodic data,

- to avoid ambiguous data patterns that allow decoder false lock.

De-randomization by the CORTEX HDR complies to the CCSDS recommendation 101.0-B-3 (Blue Book - May
1992). The pseudo-random sequence is generated using the following polynomial :

h(x) = x8 + x7 + x5 + x3 + 1

Customized de-randomization can also be used (refer to the following paragraph).

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3.4.4 Customized Data De-randomization

The Cortex HDR provides a fully programmable de-randomization function.

Are programmable:

- the polynomial of the generator of the pseudo-random sequence The supported maximum degree of the
polynomial is 16 (refer to the examples below)

- the initial value of the generator (fully programmable between 0x0000 and 0xFFFF).

Example 1: Polynomial: X15 + X +1 (polynomial set-up value: 0x8003)

8 7 5 3
Example 2: Polynomial: X + X + X + X +1 (polynomial set-up value: 0x1A9)

For modulation schemes with separate I and Q, each de-randomization function is configurable
independently of each other.

The customized de-randomization can performed before or after the associated decoding (Reed Solomon or
LDPC). That is programmable (refer to CADU window).

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3.4.5 CRC Frame Checking

Reconstructed frames will be verified only if parameter Frame Checking is set to CRC .

The CRC is user-programmable via two parameters : CRC Polynomial (CRC16, CCITT, etc…) and CRC Preset
Value (usually all bits set to 0 or to 1).

The CRC value is supposed to be the last two bytes of each frame. The CRC Preset Value is added to the
computed checksum.

3.4.6 (255,223) Reed-Solomon Decoding

Reed-Solomon coding technique is well suited for burst error correction. It can be used in conjunction with
convolutional encoding to allow data reconstruction with the lowest error probability. Reed-Solomon decoding and
error-correction by the CORTEX HDR complies to the CCSDS recommendation 101.0-B-3 (Blue Book - May
1992). The following coding characteristics should be used :

 J = 8 bits per R-S symbol

 Conventional and dual basis supported

 E = 16 R-S symbol error correction capability within a R-S codeword (coded to decoded information
ratio = 255/223),

 Interleaving depth : auto-adjusted from 1 to 8 (frame-length dependent),

 Virtual filling for shorten RS code

 Other characteristics : see CCSDS recommendation 101.0-B-3.

The Virtual fill length and Interleaving depth are automatically deduced by the HDR from the CADU length
set by the operator with the following formula:

For I = 1 : 240 + 4 ≤ CL = (255-V) + 4 ≤ 255 + 4

For 1 < I ≤ 8 : 240 x I + 4 < CL = (255-V) x I + 4 ≤ 255 x I + 4

V max = 15
CL max = 2044
CL min = 244

I: Interleaving depth
CL: CADU length (in bytes)
V: Virtual fill length (in bytes)
Vmax: Virtual fill length max (in bytes)

The R-S decoder status includes two counters (good frames and bad frames), the number of corrected errors (per
frame) and the BER.

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3.4.7 (255,239) Reed-Solomon Decoding

This (255,239) Reed Solomon is recommended by the ECSS for links which have 4D-8PSK-TCM modulation :

 J = 8 bits per R-S symbol

 Conventional and dual basis supported

 E = 8 R-S symbol error correction capability within a R-S codeword (coded to decoded information
ratio = 255/239),

 Interleaving depth : 1 to 8

 Virtual filling for shorten RS code

 Other characteristics : refer to: ECCS - Space data links – Telemetry synchronization and channel
coding ECCS-E-50-01.

Interleaving depth and virtual filling length are automatically deduced from the CADU length set by the operator
with the same formula as for RS (255,223).

3.4.8 (10,6) Reed-Solomon Frame Header Decoding

This CCSDS shorten (10,6) Reed Solomon can be optionally used for transfer frame header error control:

 J = 4 bits per R-S symbol

 E = 2 R-S symbol error correction capability within a R-S codeword,

Other characteristics : refer to: CCSDS – AOS Space Data Link Control- CCSDS 732.0-B-1 Blue Book .

3.4.9 Specific Decoding

The HDR XXL provides specific decoding scheme, i.e. separate de-randomizer and Reed Solomon decoding on
each I and Q outputs of the demodulator.

On each I and Q separate outputs, the supported format of a CADU is the following:

 CADU length: 9424 bytes

 19 RS frames per CADU

 RS frame format: 2 interleaved (223,255)RS blocks with 7 bytes of virtual filling per RS block

 CADU synchronization word: RS encoded

 De-randomizer: CCSDS type.

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3.4.10 LDPC Decoding

3.4.10.1 Introduction
Low Density Parity Check codes are powerful linear block codes. They are defined by their parity check matrix.
The construction of these codes involves the juxtaposition of smaller cyclic sub-matrices. Nowadays, iterative
algorithms, which offer near-optimum performance at a manageable complexity, are used for the decoding of large
linear LDPC codes.

In conformity with the CCSDS experimental specification, the CORTEX HDR supports:

- the 7/8 LDPC code optimized for near-earth applications

- the 1/2 and 2/3 LDPC codes optimized for deep space applications

For more details on these codes, refer to the following CCSDS document:
Low Density Parity Check codes for use in near-earth and deep space applications
Experimental Specification - CCSDS 131.1-O-2
September 2007

3.4.10.2 LDPC 7/8 for near-earth applications

As specified by the CCSDS, the implemented (8160, 7136) LDPC code is a shortened version of the baseline
(8176, 7156) LPC code, i.e.

- information block length k: 7136 bits (892 bytes)

- code block length n: 8176 bits (1022 bytes)

3.4.10.3 LDPC 1/2 and 2/3 codes for deep space applications
The Cortex HDR supports a subset of the LDPC codes family optimized for deep space applications and specified
by CCSDS. These codes are also known as AR4JA LDPC codes.

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The supported codes are the following:

 1/2 rate LDPC 1K code

- information block length k: 1024 bits (128 bytes)

- code block length n: 2048 bits (256 bytes)

 1/2 rate LDPC 4K code

- information block length k: 4096 bits (512 bytes)

- code block length n: 8192 bits (1024 bytes)

 1/2 rate LDPC 16K code

- information block length k: 16384 bits (2048 bytes)

- code block length n: 32768 bits (4096 bytes)

 2/3 rate LDPC 1K code

- information block length k: 1024 bits (128 bytes)

- code block length n: 1536 bits (192 bytes)

 2/3 rate LDPC 4K code

- information block length k: 4096 bits (512 bytes)

- code block length n: 6144 bits (768 bytes)

LDPC 2/3 is not available without the optional Extension Board.

LDPC 1/2 is limited to 50 Mbps without the Extension Board.

3.4.10.4 Implementation
The LDPC decoder is implemented after a frame synchronizer and after the de-randomizer if the randomization is
used. The LDPC is a block decoder that can be synchronized to CADU processing and when it is, from this aspect
it is identical to the Turbo decoding and very close to the Reed Solomon decoding. The LDPC code can also be
asynchronous from the CADU (refer to § 1.6.1.7 Transport layer (RSDVB or asynchronous LDPC layer)).

 Any phase ambiguity at the output of the demodulation has to be resolved by the frame synchronizer
before the decoding

 The decoder uses soft decision at the output of the bit synchronizer

 If a de-randomizer is used, this one has to work on soft decision

The LDPC decoding is implemented as an iterative process with parity decoding.

In the HDR implementation, after the last iteration the parity control is processed one more time. This control is
able to detect bit errors before and after decoding. This allows to elaborate a BER estimation before and after the
decoding and also a quality indication “Good/Bad” of the decoded CADU.

In the Cortex HDR, the LDP decoder can be enable in the CADU layer or in the Transport Layer if this one is used.
The selection can be done from the GUI

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3.4.10.5 Performances
The following BER curves give the performances of the Cortex HDR in QPSK, OQPSK and 8PSK modulation
modes with LDPC 7/8. Curves are given for the following Bit rates: 150, 200 and 400 Mbps. Performance depends
on the number of iterations used by the LDPC decoding process and consequently depends on the Bit Rate
value. These BER curves can be compared with the given NASA CCSDS reference curve.

QPSK Modulation:

Ref Nasa 150M 400M

1,00E-01

1,00E-02

1,00E-03

1,00E-04

1,00E-05
BER

1,00E-06

1,00E-07

1,00E-08

1,00E-09

1,00E-10
3 3,2 3,4 3,6 3,8 4 4,2 4,4 4,6 4,8 5 5,2 5,4 5,6 5,8

Eb/N0 [dB]

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OQPSK Modulation:

Ref Nasa 150M 400M

1,00E-01

1,00E-02

1,00E-03

1,00E-04

1,00E-05
BER

1,00E-06

1,00E-07

1,00E-08

1,00E-09

1,00E-10
3 3,2 3,4 3,6 3,8 4 4,2 4,4 4,6 4,8 5 5,2 5,4 5,6 5,8

Eb/N0 [dB]

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8PSK Modulation:

LDPC decoder performance :8PSK 200 Mbps

1,00E+00

1,00E-01

1,00E-02

1,00E-03

1,00E-04
BER after 14 iterations
BER

BER Av
1,00E-05

1,00E-06

1,00E-07

1,00E-08

1,00E-09
6,0 6,5 7,0 7,5
En/N0(dB)

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The following table gives the performance of the LDPC decoder of the HDR, in term of Eb/No @ BER = 10-6
(QPSK mode). The performance is given here in function of the number of iterations of the decoding process.

DESIGN ITERATIONS EB/N0

NASA CCSDS 10 4,1
HDR (4 bit-input) 10 3.75
HDR 7 4.1
HDR 5 4.6
HDR 4 5.1

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3.4.11 Recording and Data Transmission over Ethernet

3.4.11.1 Data Storage
Data can be recorded internally on a hard disk or externally.

With the external data storage option, DAS RAID5 is supported as archiving system using an SCSI interface
(DR2912) or optical fibre interface (ER2912).

Example : DR2912-SA

The ZDS NTU 100272 document gives a description of the installation of the RAID system with the HDR-XXL.

In each case (internal or external) data recovery can be done by transferring files via an FTP server.

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3.4.11.2 TCP-IP Data Recovery

In TCP-IP mode, up to 6 clients can connect to the telemetry port (port # 3075) for receiving real-time or
recorded data. Connected clients must send a data request specifying :

 The data source (Data Processing Unit number : A, B or C),

 The message size (number of TM Blocks per TCP-IP message)

 The requested Virtual Channel(s), for CCSDS applications

 The first TM Block to transmit : first block in the HDR real-time buffer or TM block with specified time-tag
(real-time or recorded data).

Next figure illustrates the data formatting for real-time and recorded TM Messages. See Annex 1, STI
100013_HDR Section 2.6 for more details on the Ethernet interface.
Message preamble
& status

Recorded data playback

Real-time or recorded data to remote Ethernet Clients Real-time or recorded
Up to 131,072 TM Blocks per TM Message TM Block(s) Real-time data

Message postamble
RAM Buffers TM Message
X, Y & Z defined in DRG table # 1
FIFO-structured
(applies also to disk partitioning)
8 TM packets per buffer
Header (512-byte alignment)
TM Packet # 1 TM Block # 1 SW Frame…
TM Packet # 2 TM Block # 2
PC RAM Buffer
or raw data
for TM-A … …
(8-byte words + filler
… …
X%
… … Time-tag (8 bytes)

… TM Block # N Status (8 bytes)

TM Packet # 7 TM Packet = N x TM Blocks
Up to 8 optional
TM Packet # 8 N is computed from spare words
X% and frame size DRU table # 23
~ 1 Gbytes

PC RAM Buffer
TM Block :
for TM-B
TM Block size : up to 1,048,656 bytes
(DRU table # 35)
Y%
Frame size : up to 1,048,576 bytes
(DPU table # 3)

Free space
Z% Data storage in TM files on the hard disk
Number of TM packets per file : DRU table # 4

Figure 39 : Data Transmission over TCP-IP. Message Formatting

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3.4.11.3 Archiving and FTP Recovery

3.4.11.3.1 GENERALITY
3.4.11.3.1.1 OVERVIEW
The main objective of the functionality is to record the down-link data coming from a satellite during its successive
passes and to place them at the disposal of different Users.

The data are recorded at the frame level after the Reed-Solomon decoding if used (CADU). The data are recorded
on an external DAS archiving system connected with the CORTEX HDR unit.

Before being recorded, successive filtering and sorting operations can be applied on specific words inside the
incoming data frames in order to store into dedicated directories the frames which are useful for the Users.
Nevertheless the other frames are temporary recorded in a specific “trash” directory. These operations are fully
programmable and can be individually selected or not.

There are basically 6 successive filtering and sorting operations:

 RS filtering, allows to discard or not the Reed-Solomon code blocks declared as non corrected,

 Filter A,

 Sort A,

 Sort B,

 Sort C.

The filtered and sorted frames are recorded inside binary files. To be easily recovered by the Users, the binary
files are written inside specific dedicated directories of which tree construction and names are fully
programmable and are in relation with the successive filtering and sorting operations.

For each recording session, a pass report file is created. A the end of a recording session, the corresponding text
file provides information about the recorded data files. These report files are also placed at the disposal of the
Users in a dedicated directory.

The names of the files are automatically defined at the starting of a recording session. The names are divided into
several fields providing the start date of the recording session, specific markers and programmable characters
strings associated with the different filtering and sorting operations.

The HDR unit is fitted with a standard FTP server “FileZillaServer” and the users can recover the useful files from
the dedicated directories using a standard remote FTP client in a simple read operations.

The files storage durations are programmable and depend on the directory type: the directories containing useful
data files have a nominal storage duration and the “trash” directories have a temporary storage duration.

For the setting and operation of the functionality basically there are two steps. The first step is the static set-up and
it is done one time for the mission of the unit,. The static set-up consists in the definition of the partition of the
memory space for data and report directories, the definition of the rules to construct the dedicated directories and
the definition of the roots of the files names. A static set-up is defined inside a set of configuration files which are
text files, there can be several different sets of configuration files. The second step is the dynamic set-up and it is
done before a pass of a given satellite. It consists in selecting the filtering and sorting operations for the given
pass, its set of configuration files and if necessary the generation of the associated directories tree, in
programming fields to complete the construction of the files names, in giving a start and a stop dates for the
recording. This dynamic set-up is done through the TCP/IP Control TCP/IP port of the HDR unit. Detailed
instructions to program the functionality are given in the “Recording and FTP Recovery” User Manual DTU
100381.

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3.4.11.3.1.2 DATA FILES STRUCTURE

The recorded data files are binary files.

A data file contains a variable number of TM blocks.

The maximum number of TM blocks per file is defined by the current configuration of the CORTEX HDR. The
effective number of TM blocks per file can be less that the maximum only when the recording session is stopped.

TM Block 1 Telemetry Frame :

Synchronization Word
TM Block 2
& Data Words
(8 Bytes aligned)

… /…
Time Tag
(8 Bytes)

Status
(8 Bytes)

TM Block N Optionnal spare field

(0 to 8 words
of 8 Bytes)

Figure 40 : Recorded Data File Structure

When the frame synchronizer is disabled, the Status field is never included inside the TM blocks. On the other
hand and independently, the insertion of the Time Tag field can be disabled or not (it is a set-up parameter, refer
to the “Real Time” window in chapter 4).

For example, in order to record raw data without any added bytes inside the binary files, the following set-up
conditions must be satisfied:

1 - the frame synchronizer must be disabled

2 - the selected TM data block size must be set to N x 8 bytes (example: 1024 bytes)

3 - the insertion of the Time Tag must be disabled

4 – the number of added spare words must be set to 0.

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3.4.11.3.1.3 REPORT FILES STRUCTURE

The pass report files are ASCII files.

The CORTEX HDR generates a pass report file in the result passes directory. The name of the report file is
reconstructed as the TM file name, except for its extension.

There is one line per TM file in the ASCII report file. Each line is composed of 5 fields separated by ‘; ‘ .

The number of TM blocks in the file,

The number of TM blocks not corrected in the file,

The date of the first TM block in the file,

The date of the last TM block in the file,

The full path and name of the file.

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3.4.11.3.2 STANDARD FTP CCSDS MODE

The standard mode delivered with the FTP functionality is the sorting and storage of received CCSDS VCDU.

In this mode, 64 directories for the storage of the data are created (VC_00 to VC_63) per defined reception
channel. Each directory corresponds to a given VCID.

Only the Sort A operation is used (the other filtering and sorting operations are disable by set-up in the FTP
window). The Sort A operation consists in extracted from each received CADU its VCID and comparing it with the
different possible VCID values (from 0 up to 63), its operation is defined inside the configuration file:
SORT_A_0.txt. The VCDU are store inside dedicated files in their corresponding directories and put at the
disposal of remote Users using a FTP client software.

For each session a corresponding report file is generated included information on the recorded files. These files
are store in specific directories.

The created directories arborescence is given by the following figure:

DiskController_1_00
Directories for session report
Report_TMA files for TMA and TMB
1 report file per recording
session
Report_TMB

DiskController_1_01

VC_00

TMA
VC_01 Directories for the 64 VCID
+
Directory for unidentified VCID (>63)

VC_63

VC_XX

TMB
DiskController_1_02 (same structure as TMA)

Figure 41 : CCSDS FTP Mode Storage Directories

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The names of the recorded data files are defined by the SORT_A_0.txt configuration file and by the set-up in the
FTP window, an example of a file name is given below :

R_20070225093835_00001.TMI

File extension defined in the FTP

window set-up

Files number enable in the FTP

window set-up

Marker for VCID 0, defined in the

SORT A configuration file and enable
in the FTP window set-up

Date of the creation of the file (default name)

Read / Write indicator:

W_ : the file is currently being writing
R_ : the file is available and can be get
Marker enable in the FTP window set-up

The contents of the data files are defined in the paragraph 3.4.6.4.1.2.

The names of the session report files are defined by the set-up in the FTP window :

R_20070225093835.TXT

Report File extension defined in the

FTP window set-up

Date of the creation of the file (default name)

Read / Write indicator:

W_ : the file is currently being writing
R_ : the file is available and can be get
Marker enable in the FTP window set-up

The contents of the session report files are defined in the paragraph 3.4.6.41.3.

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3.4.11.3.3 FTP USER DEFINED MODE

The FTP functionality is fully programmable and open device: filtering and sorting operations, directories
arborescence and names of the files. The previously described standard CCSDS mode is a simple example from
which a number of more complex modes can be constructed.

For detailed explanation on how to program and operate the FTP functionality refer to the “Recording and FTP
Recovery” User Manual DTU 100381.

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3.4.12 Playback function

3.4.12.1 Operating Modes
The Cortex HDR provides two different operating modes for the Playback function:

 Replay of data using the Test Modulator (Test Modulator mode). In this case the data are sent to the Test
Modulator for modulation and re-transmission at the IF level (720 MHz or 1.2 GHz). The data can be
demodulated by the Demodulators just as in real time reception.

Figure 42 : Playback function : Test Modulator operating mode

 Replay of data at the ECL outputs (Data + Clock mode). In this case the data are sent directly to the ECL
outputs of the selected demodulator(s) in the selected output format. The Test Modulator is not used nor
the demodulation function of the Demodulators.

Figure 43 : Playback function : Test Modulator Data + Clock mode

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3.4.12.2 Sources of the data to replay

The data to be replayed can be provided from files coming from different sources:

 Recorded data by the Cortex HDR itself during a pass of a satellite (Report TM mode)

 Files containing User data

 PRN data or data from simulation files (BER analysis)

In the first case, all the data contained inside files recorded during a pass of a satellite and corresponding to a
report are replayed in the chronological order. It is also possible to select only one specific file of a selected report.

In the second mode (User Data), in order to be easily selected from the Playback Window, the data files must be
written in a sub-directory called “PLAYBACK” in a selected recording partition (example: TMA, TMB,… refer to the
recording section). The files can be written directly in this directory, then it is necessary to change their names by
1, 2, 3 …. or inside sub-directories , in this second case the names of the subdirectories have to be named: 1, 2,
3…The format of the User files must be compatible with the standard HDR files, i.e. binary files.

During the playback, the recording function can be used simultaneously.

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3.4.13 Multi-DPU processing

3.4.13.1 Generality
The Cortex HDR provides the multi-DPU (Data Processing Unit) capabilities.

The multi-DPU capabilities (4 DPU or 8 DPU) are license dependent.

The multi-DPU functionalities are implemented inside a specific demodulator menu (menu 52) and a
specific test modulator menu (menu 5), which can be configured by parameters setting.

Basically this menu supports the following configurations described in the following figures:

- One channel QPSK demodulation with 2 DPU connected to the demodulator outputs (DPU A and
DPU C)

- One channel QPSK or 16QAM demodulation with 4 DPU connected to the demodulator outputs
(DPU A, DPU C, DPU E and DPU G)

- One channel 16QAM demodulation with 8 DPU connected to the demodulator outputs (DPU A, DPU
B, DPU C, DPU D, DPU E, DPU F, DPU G and DPU H)

- One channel QPSK or 16QAM demodulation with 1 DPU (DPU A) connected to the demodulator
merged output, essentially used for BER measurement purpose

For each configuration, the input is done at 720 MHz IF level, the demodulated and processed data at the
output of each DPU can be recorded inside the internal hard disks of the unit (1 Terra Bytes available). The
data can be recovered using FTP.

For each possible configuration, the test modulator can provide:

- the symmetrical functions as described in the following figures

- or a single data channel test modulation as described in the last figure

The differential decoding is a NRZ-M to NRZ-L decoding

Each DPU (data processing Unit) consists in the following CCSDS compliant functions:
- a frame synchronizer

- a de-randomizer

- a Reed Solomon RS(223,255) decoder with supported interleaving and virtual filling
- a VCDU detector

The total internal recording capability (internal Hard disks) is 1 Terra Bytes.

In the different configurations, each function (differential coder/decoder, randomiser/de-randomiser, CCSDS

encoder/decoder can be enabled or disabled.

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Figure 44 : QPSK demodulation with 2 DPU

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Figure 45 : QPSK or 16QAM demodulation with 4 DPU

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Figure 46 : 16QAM demodulation with 8 DPU

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Figure 47 : QPSK or 16QAM demodulation with 1 DPU

Figure 48 : QPSK demodulation with 2 DPU

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3.4.13.2 Ambiguity resolution by the DPUs

The ambiguity resolution is done by a specific process consisting in analysing the timing of the received CADU at
the input of the DPUs and allowing a feed-back towards the DMU to route the data flows to the right DPUs. For
that, The DPUs expect to receive the CADUs with a specific arrangement.

For example with the 16 QAM – 8 DPU mode, the received data flows at the inputs of the DPUs is given in the
following figure. An offset of 1 byte is inserted between the successive CADUs.

Figure 49 : 8 DPU Data Flow for automatic ambiguity resolution

An identical mechanism is implemented for the QPSK – 4 DPU mode and the QPSK – 2 DPU mode.

The following tables gives the correspondence between the offsets and the DPUs for the different modes. For
each mode, two mapping are today available and selectable from the GUI (parameter: DPU Map in the DPU
CADU window).

16QAM – 8 DPU, DPU Map = 0

Bit number odd-b1 even-b1 odd-b2 even-b2 odd-b3 even-b3 odd-b4 even-b4
DPU-X DPU-A DPU-C DPU-E DPU-G DPU-B DPU-D DPU-F DPU-H
Offset (bytes) 0 1 2 3 4 5 6 7

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16QAM – 8 DPU, DPU Map = 1

Bit number odd-b1 odd-b3 even-b1 even-b3 odd-b2 odd-b4 even-b2 even-b4
DPU-X DPU-A DPU-C DPU-E DPU-G DPU-B DPU-D DPU-F DPU-H
Offset (bytes) 0 4 1 5 2 6 3 7

QPSK – 4 DPU, DPU Map = 0

Bit number odd-b1 even-b1 odd-b2* even-b2*

DPU-X DPU-A DPU-C DPU-E DPU-G
Offset (bytes) 0 1 2 3

QPSK – 4 DPU, DPU Map = 1

Bit number odd-b1 odd-b2 even-b1 even-b2

DPU-X DPU-A DPU-C DPU-E DPU-G
Offset (bytes) 0 4 1 5

QPSK – 2 DPU, DPU Map = 0 (No ambiguity resolution process)

Bit number b1 b2
DPU-X DPU-A DPU-C
Offset (bytes) N/A N/A

QPSK – 2 DPU, DPU Map = 1

Bit number b1 b2
DPU-X DPU-A DPU-C
Offset (bytes) 0 4

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3.4.13.3 BER measurements

The BER can be done at the DMU (Demodulator Unit) outputs and at each DPU (Data Processing) output. The
BER can be done at different levels inside the DPU by enabling or not the different operations (Differential
encoder/decoder, Frame synchronizer, CCSDS encoder/decoder).

3.4.13.4 Data output

Data at the output of each DPU can be recorded in specific directories of the internal hard disk named “T” or/and
output at the ECL connectors as a single data stream with its clock.

The recording directories architecture is the following:

The report files are recorded in:

T:\DiskController_1_00\Report_TMA for DPU A

T:\DiskController_1_00\Report_TMB for DPU B

T:\DiskController_1_00\Report_TMC for DPU C

T:\DiskController_1_00\Report_TMD for DPU D

T:\DiskController_1_00\Report_TME for DPU E

T:\DiskController_1_00\Report_TMF for DPU F

T:\DiskController_1_00\Report_TMG for DPU G

T:\DiskController_1_00\Report_TMH for DPU H

The data files are recorded in:

T:\DiskController_1_01\.... for DPU A

T:\DiskController_1_03\.... for DPU C

T:\DiskController_1_05\.... for DPU E

T:\DiskController_1_07\.... for DPU G

T:\DiskController_1_02\.... for DPU B

T:\DiskController_1_04\.... for DPU D

T:\DiskController_1_06\.... for DPU F

T:\DiskController_1_08\.... for DPU H

If the CCSDS Virtual Channel sorting is disabled (TFP window), the data files are recorded inside the sub-
directories CV_XX of each directory.

If the CCSDS Virtual Channel sorting is enabled, the data files are recorded inside the specific sub-
directories: CV_NN with NN = 00 to 63 being the Virtual Channel ID number.
Multi-DPU outputs on ECL connectors are described in chapter 2.

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3.4.13.5 Guide for multi DPU Operation

CONFIGURATION

The Configuration window allows to mount and connect up to 8 DPU (Data Processing Unit) with the DMU
(Demodulation Unit A).

From the following windows examples it can be seen that the hardware menu (FPGA basic menu) number is 5 for
the test modulator and 16 for the demodulator. These menus support the multi-DPU processing.

In the following first example, the 8 DPU and associated 8 DRU (Data Recording Unit) are enabled. This selection
corresponds to the 16QAM – 8DPU configuration.

16QAM – 8DPU Configuration

In the following second example, 4 DPU and associated 4 DRU are enabled. This selection corresponds to the
QPSK or 16QAM – 4DPU configuration.

Remark that with the 4 DPU configuration, must be selected : DPU and DRU A, C, E and G.

For the standard QPSK- 2 DPU configuration, must be selected only DPU and DRU A and C .

Only one DMU (DMU A) is available with this demodulator hardware menu number 16.

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QPSK– 4DPU Configuration

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DEMODULATION UNIT

The demodulation function contains a specific feature, this is at this point of the data processing chain that the
data flow is arranged in order to meet the 8 bits symbol shift special feature for ambiguity resolution purpose. To
properly work it receives the frame synchronisation signals from the “Frame Sync”. This way it can reorder bits to
route the right channel to the right DPU.

The configuration field in the MCS is the I/Q Polarity filed. If the used configuration used is 16QAM, 8 channels we
must select the “Ambig 8DPU” item, if the used configuration used is QPSK 4 channels we must select the
“Ambig 4DPU” item and if the used configuration used is QPSK 2channels we must select the “Ambig DPUA+C”
item.

The setting of the demodulator for the 16QAM 8 DPU mode is the following:

The setting of the demodulator for the QPSK 4 DPU mode is the following:

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The setting of the demodulator for the QPSK 2 DPU mode is the following:

Remark 1: The ambiguity resolution for multi DPU works only if all of the concerned channels are valid (e.g. the 2,
4 or 8 Frame sync are locked), if one of these channels becomes and stays unlocked during equivalent time of 15
frames, the ambiguity resolution state machine will consider itself in a bad ambiguity resolution state and then will
search for a new one. As a result, if one of the channels does not work broken for any reason, it will impact all the
channels.

Remark 2: The mode “8DPU Ambig” does work only for 16 QAM’s mapping : map 2.

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DATA PROCESSING UNIT

For each DPU, a specific parameter (Input Selection) must be set. The role of this parameter is to split the data
flow coming from the demodulator and depending on the DPU configuration. This is at this stage that the data flow
is split in 2, 4 or 8 depending on the configuration needed.

The configuration fields in the MCS are those corresponding to “Input selection” section.

The NRZ-M to NRZ-L decoding function is activated in the MCS by ticking the “NRZM DPU” field.

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BER TESTER

It is possible to perform BER testing at the output of each DPU.

The PRN tester has been added at the DPU level. It can be configured via the MCS “Operating mode” field:

- Possibility to test an inverse PRN has been added too (it is done by inverse the binary flow before the PRN
tester). It can be configured via the MCS “Inverse” field.

- Possibility to test whole data or only user data has been added. “Whole data” consists in the entire data flow with
the Synchronization word and the RS parity bytes. “User data” excludes synchronization word and RS parity
bytes. It can be configured by the field “Tested Data”.

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TEST MODULATOR

The test modulation function provides the possibility to select: 1, 2, 4 or 8 parallel data processing channels. This
selection is controlled by the MCS field “Parallel Channels” in the “PCM” window of the test demodulator.

For “2 Data Units”, ” 4 Data Units” and “8 data Units” selections, the generated data frames are delayed by one
byte from on unit to the other an following the rules described earlier.

The “Inverse Data” selection allows to inverse the data to be modulated.

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A registry key must be set

The path of the registry is:

HKEY_LOCAL_MACHINE\SOFTWARE\IN-SNEC\CrtxHdr\SetDefault\Signal Processing\Tstu

The keys to set are:

DpuOffset2=0x40
DpuOffset4=0x5140
DpuOffset8=0x75316420

The signification of this Registry is the following:

Mode 16QAM/ 8 DPU:

o-b1 = TSTU Ch#1 = offset 0 byte,
o-b2 = TSTU Ch#2 = offset 2 bytes,
o-b3 = TSTU Ch#3 = offset 4 bytes,
o-b4 = TSTU Ch#4 = offset 6 bytes,
e-b1 = TSTU Ch#5 = offset 1 byte,
e-b2 = TSTU Ch#6 = offset 3 bytes,
e-b3 = TSTU Ch#7 = offset 5 bytes,
e-b4 = TSTU Ch#8 = offset 7 bytes.

Mode QPSK / 4 DPU:

o-b1 = TSTU Ch#1 = offset 0 byte,
o-b3 = TSTU Ch#2 = offset 4 bytes,
e-b1 = TSTU Ch#3 = offset 1 byte,
e-b3 = TSTU Ch#4 = offset 5 bytes.

Mode QPSK / 2 DPU:

b1 = TSTU Ch#1 = offset 0 byte,
b3 = TSTU Ch#3 = offset 4 bytes,

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The test modulator NRZ-M encoding function is a specific feature. It is controlled by ticking the NRZM-DPU
selection field on the encoding page of the modulator unit.

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Access to specific parameters of the test data:

To access and set the PN generators of the test modulator for each Data Unit as some other parameters at the
“engineering level”, there are two possibilities:

1 - Access by Windows Registry Keys

2 - Access using the uihm tool (Also named HDR debug MMI)

The uihm tool (HDR debug MMI) is a software integrated inside the HDR and can be started and operated from
the screen of the HDR. This tool connects the HDR software (SPS) and allows through specific windows the User
to monitor and control some specific internal parameters as the setting of the PN generator.

To start uihm, double click on “uihm.exe” in C:/Program Files/IN-SNEC/uihm. A first window will appear. Click on
“Connect” (to connect the interfaces between uihm and the SPS). Then select the folder “Parameters”. Two
buttons are dedicated to the control of the channels of the test modulator. They are: MODRG1 and MODST1.

The first button MODRG1 (see the following figure) allows the User to change parameters which are also in
registry (Sync Word and Pseudo generator initial values) independently on each channel. The first parameter
(DPU Offset) allows the user to define the Sync Word offset (in bytes) between each channel. The values are (0
for 1 byte offset, 1 for 2, 2 for 3… and –1 for 0). For example, as per MELCO specification this field must contain 0
which correspond to an offset of one byte between each channel.

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Remark 1: the number of bits used to initialize the PRN generator depends on the PRN type, the bits used are in
any case the LSB.

Remark 2: the size (in bytes) of the Sync Word depends on the corresponding STI parameter, the bytes used if the
size is less than 8 bytes are the MSB.

Remark 3: the default values of these parameters can be configured directly in registry.

/HKEY_LOCAL_MACHINE/SOFTWARE/IN-SNEC/CrtxHdr/SetDefault/SignalProcessing/Tstu

"PRN1" to "PRN8"= dword:11111111

"SW1" to "SW8”

"DpuOffset"

The second button: MODST (see the following figure) allows the User to configure parameters which are defined
in STI (SW size, operating mode, file number, file size, block code) independently (refer to the STI documents). If
we want to command these parameters via the debug windows we must first disable STI, this is done by setting
the first field to 1.

The precise description of each field is defined in STI document (STI10013 HDR).

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3.5 POLARIZATION COMBINING

3.5.1 General
The CORTEX HDR allows to combine two IF signals from different polarizations in post-detection mode. Two
combining modes are available:

- Automatic selection of the best channel

- Combining of the two channels, through optimal weighting. In this case up to 3 dB gain can be achieved
when both signals have the same Eb/N0.

The combining system, also named Diversity Combining Unit (DCU), receives data from two demodulators. It
resolves phase ambiguity between the two channels, and deals with the different locking states possible. Its output
feeds a FEC device, followed by a Format Output.

Note : Only DMU1 and DMU3 can be combined in the HDR-XXL.

3.5.2 Data Path

When active, the combining system output is routed to the FEC input of the first demodulator while the data path of
second demodulator remains unchanged.

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Three choices are possible concerning the output routing:

- m = 100 %, n = 0 % : channel A is directly routed to the output. No combining is performed.

- m = 0 %, n = 100 % : channel B is directly routed to the output. No combining is performed.

- m and n are dynamically adjusted by the combining system. This is described in the “Signal processing”
section.

3.5.3 Signal Processing

When both channels are locked, the combining system identifies and compensate the relative phase ambiguity
before combining. The supported modulations are QPSK, OQPSK and 8PSK.

Two combining modes exist :

- Best channel: only the signal of the channel with the best Eb/N0 is fed through the combining system.

- Combining: signals of both channels are combined using optimal weighting. In this case, the combining
gain versus the best channel is :

EbN 
0
 
 Eb
(dB)combining N0 (dB)best_ channel
10Log10 110 Level(dBm) worst _ channel Level(dBm)best _ channel
10 

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The relative amplitude of a channel (A or B) is given by :

Amplitude _Channel
x100
Amplidude _Channel _ A Amplitude _Channel _ B

The sum of the relative signal amplitudes is 100. The best case (3-dB gain) is achieved when both IF Receivers
are locked onto equal-strength signals.

Moreover, the system can be in different states :

- N/A if Channel A or Channel B has been chosen as output of the DCU.

- Unlocked if the output is set to combining, and both demodulators are unlocked.

- Single channel if only one demodulator is locked.

- Acquisition if both demodulators are locked, and the system searches for a fit between both signals. The
system identifies the differential ambiguity between both signals.

- Locked if combining is performed normally.

- Check if the system verifies the differential ambiguity found during the acquisition phase. This happens
when the observed combining gain is lower than the theory by more than 0.3dB. This is also the normal
working state when “Best channel” mode is selected.

Specific attention should be paid to the following points otherwise warnings will be issued :

- modulations must be identical, and must be one of the following : QPSK, OQPSK, 8PSK.

- bitrates must be identical.

- PCM codes must be identical.

- IF inputs must be different (no gain can be achieved with the same signal feeding both inputs).

- Configuration of matched filters must be identical (data paths before the DCU must be equivalent).

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3.6 TEST MODULATION

The Test Modulator allows to test the carrier acquisition, demodulation and decoding processes :

Functional tests Telemetry reception and processing without noise (IF demodulation, bit synchronization, BER
measurement).

BER tests BER measurement in the presence of noise. Bit-by-bit comparison of the simulated PCM to
the regenerated PCM from the bit synchronizer (File mode or pseudo random mode).

3.6.1 IF Signal Generation

The following characteristics of the simulated telemetry signal can be configured :

 Carrier frequency and level. Carrier ON/OFF. Modulation ON/OFF.

 PCM data : bit rate, PCM code.

 Noise conditions (programmable Eb/No). Noise generator ON/OFF.

Note : the signal-to-noise ratio (Eb/No) can be computed from the following formula :

Eb/No = C_carrier – C_noise – 10 Log10 (BitRate)

Where :
C_carrier : carrier level (in dBm)

C_noise : noise level in a 1-Hz bandwidth (in dBm/Hz)

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3.6.2 PCM Generation

Three PCM data sources are available :

 Pseudo-random data (for BER testing),

 Data from hexadecimal-coded files on the hard disk,

 External data (PCM + clock).

3.6.2.1 Pseudo Random Data

Four PRN generators (Pseudo Random Noise) providing pseudo-random bit sequences of programmable length
and period can be selected for BER analysis. Data sequences are sequences of maximum length which are
generated by means of feedback shift registers.

Example : 10-bit generator with feedbacks after register 3 and 0 :

9 8 7 6 5 4 3 2 1 0

PRN10 data

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Next table describes all PRN generators available :

PRN LENGTH IN BITS FEEDBACK AFTER COMMENTS

GENERATORS

PRN 7 27- 1 = 1027 Register 1, 0

PRN 10 210- 1 = 1023 Register 3, 0

PRN 11 211- 1 = 2047 Register 2, 0

PRN 15 215- 1 = 32767 Register 1, 0 PRN 15 is configured according

to CCITT Rec. 0.151/152/153

PRN 23 223- 1 = 8388607 Register 5, 0 PRN 23 is configured according

to CCITT Rec. 0.151/152/153

PRN 31 231- 1 = 2147483647 Register 3, 0

Table 15 : PRN Generator for BER Analysis

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3.6.2.2 PCM Simulation from File

3.6.2.2.1 FILE FORMAT

PCM data can be retrieved from files on the disk. Files are hexadecimal-coded and can be edited using Notepad
or any other text editor. Access path to the simulated telemetry files is :

C:\Program Files\In-snec\crtxnt\BER

3.6.2.2.2 CYCLE LENGTH

Parameter Cycle Length specifies which part of the file must be modulated. It can be set to any value from 32 to
2,097,152 bytes

3.6.2.3 PCM Simulation from External Data & Clock

Ensure the data & clock timing comply to the CORTEX HDR requirements (see Section 1.6.5).

Data-to-clock timing requirements :

- Square 180° clock

- 50% duty cycle (worst case : 45/55)

- Tset_time < 1 ns

- Thold_time < 0.6 ns

Because this clock signal is directly used by the modulator, the phase jitter should be as low as possible (<  1 ns).
One recommends to connect the input clock before selecting the External Data mode. In this mode, the external
clock must be permanently provided.

In UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, the external data stream is supposed to be I Channel (Q
Channel is generated by the internal Test Modulator)

Warning : In the External Mode, the programmed bit rate on the Test Modulator must be the addition of the bit
rates on I & Q Channels (QPSK, OQPSK). This number must be multiplied by 2 if data are convolutionaly encoded
by the Test Modulator.

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3.6.2.4 Constellation Mapping

In QPSK mode, two mapping are supported :

01 00 10 00

11 10 11 01

Normal mapping Inverse mapping

(counter clock-wise) (clock-wise)

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In 8PSK, the following mapping are supported :

Q Q Q Q
First bit
111 101 111 101 111 011 111 110

110 100 011 001 101 001 101 100

I I I I

010 000 010 000 100 000 001 000

011 001 110 100 110 010 011 010

CCSDS Gray 1 CCSDS Gray 2 CCSDS Gray 3 CCSDS Gray 4

Q Q Q Q

111 011 111 110 101 110 101 011

110 010 011 010 100 111 001 111

I I I I

100 000 001 000 011 000 110 000

101 001 101 100 010 001 010 100

CCSDS Gray 5 CCSDS Gray 6 CCSDS Natural 1 CCSDS Natural 2

Q Q Q Q
First bit
011 001 110 100 110 010 011 010

010 10. C 000

I
010 3. C 000
I
100 4. C 000
I
001 5. C 000
I

110 100 011 001 101 001 101 100

111 C 101 111 C

101 111 C
011 111 C
110

Inverted Gray 1 Inverted Gray 2 Inverted Gray 3 Inverted Gray 4

101
Q
001 101
Q
S 100 010
S Q
001 010
S Q
100

100 6. C 000
I
001 7. C 000
I
011 8. C 000
I
110 9. C 000
I

110 010 011 D 010 100 D 111 001 D 111

111 C
011 111 C 110 101 CS 110 101 CS 011

Inverted Gray 5
S
Inverted Gray 6
S
Inverted Natural 1
S
Inverted Natural 2

S S DS DS
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DI 13.
DI 15. I
NA 12.
NAI
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In 16QAM, the following mappings are supported :

Q Q Q

B 9 1 3 2 6 E A 2 3 1 0

A 8 0 2 3 7 F B A B 9 8

E C 4 6 1 5 D 9 E F D C

F D 5 7 0 4 C 8 6 7 5 4

16 QAM mapping 1 (Hexa) 16 QAM mapping 2 (Hexa) 16 QAM mapping 3 (Hexa)

In 16APSK, the following mappings are supported :

Q MSB
LSB
0111 0011

19. I 0100
0110
20. I
0101
R2

0001
0010

0000
R1 F = p/4 F =p/12 I

1100 1101 1001 1000

1110 1010
1111 1011

16 APSK mapping 1 16 APSK mapping 2

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In 32APSK, the following mapping is supported :

In 64APSK, the following mapping is supported :

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3.7 SYSTEM BER VS EB/NO

This section provides information on how to evaluate the system link performances in term of Bit Error Rate (BER).

3.7.1 Theoretical Probability of Bit Error

Theoretical probability of bit error versus Eb/No is given by the following curves, in case of :

 No PCM coding (NRZ-L) or differential coding (NRZ-M or S, DNRZ) (see Figure 50).

 Convolutional coding possibly combined with PCM coding (see Figure 51).

 Reed-Solomon coding possibly combined with convolutional coding (see Figure 52).

 8PSK with or without 4D-TCM and R-S coding (See Figure 53)

 GMSK (see Figure 54)

Probability of bit error versus Eb/N0

0
10

<---------------- NRZ-L or BP-L

-2
10

<----- NRZ-M or DQPSK

-4
10

-6
10

-8
10
0 2 4 6 8 10 12
10log(Eb/N0) (dB)

Figure 50 : Probability of Bit Error vs Eb/No for Different PCM Codes

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Probability of bit error versus Eb/N0 for various coding techniques

-2
10

<-VITERBI
-4 <- NRZ-L
10

<- NRZ-M or DNRZ

-6
10

-8
10

<-VITERBI+NRZ-M
-10
10

2 3 4 5 6 7 8 9 10 11 12
10log(Eb/N0) (dB)

Figure 51 : Probability of Bit Error vs Eb/No with convolutional Coding (rate: 1/2)

-1
10

-2
10

-3 <- RS
10

<-VITERBI
-4 <- no code (NRZ-L or BP-L)
10

-5
10

-6
10

-7
10

-8
10
<-VITERBI+RS

-9
10

-10
10
0 2 4 6 8 10 12 14
10log(Eb/N0) (dB)

Figure 52 : Probability of Bit Error vs Eb/No with Reed-Solomon Coding

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8PSK (th) 4D-8PSK-TCM (th)

8PSK-4D-TCM-RS-DVB (th) 8PSK (ty)
4D-8PSK-TCM (ty) 8PSK-4D-TCM-RS-DVB (ty)
1,E-01

1,E-02

1,E-03

1,E-04
BER

1,E-05

1,E-06

1,E-07

1,E-08

1,E-09
4 5 6 7 8 9 10
EbNo

Figure 53 : Probability of Bit Error vs Eb/No in 8PSK Mode with or at 2,5 bit/symbol

1,E-01

1,E-02

1,E-03

1,E-04

1,E-05
BER

1,E-06
4D-TCM-RS 2.5b/Hz (th)
1,E-07
4D-TCM-RS 2.5b/Hz (ty)
1,E-08

1,E-09

1,E-10
5,5 5,7 5,9 6,1 6,3 6,5 6,7 6,9 7,1 7,3
Eb/No

(th = theoretical degradation. Ty = typical degradation values for the CORTEX HDR)

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NRZ-L GMSK 0,5 GMSK 0,25

1,0E+00

1,0E-01

1,0E-02

1,0E-03
BER

1,0E-04

1,0E-05

1,0E-06

1,0E-07

1,0E-08
-2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Eb/No

Figure 54: Probability of Bit Error vs Eb/No with GMSK

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Theoric 16QAM 800 Mbps

1,00E-01

1,00E-02

1,00E-03
ber

1,00E-04

1,00E-05

1,00E-06

1,00E-07
8 9 10 11 12 13 14 15 16
EB/N0

Figure 55: Probability of Bit Error vs Eb/No with 16QAM and RS decoding (800 Mbps)

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3.7.2 Eb/No vs C/No at Demodulator Input

Depending on the selected modulation scheme (modulation type & data bit rate), the theoretical Eb/No value is
computed differently from the carrier to noise ratio (C/No) at the Demodulator input :

 BPSK : Eb/No = C/No - 10 log BR

 QPSK, OQPSK (SQPSK) : Eb/No = C/No - 10 log BR

 UQPSK (for I Channel) : Eb/No = C/No - Q_Power - 10 log I_BR

Where : BR : data Bit Rate

C/No : Carrier to Noise ratio in a 1-Hz bandwidth

Q_Power : Q Channel power

I_BR : data Bit Rate on I Channel

Note : When convolutional encoding is used, Eb/No (Eb : energy per information bit) should be computed from the
above formula, using as BR value the information bit rate (For convolutionally encoded data (rate ½), the effective
data bit rate on the RF downlink is twice the information bit rate).

3.7.3 Some System Examples

-6
Hereafter are some examples of link budget computation (C/No required for a targeted BER of 10 ) for
several in-orbit satellites :

3.7.3.1.1 PROCEDURE

 Step 1 :

 From the type of modulation and PCM coding, select the appropriate BER curve in section 3.7.1.

 Compute the theoretical Eb/No for a BER of 10-6.

 Step 2 :

 Calculate the effective required Eb/No :

Effective Eb/No = Theoretical Eb/No + Implementation Loss (in dB)

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Important :

In case there is no convolutional or R-S coding, the effective BER on the transmission link corresponds to
the system BER.

If convolutional or R-S coding is used, the effective BER on the transmission link is higher than the
system BER. In this case, to obtain the implementation loss, the transmission link effective BER should
be considered, and not the targeted BER.

Typically, a targeted BER of 10-6 after Viterbi decoding corresponds to an effective BER of 10 -2 on the
transmission link (see Figure 51 : Probability of Bit Error vs Eb/No with convolutional Coding).

 Step 3 :

 From the effective Eb/No and the system configuration parameters, calculate the required C/No (see
formulas in Section 3.7.2).

3.7.4 Examples
 RADARSAT :

System Configuration :

 QPSK modulation

 Bit Rate : 105 Mbps (10 log BR = 80.2 dB)

 D-NRZ

 No convolutional coding, no Reed-Solomon coding

Minimal C/No required :

 Theoretical Eb/No = 10.8 dB

 Implementation loss = 1 dB

 Effective Eb/No = 11.8 dB

Required C/No : 92 dB.Hz

 NPP :
System Configuration :

 SQPSK modulation

 Bit Rate : 300 Mbps (10 log BR = 84.77 dB)

 NRZ-M coding, Reed-Solomon coding

Minimal C/No required :

 Theoretical Eb/No = 6 dB

 Implementation loss = 1 dB (at effective BER around 10-2)

 Effective Eb/No = 7 dB

Required C/No : 91.77 dB.Hz

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 CORRIOLIS :
System Configuration :

 SQPSK modulation

 Encoded Bit Rate (Viterbi decoder input) : 102.4 Mbps

 NRZ-M coding

 Convolutional coding (rate ½)

 Information Bit Rate (Viterbi decoder output) : 51.2 Mbps (10 log BR = 77.1 dB)

Minimal C/No required :

 Theoretical Eb/No = 5 dB

 Implementation loss = 1dB (at effective BER around 10-2)

 Effective Eb/No = 6 dB

Required C/No : 83.1 dB.Hz

 TERRA :

System Configuration :

 UQPSK modulation

 Encoded Bit Rate I : 26.25 Mbps

 NRZ-M coding

 Convolutional coding (rate ½)

 Information Bit Rate : 13.125 Mbps (10 log BR = 71.2 dB)

Minimal C/No required :

 Theoretical Eb/No = 5 dB

 Implementation loss = 1dB (at effective BER around 10-2)

 Effective Eb/No = 6 dB

 Q_Power = 1.2 dB

Required C/No : 78.4 dB.Hz

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3.8 CABLE EQUALIZER FILTER

The purpose of the optional cable equalizer filter is to compensate for cable degradation by means of a digital
equalizer integrated to the receiver. Analog equalizers are commonly used to solve this problem, however a digital
implementation offers the following advantages :

 More flexibility,

 Higher performances.

The primary cause of transmission loss below 1 GHz is skin effect, which is proportional to the square root of
frequency :

Amplitude Loss (dB) = A * sqrt (frequency)

Figure 56 : Example of Non-linearity in a RG188A/U Cable

Since this type of non-linearity is almost linear between 500 MHz and 1 GHz (above figure), it can be well
compensated by a straight line with opposite rope of the tangent.

The sampled signal is filtered before baseband transposition. By this way, a symmetrical low-pass filter can be
implemented :

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Main features of this low-pass filter are :

 Fully programmable solution : the gain slope defined by the amplitude difference between the
transmission at 570 MHz and 870 MHz. This gain slope can be locally or remotely programmed
between 0 to 12 dB.

 Gain compensation performance in the bandwidth better than 0.1dB (see Figure 56)

 Intrinsic phase linearity performance.

960 MHz 860 MHz 760 MHz 660 MHz 560 MHz

Figure 57 : Example of Compensation - Symbol Rate = 150 Mbps

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3.9 DATA LOGGING

The HDR XXL provides capacities to record inside logging text files, for each mounted TM channel, lists of pre-
defined control parameters and/or status and their corresponding values. The recording can be periodical, on
transition of a parameter/status value or on variation of a parameter/status value versus a pre-defined threshold.
All the control parameters or status of the HDR-XXL can be recorded.

The logging files are recorded inside the following directories:

C:\Program files\IN-SNEC\log\param_surv\TMx

with x equal A, B, C or D for TMA, TMB, TMC or TMD.

The names of the logging files are defined by the type of recording (periodic, transition or variation) associated
with a configuration file number N (0 to 100):

periodic_logN.txt

transition_logN.txt

variation_logN.txt

These files contain the date of the recording, the label of the parameters to log and their corresponding values.
They can be edited with “Notepad”.

The following listing gives an example of the contains of a generated periodic_log0.tx file:

………………………………………..

SURVTMA(date,IFLevel_A,eb_n0_A,bitSync_A,frameSync_A);7671.678239;-20.0;25.8;1=Locked;2=Locked

SURVTMA(date,IFLevel_A,eb_n0_A,bitSync_A,frameSync_A);7672.188597;-20.1;25.8;1=Locked;2=Locked

SURVTMA(date,IFLevel_A,eb_n0_A,bitSync_A,frameSync_A);7672.689086;-20.0;25.7;1=Locked;2=Locked

SURVTMA(date,IFLevel_A,eb_n0_A,bitSync_A,frameSync_A);7673.204423;-20.0;25.7;1=Locked;2=Locked

SURVTMA(date,IFLevel_A,eb_n0_A,bitSync_A,frameSync_A);7673.719847;-20.1;25.7;1=Locked;2=Locked

…………………………………………..

In this example, have been periodically recorded for TMA the values of the IF level (label: IFLevel_A), Eb/N0
(label: eb_n0_A), the status of the bit synchronizer (label: bitSync_A), the status of the frame synchronizer (label:
frameSync_A).

The rules for the recording are defined inside text files named: spyconfN.txt recorded in the following directories:

C:\Program files\IN-SNEC\log\param_surv\conf\TMx

with x = A, B, C or D and N the configuration file number.

A specific window allows the user to build this control file: definition of the control parameters/status to record,
labels of these parameters, occurrence of the recording or thresholds.

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4. OPERATING MANUAL

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4.1 STARTING AND CONFIGURING THE CORTEX HDR

4.1.1 First Steps
4.1.1.1 Starting the PC Workstation
1. Verify that the CORTEX HDR has not been damaged during transportation. If needed, open the top cover and
verify that the electronic sub-assemblies are in good condition.

2. Check that the CORTEX HDR chassis is properly grounded and connected to the AC power via the appropriate
power cord.

3. Switch on the chassis (ON/OFF switch is at the rear panel). Allow 8 to 10 seconds for the power supply to start.

4. At the front panel display, follow the boot-up sequence. Depending on the Autolog setting (ON or OFF),
manual intervention may be required (type Ctrl + Alt + Delete, then enter the login password). Default password
at delivery is cortex. Default Autolog setting at delivery : ON.

4.1.1.2 Signal Processing Software. Start-up Menu

At the end of the boot-up sequence, the Signal Processing Software (SPS) is automatically started.

If the Demodulator board is present, the following SPS icon appears at the lower right corner of the screen :

If the board is not mounted or in the case of a major hardware problem, the following message is displayed :

4.1.1.3 Starting the Monitoring & Control Software

Once the Signal Processing software is running, the Monitoring & Control software is automatically started. If
needed, connect the MCS to the SPS for starting the GUI.

A detailed description of the Graphical User Interface is given in the next sections.

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4.1.2 Factory Configuration

The CORTEX HDR has been configured in factory in accordance with the required hardware components
(electronic cards, etc…) and software licenses (maximum bit rate supported, data decoding licenses, filter
licenses, data processing licenses, etc…).

Each CORTEX HDR unit comes with a factory acceptance test book showing the detailed hardware and software
configuration of the unit at delivery.

4.1.3 Software Exit & CORTEX HDR Shutdown

4.1.3.1 Exiting the Monitoring & Control Software
To exit the Monitoring & Control Software, click on File menu and select Exit. or click on in the upper right
corner of the MCS window. If any configuration parameter has been changed since the MCS Document was
updated on the disk, the following message is displayed :

Click on Yes to update the MCS File on the disk. Otherwise, click on No or Cancel the command.

4.1.3.2 Exiting the Signal Processing Software

To exit the Signal Processing Software (SPS), click on the SPS icon at the lower right part of the screen
and select Exit.

4.1.3.3 Restarting the SPS & MCS

Assuming the application software (SPS + MCS) has been stopped, click on shortcut menu Start / All Programs /
Startup / crtxstart to restart it.

To restart the MCS only, click on shortcut menu Start / All Programs / Cortex HDR-XXL / HDR XXL Monitoring
and Control.

To restart the SPS only, click on shortcut menu Start / All Programs / Cortex HDR-XXL / HDR XXL Signal
Processing Software.

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4.1.3.4 CORTEX HDR Shutdown

PRIOR TO SWITCHING OFF YOUR CORTEX PRODUCT

SHUT DOWN THE PC-COMPATIBLE WORKSTATION (CLICK ON Start / Shutdown / Shut down the computer).

FAILURE TO OBSERVE THIS PROCEDURE CAN AFFECT DATA ON THE DISK AND THE SYSTEM ITSELF.

4.1.4 Screen Saver

WARNING:
THE SCREEN SAVER INSTALLED AT DELIVERY ALLOWS TO SWITCH THE LCD BACKLIGHT OFF.

TO AVOID PREMATURE AGEING / FAILURE OF THE LCD AND DATA TRANSFER PROBLEMS ON THE PCI BUS,

DO NOT CHANGE THE SCREEN SAVER SETTING.

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4.2 SIGNAL PROCESSING SOFTWARE (SPS)

4.2.1 CTX Documents
CTX Documents are configuration files created and managed by the CORTEX SPS. A CTX Document contains
the whole set of configuration parameters that have been previously stored on the disk under file extension .CTX.

A CTX Document is loaded by the SPS every time the CORTEX is started and the CORTEX is automatically
configured from the contents of this CTX file.

If the machine has never been started since its software was installed, the default loaded CTX file is menu1.ctx.
Else (usual case), the CTX document which is loaded is the last active CTX file (See 4.2.6.1.1 and 4.2.6.1.2).

A copy of this file (CTX Table) is maintained in SRAM and is updated whenever the CORTEX configuration is
changed by the operator. The CTX Table is automatically saved to the CTX Document on the hard disk every 10
seconds and at application ending.

Additional CTX Documents reflecting mission-specific configurations can be created at will by the operator.

CTX Documents are binary files; they cannot be displayed on the screen or printed out.

4.2.2 SPS Start Sequence

The last active CTX Document is loaded by the SPS when the CORTEX is started. The CORTEX is configured
from the content of this file.

STEP 0 : Windows boot up sequence.

cortex-nt.CTX file
STEP 1 : The Signal Processing Software (SPS) is
automatically started. The CORTEX is configured
CORTEX
Configuration
Parameters from parameters stored in the last active CTX file. A
(see STI100013)
copy of the file is maintained in RAM (CTX Table).

STEP 2 : The Monitoring & Control Software (MCS)

1
(local GUI or remote MCS) opens a TCP-IP
connection to the Monitoring port and starts
monitoring the machine. The CTX Table is updated
3
CTX table when configuration requests are received on the
2 TCP-IP Control port.
CORTEX
TCP-IP Configuration
Parameters STEP 3 : The CTX file is automatically refreshed
IP address
Local GUI or (see STI100013)
every 10 seconds and at application ending.
Remote MCS Clients

CORTEX SPS

Figure 58 : SPS Start Sequence

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4.2.3 Configuring the CORTEX from CTX Documents

CTX Documents are stored on the disk in C:\Program Files\IN-SNEC\crtxnt\Menus\CTX directory.

A copy of the original CTX files (those installed from the reference CORTEX CD ROM) is available in C:\Program
Files\IN-SNEC\crtxnt\Menus\CTX_ref directory. These files are set to read-only. They can be copied to
C:\Program Files\IN-SNEC\crtxnt\Menus\CTX, if required, for being used by the SPS (remove the read-only
protection on the copies).

4.2.3.1 CTX Document Name Table

Management of the CTX Documents is via the CTX Document Name Table (See 4.2.6.1.1). This table assigns a
name to each CTX Document, to make file selection easier for the operator (see STI 100013 for table format).

The CTX Document Name Table is ASCII-coded and is transmitted over the LAN on reception of a monitoring
request with component code 200H.

The CTX Document Name Table is not included in the set of tables returned to the monitoring client on reception
of a monitoring request for All component tables.

The CTX Document Name Table is automatically saved to the disk (C:\Program Files\In-snec\Crtxnt\
CTXDocument\NameTable.TXT) whenever the name of a CTX Document is changed or at application ending.

4.2.3.2 CTX Document Storage and Loading

CTX Documents can be created, modified, (re)named and loaded via two configuration commands (see Annex 1,
section 2.3.2.3) available in the CTX Document Management window (see section 4.3.9) :

 Save command : name and store the active CTX Table into one of the 10 CTX Documents on the disk.

 Load command : select and load one of the 10 CTX Documents and reconfigure the CORTEX.

The CTX Document name can also be modified by editing the NameTable.TXT file before starting the CORTEX
SPS. If a CTX Document is not available (not existing or corrupted), the assigned name is set to an empty
character string.

In the CORTEX Series monitoring table (offset 16) and in the Global CORTEX monitoring table (offset 22), the
CTX Document ID status indicates which one of the 10 CTX Documents was previously loaded or stored and
whether or not this CTX Document was modified since loaded or stored (Update CTX Document status). See
STI 100013 and STI 100013_HDR in Annex 1 for more details.

Both status are set to 0 at boot.

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CORTEX SPS Last Active CTX Document CTX Document Name Table CTX Document # N
REMOTE USERS (Disk) (Disk) (disk)
Start Application
Applicati

Load CTX Document in RAM

Set CTX Document ID status to 0
Set Update CTX Document status to 0 Loaded

Load CTX Document Name Table

Loaded

Store CTX Document #N with Label

Accept

Save Active CTX Table to CTX Document # N

Set CTX Document ID status to N.
Saved
Set Update CTX Document status to 0.
Update label to CTX Document #N
in CTX Document Name Table Save CTX Document Name Table

Saved

Configuration Request

Accept

Every 10 seconds : save Active CTX Table to the disk

Set Update CTX Document status to 1 Saved

Load CTX Document #N

Accept

Load CTX Document #N to Active CTX Table (*)

Set CTX Document ID status to N.
Set Update CTX Document status to 0 Loaded
Apply all configuration parameters

(*) If file error: set all parameters

to their default value

Figure 59: CTX Document Management

4.2.4 Start-up Menu Selection by Remote Access Control (RAC)

The RAC functionality is supported by all CORTEX products (CRT, HDR, ACS, …) from SPS Kernel version 2.7
and MCS kernel version 1.9.

4.2.4.1 General
On some CORTEX products (CORTEX CRT, CORTEX HDR, etc…) a start-up menu offers several high-level
architectures (combination of hardware and software resources) corresponding to different mission requirements.

When starting up the CORTEX software, menu selection can be done either locally (user interface described
hereafter) or remotely (Remote Access Control) by sending control commands to a specific RAC data server on
the CORTEX machine (RAC port # 3003). Control commands are described in the Ethernet ICD STI 100013,
section 2.6.

Starting a new menu while the CORTEX is running takes only a few seconds (2 seconds best case, up to 20
seconds when a new FPGA software needs to be downloaded from the hard disk to the target FPGA).

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The following commands are supported :

 Stop the active menu : the CORTEX application software is not stopped but all IP connections (to the
monitoring port, telemetry port, ranging ports, etc…), except the connections to the RAC port, are
automatically closed. The connection status on the top level window of the GUI indicates
DISCONNECTED.

 Start a new menu : select and start a new menu.

 Check the active menu : indicates the active menu.

 Load the menu table : on reception of this command, the CORTEX returns the list of available menus.

4.2.4.2 MCS Graphical User Interface

From the IN-SNEC MCS, the operator can access the RAC server by clicking successively, in the upper toolbar,

on Window  Menu_Selection, or by clicking on the icon.

Next picture shows the operational scenarios offered by the start-up menu. Use the Stop active menu and Start
new menu pushbuttons to re-configure the CORTEX.

Figure 60 : MCS Menu Management Window

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4.2.4.3 Menus Description File

A detailed description of the start-up menu is available in C:\Program Files\IN-SNEC\crtxnt\Menus\menu.txt .

How to read this file ? :

Lines of comments (or disabled choices) starts with a # character (see the four first lines of the file). Other lines are
menu lines.

A menu line consists of several arguments separated by a semi-comma character. Arguments are (from left to
right) :

 Menu index : the above menu allows for different configuration. Indexes 1 through 7 are for basic menus
while others indexes are for mission menus.

 Menu name : basic menus are named Menu 1 through Menu 7 while missions menus refer mainly to the
satellite to be tracked.

 Registry base : access path to the CTX file to be loaded.

 CTX file : CTX file to be loaded.

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4.2.5 SPS Version Identification

4.2.5.1 Common Data
Software version at delivery is described in Annex 5 (Section 1) and, with more details, in the CORTEX
Acceptance Test Report.

 To know the version of the PROMed software (ZDS electronic cards), refer to the Acceptance Test Report
(see also the marking on the PROM chips).

 To know the Signal Processing Software (SPS) version and what version of software is downloaded at boot to
the ZDS electronic cards, click on at the lower right corner of the display and select About
Cortex :

Figure 61 : About CORTEX SPS Version

The SPS is built around an SPS kernel (supporting multiple CORTEX products such as the CORTEX CRT,
CORTEX HDR, CORTEX ACS, CORTEX RTR, etc…) and a product-specific SPS software layer.

The header of the above window shows the version of the SPS kernel (example : Version 2.4).

4.2.5.2 CORTEX HDR Specific Data

The inner window shows the version of the SPS software layer specific to the CORTEX HDR product (example :
2.2.0.0).

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4.2.6 CORTEX HDR System Parameters in Registry

4.2.6.1 CORTEX Station
4.2.6.1.1 MENUS DESCRIPTION
Access path to the Menu Description file (menu.txt).

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/Cortex Station/Remote Control

Keyword : MenuDescription
Default setting : "C:\\Program Files\\IN-SNEC\\crtxNt\\Menus\\menu.txt”

4.2.6.1.2 LAST USED MENU

This status indicates what was the working menu before shutting down the machine

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/Cortex Station/Remote Control

Keyword : LastConfiguration

4.2.6.1.3 RAC PORT NUMBER

Allows changing the RAC port number :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/Cortex Station/Remote Control

Keyword : PortCntx
Default setting : 3003

4.2.6.2 Demodulation Unit

4.2.6.2.1 OUTPUT CLOCK ON/OFF
Enabling or disabling the data clock from the Bit Synchronizer :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Preferences/Dmu#n

Keyword : ClkOut

Enter 0 for permanent clock

Enter 1 for disabling the clock signal when the Bit Synchronizer is unlocked.

Enter 2 for limiting the clock signal frequency deviation to 0.1% of the programmed bit rate when the Bit
Synchronizer is unlocked, and outputting the effective bit rate when the Bit Synchronizer is locked.

Enter 3 for clock setting accuracy better than 1 ppm when the Bit Synchronizer is unlocked and outputting the
effective bit rate when the Bit Synchronizer is locked.

Enter 4 for clock disabling during frequency acquisition.

Default setting : 0 (clock always present)

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4.2.6.2.2 PUNCTURED VITERBI SETTING

Setting of the punctured codes and swap function :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Preferences/Dmu#n

Keywords : ViterbiPunctCode0, ViterbiPunctCode1 and ViterbiPunctSwapp
For Code 0 and code 1 : enter 0 for no puncturing and 1 for punctured Viterbi. Enter 0 for swap OFF, 1 for swap
ON convention 1 and 2 for swap ON convention 2.
Default setting : 0.

4.2.6.2.3 BER ON MERGED OR SEPARATE I/Q

Selecting the BER measurement technique in PRN BER mode (see 3.3.8) and BER display on the GUI :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keyword : BerIQ
Enter 0 for one BER value on merged I & Q (using method 1).
Enter 1 for two BER values (on I & on Q) (using method 1).
Enter 2 for one BER value on merged I & Q (using method 2).
Default setting : 0.

4.2.6.2.4 HIGH EBNO TRACKING MODE

This key describes the mode of tracking of the high EbNo :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keywords : TrackBERHigh
Default setting : Enter 0 for EbNo computed from the I/Q constellation. Enter1 for high EbNo (> 12 dB) update
from IF level measurements (assuming the noise level is constant).

4.2.6.2.5 I/Q SYNCHRONIZATION IN CAPTURE MODE (MENU # 7)

Expected timing for external I/Q input signals (external I/Q data recovery mode) :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keywords : BitSyncMode_IQ_sync
Enter 0 for synchronized I/Q and 1 for Q data timing delayed by ½ symbol compared to I data.
Default setting : 0

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4.2.6.2.6 DNRZ PCM DECODING

Selecting the DNRZ code in QPSK and OQPSK demodulation mode :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keywords : DNRZ_code
Default setting : 0

4.2.6.2.7 OQPSK (SQPSK) ALGORITHM

OQPSK demodulation algorithm definition

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keywords : Algo_OQPSK
Enter 0 for standard algorithm and 1 for enhanced algorithm (better resistance to pattern, but higher
synchronization threshold).
Default setting : 0.

4.2.6.2.8 DVB-S2 RANDOMIZATION POLYNOMIAL

Selection of the randomization polynomial for DVB-S2 standard

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing

/Dmu#n
Keywords : DVBS2_PIScrambling_Num
Enter 0 to 262141 (refer to the DVBS2 standard, document EN 302307 V1.1.1 § 5.55.4)
Default setting : 0.

4.2.6.3 Transport Layer : Frame Synchronizer Setting

4.2.6.3.1 CHECK TO LOCK STRATEGY (CTL) FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_Ctl
Enter an integer value between 0 and 10.
Default setting : 2.

4.2.6.3.2 LOCK TO SEARCH STRATEGY (LTS) FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_Lts
Enter an integer value between 0 and 10.
Default setting : 2.

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4.2.6.3.3 SYNCHRONIZATION THRESHOLD (SYN) FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_Syn
Enter an integer value between 0 and 10. (maximum number of corrupted bits in the 32-bit synchronization word)
Default setting : 2.

4.2.6.3.4 SYNCHRONIZATION W ORD FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_DATA_SW
Enter an integer value between 0 and 255 (0xFF).
Default setting : 184 (0xB8).

4.2.6.3.5 IDLE SYNCHRONIZATION WORD FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_IDLE_SW
Enter an integer value between 0 and 255 (0xFF).

Default setting : 150 (0x96).

4.2.6.3.6 FRAME SIZE FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_FrameSize
Enter the transport frame size in bytes (synchronization word included) : 0 and 65535 (0xFFFF).

Default setting : 4080 (0xFF0).

4.2.6.3.7 CONTROL OF THE R-S DVB DECODING CHAIN FOR RS DVB

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : RSDVB_Ctrl

Default setting : 15 (0x0F).

4.2.6.3.8 CHECK TO LOCK STRATEGY (CTL) FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_Ctl
Enter an integer value between 0 and 10.
With #m: 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

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4.2.6.3.9 LOCK TO SEARCH STRATEGY (LTS) FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_Lts
Enter an integer value between 0 and 10.
With #m : 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.10 SYNCHRONIZATION THRESHOLD (SYN) FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_Syn
Enter an integer value between 0 and 10. (maximum number of corrupted bits in the 32-bit synchronization word)

With #m: 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.11 DERANDOMIZATION FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_descrambling
Enter 0 (disable) or 1 (enable)
With #m : 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.12 SYNCHRONIZATION W ORD LSB FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_SW_lsb
Enter an integer value between 0x0 and 0xFFFFFFFF
With #m: 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.13 SYNCHRONIZATION W ORD MSB FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_SW_msb
Enter an integer value between 0x0 and 0xFFFFFFFF
With #m: 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.14 SYNCHRONIZATION MASK LSB FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_SW_MASK_lsb
Enter an integer value between 0x0 and 0xFFFFFFFF
With #m: 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

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4.2.6.3.15 SYNCHRONIZATION MASK MSB FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_SW__MASK_msb
Enter an integer value between 0x0 and 0xFFFFFFFF

With #m : 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.16 SYNCHRONIZATION W ORD LENGTH FOR LDPC

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : LDPC#m_SW_size
Enter the transport frame sync word size in bits (synchronization word included) : 0 and 64

With #m : 12 for LDPC 1/2, 23 for LDPC 2/3 , 78 for LDPC 7/8

4.2.6.3.17 DECODER REFRESH PERIOD

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n
Keywords : DecoderRefreshPeriod
Period of the update of the decoder in millisecond.

Default setting : 0x3e8 (1000 ms)

4.2.6.3.18 TRANSPORT LAYER STATUS

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/SignalProcessing/Dpu#n

Keywords : PermanentTransportStatus

0: when the frame synchronizer of the CADU layer is unlock, the counters of the Transport layer are set to 0 and
not updated

1: when the frame synchronizer of the CADU layer is unlock, the counters of the Transport layer are updated.

Default setting : 0

4.2.6.4 Test Modulation Unit

4.2.6.4.1 SELECTING THE DNRZ CODE IN QPSK AND OQPSK MODULATION MODE :
Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing /tstu
Keywords : DNRZ_code
Default setting : 0

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4.2.6.5 Global HDR

4.2.6.5.1 SELECTING LVDS / ECL INPUTS OF THE TEST MODULATOR :
Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing
/Global
Keywords : LVDS_input

0: selection of the ECL inputs

1: selection of the LVDS inputs

Default setting : 0

4.2.6.5.2 RECORDING IN RAW DATA MODE :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing
/Global
Keywords : UnlockedNoTM

0: in raw data mode, data are recorded even if the demodulator is not locked

1: in raw data mode, data are recorded only if the bit synchronizer of the demodulator is locked

Default setting : 0

4.2.6.5.3 DMX TABLE :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing
/Global
Keywords : DisableDmxAllTable

1: disable the DMX table from the All Components table (refer to the document STI 100013 HDR )

0: enable the DMX table inside the All Components table

Default setting : 0 for a new software installation

Default setting: 1 for a software upgrade installation

4.2.6.5.4 TCP/IP DATA TRANSMISSION :

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/CrtxHdr/SetDefault/Signal Processing
/Global
Keywords : TimeoutTcp
Delay (in second) before transmitting of an uncompleted Telemetry Data Message over TCP/IP

Default setting : 0

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4.3 MONITORING & CONTROL SOFTWARE (MCS)

4.3.1 General
Main MCS functions are :

 Display the current CORTEX configuration and status from the monitoring tables transmitted by the SPS,

 Modify the setting of the equipment. This function is password-protected,

 Reset the TCP-IP connections to the CORTEX (close all TCP-IP connections to a given port or close all
connections to the CORTEX). This function is password-protected.

 Product-specific functions : telemetry Quick Look (CORTEX CRT), satellite commanding and ranging
(CORTEX CRT), etc…. For more details, see next sections.

The MCS can be installed in any PC workstation using and having 32 Mbytes of RAM or more. The MCS and SPS
communicate via an Ethernet link under TCP-IP.

Some of the TCP-IP ports of the CORTEX (monitoring, logging, etc…) accept simultaneous connections of several
clients while other ports (Control, Reset, etc…) accept only one connection at a time. For more details concerning
the Ethernet interface, refer to :

 CORTEX Series TCP-IP Ethernet interface (reference STI 100013) : Ethernet ICD common to all CORTEX
products),

 CORTEX XXX TCP-IP Ethernet interface : product-specific Ethernet interface extension, where XXX is the
product extension name. Example : STI 100013_CRT is the CORTEX CRT Ethernet ICD, STI 100013_HDR is
the CORTEX HDR Ethernet ICD, STI 100013_ACS is the CORTEX ACS Ethernet ICD, etc….

The MCS is built around an MCS kernel (supporting multiple CORTEX products such as the CORTEX CRT,
CORTEX HDR, CORTEX ACS, CORTEX RTR, etc…) and a product-specific SPS software layer which is
automatically identified when the MCS connects to the CORTEX SPS.

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4.3.2 MCS Documents

MCS Documents are configuration files created and managed by the CORTEX MCS.

An MCS Document contains the whole set of configuration parameters that have been previously stored on the
disk under file extension .MCS.

The MCS document also contains the name or Ethernet address of the CORTEX whose configuration has been
saved in the MCS document. This name or address is displayed on top of the graphical window.

A default MCS Document (cortex-nt.mcs) is loaded by the MCS when the CORTEX is started; it can be then used
to re-configure the machine. A copy of this file (MCS Table) is maintained in RAM and is updated whenever the
CORTEX configuration is changed by the MCS operator. The MCS Table can be manually saved to the MCS
Document on the hard disk by MCS Operator.

Additional MCS Documents can be created at will by the operator. A set of MCS Documents (common satellites
configuration) is available on the hard disk C:\Program Files\IN-SNEC\crtxMcs\DefaultConfig).

A copy of the original MCS files (those installed from the CORTEX reference CD-ROM) is available in directory
C:\Program Files\IN-SNEC\crtxMcs\DefaultConfig_ref. These files are in read-only mode. They can be copied to
the working directory (C:\Program Files\IN-SNEC\crtxMcs\DefaultConfig) if necessary (remove the read-only
protection on the copies).

MCS documents are binary files. They cannot be displayed on the screen or printed out, except if the MCS
software package is installed in a remote PC with printing capability (PRINT PREVIEW & PRINT commands).

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4.3.3 MCS Start Sequence. MCS Control Status

cortex-nt.mcs
IP address

Configuration
Parameters only

(see STI100013)

Global status
setting
TM Quick look
setting
1

CTX table
MCS table
IP address
2 Configuration
Parameters
Configuration 3 TCP-IP And
Parameters GUI IP address Status
& Global status
4
shhjdssdh
shhjdssdh
shhjdssdh
kjdsk
kjdsk
kjdsk
wks
wks
wks
,jhkjhsh
,jhkjhsh
,jhkjhsh
kjshchsckd
kjshchsckd
kjshchsckd
lisclslk
lisclslk
lisclslk
lkdjlkj
lkdjlkj
lkdjlkj
M&C Clients
(see STI100013) shhjdssdh
shhjdssdh
kjdsk
kjdsk
wks
wks
,jhkjhsh
,jhkjhsh
kjshchsckd
kjshchsckd
lisclslk
lisclslk
lkdjlkj
lkdjlkj (see STI100013)
shhjdssdh kjdsk wks ,jhkjhsh kjshchsckd lisclslk lkdjlkj
shhjdssdh kjdsk wks ,jhkjhsh kjshchsckd lisclslk lkdjlkj

TM Quick look
? shhjdssdh
shhjdssdh
kjdsk
kjdsk
wks
wks
,jhkjhsh
,jhkjhsh
kjshchsckd
kjshchsckd
lisclslk
lisclslk
lkdjlkj
lkdjlkj

setting
OK / DIFFER
5 CORTEX SPS
IN-SNEC MCS

Figure 62 : MCS Start Sequence

STEP 1 : When the Monitoring & Control Software (MCS) is started, it opens the default MCS Document (program
argument) c :\Program Files\In-snec\crtxMcx\cortex-nt.mcs on the disk and makes a copy in RAM (MCS Table). If
the default MCS Document is not found the following warning message is displayed :

 STEP 2 : The MCS connects to the Monitoring port of the CORTEX and starts monitoring the machine. If the
MCS fails to open the connection, the MCS Login window indicates Disconnected and a warning message is
displayed.

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 STEP 3 : Once the connection to the CORTEX has been established, the configuration parameters, the status
and alarms received from the connected machine are refreshed in real time on the GUI. Configuration
commands entered at the GUI are executed and the MCS Table refreshed accordingly.

 STEP 4 : The MCS permanently compares the configuration parameters from the MCS Table to the ones
displayed on the GUI.

 STEP 5 : If the GUI strictly reflects the contents of the MCS Table, the MCS control status at the bottom of the
Top Level window displays :

Else (the CORTEX has been reconfigured by a remote M&C client or the MCS document has not been saved
properly prior shutting down the machine) the MCS control status is changed to :

 Click on icon to reconfigure the CORTEX from the MCS Table, or

 Click on icon to update the MCS Table from the configuration parameters on the GUI (CTX table).

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4.3.4 M&C Session. MCS Documents Management

4.3.4.1 Close the Active M&C Session
 Click on FILE → CLOSE. If required, save the active MCS Table to the disk.

4.3.4.2 Open an M&C session with a CORTEX

 Click on FILE → NEW. An empty MCS Login window appears on the screen. The MCS creates an empty
MCS Table in RAM.

 Enter the IP address or name of the CORTEX unit and click on (or click on CONNECT). Once the

monitoring connection is established, the MCS starts monitoring the unit and initializes the contents of the

MCS Table (IP address or name of the unit included). The MCS control status is set to ,

indicating that the contents of the MCS Table strictly matches the configuration of the unit. The MCS Table is

automatically updated every time the Operator modifies the setting of the unit from the MCS on which the

M&C session has been started (the MCS control status remains to ).

 The MCS control status automatically turns to if any remote Monitoring & Control system modifies
the configuration of the unit.

 For saving the MCS Table to an MCS Document on the disk, see next section. Note : multiple M&C sessions
can be simultaneously started from the MCS.

4.3.4.3 Save the CORTEX Configuration to an MCS Document on the Disk

 Verify that the MCS control status is set to . If it is set to click first on .

 If the MCS Table has never been saved to the disk, click on FILE → SAVE or FILE → SAVE AS and either
confirm the name proposed in the dialog box or enter another name.

 If the MCS Table has already been previously saved to the disk, click on FILE → SAVE to save it again to the
same MCS Document or click on FILE → SAVE AS to save it to another new or existing MCS Document.

4.3.4.4 Reconfigure the CORTEX from an Existing MCS Document

 Close the active M&C session (click on FILE → CLOSE).

 Click on FILE → OPEN and select an MCS Document in the proposed list. The selected MCS Document is
copied to an MCS Table in RAM.

 Click on to reconfigure the CORTEX from the new MCS Table. The MCS control status is changed to

, indicating that the unit has been successfully reconfigured.

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4.3.5 Graphical User Interface

The following window appears on the screen when the MCS is started :

Figure 63 : MCS Top-Level Window

The window name (Monitoring Control Software) is followed by the name of the MCS Document opened by the
Monitoring & Control Software.

4.3.5.1 MCS Login Window

Figure 64 : MCS Login Window

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The MCS login window allows to connect or disconnect to the Cortex SPS and check the connection status. The
connection buttons are disabled if no machine name or IP address is provided in the host identification zone. Start
entering the machine name or IP address and the connection button will automatically be enabled.

Connect the MCS to the SPS by clicking on or by pressing the RETURN or ENTER key. If the host machine

accepts the connection, the disconnection button is enabled and the connection status turns to .
Otherwise, a connection error message appears on the screen.

After the connection is established the host identification zone becomes gray. Changing the IP address is no more

possible unless the disconnect button is pressed.

Next sections describe the commands en status available from the MCS window after the connection is
established.

4.3.5.2 MTDI (Multiple Tabbed Document Interface)

The MCS software is based on MTDI (Multiple Tabbed Document Interface) space. The MTDI allows to separate
in different working spaces the MCS Documents. Every document is identified by the host name and shows all the
windows corresponding to this connection. The tabs allow to go from a working space to another. The tabs can be
placed either at the bottom or right side (default setting) of the MCS window (menu PREFERENCES).

Figure 65 : Multiple Tabbed Document Interface

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The tabs allow to know the status of the connection and host CORTEX :

 in black on green back : MCS is connected and host CORTEX is OK,

 in white on red back : MCS is connected and host CORTEX is in alarm,

 in blue on gray back : MCS is disconnected.

In case of host CORTEX alarm the tabs turn to red.

Another option allows to display on the tab the name of the host machine or MCS Document (menu
PREFERENCE).

4.3.5.3 Upper Toolbar

4.3.5.3.1 COMMON DATA

The following commands are common to all of the CORTEX products. For product specific commands, see
next section.

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FILE NEW : Create a new MCS Document to open a new M&C session.
OPEN : Open an M&C session from an existing MCS Document on the disk
CLOSE : Close the current M&C session and document. If the document is not saved, a
messages proposes to save it. The workspace is closed too.
SAVE : Save the active MCS Document to the original document on the disk.
SAVE AS : Save and rename the active MCS Document to the disk.
PRINT : Print out the contents of the active MCS Table.
PRINT PREVIEW : Display the contents of the active MCS Table.
PAGE SETUP : Change the printer and printing options.
EXIT : Exit the MCS.
<file_list > : Select an existing MCS document from the list.

CONNECT CONNECT TO : Connect the MCS to the monitoring port of a CORTEX. Command
available only if an IP address is provided in the host identification zone.
DISCONNECT : Close the monitoring connection to the CORTEX.

EXECUTE CONTROL ACCESS : Activate or inhibit the configuration mode.

OPEN CONTROL PORT : Open a TCP-IP connection to the Control port. Opening the
connection will inhibit access to the Control port by other remote Control Clients.
CLOSE CONTROL PORT : Close the TCP-IP connection to the Control port.
SPECIAL COMMANDS
INITIALISATION : Re-program the CORTEX to boot up state.
RESTART DEMODULATOR : Restart the acquisi11tion of the demodulator.
CLOSE TCP : Close the TCP-IP connection for the active window.
INITIALISATION : Re-program the CORTEX to boot up state.
LOAD CONFIGURATION : Load a User configuration

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PREFERENCES TOOL BAR : Display or hide the tool bar.

STATUS BAR : Display or hide the status bar.
BOTTOM TABS : Move the document tabs to the bottom or to the right side of the MCS
window (MTDI).
VIEW HOSTNAMES : Display on the tabs the name of the host machine or the name of the
active MCS Document.
OK / DIFFER MANAGEMENT : Management of the CONFIG/APPLY mode :
STANDARD or PROTECTED or AUTOMATIC
See Section 4.3.6.4 for a detailed description of the CONFIG/APPLY modes

WINDOW NEW MAIN WINDOW : Create a new product main window.

MENU_SELECTION : Start-up menus management (see section 4.2.4)
CASCADE : Reorganize the windows in cascade.
TILE : Reorganize the windows in order to display everything.
ARRANGE ICONS : Represent the windows in icons.
<list_window > : List the opening windows in the workspace.

HELP ABOUT : Display the versions of the MCS kernel, products and plugins.

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4.3.5.4 Lower Toolbar

Hide or display the lower toolbar from menu PREFERENCE / TOOL BAR. The lower toolbar appears on the
screen only after the MCS is started.

4.3.5.4.1 COMMON DATA

The following commands are common to all of the CORTEX products. For product specific commands, see next
section.

Same as command FILE - NEW.

Same as command FILE - OPEN.

Same as command FILE - SAVE.

Same as command FILE - PRINT.

Same as command HELP - ABOUT.

Update the MCS Table from the real configuration of the connected CORTEX.

Reconfigure the connected CORTEX from the active MCS Table.

Connect to the monitoring port of the CORTEX.

Close the connection to the monitoring port of the CORTEX.

Activate/inhibit the configuration mode. Password-protected function.

Open the TCP window.

Toggle command : open/close the connection to the Control port (see section 4.3.6.3).

Open the CTX Document management window (see section 4.3.9).

Open the MCS Menu Management window (see section 4.2.4.2).

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4.3.5.4.2 CORTEX HDR SPECIFIC DATA

Restart signal acquisition by the Demodulator. Turns to yellow when the Demodulator is locked.
Turns to gray when the Demodulator is unlocked (see SPECIAL COMMAND - RESTART IFR).

Reset the BER counter for the active Demodulator Unit window or
Restart the status counter for the active Data Processing Unit window.

Close the TCP-IP connection for the active window. Turns to red when the connection is active and
to gray when the connection is closed (see SPECIAL COMMAND - CLOSE TCP)

Open the data logging set-up window (refer to Logging window)

Open the Disk Partitioning & Memory Allocation window.

Toggle command : select the Configuration or Acquisition mode.

In Acquisition mode, close all open data acquisition processes to toggle in Configuration mode.

Invert one bit in the simulated data pattern (pseudo-random pattern or file). Bit inversion takes
place before convolutional encoding (if enabled).

Allows the setting of a same parameter in all the active channels from a single window.

Recall the MCS Login window.

Load a User Configuration MCS file

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4.3.5.5 Bottom Status Toolbar

From left to right :

 OK/DIFFER mode : Standard (Std), Protected (Prot) or Automatic (Auto). See section 4.3.6.4)

 Alarm status :

OK (gray background).

Alarm (red background) if any CORTEX component is in alarm. Detailed information on the alarm is
available at the GUI.

Temperature (red background) if any temperature monitored by the IPMIMonitor tool exceeds the
alarm threshold (see section 5.3.2).

 Host name & connection status : (connected) or (disconnected)

 MCS control status : or (see section 4.3.3).

 Date and time from the built-in time code reader : . Yellow background if the time
decoder is unlocked or in flywheel mode; gray background if the decoder is locked.

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4.3.6 CORTEX Monitoring & Configuration

4.3.6.1 Default Operating Mode
At start up, the default CORTEX MCS operating mode is Monitoring only. In all configuration windows, control
pushbuttons are inhibited :

Configuration changes (by the MCS Operator or by any remote Control client), status and alarms are refreshed in
real time on the GUI.

4.3.6.2 CORTEX Configuration

To reconfigure the CORTEX in a single-operator environment (no configuration conflict due to simultaneous
access of several Control clients to the machine) :

 Click on in the lower toolbar :

 Enter the Control password. Default setting at delivery : no password. Control pushbuttons are changed to :

 Click on . The pushbutton is changed to .

 Change the parameter setting and click on . The MCS :

1. opens a connection to the Control port,

2. transmits the configuration commands to the Signal Processing Software,

3. closes the connection to the Control port and returns to the monitoring mode. The pushbutton is

changed to .

To cancel the modifications, click on instead of or close the window.

To reconfigure the CORTEX in a multi-operator environment, read section 4.3.6.4.

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4.3.6.3 Forced Connection to the Control Port (Pseudo Local Mode)

After entering the Control password, the CORTEX can be set to a pseudo local mode by keeping open a TCP-IP
connection to the Control port : reconfiguration of the unit by remote Control Clients remains impossible until the
connection is released by the local Operator or a Reset Control port command is received on the Reset port.

To open a connection to the Control port, click on EXECUTE  OPEN CONTROL PORT. To close the connection
to the Control port, click on EXECUTE  CLOSE CONTROL PORT.

4.3.6.4 OK/DIFFER Management Mode

The OK/DIFFER management mode is used to customize the configuration process. Three modes are proposed :
STANDARD, PROTECTED and AUTOMATIC. Mode selection is from menu PREFERENCES.

4.3.6.4.1 STANDARD MODE

When the CONFIG button is pressed, the status part of the GUI keeps on being refreshed in real time but the
parameter part shows the contents of the active MCS Table (and not the parameter values returned in the
monitoring tables). At this point, it should be noted that if the MCS control status is set to , clicking
on APPLY will reconfigure the equipment from the contents of the MCS Table !

New parameter values entered by the Operator are stored in the MCS Table and when the APPLY button is
pressed, the CORTEX is re-configured from the MCS Table and the MCS control status indicates .

4.3.6.4.2 PROTECTED MODE

This mode is identical to the Standard mode above except that, if the MCS control status were before
clicking on CONFIG, a confirmation message is displayed on the screen when the APPLY button is pressed :

This message is to warn the Operator that the CORTEX will be re-configured from the MCS Table and that one or
several parameters, else than those modified by the Operator, will be changed, thus affecting other remote
CORTEX Operators. Click on NO to abort or YES to re-configure the machine.

4.3.6.4.3 AUTOMATIC MODE

In this mode, the MCS Table is automatically updated whenever a change in the configuration is made by the
operator. Consequently, the MCS control status remains permanently to , indicating that the contents
of the MCS Table and the contents of the monitoring tables always match.

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4.3.7 MCS Version Identification

To know the Monitoring & Control Software (MCS) version, click on or click on Help in the top-level window,
then select About.

Figure 66 : Cortex MCS About : Software Version

The MCS is built around an MCS kernel (supporting multiple CORTEX products such as the CORTEX CRT,
CORTEX HDR, CORTEX ACS, CORTEX RTR, etc…) and a product-specific MCS software layer.

The header of the above window shows the version of the MCS kernel.

The inner window shows the version of the MCS software layer specific to the CORTEX HDR product.

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4.3.8 Changing a Password

The following procedure applies to all passwords except the user login password.

To change a password :

1. Click on icon , or select button ‘Change’

2. Click on CHANGE,

3. Enter and confirm new password.

Figure 67 : Changing a Password

Notes :

1. The Control password does not protect the CORTEX from re-configuration by remote Control Clients.

2. The TCP-IP password does not protect from reset commands issued by remote Reset Clients.

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4.3.9 MCS Interface for CTX document management

Click on to access the CTX Document management window :

 Click on and enter the password enabling the Load and Save commands.

 Click on Save to capture the current CORTEX configuration and save it to an existing or a new .CTX
Document on the disk (maximum name size : 16 characters) :

The last loaded or saved CTX Document is identified in the upper part of the window by its ID number and name.
A configuration status indicates whether the current configuration of the unit matches the contents of the last
loaded or saved CTX Document ( ) or not ( ).

The CTX Document name can be modified only with the Save Command or by editing the NameTable.TXT file
before starting the Signal Processing Software (SPS). If a CTX Document is not available (not created or
damaged), the assigned name is blank. The Configuration Names table is transmitted over the LAN on reception
of a monitoring request with Component code 200H. This table is not part of the tables that can be monitored under
an All components tables monitoring cycle.

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4.3.10 MCS Interface for User MCS files loading

This windows allows to display and to load a configuration file (MCS file) previously recorded inside the directory:
c:\Program File\In-Snec\CrtxMcs\UserConfig or d:\ZDS\Data\HDR\CrtxMcs\UserConfig (for Windows 7) by the
user.

Note that these MCS configuration files can be also remotely loaded using a special TCP/IP command.

Click on (Upper toolbar of the GUI) to access the User Configuration Command window :

 Click on “Refresh List” to refresh the list of the available MCS files previously recorded by the user inside the
directory: …\CrtxMcs\UserConfig.

 Click on the desired line to select the configuration file,

 Click on” Send” to load the configuration inside the HDR.

The number of the selected file appears inside the “Selected” box. The status “Last Conf” is equivalent to the
OK/Differ status of GUI.

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4.3.11 MCS File System Architecture

IN-SNEC MCS software can be found in the following directories. Do not move or modify these directories :

ACCESS PATH DESCRIPTION

C:\Program Files\In-snec Root directory

Upgrade.txt : list of s/w packages (ID + version)
Or
D:\ZDS\Data\HDR

\CrtxMcs Monitoring & Control Software

Graphical User Interface

DefaultConfig MCS files

DefaultConfig_ref MCS files (read only

reference files)

UserConfig MCS files (read only

reference files)

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4.3.12 MCS System Parameters in Registry

MCS system parameters are high-level parameters in the registry. Changing them requires restarting the CORTEX
MCS application software :

4.3.12.1 Monitoring
4.3.12.1.1 MONITORING RATE
To change the time interval between two consecutive monitoring cycles by the MCS software :

Registry path HKEY_LOCAL_MACHINE / SOFTWARE\In-Snec\CrtxMcs\Tcp

Keyword Monitoring
Setting  500D . Default : 500. Expressed in ms

Example : for a monitoring request every four seconds, enter FA0 (in hexadecimal) or 4000 (in decimal). Minimum
value : 1F4H = 500D (monitor the equipment twice per second).

4.3.12.2 MCS Auto-Connect

The following registry keys allow to force the MCS to regularly attempt to reconnect to the monitoring port of the
CORTEX. The auto-connect mode is particularly useful on multi-menu CORTEX.

4.3.12.2.1 AUTO CONNECT ON/OFF

Registry path : HKEY_LOCAL_MACHINE / SOFTWARE\In-Snec\CrtxMcs\Tcp
Keyword : AutoReconnect
Setting : 0 : auto-connect mode disabled. 1 : auto-connect mode enabled

4.3.12.2.2 AUTO CONNECT TIME-OUT

Registry path : HKEY_LOCAL_MACHINE / SOFTWARE\In-Snec\CrtxMcs\Tcp
Keyword : AutoReconnect (time interval between retry to connect)
Setting : Any integer value  1. Default : 5000. Expressed in ms

4.3.12.2.3 AUTO CONNECT RETRY

Registry path : HKEY_LOCAL_MACHINE / SOFTWARE\In-Snec\CrtxMcs\Tcp
Keyword : NbRetryAutoReconnect (maximum number of retry to connect)
Setting : Any integer value  1. Default : 3

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4.3.12.3 MCS Preferences

4.3.12.3.1 SYNCHRONIZATION W ORD : BIT MASKING CONVENTION
Synchronization Word bit masking convention for frame synchronization.

Registry path : HKEY_LOCAL_MACHINE/SOFTWARE/In-Snec/ CrtxMcs/Product/Product4/Preferences

Keyword : SW Mask

Enter 0 (ignore SW bits corresponding to bits set to 1 in the mask) or 1 (ignore SW bits corresponding to bits set
to 0 in the mask).

Default setting : 0.

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4.4 OPERATING SYSTEM AND FILES ARCHITECTURE

4.4.1 Introduction
From the release E9R0, the Cortex HRD units come with Windows 7 embedded operating system in place of the
former Windows 2000 and Windows XP.

Depending on the Operating System, the Cortex HDR software and files can be found in different directories. The
paths of these different directories are given in the following paragraphs.

To improve security, with Windows 7, the Cortex user does not have access to C drive anymore. The
configurations files have been moved to D drive.

4.4.2 Files Architecture

4.4.2.1 Files associated with Monitoring & Control Software

FILE WINDOWS 7 WINDOWS 2000 AND XPE

MCS Application C:\Program Files\ZDS\CrtxMcs C:\Program Files\IN-SNEC\CrtxMcs
MCS Files D:\ZDS\Data\HDR\CrtxMcs\DefaultConfig C:\Program Files\IN-SNEC\CrtxMcs\DefaultConfig
D:\ZDS\Data\HDR\CrtxMcs\DefaultConfig_ref C:\Program Files\IN-SNEC\CrtxMcs\DefaultConfig_ref
(and subdirectories) (and subdirectories)
User’s MCS Files D:\ZDS\Data\HDR\CrtxMcs\UserConfig C:\Program Files\IN-SNEC\CrtxMcs\UserConfig

4.4.2.2 Files associated with the Signal Processing Software

FILE WINDOWS 7 WINDOWS 2000 AND XPE

SPS Application C:\Program Files\ZDS\crtxnt C:\Program Files\IN-SNEC\crtxnt
Menu List D:\ZDS\Data\HDR\crtxnt\Menus C:\Program Files\IN-SNEC\crtxnt\Menus
Menu CTX Files D:\ZDS\Data\HDR\crtxnt\Menus\CTX C:\Program Files\IN-SNEC\crtxnt\Menus\CTX
D:\ZDS\Data\HDR\crtxnt\Menus\CTX_ref C:\Program Files\IN-SNEC\crtxnt\Menus\CTX_ref
User’s CTX Files D:\ZDS\Data\HDR\crtxnt\NameTable.txt C:\Program Files\IN-SNEC\crtxnt\NameTable.txt
D:\ZDS\Data\HDR\crtxnt\SatCnfXX.ctx C:\Program Files\IN-SNEC\crtxnt\SatCnfXX.ctx
(with XX = 01 to 10) (XX = 01 to 10)
BER Files D:\ZDS\Data\HDR\crtxnt\BER C:\Program Files\IN-SNEC\crtxnt\BER
VCM Files D:\ZDS\Data\HDR\crtxnt\VCM C:\Program Files\IN-SNEC\crtxnt\VCM
DVB S2 & SCCC D:\ZDS\Data\HDR\crtxnt\VCM\gamma C:\Program Files\IN-SNEC\crtxnt\VCM\gamma
Gamma Files
FIR Files D:\ZDS\Data\HDR\crtxnt\fir C:\Program Files\IN-SNEC\crtxnt\fir
Test Definition D:\ZDS\Data\HDR\crtxnt\TEST C:\Program Files\IN-SNEC\crtxnt\TEST
Files
Script Files D:\ZDS\Data\HDR\crtxnt\Qual C:\Program Files\IN-SNEC\crtxnt\Qual
D:\ZDS\Data\HDR\crtxnt\Scripts C:\Program Files\IN-SNEC\crtxnt\Scripts
(and subdirectories) (and subdirectories)
Storage D:\ZDS\Data\HDR\Storage D:\ZDS\Data\HDR\Storage
Definition Files
FTP Sorting Files D:\ZDS\Data\HDR\ftp C:\Program Files\IN-SNEC\ftp

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(and subdirectories) (and subdirectories)

CFDP Sorting D:\ZDS\Data\HDR\cfdp C:\Program Files\IN-SNEC\cfdp
Files (and subdirectories) (and subdirectories)
Log Files D:\ZDS\Data\HDR\log C:\Program Files\IN-SNEC\log
STI Logging Files D:\ZDS\Data\HDR\log\param_surv C:\Program Files\IN-SNEC\log\param_surv

4.4.2.3 Files associated with the Cortex HDR Hardware

FILE WINDOWS 7 WINDOWS 2000 AND XPE

Drivers C:\Program Files\ZDS\Drivers C:\Program Files\IN-SNEC\Drivers
(and subdirectories) (and subdirectories)
Firmware C:\Program Files\ZDS\hdr C:\Program Files\IN-SNEC\hdr
(and subdirectories) (and subdirectories)
IPMI Monitor C:\Program Files\ZDS\Tools\Monitor C:\Program Files\IN-SNEC\Tools\Monitor

4.4.2.4 Other Files

FILE WINDOWS 7 WINDOWS 2000 AND XPE

Documentation D:\ZDS\Data\HDR\DOC C:\Program Files\IN-SNEC\DOC
(and subdirectories) (and subdirectories)
CreateCFDP App C:\Program Files\ZDS\Tools\createCFDP C:\Program Files\IN-SNEC\Tools\createCFDP
CreateCFDP Files D:\ZDS\Data\HDR\Tools\createCFDP\Files C:\Program Files\IN-SNEC\Tools\createCFDP\Files
(and subdirectories) (and subdirectories)
Magic Test Tool C:\Program Files\ZDS\Tools\magicTEST C:\Program Files\IN-SNEC\Tools\magicTEST
UMMI Tool C:\Program Files\ZDS\uihm C:\Program Files\IN-SNEC\uihm
FileZilla Installer C:\Program Files\ZDS\Tools\FileZillaServer C:\Program Files\IN-SNEC\Tools\FileZillaServer
DosHdr Tool C:\Program Files\ZDS\Tools\doshdr C:\Program Files\IN-SNEC\Tools\doshdr
Disks Utilities C:\Program Files\ZDS\Tools\disks C:\Program Files\IN-SNEC\Tools\disks
Upgrade File D:\ZDS\Data\HDR\Upgrade.txt C:\Program Files\IN-SNEC \Upgrade.txt
C:\Program Files\ZDS\Upgrade.txt

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4.4.3 Windows 7 Tools & Functionalities

With Windows 7, the following tools and functionalities are available to the Cortex User:

- Network Connections (Desktop – Network Connections): Offers the possibility to modify the IP address,
subnet, gateway of the Cortex Unit.

- Rename Workstation Utility (Start Menu – All Programs – Rename Workstation): Offers the possibility to
change network name of the Cortex Unit.

Procedure: Enter the new network name and click on rename (Cortex unit will restart
automatically with its new name).

- Notepad (Start Menu – All Programs – Accessories – Notepad).

- Calculator (Start Menu – All Programs – Tools – Calculator).

- IPMI Monitor (Start Menu – All Programs – Tools – IPMIMonitor): Offers the possibility to view
motherboard integrated sensors.

- Paint (Start Menu – All Programs – Tools – Paint).

- Problem Step Recorder (Start Menu – All Programs – Tools – psr): Tool to makes a visual and text-
based documentation of everything that happens on the Cortex Unit while you’re recording.

- Regedit (Start Menu – All Programs – Tools – Regedit): Offers the possibility to modify the Cortex
application registry (HKEY_LOCAL_MACHINE\SOFTWARE\IN-SNEC).

- Touch Screen Utility (Start Menu – All Programs – Tools – TouchUtility).

- Wordpad (Start Menu – All Programs – Tools – Wordpad).

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4.5 CORTEX HDR GUI

4.5.1 Conventions &Warnings
IN THE FOLLOWING SECTIONS, EACH CONFIGURATION PARAMETER, STATUS OR ALARM

IS RED-MARKED WITH THE NAME OF A CORTEX « UNIT ». THIS MARK ALLOWS TO LOCATE THE

PARAMETER, STATUS OR ALARM IN THE ETHERNET INTERFACE CONTROL DOCUMENT IN ANNEX 1.

The following marks are used :

 (SWID) : Refer to the Software & ICD Version ID table

 (GLOB) : Refer to the Global CORTEX table
 (DMU) : Refer to the Demodulator Unit table
 (DPU) : Refer to the Data Processing Unit table
 (DCU) : Refer to Diversity Combining Unit table
 (TSTU) : Refer to the Test Modulator Unit table
 (DRG) : Refer to the Data Recording Global table
 (DRU) : Refer to the Data Recording Unit table
 (PLBK) : Refer to the Playback Unit table
 (PROJ) : Refer to the Project-specific table

PROGRAMMING PARAMETERS DEFINED AS FLOAT VALUES IN THE INTERFACE CONTROL DOCUMENT

CAN BE ENTERED IN FLOAT OR REAL FORMAT (SEE ANNEX 1).

PARAMETERS DEFINED AS INTEGER VALUES MUST BE ENTERED IN REAL FORMAT.

PARAMETERS MARKED « HEX » IN THE GRAPHICAL USER INTERFACE MUST BE ENTERED

IN HEXADECIMAL FORMAT. OTHER PARAMETERS MUST BE ENTERED IN DECIMAL FORMAT.

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4.5.2 Graphical User Interface. Windows Breakdown

TOP LEVEL GLOBAL GLOBAL Demodulator M&C

Demodulation
Time TIME Unit
PHYSICAL DVBS2 / SCCC M&C
LAYER

Miscellaneous CONFIG
BER DMU BER M&C

Project-specific PROJECT
DECODING Data decoders M&C

Available Functions INFORMATION

SPECTRUM Spectrum analyzer M&C

VECTOR Vector analyzer M&C

Disk and Memory

FILTER Filter analyzer M&C
Management

STATUS Frame synchronization &

CADU
data decoding M&C
Data Processing TRANSPORT
CONFIG Unit Transport layer M&C
LAYER

BER DPU BER M&C

LOGGING
Real time telemetry
Logging Capabilities REAL TIME
FRAME transmission
Management
QUICK LOOK Telemetry Quick Look

RECORDING Telemetry recording M&C

GLOBAL

Data Recording FTP FTP M&C

Unit

VIRTUAL Virtual channels

CHANNELS extraction

MODULATION Test modulator M&C

Test Modulation
Unit PCM Test data M&C

ENCODING Data encoders M&C

PHYSICAL DVBS2 / SCCC encoder M&C

LAYER

GLOBAL Playback M&C

Data Playback
Unit FILE Playback data selection

TCP-IP
CLIENTS

ENGINEERING
DISPLAY

Figure 68 : Graphical User Interface: Windows Breakdown

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4.5.3 CORTEX HDR Top-level Windows

4.5.3.1 “Global” Window
4.5.3.1.1 CORTEX HDR ARCHITECTURE & GLOBAL STATUS

The following window appears on the screen after the MCS is connected to the SPS (note that the number of
functional units depends on the selected configuration menu and available licenses) :

  CORTEX HDR architecture:

The window opposite appears on the

screen after setting up a connection to
a CORTEX HDR. It shows the
functional resources corresponding to
the supplied hardware and software.
The CORTEX HDR is composed of
up to five different functional units :

 Demodulator Unit (DMU).

Lower icon is for Demodulator # 1
Upper icon is for Demodulator # 2.

 Data Processing Unit (DPU)

Up to 8 DPU icons available

 Test Modulator Unit (TSTU)

 Data Recording Unit (DRU)

Up to 8 DRU icons available

 Playback Unit (PLBK )

Figure 69 : CORTEX HDR : Global Window

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 Demodulator Unit global status :

Demodulator locked if the LED is green (Carrier PLL and Bit Synchronizer locked - DMU) or unlocked if the
LED is unlit (gray background). The LED turns to red if a serious hardware or software (license) problem is
detected on the demodulation chain.

 Data Processing Unit global status :

Frame synchronizer status: green LED when locked, amber LED in flywheel mode, unlit LED when unlocked
(searching). The LED turns to red if a serious hardware or software problem is detected on the demodulation
chain.

 Data Recording Unit global status :

Recorder status: green LED when recording in progress, unlit LED when recording off. The LED turns to red if
a problem is detected on the recording chain.

 Playback Unit global status :

Playback status: green LED when playback is operating, unlit LED when playback is off The LED turns to red if
a problem is detected on the playback function.

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 TCP-IP data flow status :

Number of clients connected to the Spectral port (SPA) and Vector port (VEC) : none (left), one (middle) or
more than one (right).

 IF inputs status:

Reflects the IF input selection for both demodulators with N for normal input, and A for Alternate input

 Test Modulator global status :

In normal conditions, this LED must be green. The LED turns to red if a serious hardware problem (Test
Modulator failure) or software problem is detected.

 MCS Table update : click on

 CORTEX re-configuration from the MCS Table : click on

 Open the Global Engineering window: click on

 Open the TCP-IP secondary window: click on

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4.5.3.1.2 GLOBAL ENGINEERING W INDOW

To open the Global Engineering window, click on icon

To go back to the standard windows display, click on the Exit key.

The Global Engineering window displays dynamically the current configuration and status of the Cortex HDR in a
single window. The following figure gives an example.

Figure 70 : Global Engineering Window

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4.5.3.1.3 TCP-IP SECONDARY W INDOW

For detailed information on the TCP-IP clients, click on icon :

Figure 71 : TCP-IP Secondary Window

The number of clients connected to each TCP-IP port is displayed in the above window. Each Reset button allows
closure of all the TCP-IP sockets connected to the associated port. The Reset All pushbutton allows closure of all
connections to all ports.

The TCP-IP reset function is password protected: click on and enter the TCP-IP password. Default setting at
delivery : no password. To change the TCP-IP password, see Section 4.3.8).

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4.5.3.2 “Time” Window

From the opposite window, the User can

program time offsets to cope with time-
tagging requirements with local time or UTC
time or GPS time, etc....or to have the day
counter not reset at the beginning of each
year.

Leap years should be declared in this window

to avoid potential loss of lock on the internal
Time Code Reader at the end of the year.

Expected time code must be entered for

proper synchronization of the Time Code
Reader.
Parameters, status and alarms in this window are
described in GLOB.

XL
Figure 72 : CORTEX « Time » Window

4.5.3.2.1 CONTROL

LEAP YEAR Leap year programming (365 or 366 days). Select Yes or No (ensure the external
time code generator setting is identical).

CURRENT OFFSET Configuration parameter and status. Allows to enter a time offset for immediate
application and to read the current time offset. Expressed in seconds (signed
value).
The current time offset is added to the time delivered by the internal Time Code
Reader, for time tagging telemetry frames, range measurements, etc...

DATE OF NEXT At this date, Next Offset 1 will replace the current offset. Expressed in seconds
OFFSET 1 with January 1st 00:00:00 = 0.

NEXT OFFSET 1 This time offset, expressed in seconds (signed value), will become effective
when the current date matches Date of Next Offset 1. See note 1.

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DATE OF NEXT At this date, Next Offset 2 will replace the current offset. Expressed in seconds
OFFSET 2 with January 1st 00:00:00 = 0.

NEXT OFFSET 2 This time offset, expressed in seconds (signed value), will become effective
when the current date matches Date of Next Offset 2. See note 1.
Note that if Date of Next Offset 1 = Date of Next Offset 2, then Date of Next
Offset 2 will be ignored (no offset update : priority to Offset 1).

TIME CODE Expected time code (IRIG-B or NASA-36) or NTP if expected time from an
external NTP server (refer to § 4.4.3.2.3)

Note 1 : At boot up, the current offset value is set to the latest value programmed by the Operator (automatic
adjustment of Current Offset from Next Offset 1 or Next Offset 2 is not memorized by the machine).

4.5.3.2.2 MONITORING

TIME-TAG CODING Time-tag coding in TCP-IP messages :

Code 3 Time-tags are expressed in seconds and microseconds of the
second (integer format).

DECODER STATUS Time Code Reader status : Locked or Unlocked or Flywheel.

4.5.3.2.3 NTP CILENT SET-UP

The HDR XXL is fitted with an NTP client. The activation of the NTP client is done by setting the parameter “TIME
CODE” to “NTP”.

Two parameters are available for the set-up: the address of the server and the time refresh period (Server name or
IP address, Adjustment period in seconds). The time is periodically updated when the HDR is set in
Configuration mode.

These set-up parameters are not directly accessible through the GUI. The setup is done using the tool “uihm.exe”.
This tool is available in the directory C:\Program Files\ZDS\uihm for Windows 7 otherwise C:\Program Files\IN-
SNEC\uihm.

After having started uihm.exe and connected it with the SPS software, the NTP server parameters are available
and can be set following, in the “uihm” window, the path Commands -> Hardware Configuration -> NTP
Configuration:

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4.5.3.3 Time Management Procedures

4.5.3.3.1 LOSS OF TIME CODE OR TIME CODE MISSING
In case of wrong code selection or degraded or missing time code signal, the Time Code Reader remains
unlocked and generates its own time code in flywheel mode. When operating in flywheel mode, time-tagging
accuracy is set by the reference clock (internal or external) performances (see Section 1.6.8.2). Should the time
code be missing at boot up, the time will be initialized from the Windows time.

4.5.3.3.2 LEAP SECOND MANAGEMENT

As the earth’s rotation varies in relationship to atomically maintained time (UTC), it is often necessary to officially
add or delete a second from the UTC time scale. Insertion or removal of leap seconds can occur as often as twice
per year. Pending leap second changes are notified by the Paris-based Bureau International de l’Heure (France).

If data time-tagging on the CORTEX require to be aligned on UTC, then the leap second changes can be made
either on the external Time Code Generator or on the CORTEX.

 Leap second change on the external Time Code Generator :

If the change is made on the Time Code Generator, the Time Code Reader in the CORTEX will loose lock for a
short period of time (typically : 10 seconds) at the very moment the time information, which modulates the time
code signal, is updated.

Ensure that parameters Current Offset, Next Offset 1 and Next Offset 2 are set to 0 to avoid taking twice into
account the leap second change.

 Leap second change :

Should it be mandatory to keep the Time Code Reader permanently synchronized (or if the external Time Code
Generator does not feature leap second entry), the leap seconds entry must be done on the CORTEX instead of
the external Time Code Generator.

Example : let us assume that :

 the current leap second value is 10. Non leap year.

st
 a positive leap second change (new value = 11) has been notified for July 1 , 00 h, 00 mn, 00 s

st
 the CORTEX is started before June 30 , with all time offsets set to 0.

The procedure is as follows (see next figure) :

1. Start the CORTEX and go to the « Time » window.

2. Program the following values:

Current Offset = 10

Date of Next Offset 1 = Date of Next Offset 2 = 15 638 400

Next Offset 1 = 11

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st
3. On July 1 , 00 h, 00 mn, 00 s, check that the Current Offset is automatically set to 11 and that the time-tags
st
are updated accordingly. Note : 15 638 400 = July 1 , 00 h, 00 mn, 00 s = 181 days x 86400.

4. Before December 31st, program the following values :

Date of Next Offset 1 = 31 535 989

Next Offset 1 = - 31 535 989

Date of Next Offset 1 = 0

Next Offset 1 = 11

TIME COUNTING

15 638 400 seconds = 1 year)

(if non leap year)

)
lay
sp
di
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t im
ta
da
N e(
tim e
cte
d od
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X d ed
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De

TIME

At the beginning of next year, force current offset to N seconds

Current offset = 0

N seconds before end of year, force corrected time to 0 for starting new year (Offset = - X seconds)

Leap second entry (N seconds)

Figure 73 : Leap Second Management

4.5.3.3.3 ABSOLUTE TIME REFERENCE

The IRIG-B and NASA-36 time codes are serial time format with the time-of-year coded in Binary Coded Decimal
(BCD) notation as days, hours, minutes and seconds. Years are not coded and the day counter is reset every
st
January 1 , 00 h, 00 mn, 00 s. Time parameters can be programmed so that the day counter will not be restarted
every year.

Example :

 The absolute time reference is January 1st, 1998 at 0 AM.

 The CORTEX is started in the course of 1998 with Current Offset = 0.

The procedure is as follows :

1. Enter : Date of Next Offset 1 = Date of Next Offset 2 = 0

Next Offset 1 = 31 536 000 (year 1998 = 365 days = 31 536 000 seconds)

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st
2. On January 1 , 1999 at 0 AM, check that the Current Offset is set to 31 536 000 and that the time-tags are
updated accordingly (365 days are automatically added to the time-tags). The day counter is equal to 366.

3. In the course of 1999, enter Next Offset 1 = 63 072 000 (year 1999 = 365 days = 31 536 000 seconds).

st
4. On January 1 , 2000 at 0 AM, check that the Current Offset is set to 63 072 000 and that the time-tags are
updated accordingly. The day counter is now equal to 731.

5. Each following year, increment parameter Next Offset 1 by the number of seconds of the current year.

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4.5.3.3.4 ABSOLUTE REFERENCE TIME & LEAP SECOND MANAGEMENT

The following scenario is a combination of the two previous scenarios.

Example :

 The absolute time reference is January 1st, 1998 at 0 AM.

 The CORTEX is started on January 1st 1999 at 0 AM with Current Offset = 0.

 The current leap second value is 10.

The procedure is as follows :

1. Enter : Date of Next Offset 1 = 3600

Next Offset 1 = 31 536 010 (one non leap year + 10 seconds)

st
2. On January 1 , 1999 at 1 AM, (3600 seconds after boot up) check that the Current Offset is set to 31 536 010
and that the time-tags are updated accordingly. The day counter is now equal to 366.

3. In the course of 1999, enter :

Date of Next Offset 1 = 0 (January 1st 2000)

Next Offset 1 = 63 072 010 (two non leap years + 10 seconds)

Next Offset 2 = Date of Next Offset 2 = 0

st
4. On January 1 , 2000 at 0 AM, check that the Current Offset is set to 63 072 010 and that the time-tags are
updated accordingly. The day counter is now equal to 731.

5. Repeat step 3 every following year.

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4.5.3.4 “Config.” Window

From the window opposite, the User can

monitor & control miscellaneous system
parameters.

Parameters, status and alarms in this window

are described in GLOB.

Figure 74 : CORTEX HDR : Config. Window

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When the HDR XXL is fitted with the

extension board, a third field for the Menu
number selection is available “Ext”.

Figure 75 : CORTEX HDR : Config. Window with Extension Board

4.5.3.4.1 CONTROL

UNIT MOUNTED Identification of the mounted units in the current configuration. A green LED
indicates that the unit is mounted and enabled. A unit can be enabled or disabled
by clicking in the associated selection box:
DMU: Demodulator Unit
DPU: Data Processing Unit
DRU: Data Recording Unit
TSTU: Test Modulator Unit
PLBK: Playback Unit

TESTS NUMBER Reserved for internal tests.

MONITORING FLOW ID Identification of the monitoring data flow. This value is reported in all TCP-IP
messages transmitted over the Monitoring port (MON). Enter any hexadecimal
value from 0 to FFFFFFF. The Flow ID value in the incoming monitoring

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requests must match the programmed value.

LOGGING FLOW ID Identification of the logging flow. This value is reported in all TCP-IP messages
transmitted over the Logging port (LOG). Enter any hexadecimal value from 0
to FFFFFFFF.

CABLE Determines the evaluated loss (in dB) due to cables among the propagating path.
COMPENSATION This value is reported in the calculation of the compensating filter’s coefficients.
Enter any value from 0 to 12 (Option)

REFERENCE Selection of the frequency reference internal or external.

FREQUENCY

CONFIGURATION The easier way to configure the unit is to load the selected MCS file (refer to
MENU paragraph 4.3). As soon as the MCS file is loaded, the unit can automatically
load the firmware corresponding to this MCS file.
The Configuration Window allows the User to force the selection of a basic
menu and gives also indications about the status of the selection an loading
operations.
In manual mode (Mode: On Request or On Accept) the operator can input in the
field: Menu Nbr the numbers of a basic menus (Demodulator, test Modulator
and the optional Extension board when present). If the operation mode is set to
On Accept, the loading will be effective only after having clicked the button
Accept Request Menu
In automatic mode (Automatic or Automatic with Accept) the basic menu
corresponding to the current configuration is selected automatically and its
number is displayed in the Recommended status field. If the operational mode is
set to Automatic with Accept, the loading will be effective after having clicked
the button Accept Requested Menu.

In all cases the number of the current and active basic menu is displayed in the
Active status field.
A status field indicates if the menu is being loaded or has been loaded and is
ready to operate. This status is displayed in the Configuration Window and in
the upper right corner of the Global Window:

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For detailed information on the current configuration and the possible basic menus, click on icon to acces
the help windows:

Figure 76 : Configuration help Window for the Demodulator

Figure 77 : Configuration help Window for the Test Modulator

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The help windows recall inside a single table the capabilities of each basic hardware menu available for the
demodulator, the test modulator and the optional extension board.

The tables indicate also which basic menu(s) is or are authorized for the current loaded configuration: green or
yellow columns (green: full compliance between the menu and the loaded configuration, yellow: full compliance
only for the demodulation channel #1). For the other non authorized menus, a red stamp is applied on the
function(s) or performance(s) which do not match what is required by the loaded configuration.

4.5.3.4.2 MONITORING

 Demodulator board : software ID. From left to right :

DSP software version : Edition (2 digits) + Revision (2 digits).
DSP software : build number (4 digits).

 Demodulator board : Hardware ID.

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4.5.3.5 “Project” Window

From the window opposite, the User can
monitor & control parameters, status and
alarms that have been implemented from
Customer-specific requirements. Should
be all zeros for the standard CORTEX HDR
product.

Unless otherwise specified, parameters,

status and alarms in this window are
described in PROJ.

Figure 78 : CORTEX HDR : Project Window

4.5.3.5.1 CONTROL

PARAMETER 1 to 32 32 project-specific parameters (project-specific parameters are described in

Annex 5).

4.5.3.5.2 MONITORING

From left to right:

 CORTEX HDR number (GLOB).

 Software and Ethernet ICD version ID (SWID).
 Project ID. 0 for generic CORTEX HDR. Other values reserved for custom design (see Annex 5).

STATUS 1 to 32 32 project-specific status & alarms. (project-specific status and alarms are
described in Annex 5).

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4.5.3.6 “Information” Window

From the window opposite, the User can
check the availability of the different
functionalities of the CORTEX HDR.

Some functionalities are menus and licenses

dependent refer to paragraph Licenses and
Basic Menus.

Figure 79 : CORTEX HDR : Information Window

An other way to check the availability of the functionalities is to position the mouse cursor on the Function status in the
different windows

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4.5.4 Demodulator Windows

4.5.4.1 “Global” Window

 BPSK, QPSK Modulation,I&D filter :

Figure 80 : Demodulator : Global Window for QPSK Modulation + I & D Filter

 BPSK, QPSK Modulation, Raised cosine filter :

Figure 81 : Demodulator : Global Window for QPSK Modulation + Raised Cosine Filter

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 BPSK, QPSK Modulation, custom filter :

Figure 82 : Demodulator : Global Window for QPSK Modulation + Custom Filter

 OQPSK (SQPSK) Modulation :

Figure 83 : Demodulator : Global Window for OQPSK Modulation

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 GMSK Modulation :

Figure 84 : Demodulator : Global Window for GMSK Modulation

 SOQPSK Modulation :

Figure 85 : Demodulator : Global Window for SOQPSK Modulation

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 UQPSK Modulation :

Figure 86 : Demodulator : Global Window for UQPSK Modulation

 8PSK Modulation :

Figure 87 : Demodulator: Global Window for 8PSK Modulation

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 16QAM Modulation :

Figure 88 : Demodulator: Global Window for 16QAM Modulation

 16APSK Modulation :

Figure 89 : Demodulator: Global Window for 16APSK Modulation

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 32APSK Modulation :

Figure 90 : Demodulator: Global Window for 32APSK Modulation

 64APSK Modulation :

Figure 91 : Demodulator: Global Window for 64APSK Modulation

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 VCM QPSK / 8PSK Modulation :

Figure 92 : Demodulator: Global Window for VCM QPSK / 8PSK

 DVB-S2 / SCCC Modulation :

Figure 93 : Demodulator: Global Window for DVB-S2 /SCC

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 Multi-DPU Modulation (16QAM or QPSK) :

Figure 94 : Demodulator: Global Window for Multi-DPU Operation

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4.5.4.1.1 CONTROL
Parameters in this window are described in DMU.

4.5.4.1.1.1 IF PROCESSING

INPUT PORT IF input port selection.

For 1.2 GHz input: IF1 Nom (1.2 GHz), IF1 Alt (1.2 GHz)
For 720 MHz inputs: IF2 Nom (720 MHz), IF2 Alt (720 MHz), IF3 Nom (720 MHz)
or IF3 Alt (720 MHz)

INPUT FREQUENCY Expected IF 520 to 920 MHz (720 MHz IF input) or 900 to 1500 MHz (1.2 GHz IF
input). expressed in Hz. Enter any value in float or real format. Example: for 720 MHz,
type: 72e+7 or 720000000. The programmed value is always displayed in float format.
Resolution step : 32-bit float format.

ACQUISITION RANGE Carrier acquisition peak range (from the expected carrier frequency) and PLL tracking
range. Expressed in Hz. Enter any value from 10,000 to 1e6. Select a value that takes
into account the frequency offset in the worst operational conditions. (Doppler,
frequency uncertainties, etc.).

Carrier acquisition can be restarted at any moment by clicking on .

DEMODULATION  BPSK BPSK demodulation.

 QPSK QPSK demodulation.
 OQPSK OQPSK or SQPSK or SOQPSK demodulation.
 UQPSK UQPSK or AQPSK, AUQPSK, AUSQPSK demodulation
 8PSK 8PSK demodulation
 16QAM 16 QAM demodulation
 16APSK 16 APSK demodulation
 32 APSK 32 APSK demodulation
 64 APSK 64 APSK demodulation
For GMSK Select OQPSK + Matched filter = GMSK and then enter BTs value
For SOQPSK Select OQPSK + Matched filter = SOQPSK and then select the
dedicated filter

VCM - 8PSK/OQPSK Enable the automatic switch function between 8PSK and OQPSK demodulation. This
function is only available with OQPSK and 8PSK modulation. In this mode, the
programmed symbol rate is constant.

BIT RATE Telemetry bit rate. Expressed in bps. Enter any value from 1e6 to the maximum
admissible bit rate (license, modulation and firmware are menu dependent)
OR
Important : if the data are convolutionally encoded, enter the bit rate at the Viterbi
SYMBOL RATE
decoder input (bit synchronizer output).

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In DVB-S2, SCCC and VCM modes, the Bit Rate is replaced by the Symbol Rate

PCM CODE Telemetry PCM coding technique : NRZ-L/M/S, DNRZ, Bi-P-L/M/S, NRZ-M Merge
Important : if NRZ-M Merge is selected, the NRZ-M to NRZ-L decoding is performed
after the merging of the data coming from I and Q. If NRZ-M is selected the decoding
is performed separately on I and Q before data merging.

RANDOMIZER Auto-synchronized de-scrambler:

 Disable de-randomizer disabled
 Worldview Worldview type (menu 11 only)
 CCITT V.35 Menu 3 only
 Intelsat V.35 Menu 3 only

I/Q POLARITY For QPSK, 16QAM and n-APSK modulations:

 Normal Direct I & Q
 I Inverted I inverted, direct Q
 Q Inverted direct I, Q inverted
 I/Q Inverted I &Q inverted
 Swap Normal I&Q swapped & direct
 Swap I Inv. I&Q swapped, I inverted & direct Q
 Swap Q Inv. I&Q swapped, direct I & Q inverted
 Swap I/Q Inv. I&Q swapped & inverted
 Ambig DPUA (B) Ambiguity resolution by DPU A (B)
 Ambig DPUC (D) Ambiguity resolution by DPU C (D)
 Ambig DPUA+C (B+D) Ambiguity resolution by DPU A&C (B&D)
 Ambig BER Ambiguity resolution by the BER tester
 Ambig 4DPU Ambiguity resolution by 4 DPU (specific menu 16)
 Ambig 8DPU Ambiguity resolution by 8 DPU (specific menu 16)
For 8PSK modulation:
 Normal Direct output (no rotation)
 Rot 45° 45° rotation of the 8PSK phase constellation
 Rot 90° 90° rotation
 Rot 135° 135° rotation
 Rot 180° 180° rotation
 Rot 225° 225° rotation
 Rot 270° 270° rotation
 Rot 315° 315° rotation
 Ambig DPUA (B) Ambiguity resolution by DPU A (B)
 Ambig DPUC (D) Ambiguity resolution by DPU C (D)
 Ambig DPUA+C (B+D) Ambiguity resolution by DPU A&C (B&D)
 Ambig BER Ambiguity resolution by the BER tester

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 Ambig 4DPU Ambiguity resolution by 4 DPU (specific menu 16)

 Ambig 8DPU Ambiguity resolution by 8 DPU (specific menu 16)

Note: DPU A and DPU C are connected to DMU 1. DPU B and DPU D are connected
to DMU 2
Note: with the specific basic menu # 16, all DPU (up to 8) are connected to the only
available demodulator DMU 1

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OUTPUT CLOCK Clock polarity : Normal, Inverted or Dual Edge

OUTPUT MODE Data output mode :

 Merged I & Q Channels are interleaved on a single output
 Split 2 I & Q Channels each on 2 separate outputs
 Split 4 Data are distributed over 4 separate outputs
 Normal Soft bits
 Merge Soft bits
 CADU DPU A (B) + sync + user
 CADU DPU A (B) + sync + good
 CADU DPU A (B) + split2 + sync
 CADU DPU C (D) + sync + user
 CADU DPU C (D) + sync + good
 CADU DPU C (D) + split2 + sync
 CADU DPU A (D) + CADU C (D)
 CADUs + Clock All CADUs data at the output of DPU and Clock are
distributed on HDR outputs (specific menu 16)
 CADUs + User Clock All CADUs data at the output of DPU and
Clock are distributed on HDR outputs the clock is present only with the
useful data (specific menu 16)
 Good CADUs + User Clock All good CADUs data at the output of
DPU and Clock are distributed on HDR outputs the clock is present
only with the useful data (specific menu 16)
 Split 8 Data at the output of DMU are distributed over 4 separate
HDR outputs (specific menu 16)
 Playback Merge To be used jointly with the Playback function
 Playback Split2 To be used jointly with the Playback function

Note: DPU A and DPU C are connected to DMU 1. DPU B and DPU D are
connected to DMU 2

PLL BW AUTO Selection of the PLL BW automatic adjustment.

If not selected , a value must be set from 1 to 255, with unit: 0.01 % of the bit
rate

EBN0 MIN AUTO Selection of the automatic adjustment of the acquisition threshold.
If not selected , a value must be set from –3 to 10 dB, with unit: 1 dB

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In OQPSK mode, the following additional parameters appear at the GUI for controlling the I/Q delay
compensation :

OQPSK I/Q DELAY OQPSK I/Q delay compensation :

 OFF No compensation
 ON (Auto) Automatic compensation
 ON (Fixed) Fixed compensation (see I / Q shift parameter)

I/Q SHIFT When OQPSK I/Q DELAY is set to ON (Fixed) :

I/Q delay compensation : enter any value from -0.25 to +0.25 (symbol)
Enter 0 for no compensation (optimal OQPSK)

Important : in UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, parameters BIT RATE, PCM CODE and
OUTPUT CLOCK described here above are for the I Channel. The following additional parameters appear at the
GUI for controlling the Q Channel :

BIT RATE Q Telemetry bit rate for the Q Channel. Expressed in bps. Enter any value from
1e6 to 480.e6 (model dependent)
In AQPSK mode, the I Channel bit rate is supposed to be higher or equal to the
Q Channel bit rate.

PCM CODE Q PCM code on the Q Channel : NRZ-L/M/S, DNRZ, Bi-P-L/M/S

OUTPUT CLOCK Q Clock polarity for the Q Channel : Normal or Inverted

I/Q RATIO Power ratio between I Channel & Q Channel in dB : from 0 to 100

In 8PSK mode, the following additional parameters appear at the GUI:

PHASE ROTATION Select CCSDS (Counter Clock Wise) or Inverted (Clock Wise). (see section
3.6.2.4)

8PSK MAPPING Select Natural, Natural2, Gray1, Gray2, Gray3, Gray4, Gray5 or Gray6
mapping (see section 3.6.2.4)

In 16QAM mode, the following additional parameter appears at the GUI:

16QAM MAPPING Select Map 1, Map 2 or Map 3(see section 3.6.2.4)

In 16APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 16APSK constellation

16APSK MAPPING Select Map 1 or Map 2 (see section 3.6.2.4)

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In 32APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 32APSK constellation

GAMMA2 Allow to adjust R3/R1 of the 32APSK constellation

In 64APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 64APSK constellation

GAMMA2 Allow to adjust R3/R1 of the 64APSK constellation

GAMMA3 Allow to adjust R4/R1 of the 64APSK constellation

In DVB-S2 and SCCC modes, the demodulation mode is controlled from the Physical Layer window.

In Multi DPU mode, the following additional parameter appears at the GUI:

DPU MAP Select 0 or 1 for th emulti-DPU processing mapping (refer to paragrah 3.4.13)

4.5.4.1.1.2 FLOW ID. (HEX)

SPECTRUM Identification of the Spectrum data flow. This value is reported in all TCP-IP
messages transmitted over the Spectrum Analysis Data port (SPA). Enter any
hexadecimal value from 0 to FFFFFFFF

VECTOR Identification of the Vector Analysis data flow. This value is reported in all
TCP-IP messages transmitted over the Vector Analysis Data port (VEC). Enter
any hexadecimal value from 0 to FFFFFFFF

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4.5.4.1.1.3 MATCHED FILTER

FILTER Bit synchronizer filter. Satellite-dependent parameter :

 Integral Integral & Dump
 Raised Raised Cosine (See Roll-off)
 Root Raised Root Raised Cosine (See Roll-off)
 Custom Custom filters (See Fir Cust. Nb)
 GMSK GMSK filters (See BT)
 SOQPSK SOQPSK filters (See SOQPSK Norm)

ROLL-OFF Filter roll-off factor: enter any value from 0.1 to 1.0.

FIR CUSTOM NB FIR custom Number : enter any value from 1 to 1000.

BT FACTOR GMSK Filter BT factor : 0.25 or 0.5.

SOQPSK NORM  MIL MIL standard filter

 TG IRIG standard filter (IRIG standard 106-04)
 A CCSDS A-type filter (CCSDS 413.0-G-1)
 B CCSDS B-type filter

ASYM Select asymmetrical FIR coefficients, else symmetrical FIR coefficients are
applied.

COMP Select complex FIR coefficients, else real FIR coefficients are applied
(dependent of the other FIR characteristics selections).

ODD Select odd FIR coefficients, else even FIR coefficients are applied.

4*SR Select the sample rate of the FIR filter as 4 time the symbol rate, else 2 time the
symbol rate is applied.

DEAF Select the DEAF mode (Digital Equalization Automatic Filter).

CMA / LMS Select the algorithm of the DEAF function. It is recommended to use the LMS
algorithm for the reception of frequency non symmetrical signals.

FAST Select fast DEAF computation.

XDEAF Select the automatic cross-polarization compensation function.

4.5.4.1.1.4 OPTIONAL REJECTION FILTER

LPF Select additional Low Pass Filter +/- 128 MHz bandwidth

HBF Select additional rejection filter

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4.5.4.1.2 MONITORING
Status and alarms in this window are described in DMU

4.5.4.1.2.1 UPPER BANNER

PLL Demodulator global status:

 Locked green
 Unlocked red

BIT SYNC Bit Synchronizer status:

 Locked green
 Unlocked red

BIT SYNC Q Bit Synchronizer status for Q Channel (for UQPSK configuration) :
 Locked green
 Unlocked red

VITERBI DECODER Viterbi decoder status for I & Q Channels (logical AND of the VITERBI DECODER
I and VITERBI DECODER Q status in case of dual Viterbi configuration) :

 Locked
 Unlocked

TCM DECODER TCM decoder status (for 4D-8PSK-TCM configuration) :

 Locked
 Unlocked

FUNCTIONS One or more parameter values do not match the installed licenses, or firmware
capabilities :
 Functions (green) : OK Move the cursor to the status field to see the lists
of available capabilities
 Warning (red) : the requested configuration is not supported. Move the
cursor to the status field to check which parameter is incorrect (Tool Tip).

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4.5.4.1.2.2 OTHER STATUS & ALARMS

IF LEVEL IF carrier level in dBm. The nominal AGC range is from -10 to -50 dBm.
Degraded measurement if the level of the received signal is not within these limits.

CARRIER OFFSET Offset from the expected IF carrier frequency (real frequency - expected
frequency). Expressed in Hz. This value depends both on the oscillator drift (on-
board and ground equipment) and on the Doppler conditions.

BR OFFSET Offset from the expected bit rate (real BR - expected BR). Expressed in bit per
second.
OR
In DVB-S2 and SCCC modes, the Bit Rate Offset is replaced by the Symbol
SR OFFSET
Rate Offset

Eb/No Energy per bit in a 1-Hz noise bandwidth, measured at the bit synchronizer input.
Expressed in dB.
OR
In DVB-S2 and SCCC modes, the Eb/No is replaced by the Es/No (Es: Energy
Es/No
per symbol

In OQPSK mode, the following additional status appears at the GUI for monitoring the I/Q delay compensation :

I/Q SHIFT When OQPSK I/Q delay compensation is :

 OFF No compensation
 ON (Auto) Detected compensation value (Note 1)
 ON (Fixed) Fixed compensation value (Note 1 and 2)

Note 1 : The I/Q shift compensation applies to Q channel (after IF to base-band down-conversion). As the OQPSK
demodulation is ambiguous, the sign of the status changes in accordance with the demodulation ambiguity.

Note 2 : In fixed mode, as the demodulation is ambiguous, both signs are tested and an error estimation is done in
both cases. If the best error value is inferior to a certain threshold, the automate will be locked on this sign. If the
two errors are not acceptable (i.e. if the programmed compensation does not reflect the real delay), the automate
will indefinitely change the sign of the compensation, which is reflected by the sign change of this status. In this
unstable configuration, the I/Q shift value must be refined.

Important : in UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, status BR OFFSET, Eb/No and BIT SYNC
described here above are for the I Channel. The following additional status appears at the GUI for monitoring the
Q Channel :

BR OFFSET Q Offset from the expected bit rate for the Q Channel (real Q Channel BR –
expected Q Channel BR). Expressed in bit per second.

Eb/No Q Energy per bit in a 1-Hz noise bandwidth, measured at the bit synchronizer input
for the Q Channel. Expressed in dB.

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4.5.4.2 “Physical layer” Window

Figure 95: Demodulator : Physical layer window for SCCC and DVB-S2 standard

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4.5.4.2.1 CONTROL
Parameters in this window are described in DMU.

MODE Selection of the demodulation mode :

 OFF Standar fixed demodulation mode
 VHR E/O DVB-S2 Very High Rate DVB-S2 satandard
 SCCC SCCC standard

VCM Enable or not the VCM mode: Automatic detection of the current modulation

MODULATION If VCM mode is disabled, select the demodulation mode

 QPSK
 8PSK
 16APSK
 32APSK
 64APSK

RATE

PILOTS If enabled, indicates that the received physical frames are with pilots

SHORT FRAME If enabled, indicates that the received physical frames are short frames (only
with DVB-S2 standard).

PL SCRAMBLING If enabled, indicates that the received physical frames are randomized.

N-APSK G1, G2, G3 Set the radius ratios of the mapping for the different available APSK modes
(16APSK, 32APSK and 64APSK)

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4.5.4.2.2 MONITORING
Status and alarms in this window are described in DMU

FRAME Counter of the received frames of the physical layer.

DROP OUT Number of drop out events at the physical layer level.

ACM NB Detected current ACM number: Modulation and Coding format (refer to DVB-S2
and SCCC standard).

MODULATION Detected current modulation mode (refer to DVB-S2 and SCCC standard).

CODING RATE Detected current coding rate (refer to DVB-S2 and SCCC standard).

PILOT Presence or not of pilot inside the current received frame (refer to DVB-S2 and
SCCC standard).

SHORT FRAME The received frames are short frames or not (refer to DVB-S2).

BIT RATE Bit Rate in bps of the current received frame.

EB/NO Measured Eb/No in dB.

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4.5.4.3 “BER” Window

Figure 96: Demodulator : BER Window PRN mode

Figure 97: Demodulator : BER Window File mode

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4.5.4.3.1 CONTROL
Parameters in this window are described in DMU.

BER & F/S INPUT  Reserved (Unused). Set to Internal

OPERATING MODE BER measurement mode (simulated data for BER analyzis) :
 Off BER measurement stopped (for reset purposes)
 File Simulated data from a file on the disk (note 1)
 PseudoDxx Pseudo random data, using from PN generator xx
(where xx = 7, 10, 11, 15, 23 or 31. See Section 3.6.2.1)

Note : In File mode, the BER is computed by comparing the original frame to the reconstructed frame from the frame
synchronizer. The BER value is not significant if the frame synchronizer is not correctly configured and locked.

FILE NUMBER File number for BER in file mode : enter any value from 1 to N for each
associated DPU.

BER COUNTER Total number of bits to process for BER measurement in Pseudo mode
Resolution step : 65536 bits. In File Mode, Infinite accumulation.

Reset the BER counter for the active Demodulation window.

(upper banner)

4.5.4.3.2 MONITORING
Status and alarms in this window are described in DMU

4.5.4.3.2.1 UPPER BANNER

See section 4.5.4.1.2.1.

4.5.4.3.2.2 OTHER STATUS & ALARMS

For BER measurement in PRN mode, on I & Q merged and if the demodulation mode is not UQPSK :

BER I + BER Q Display a BER value between 0 and 1, or

No data if the demodulation chain is unlocked or if the total number of bits
regenerated by the bit synchronizer is less than the programmed value for
parameter BER Counter.

NUMBER OF ERROR I + Q Number of bits in error since the BER counter was reset.

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If Separate I/Q BER display requested or in UQPSK demodulation :

BER I Display a BER value between 0 and 1, or

No data if the demodulation chain is unlocked or if the total number of bits
regenerated by the bit synchronizer is less than the programmed value for
parameter BER Counter.

NUMBER OF ERROR I Number of bits in error since the BER counter was reset.

BER Q Display a BER value between 0 and 1, or

No data if the demodulation chain is unlocked or if the total number of bits
regenerated by the bit synchronizer is less than the programmed value for
parameter BER Counter.

NUMBER OF ERROR Q Number of bits in error since the BER counter was reset.

For BER measurement in File mode, for each associated DPU :

BER DPU N Display a BER value between 0 and 1, for DPU #N

NUMBER OF ERROR DPU N Number of bits in error since the BER counter was reset for DPU #N

Note : From this window, by clicking on “Show DPU Details”, it is possible to view the BER values computed at the
output of each DPU associated with the DMU and the used BER mode.

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4.5.4.4 “Decoding” Window

For BPSK, QPSK, OQPSK, UQPSK modulations, ½ and ¼ Viterbi decoder are available (if licence purchased) :

½-based, punctured Viterbi are available too :

 BPSK Modulation :

Figure 98 : Demodulator : Decoding Window for BPSK Modulation

 QPSK or OQPSK (SQPSK) Modulation : Viterbi single

Figure 99 : Demodulator : Decoding Window for QPSK & OQPSK Modulation (Viterbi Single)

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 QPSK or OQPSK (SQPSK) Modulation : Viterbi dual

Figure 100 : Demodulator : Decoding Window for QPSK & OQPSK Modulation (Viterbi Dual)

 UQPSK (AQPSK, AUQPSK, AUSQPSK) Modulation :

Figure 101 : Demodulator : Decoding Window for UQPSK Modulation

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For 8PSK modulation, TCM decoder is available (license dependent) :

 8PSK Modulation :

Figure 102 : Demodulator : Decoding Window for 8PSK Modulation

4.5.4.4.1 CONTROL
Parameters in this window are described in DMU.

TCM DECODER TCM decoder setting , in 8PSK mode:

 Off TCM disabled
 2.00/3 TCM 2.00 enabled
 2.25/3 Not implemented today
 2.50/3 TCM 2.50 enabled
 2.75/3 TCM 2.75 enabled
Inportant : TCM and Viterbi decoding are mutually exclusive.

VITERBI DECODER Viterbi decoder setting for the I Channel in BPSK or UQPSK (AQPSK, AUQPSK,
AUSQPSK) mode or for both I & Q Channels in QPSK, OQPSK (SQPSK) mode :
 Off Viterbi decoder disabled
 G1 G2 Inv Viterbi decoder enabled with G2 inverted. G1transmitted first
(CCSDS recommendation)
 G1G2 Viterbi decoder enabled with G2 normal. G1 transmitted first.
 G2 InvG1 Viterbi decoder enabled with G2 inverted. G2 transmitted first
 G2 G1 Viterbi decoder enabled with G2 normal. G2 transmitted first
Refer to the CCSDS recommendations for “G2 Normal/ G2 Inverted” definition.

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VITERBI DECODING Viterbi decoder setting in QPSK, OQPSK (SQPSK) mode :

 Single- 1 I+Q Single Viterbi decoder common to I & Q Channels
 Dual – nI / nQ Separate Viterbi decoders for I & Q Channels, n is the number
of parallel decoders and can be selected between 1 and 16.
See Section 1.6.1.5 for more details

VITERBI Viterbi puncturing setting for I Channel in BPSK or UQPSK (AQPSK, AUQPSK,
PUNCTURING AUSQPSK) mode or for both I & Q Channels in QPSK, OQPSK (SQPSK) mode :
 Off Viterbi puncturing disabled
 ON ( registry) Puncturing scheme defined in registry.
 2/3 2/3 Viterbi
 ¾ (conv.1) 3/4 Viterbi (convention 1)
 ¾ (conv.2) 3/4 Viterbi (convention 2)
 4/5 4/5 Viterbi
 5/6(conv.1) 5/6 Viterbi (convention 1)
 5/6(conv.2) 5/6 Viterbi (convention 2)
 6/7 6/7 Viterbi
 7/8 (conv.1) 7/8 Viterbi (convention 1)
 7/8 (conv.2) 7/8 Viterbi (convention 2)
 1/4 Esrin 1/4 Viterbi (ESA / ESRIN type)

VITERBI DECODER Q Viterbi decoder setting for Q Channel in UQPSK (AQPSK, AUQPSK, AUSQPSK)
mode :
 Off Viterbi decoder disabled
 G1 G2 Inv Viterbi decoder enabled with G2 inverted. G1transmitted first
(CCSDS recommendation)
 G1G2 Viterbi decoder enabled with G2 normal. G1 transmitted first.
 G2 InvG1 Viterbi decoder enabled with G2 inverted. G2 transmitted first
 G2 G1 Viterbi decoder enabled with G2 normal. G2 transmitted first
Refer to the CCSDS recommendations for “G2 Normal/ G2 Inverted” definition.

VITERBI Viterbi puncturing setting for Q Channel in UQPSK (AQPSK, AUQPSK, AUSQPSK)
PUNCTURING Q mode :
 Off Viterbi puncturing disabled
 ON ( registry) Puncturing scheme defined in registry.
 2/3 2/3 Viterbi
 3/4 (conv.1) 3/4 Viterbi (convention 1)
 3/4 (conv.2) 3/4 Viterbi (convention 2)
 4/5 4/5 Viterbi
 5/6(conv.1) 5/6 Viterbi (convention 1)
 5/6(conv.2) 5/6 Viterbi (convention 2)
 6/7 6/7 Viterbi

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 7/8 (conv.1) 7/8 Viterbi (convention 1)

 7/8 (conv.2) 7/8 Viterbi (convention 2)
 1/4 Esrin 1/4 Viterbi (ESA / ESRIN type)

4.5.4.4.2 MONITORING
4.5.4.4.2.1 UPPER BANNER
See section 4.5.4.1.2.1.

4.5.4.4.2.2 OTHER STATUS & ALARMS

 For TCM configuration :

BER TCM Bit Error Rate (must be 0 if no error detected). Important : the BER is
analyzed at the bit synchronizer output (before TCM decoding)

TCM DECODER TCM decoder status :

 Locked
 Unlocked
 Disabled

 For single Viterbi configuration :

BER Viterbi Bit Error Rate (must be 0 if no error detected). Important : the BER is
analyzed at the bit synchronizer output (before Viterbi decoding)

VITERBI DECODER Viterbi decoder status :

 Locked
 Unlocked
 Disabled

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 For dual Viterbi configuration :

BER I Viterbi Bit Error Rate on I Channel (must be 0 if no error)

BER Q Viterbi Bit Error Rate on Q Channel (must be 0 if no error)

VITERBI DECODER I Viterbi decoder status for I Channel :

 Locked
 Unlocked
 Disabled

VITERBI DECODER Q Viterbi decoder status for Q Channel :

 Locked
 Unlocked
 Disabled

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4.5.4.5 “Spectrum” Window

Figure 103 : Demodulator : Spectrum Window

 Starting the Spectrum Analyzer :

 In the Demodulator Spectrum window, click on Enable. A TCP-IP connection is opened to the Spectrum

port (SPA). To close the connection, click on Disable or click on icon or exit the Spectrum window.

 Selecting the video average display mode :

In the Demodulator Spectrum window, click on Vid Avg En.. The averaging mode display is selected. To
return to the non averaging display mode , click on Vid Avg Dis..

 Level Scale Adjust :

 Adjust the signal level scale (vertical toolbar) from 0.1 to 10 dB/division.

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 Reference Level Adjust :

 Adjust the reference signal level from 0 dBm to –60 dBm.

 Marker Setting & Center Frequency Selection :

 Clicking in the spectrum, with the left key of the mouse, will set a red marker. The signal frequency and
level at this point is displayed in the window entitled Center Frequency Selection (F1 marker).
To center the spectrum on frequency F1 :
- Click on CONFIG,
- Set the red marker with the left key of the mouse,
- Click on F1 marker,
- Click on APPLY.
 Clicking in the spectrum, with the right key of the mouse, will set a green marker. The signal frequency and
level at this point are displayed in the next window under F2 marker. To center the spectrum on frequency
F2, follow the above procedure using F2 marker.

 The frequency and level offsets between markers F1 and F2 are displayed in a separate window :

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4.5.4.6 “Vector” Window

 BPSK Modulation :

Figure 104 : Demodulator : BPSK Vector Window

 QPSK, OQPSK (SQPSK) or UQPSK Modulation :

Figure 105 : Demodulator : QPSK(OQPSK) Vector Window

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 8PSK Modulation :

Figure 106 : Demodulator : 8PSK Vector Window

 16QAM Modulation :

Figure 107 : Demodulator : 16QAM Vector Window

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 16APSK Modulation :

Figure 108 : Demodulator : 16APSK Vector Window

 32APSK Modulation :

Figure 109 : Demodulator : 32APSK Vector Window

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 Starting the Vector Analyzer :

 In the Demodulator Global window (see section 4.5.4.1.1.1), set parameter Mode to Demod.

 In the Demodulator Vector window, click on Enable. A TCP-IP connection is opened to the Vector port

(VEC). To close the connection, click on Disable or click on icon or exit the Vector window.

 Vector display :

 Vectors are transmitted to the local MCS in bursts (TCP-IP packets) of 256 vectors.
 In Single mode, the display is refreshed burst by burst, with all vectors displayed.
 In Cumulative mode, the display is refreshed every 20 bursts only.

 In Average S mode, the MCS displays the average vector value for the received burst of vectors in each
I/Q quadrant.
 In Average C mode, the MCS displays the average vector value for the 20 last bursts of vectors in each I/Q
quadrant.
 Click on the Reset button to reset the display.

 Vector analysis :

 I & Q values and associated signal-to-noise ratio (Eb/No) are displayed for each quadrant.

 Signal analysis :

 IF level gives the level of the input signal.

 Nb Vector gives the number of displayed bursts of vector values.

 Ampli. Err. And Phase Err. give respectively the RMS errors on the Amplitude and phase measurements.

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4.5.4.7 “Filter” Window

 Time Display Mode :

Figure 110 : Filter: Time Display Selection

 Frequency Display Mode :

Figure 111 : Filter: Frequency Display Selection

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Note: The “Filter” Window allows to give a representation of the characteristics of the digital matched filter used in
the demodulation process just before the Bit Decision. Depending on the User’s selection, this representation can
be done in the time domain (pulse response, i.e. taps of the digital filter) or in the frequency domain (amplitude and
phase responses). If the DEAF filter mode is selected, the display is continuously updated with new computed
filter characteristics. The selection of the filter type and consequently its characteristics is done in the “Global”
Window (Matched Filter box).

 Selection of the display mode :

 To select the time domain display mode, click on Time

 To select the frequency domain display mode, click on Frequency

 Control of the DEAF mode :

 To select the auto-adaptive mode and to get a dynamical update display of the filtering characteristics, click

on DEAF

 Saving the filter parameters in a custom filter file (save and learn mode) :

 In DEAF mode Click on Store to freeze the display and to temporary save the filter characteristics in a

buffer.

 Select a filter file number from 0 to 1000, this number will be used to recall the custom filter in the DEMOD

global window.

 Click on Save to store the filter parameters in the selected custom file.

 Level Scale Adjust :

 Adjust the signal level scale (vertical toolbar).

 Reference Level Adjust :

 Adjust the reference signal level.

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4.5.5 Data Processing Unit Windows

4.5.5.1 “CADU” Window

Figure 112 : DPU : CADU Window

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Position the mouse cursor on Function to see which DPU-related licenses are available.

Depending on the available option (DVB Transport Layer, CCSDS Reed Solomon, or LDPC decoding), the right
low part of the window lets appear the status of the corresponding function: RS DVB Status, Reed Solomon Status
or LDPC Status.

4.5.5.1.1 CONTROL
Parameters in this window are described in DPU.

FRAME SYNC. Click on the check box to enable or disable the frame synchronizer :

Enable Frame synchronizer ON. Minor frames reconstruction

according to the programmed strategy.
Disable Frame synchronizer OFF. Transmission of raw data frames to
the Telemetry Clients.

NRZM DPU Click on the check box to enable or disable the function :

Enable The received data in the DPU are decoded from NRZ-M to
NRZ-L before being sent to the frame synchronizer
Disable No PCM decoding is performed

AUTO AMBIG. Click on the check box to enable or disable the ambiguity resolution operation
by the frame synchronizer :

Enable Automatic Ambiguity Resolution ON.

Disable Automatic Ambiguity Resolution OFF.

LSB FIRST Enable The frame synchronizer works with LSB first byte format
Disable The frame synchronizer works with MSB first byte format

SYNC. WORD Synchronization Word. Enter any 64-bit hexadecimal value (left field = 32 MS
bits, right field = 32 LS bits). MSB-aligned value. Example : If the
Synchronization Word is 1ACFFC1DH, enter 1ACFFC1D00000000H).

SW MASK Synchronization Word mask. Enter any 64-bit hexadecimal value. MSB-aligned
value. « 1 » bits in the mask indicate which bits in the Synchronization Word
must be ignored by the frame synchronizer. Enter 0 for no mask. Example : for
a 32-bit Synchronization word, enter 00000000XXXXXXXXH (no masked bits).

SYNC. WORD SIZE Synchronization Word size, in bits. Must be an integer number of bytes. Enter
8, 16, 24, 32, 40, 48, 56, 64 or 128.
Example : if the Synchronization Word is 1ACFFC1DH, enter 32.
For an non integer number of bytes specification, use the upper integer number
of bytes value and use the mask to meet specification.

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FRAME/BLOCK SIZE Telemetry frame length, in bytes. Enter any integer from 16 to 1048580.
Includes the Synchronization Word.

SYNCHRONIZATION Frame synchronizer strategy :

STRATEGY

SYN Number of errors tolerated in the Synchronization Word. Enter any

integer from 0 to 15.
CTL Check-to-Lock threshold. Number of consecutive occurrences of
correct Synchronization Words before going from the CHECK phase to
the LOCK phase. Enter any integer from 0 to15.
LTS Lock-to-Search threshold. Number of consecutive occurrences of
incorrect Synchronization Words before going from the LOCK phase
to the SEARCH phase. Enter any integer from 0 to 15.
Slip Number of bit slip tolerated for the search of the synchronization word
in LOCK phase. Enter 0, 1 or 2.

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INPUT SELECTION 1 Allows to connect the DPU with the DMU :

DMU 1 Connect the DPU with DMU 1

DMU 2 Connect the DPU with DMU 2
ECL IN Input external data (Data + Clock) in DPU only with menu 30
and 31
Connect the DPU input with the merged I&Q output of the
Merged (I&Q)
selected DMU
Connect the DPU input with the I of the selected DMU
Split 2 (I)
Connect the DPU input with the Q of the selected DMU
Split 2 (Q)
Connect the DPU input with the I of the selected DMU and
Split 2 (I 1/2)
take one data on two
Connect the DPU input with the Q of the selected DMU and
Split 4 (Q 1/2)
take one data on two
Connect the DPU input with the I of the selected DMU and
Split 8 (I 1/4)
take one data on four
Connect the DPU input with the Q of the selected DMU and
Split 8 (Q 1/4)
take one data on four

In1+In2
Both ECL data inputs are merged and sampled on the rising
(rising edge)
edge of the clock
In1
Select ECL data input 1 and sample on the rising edge of the
(rising edge)
clock
In2
Select ECL data input 2 and sample on the rising edge of the
(rising edge)
clock
In1+In2
Both ECL data inputs are merged and sampled on the falling
(falling edge)
edge of the clock
In1
Select ECL data input 1 and sample on the falling edge of the
(falling edge)
clock
In2
Select ECL data input 2 and sample on the falling edge of the
(falling edge)
clock

FRAME HEADER RS Header RS(6,10) ENABLE or DISABLE

Reed Solomon decoding of the header of the transfer frames in AOS CCSDS

DESCRAMBLING OFF
CCSDS CCSDS derandomization
Custom Customized derandomization applied before decoding
Custom after decoding Customized derandomization applied after decoding

DESCR. POLY. (HEX) Derandomizer polynomial value, in hexadecimal (16 bits max)

INIT. (HEX) Preset value for the derandomizer, in hexadecimal

DECODING By menu Automatic selection by menu

RS 223 (CCSDS) CCSDS RS (223,255) decoding standard basis

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DVB Transport Layer RS decoding for DVB Transfer Layer

LDPC 7/8 LDPC 7/8 decoding
Worldview RS Specific RS decoding for Worldview satellite
RS 239 (CCSDS) CCSDS RS (239,255) decoding
Turbo decoder Turbo decoder (future release)
LDPC 1/2 LDPC 1/2 decoding
LDPC 2/3 LDPC 2/3 decoding
RS 223 (Dual) CCSDS RS (223,255) decoding dual basis
RS 239 (Dual) CCSDS RS (239,255) decoding dual basis
LDPC 7/8 Transport Layer LDPC 7/8 decoding with Transport Layer
LDPC 1/2 1K Transport Layer LDPC 1/2 (1K) decoding with Transport Layer
LDPC 1/2 4K Transport Layer LDPC 1/2 (4K) decoding with Transport Layer
LDPC 1/2 16K Transport Layer LDPC 1/2 (16K) decoding with Transport
Layer
LDPC 2/3 1K Transport Layer LDPC 2/3 (1K) decoding with Transport Layer
LDPC 2/3 4K Transport Layer LDPC 2/3 (4K) decoding with Transport Layer

FRAME CHECKING CRC 16 Bit CRC enabled

OFF 16 Bit CRC disabled
CRC POLY. (Hex) CRC polynomial value, in hexadecimal. Enter 8005 for a CRC16 (X16 + X15 +
X2 + 1) or 1021 for a CCITT compliant CRC (X16 + X12 + X5 + 1)
CRC PRESET (Hex) Preset value for CRC calculation, in hexadecimal. Enter 0000 for a CRC16 or
FFFF for a CCITT compliant CRC

Note 1 : An input selection not available is indicated by the mention “N/A” .

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Note 2 : Frame synchronizer input selection vs demodulation and Viterbi mode :

QPSK/OQPSK : No Viterbi or dual Viterbi mode Merged I & Q : select Merged (I&Q)
Separate I & Q : select Split 2(I) or(Q)

QPSK/OQPSK : Single Viterbi mode Select Split 2 (I)

BPSK with or without Viterbi Select Split 2 (I)

UQPSK with or without Viterbi Select Split 2 (I) or (Q)

4.5.5.1.2 MONITORING
Status and alarms in this window are described in DPU.

4.5.5.1.2.1 UPPER BANNER

See section 4.5.4.1.2.1.

4.5.5.1.2.2 FRAME SYNCHRONIZER STATUS

FRAME COUNTER Telemetry frame counter. Reset to 0 when the frame synchronizer unlocks or by

clicking on in the upper tool bar (the DPU window must be active).

BIT SLIP Bit slippage measured by the frame synchronizer.

DROP OUT COUNTER Number of loss of lock on the frame synchronizer. Reset to 0 by clicking on
in the upper tool bar (the DPU window must be active).

FRAME CHECK CRC or Check-Sum test result : Alarm or OK. Forced to OK if parameter Frame
Checking is set to Off.

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4.5.5.1.2.3 REED SOLOMON DECODERS STATUS

CORRECTED ERRORS Number of symbols corrected by the Reed-Solomon decoder (average value
computed over a one-second period of time). Displays Exceeded if the maximum
correction capability is reached (number of corrected symbols greater than [16 x
Interleave Factor]).

GOOD FRAMES Number of good transfer frames received from the Reed Solomon decoder. Reset
to 0 when the Frame Synchronizer or the Reed Solomon decoder is set to OFF or

by clicking on in the upper tool bar (the DPU window must be active).

BAD FRAMES Number of bad transfer frames received from the Reed Solomon decoder. Reset
to 0 when the Frame Synchronizer or the Reed Solomon decoder is set to OFF or

by clicking on in the upper tool bar (the DPU window must be active).

BIT ERROR RATE Ratio between the number of corrected bits and the total number of bits processed
by the Reed Solomon decoder. Reset to 0 when the Frame Synchronizer or the

Reed Solomon decoder is set to OFF or by clicking on in the upper tool bar
(the DPU window must be active).
Important : the BER is calculated before Reed Solomon decoding.

4.5.5.1.2.4 LDPC STATUS

CORRECTED ERRORS Number of symbols corrected by the LDPC decoder (average value computed
over a one-second period of time).

GOOD FRAMES Number of good transfer frames received from the LDPC decoder. Reset to 0
when the Frame Synchronizer or the LDPC decoder is set to OFF or by clicking

on in the upper tool bar (the DPU window must be active).

BAD FRAMES Number of bad transfer frames received from the LDPC decoder. Reset to 0 when
the Frame Synchronizer or the LDPC decoder is set to OFF or by clicking on

in the upper tool bar (the DPU window must be active).

BIT ERROR RATE ON Estimation of the BER at the input of the LDPC decoding. Reset to 0 when the
INPUT DATA
Frame Synchronizer or the LPC decoder is set to OFF or by clicking on in
the upper tool bar (the DPU window must be active).

BIT ERROR RATE ON Estimation of the BER at the output of the LDPC decoding. Reset to 0 when the
OUTPUT DATA
Frame Synchronizer or the LDPC decoder is set to OFF or by clicking on in
the upper tool bar (the DPU window must be active).

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4.5.5.1.2.5 CRC STATUS

GOOD FRAMES Number of good transfer frames received from the CRC decoder. Reset to 0 when
the Frame Synchronizer or the Reed Solomon decoder is set to OFF or by clicking

on in the upper tool bar (the DPU window must be active).

BAD FRAMES Number of bad transfer frames received from the CRC decoder. Reset to 0 when
the Frame Synchronizer or the Reed Solomon decoder is set to OFF or by clicking

on in the upper tool bar (the DPU window must be active).

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4.5.5.2 “Transport Layer” Windows

This window is only available with RS DVB and LDPC decoding. It gives the status of the Transport layer.

Figure 113 : DPU : Transport Layer Window (R-S DVB Mode)

4.5.5.2.1 CONTROL (TRANSPORT LAYER W INDOW)

Unless otherwise specified, parameters in this window are described in DPU.

TRANSPORT LAYER Set the Transport Layer ON or OFF

IDLE DISCARDED Discard (ON ) or transmit the idle frames to the CADU frame synchronizer
(OFF)

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4.5.5.2.2 MONITORING (TRANSPORT LAYER W INDOW )

Unless otherwise specified, status & alarms in this window are described in DPU.

DROP OUT COUNTER Number of frame drop-out events at transport layer level

CORRECTED ERRORS Number of bits corrected by the decoder at transport layer level

BIT ERROR RATE Bit error rate at transport layer level

IDLE COUNTER Number of received idle frames at transport layer level

GOOD FRAMES Number of good frames

BAD FRAMES Number of bad frames (could not be corrected)

TRANSPORT LAYER Frame Synchronizer status. From left to right :

Search, Check, Locked or Flywheel
Data or Idle frames

Note : When the frame synchronizer of the CADU layer is lock, the status of the counters in the Transport layer
can be updated or not. That is controlled by a Registry key (PermanentTransportStatus).

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4.5.5.3 “BER” Windows

Figure 114 : DPU : BER Window

4.5.5.3.1 CONTROL
Unless otherwise specified, parameters in this window are described in DPU.

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OPERATING MODE BER measurement mode (simulated data for BER analyzis) :
Off BER measurement stopped
File Simulated data from a file on the
PseudoDxx Pseudo random data, using from PN generator xx
(where xx = 7, 10, 11, 15, 23 or 31)

INVERSE Inverse (Enable) or not (Disable) the data used for BER computation

TESTED DATA User Data Compute the BER only on the User data of the frames
(excluded added check symbols)
Whole Data Compute the BER on all the received data of the frames

FILE NUMBER File number for BER in file mode : enter any value from 1 to N.

BER COUNTER Total number of bits to process for BER measurement in Pseudo mode
Resolution step : 65536 bits. In File Mode, Infinite accumulation.

4.5.5.3.2 MONITORING
Unless otherwise specified, status & alarms in this window are described in DPU.

BER Computed Bit Error Rate

NUMBER OF ERROR Cumulated number of errors

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4.5.5.4 “Real Time Frame” Window

Figure 115 : Data Processing Unit : Real Time Frame Window

4.5.5.4.1 CONTROL
Parameters in this window are described in DPU.

 Ingestion parameters :

FRAME SYNC. Enable or disable the frame synchronizer

TM FLOW ID. Identification of the telemetry flow. This value is reported in all telemetry
messages over the Telemetry port (TM). Enter any hexadecimal value from 0 to
FFFFFFFF.

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 Decommutation :

VIRTUAL CHANNEL Virtual Channels 64-bit mask selection (0 = select, 1 = discard)

VC POSITION Offset, in bits, between the last bit of the synchronization word and the first
bit of the Virtual Channel ID field. Example : enter 0 if the VC ID field
starts right after the synchronization word.

SPARE DATA Select number of spare fields in the TM Block. Enter 0 to 8. See Figure 39 :
Data Transmission over TCP-IP. Message Formatting

 TM block configuration :

SPARE DATA Allows to add spare data (64 bits word) at the end of the TM data blocks
(recorded and transmitted over TCP/IP). Possible values: 0 to 8.

DISABLE FRAME Allows to disable the insertion of the 8 time tag bytes at the end of the TM
DATATION data blocks (recorded and transmitted over TCP/IP)

4.5.5.4.2 MONITORING
Status & alarms in this window are described in DPU.

4.5.5.4.2.1 TCP-IP STATUS

RECEIVED FRAMES Number of demodulated TM Blocks. Reset to 0 when the CORTEX HDR is
restarted.

TRANSMITTED FRAMES Total number of TM Blocks (for all TM Clients) over TCP-IP. Reset to 0
when the CORTEX HDR is restarted or when switching from Acquisition
mode to Configuration mode

OVERRUN Amount of data lost during overrun conditions. Expressed in number of

buffers of TM Packets (one buffer = 8 TM Packets).

4.5.5.4.2.2 FRAME SYNC. STATUS

See section 4.5.5.1.2.2.

4.5.5.4.2.3 UPPER BANNER

See section 4.5.4.1.2.1.

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4.5.5.5 “Quick Look” Window

Figure 116 : Data Processing Unit : Quick Look Window

4.5.5.5.1 CONTROL
Parameters in this window are described in DPU.

ENABLE/DISABLE Enable (the MCS opens a connection to the telemetry port) or Disable the Quick
Look display.
Important : the Quick Look can only be enabled if the Acquisition mode is

selected (click on icon ). Switching back to the Configuration mode is

impossible as long as the Quick Look is enabled.

CLEAR Clear the Quick Look window

SAVE Save the data displayed on the Quick Look to a text file on the disk (click on
SAVE only after the Quick Look has been disabled).

NUMBER OF Frame display rate. Enter any value from 1 to 10 :

CONSECUTIVE
1 : display one frame every second
FRAMES
2 : display two consecutive frames every two seconds
etc…

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4.5.5.5.2 TELEMETRY BLOCKS QUICK LOOK

Telemetry Blocks are displayed back to back on the Quick Look window.

Offset 0000 marks the beginning of a Telemetry Block.

Telemetry Blocks are structured as follows (see section 3.4.11: for more details) :

TM Block 1 Telemetry Frame :

Synchronization Word
TM Block 2
& Data Words
(8 Bytes aligned)

… /…
Time Tag
(8 Bytes)

Status
(8 Bytes)

TM Block N Optionnal spare field

(0 to 8 words
of 8 Bytes)

Figure 117 : Telemetry Block Description

Telemetry frame :

Synchronization Word + telemetry frame (if frame synchronizer ON) or raw data (if frame synchronizer
OFF). At the end of the frame, spare bytes for 8 bytes alignment (if required). These added spare bytes
can have any values.

TM Block time tag (8 bytes) :

Bits D0-31 (offset N) : number of seconds elapsed since January 1st, 00:00:00 of current year

Bits D32-63 (offset N+1) : number of microseconds in the current second

Both 32-bit fields are integers coded in hexadecimal form.

The time tag can be disabled by set-up (refer to “Real Time Frame” window: disable frame datation).

Telemetry Block status (8 bytes) : the Telemetry Block status is captured and displayed in this field only if the
frame synchronizer is ON.

Optional spare field (from 0 to 8 words of 8 bytes) : the number of spare data words (64 bit words) is selected
in the “Real Time Frame” Window. These data words are filled with “00000000” values.

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4.5.5.5.3 MONITORING
Status & alarms in this window are described in DPU.

TIME TM Block time-tag, with the display format :

Day - Hour:Minute:Second.Microsecond

STATUS TM Block status, expressed in hexadecimal.

The left-hand digits of the status corresponds to offset N+4 of the Telemetry
Block Description (see STI 100013_HDR, Table 21).
The right-hand digits of the status corresponds to offset N+5 of the Telemetry
Block Description.

4.5.5.5.3.1 UPPER BANNER

See section 4.5.4.1.2.1.

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4.5.6 Polarization Combining Windows

4.5.6.1 “Global” Window

Figure 118 : Polarization Combining: Global Window

4.5.6.1.1 CONTROL
Parameters in this window are described in DCU

OUTPUT Affects the output of the DCU. Possible values are : DMU1, DMU3
or Combining.

OPERATING MODE Best channel only the best channel is fed to the output

Combining both channels are combined using optimal weigts

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4.5.6.1.2 MONITORING
Status of the channels:

DMU 1/3 Locking state of each channel. Displays “Locked” (green) when the PLL
and the Bit Synchronization loops are locked, “Unlocked” (red)
otherwise.

IF LEVEL IF carrier level. Expressed in dBm.

CARRIER OFFSET Offset from the specified IF carrier frequency (real frequency – expected
frequency). Expressed in Hz.

Eb/N0 Energy per bit in a 1-Hz noise bandwith. Expressed in dB.

Status of the combining:

COMBINING STATUS Locked (green), Check (green), Acquisition (amber), 1-channel (green),
Unlocked (red), N/A (gray).

RELATIVE GAINS Comining weights, expressed in %. In Best Channel mode one weights is
equal to 0, % the other one equals 100 %. The same goes when the unit is
in Single channel state.

EB/N0 Energy per bit in a 1-Hz noise bandwith of the combining unit output.
Expressed in dB.

COMBINING GAINS Gain in energy per bit in a 1-Hz noise bandwith of the combining unit
output. Expressed in dB.

4.5.6.1.3 OTHER STATUS AND ALARMS

The upper right part of the window gives general information concerning the DCU. When everything is configured
right, it displays.

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When an incorrect configuration is detected (different bitrates of both demodulators, same IF input…), the box
displays “Warning” (red). A tool tip is displayed when the pointer stops on the box. Below stands an example of
an incorrect configuration :

4.5.6.2 “BER” Window

This window enables the user to monitor the BER at the output of the combining system. Please refer to the
Demodulator Unit section for further details on this feature.

4.5.6.3 “Decoding” Window

This window enables the user to control and monitor the decoding features (Viterbi, TCM) at the output of the
combining system. Please refer to the Demodulator Unit section for further details on this feature.

4.5.6.4 “Vector” Window

This window enables the user to monitor the constellation at the output of the combining unit. It is the same as the
standard demodulator Vector windows, with the exception of three status (IF level, Amplitude Error, Phase Error)
that do not apply to the combining feature. Please refer to the Demodulator Unit section for further details on this
window.

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4.5.7 Data Recording Unit Windows

4.5.7.1 “Global Disk and Memory Management” Window

In the upper toolbar, click on to open the Disk Partitioning & Memory Allocation window :

Figure 119 : Global Disk & Memory Management Window (Configuration)

Figure 120 : Global Disk & Memory Management Window (Status)

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4.5.7.1.1 CONTROL
Parameters in this window are described in DRG.

 Channels configuration:

DISK AND MEMORY Disk and PC RAM buffer partitioning. For TCP-IP and FTP recording modes,
ALLOCATION % allows to allocate a percentage of the available memory for each mounted TM:
0% to 100 %
FOR EACH MOUNTED
DPU

LOGICAL CHANNEL For FTP mode only, allows for the current pass to select a logical channel (first
level FTP directory) 0 to 255.
FOR EACH MOUNTED
DPU

ACTIVE PARTITION For FTP mode only, allows for the current pass to select the active partition 0 to
64.
FOR EACH MOUNTED
DPU

ACTIVE DISK For FTP mode only, allows for the current pass to select the active disk
CONTROLLER controller 0 or1. In case of one available controller, the value must be set to 0.
FOR EACH MOUNTED
DPU

DISK LATE % Status of the delay during the recording of the data on the disk.

DISK OVERRUN Overrun during the recording of the received data (disk).

MEMORY LATE % Status of the delay during the writing of the received data in the buffer memory.

MEMORY OVERRUN Overrun during the writing of the received data (buffer memory).

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 Disk Management:

MODE In TCP-IP mode only. Select FIFO Mode (permanent recording. The
storage area is structured as a FIFO) or Manual Erase (record data until the
storage area is full, then stop and wait for manual erase of the recorded
session).
Note : it is recommended to use the FIFO mode (with auto-erase) only for
single recording session (auto-erase of the least recent TM Files).

LEVEL PERCENTAGE Warning In FTP mode only. If different from 0, allows to

define a storage level threshold above which a
warning is reported. Value expressed in percentage:
1% to 80%

Alarm In FTP mode only. If different from 0, allows to

define a storage level threshold above which an alarm
is reported. Value expressed in percentage: 1% to
80%.
In case of alarm, the oldest files are deleted until to
obtain a level equivalent to the warning storage level

FILES KEEPING Temporary In FTP mode only. Duration of the temporary storage
for the directories keeping the files declared as NOK
by the filtering operations.
The unity is in days for values between 1 and 128
The unity is in minutes for values between -1 and -
128

Nominal In FTP mode only. Duration of the nominal storage

for the directories keeping the files not declared as
NOK by the filtering operation.
The unity is in days for values between +1 and +127
The unity is in minutes for values between -1 and -
128

Build or Erase Allows to build or erase the files and/or the

directories in FTP mode. This button appears in the
window only when the HDR is set in
“Configuration” mode. When pressed a pop-up
menu appears with all the possible operations.

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 Storage Selection:

Click on to open the Storage Selection window :

To select a storage type click on the corresponding line in the upper window and then click on “Select”.

The proposed standard internal storage is the storage number 2 ( 002_Disk_T_CCSDS ).

Storage types with the label “Disk_T” are used for internal hard disk storage. Storage type with the label “DR2912”
are used for external storage on a RAID 5 DR2912 or ER2912 recorder.

Storage types with the label “Pleiades” are used for specific projects.

Storage number 8 and 9 are reserved for CCSDS Packet data and CCSDS CFDP recording in AOS mode and
Telemetry mode.

 Set default:

Click on to select the current storage number as the default storage number. The following window
will be displayed to confirm:

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4.5.7.1.2 MONITORING
Status & alarms in this window are described in DRG.

STORAGE TYPE Indicates which mode of storage is active example: FTP CCSDS (standard)

MODE CORTEX HDR mode : Configuration or Acquisition.

Important : in the Acquisition mode, the Data Processing Unit(s) cannot be re-
configured. The maximum number of TM Packets per TM file (Data Recording
Unit) cannot be changed. Data Recording Global (DRG) parameters cannot be
changed.

Click on for changing the mode. Switching to Configuration mode is

impossible if a TM Client is connected to the telemetry port (3075) or if telemetry
storage is in progress. Switching to Acquisition mode is impossible if the requested
configuration is incorrect.

SELF TEST In configuration mode, a periodical auto-test is performed on the defined partitions.
This test consists in writing a file in the directories and trying to read it. The result is
OK or Non OK as soon as one partition is in error.

DIRECTORIES Status of the FTP directories.

CONFIGURATION General status of the actual configuration.

OTHER FIELDS Disk partitioning information and status.

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4.5.7.2 “Recording Global” Window

Figure 121 : DRU : Recording Global Window

4.5.7.2.1 CONTROL
Unless otherwise specified, parameters in this window are described in DRU.

START TIME Storage start time : Day-Hour:Minute:Second

STOP TIME Storage stop time : Day-Hour:Minute:Second

TM BLOCK PER FILE Maximum number of TM blocks per recorded File (defines the recorded files
maximum size). If set to 0, the recorded files maximum size will be 2 Gbytes.

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Start writing data to the disk.

Stop writing data.

Show recorded reports (see below).

To access to the erase functions by DRU (Refer to the paragraph “Global Disk and Memory
Management window).

When clicking on the following window appears on the screen :

Select a report by clicking on the corresponding line in the upper window to display the recorded files listing
corresponding to the report.

.
Once the storage is started, the following message appears on the screen :

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If the HDR is set in “Configuration” mode, the following message is display :

The recording cannot be started as long as the HDR is not set in “Acquisition” mode; use the button to switch
from “Configuration” mode to the “Acquisition” mode.

4.5.7.2.2 MONITORING
Status & alarms in this window are described in DRU.

4.5.7.2.2.1 UPPER BANNER

See section 4.5.4.1.2.1.

4.5.7.2.2.2 RECORDER STATUS

 Session Status :

RECORDED DATA Amount of recorded data for the current recording session. Expressed in
Mbytes

NBR. OF RECORDED FILES Recorded TM file number for the current recording session. 0 to N

DATE OF FIRST BLOCK Time-tag of the first recorded TM Block for the current recording session

DATE OF LAST BLOCK Time-tag of the last recorded TM Block for the current recording session

 TM Status :

CTRL/PART Active hard disk controller (0 or 1) / Active hard disk partition (1 to 64)

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 Disk Information :

CAPACITY Total data recording capacity for both hard disk controllers (in Mbytes)

OCCUPIED Occupied capacity for both hard disk controllers (in Mbytes)

FREE Free capacity for both hard disk controllers (in Mbytes)

NUMBER OF SESSION Number of recording sessions on the disk

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 TM Information :

FILE SIZE Size of the TM File (in bytes). This value corresponds to the TM block size
multiplied by the value set in “TM block per”. The maximum value is 4
Gbytes.

FILE HEADER TM File header

BLOCK SIZE TM Block size (in bytes). Up to 1,048, 656 bytes. This value corresponds to
the defined frame (CADU) size plus a few bytes of time tagging and frame
sync. Status.

TIME-TAG FORMAT Time tag format.

3 is the standard code format : field N is the number of seconds elapsed since
January 1st, 0 :00 :00 :000 of current year. Field N+1 is the number of
microseconds in the current second. Both fields are 32-bit integers coded in
hexadecimal form. Other codes reserved.

STATUS FORMAT TM Block status format

NUMBER OF TM FILES Number of TM Files on the disk

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4.5.7.3 “FTP” window

Figure 122 : DRU : FTP Window (Generic)

Figure 123 : DRU : FTP Window (CCSDS standard)

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4.5.7.3.1 CONTROL
Parameters in this window are described in DPU.

 Filtering and sorting :

RS FILTER Enable or disable the filtering of Reed Solomon code blocks in errors.

SORT BAD Enable or disable the sorting of the RS code blocks considered as not corrected

FILTER A Enable or disable the Filter A operation

Offset: Offset in bits in the frame of the position of the word to extract to
compare with the filter A value (0 is the first bit of the synchronization marker)
Size: Size in bits of the word to extract, from 0 to 8
File: Index of the Filter A configuration file, from 0 to 255

SORT A OR VIRTUAL Enable or disable the Sort A operation (Generic mode) or the Virtual Channels
CHANNEL sorting (CCSDS mode)
Offset: Offset in bits in the frame of the position of the word to extract to be
used for the sorting A operation (0 is the first bit of the synchronization marker)
Size: Size in bits of the word to extract, from 0 to 8
File: Index of the Sort A configuration file, from 0 to 255

SORT B Enable or disable the Sort B operation

Offset: Offset in bits in the frame of the position of the word to extract to be
used for the sorting B operation (0 is the first bit of the synchronization marker)
Size: Size in bits of the word to extract, from 0 to 8
File: Index of the Sort B configuration file, from 0 to 255

SORT C Enable or disable the Sort C operation

Offset: Offset in bits in the frame of the position of the word to extract to be
used for the sorting C operation (0 is the first bit of the synchronization marker)
Size: Size in bits of the word to extract, from 0 to 8
File: Index of the Sort C configuration file, from 0 to 255

EXTRACT A Enable or disable the operation of Extract A, the operation is the same as for
Sort A,B and C operations except that it impacts only the files names and not
the directories.
Offset: Offset in bits in the frame of the position of the word to extract to be
used for the Extract A operation (0 is the first bit of the synchronization marker)
Size: Size in bits of the word to extract, from 0 to 8
File: Index of the Extract A configuration file, from 0 to 255

Note: the data values used in the filtering, sorting and extract operations are defined in their
corresponding configuration files selected by the index values.

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 Filename:

The basic name of a recorded file is the date of its creation (default name). From this basic name a number of
programmable markers can be added:

R/W Enable or disable the insertion of the R/W marker in the recorded files
names

CHANNEL Enable or disable the insertion of the selected Logical Channel marker in
the recorded files names (The selection of the logical channel for a recording
session is done in the “Global Disk and Memory Management Window)

EXTRACT A Enable or disable the insertion of the Extract A marker in the recorded files
names

FILE NBR Enable or disable the insertion of the File Number marker in the recorded
files names (counter of the number of generated files during a recording
session inside a dedicated directory)

FILTER RS Enable or disable the insertion of the RS Filter marker in the recorded files
names

FILTER A Enable or disable the insertion of the Filter A marker in the recorded files
names

SORT A OR VIRTUAL Enable or disable the insertion of the Sort A marker (Generic mode) or the
CHANNEL Virtual Channels marker (CCSDS mode) in the recorded files names

SORT B Enable or disable the insertion of the Sort B marker in the recorded files
names

SORT C Enable or disable the insertion of the Sort C marker in the recorded files
names

SPECIFIC PROJECT P1, P2, P3, and P4, hexadecimal values from 0 to FFFFFFFF. Theses
parameters are specific to the project.

PARAMETERS Specific user defined markers. For A, B and C, the corresponding fields
allow to enable or disable the insertion of the marker and to enter the
characters string of the marker (up to 12 characters for each field)

EXTENSIONS Allows for the recorded Data files and the session Report files to define an
extension suffix which will be inserted in the files names

Note: the characters strings markers of the filtering, sorting and extract operation are defined in their
corresponding configuration files.

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4.5.7.3.2 MONITORING
Status & alarms in this window are described in DPU.

4.5.7.3.2.1 SESSION STATUS

DIR. NBR. Number of created directories (up to 64)

NUMBER Directories indexes (DIR00 to DIR63). DIR00 corresponds to the first

directory where sorted TM files are recorded, DR01 to the second directory
and so on..

TOTAL TM BLOCK Total number of TM Blocks for all directories (All line) and for each
directory.(DR00 to DR63 lines)

BAD TM BLOCK Total number of bad TM Blocks for all directories and for each directory

SORT TM FILE Total number of Sort TM files created for all directories and for each
directory

SORT VALUE First four bytes of the last frame data which created the corresponding last
sorting.

4.5.7.3.2.2 UPPER BANNER

See section 4.5.4.1.2.1.

Detailed information for the set-up and operation of the functionality is given in the Recording and FTP
Recovery User Manual DTU 10038.

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4.5.7.4 “Virtual Channels” Window

Figure 124 : DRU : Virtual Channels Window

4.5.7.4.1 CONTROL
None

4.5.7.4.2 MONITORING
4.5.7.4.2.1 VIRTUAL CHANNELS INFORMATION
From left to right :
- Number of good TM Blocks (including corrected ones) for each virtual channel

- Number of bad TM Blocks (could not be corrected)

Click right in the window to select either Session Virtual Channel (display VC information for the current
recording) or TM File Virtual Channel (display VC information for the current TM File).

4.5.7.4.2.2 UPPER BANNER

See section 4.5.4.1.2.1.

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4.5.8 Test modulator Windows

4.5.8.1 “Modulation” Window

 BPSK-QPSK UQPSK Modulations :

Figure 125 : Test Modulator : Modulation Window for BPSK, QPSK and UQPSK

 OQPSK Modulations :

Figure 126 : Test Modulator : Modulation Window for OQPSK

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 8PSK Modulation :

Figure 127 : Test Modulator : Modulation Window for 8PSK

 16QAM Modulation :

Figure 128 : Test Modulator : Modulation Window for 16QAM

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 16APSK Modulation :

Figure 129 : Test Modulator : Modulation Window for 16APSK

 32APSK Modulation :

Figure 130 : Test Modulator : Modulation Window for 32APSK

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 64APSK Modulation :

Figure 131 : Test Modulator : Modulation Window for 64APSK

 SCCC DVB-S2 Modulation :

Figure 132 : Test Modulator : SCCC DVBS2 modulation standard

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4.5.8.1.1 CONTROL

MODULATION Enable or disable carrier modulation by clicking on the check box.

CARRIER Enable or disable the carrier by clicking on the check box.

CARRIER FREQUENCY IF carrier frequency 716 to 724 MHz. Expressed in Hz. (former modulator
board, SM 01008857 model only).
IF carrier frequency 580 to 860 MHz. (SM 01019647 model).
IF carrier frequency 1150 to 1250 MHz. (SM 01019647 model)..
Enter any value in float or real format. Example: for 720 MHz, type: 7.2e+8 or
720000000. The programmed value is always displayed in float format. The
resolution is limited by the hardware design to ~200 kHz.

CARRIER INPUT Select Internal or External carrier generation

CARRIER LEVEL Carrier level at the Nominal output port . Expressed in dBm. Enter any value
from -10 to –40. Resolution step : 1 dBm.

MODULATION Select BPSK or QPSK or OQPSK or UQPSK or 8PSK or 16QAM or 16APSK

or 32 APSK or 64 APSK

I/Q SHIFT Allows adjusting the I/Q offset in OQPSK mode for test purposes.
Enter any value from +0.5 to –0.5 (in symbol). Select 0 for optimal OQPSK
(half-symbol offset). Note : for bit rates higher than 200 Mbps only

PHASE ROTATION Select CCSDS (Counter Clock Wise) or Inverted (Clock Wise). (see section
3.6.2.4)

(8PSK) MAPPING Select Natural, Natural2, Gray1, Gray2, Gray3, Gray4, Gray5 or Gray6 (see
section 3.6.2.4)

(16QAM) MAPPING Select Map 1 or Map 2 (see section 3.6.2.4)

FILTER Allows to enable and cjhoose the modulation filter. Select OFF, RC, RRC or
GMSK
The filter is available in the symbol rate range: 500 Ksps to 120 Msps (for other
rates consult ZDS) with modulator menu #6

ROLL-OFF OR BT Roll-off factor for the RC/RRC filter or BT factor for the GMSK filter. Enter
any value from 0.1 to 1.0

DOPPLER ENABLE Enable or disable the frequency sweeping on the carrier

DOPPLER RATE Rate of frequency sweeping. Enter any value from 0 to 100 KHz/s

DOPPLER ERANGE Range of the frequency sweeping. Enter any value from 0 to +1 MHz

REFERENCE Select Internal or External reference frequency

FREQUENCY

NOISE LEVEL Noise level. Expressed in dBm/Hz. Enter any value from –132 to –93.
Resolution step : 1 dB.

NOISE Enable or disable the noise generator by clicking on the check box.

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In 16APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 16APSK constellation

In 32APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 32APSK constellation

GAMMA2 Allow to adjust R3/R1 of the 32APSK constellation

In 64APSK mode, the following additional parameter appears at the GUI:

GAMMA1 Allow to adjust R2/R1 of the 64APSK constellation

GAMMA2 Allow to adjust R3/R1 of the 64APSK constellation

GAMMA3 Allow to adjust R4/R1 of the 64APSK constellation

4.5.8.1.2 FREQUENCY REFERENCE STATUS

FREQUENCY Display the selected frequency reference Internal (10 MHz) or External.
REFERENCE

PLL ON EXTERNAL Status of the PLL on the external reference: Disabled, Locked or Unlocked
REFERENCE

4.5.8.1.3 MONITORING
Status and alarms in this window are described in TSTU

H/W STATUS 1, 2 Test Modulator hardware status : OK (green display) or ALARM (red display).
(upper banner)
See also the error code (if any) reported in the TCP-IP address field in the Top
Level window.

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4.5.8.2 “PCM” Window

 BPSK-QPSK, OQPSK, 8PSK ,16QAM and n-APSK Modulations:

Figure 133 : Test Modulator : PCM Window for BPSK, QPSK, OQPSK, 8PSK, 16QAM and n-APSK

 UQPSK Modulation:

Figure 134 : Test Modulator : PCM Window for UQPSK

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4.5.8.2.1 GENERAL SETTING

MODULATING In BPSK, QPSK, OQPSK (SQPSK), 8PSK or 16QAM modes, select Internal or
SIGNAL External
In UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, select: Internal, External I,
External Q or External I/Q.

TRANSMITTED NRZL Select: Normal or Inverted

OPERATING MODE Simulated telemetry data source :

 Off For reset purposes
 File Read data from a file
 PseudoDxx Pseudo random data from PN generator xx
(where xx = 7, 10, 11, 15, 23 or 31). See Section 3.6.2.1.
 Playback Connect the test modulator unit with the Playback
 File I/Q Select two different files for each I and Q branch

PLAYBACK AUTO If selected insert PRN data before and after the actual recorded data in Playback
mode

INVERSE DATA If selected invert the data to be modulated

PARALLEL Select the number of parallel data units to be used .

CHANNELS
 1 Data Unit
 2 Data Unit
 4 Data Unit
 8 Data Unit

FILE NUMBER File number for BER in File mode: enter any value from 1 to 4294967295 (note
1)

CYCLE LENGTH Cycle length, for File mode only (in bytes). Enter a value from 32 to 2097152.
See Section 3.6.2.2.2.

PCM CODE Telemetry PCM coding technique: NRZ-L/M/S, DNRZ, Bi-P-L/M/S .

BIT RATE Telemetry bit rate. Expressed in bps. Enter any value from 1e6 to 1500.e6
(modulation, firmware dependent). See note 2.
In QPSK or OQPSK (SQPSK) mode, the bit rate must be set to (I Channel Bit
Rate + Q Channel Bit Rate)
In BPSK, UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, enter the bit rate of I
Channel

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RANDOMIZER Auto synchronized scrambler

 Disable Scrambler disabled
 Worldview Worldview type
 CCITT V.35 CCITT V.35 scrambler
 Intelsat V.35 Intelsat V.35 scrambler

Note 1 : Click on in the lower tool bar to invert one bit in the simulated data pattern (pseudo-random pattern
or file). Bit inversion takes place before convolutional encoding (if enabled).

Note 2 : BR limitations are those of the demodulator

Important : in UQPSK (AQPSK, AUQPSK, AUSQPSK) mode, parameters BIT RATE, PCM CODE, FILE
NUMBER, CYCLE LENGTH described here above are for the I Channel. The following additional parameters
appears at the GUI for controlling the Q Channel :

BIT RATE Q Telemetry bit rate for the Q Channel. Expressed in bps. Enter any value from
1e6 to 720.e6 (modulation, firmware dependent).
See also definition of BIT RATE parameter

PCM CODE Q PCM code on the Q Channel : NRZ-L/M/S, DNRZ, Bi-P-L/M/S .

I/Q RATIO Ratio between I Channel & Q Channel in dB, from 0 to 100

FILE NUMBER Q File number for BER in File mode for the Q channel: enter any value from 1 to
4294967295

CYCLE LENGTH Q Cycle length for the Q channel, for File mode only (in bytes). Enter a value
from 32 to 2097152. See Section 3.6.2.2.2.

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4.5.8.3 “Encoding” Window

 BPSK QPSK OQPSK UQPSK 16QAM and n-APSK Modulations:

Figure 135 : Test Modulator : Encoding Window for BPSK, QPSK, OQPSK, UQPSK and 16QAM

 8PSK Modulation:

Figure 136 : Test Modulator : Encoding Window for 8PSK

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4.5.8.3.1 VITERBI ENCODER SETTING

VITERBI ENCODER Convolutional encoder setting for the I Channel in BPSK or UQPSK (AQPSK,
AUQPSK, AUSQPSK) mode or for both I & Q Channels in QPSK, OQPSK
(SQPSK) mode :
 Off Encoder disabled
 G1-G2 Inv Encoder enabled with G2 inverted (G1 first)
 G1-G2 Encoder enabled with G2 normal (G1 first)
 G2inv-G1 Encoder enabled with G2 inverted (G2 first)
 G2-G1 Encoder enabled with G2 normal (G2 first)
Refer to the CCSDS recommendations for “G2 Normal/ G2 Inverted” definition.

VITERBI ENCODER Q Convolutional encoder setting for the Q Channel in UQPSK (AQPSK, AUQPSK,
AUSQPSK) mode :
 Off Encoder disabled
 G1-G2 Inv Encoder enabled with G2 inverted (G1 first)
 G1-G2 Encoder enabled with G2 normal (G1 first)
 G2inv-G1 Encoder enabled with G2 inverted (G2 first)
 G2-G1 Encoder enabled with G2 normal (G2 first)

VITERBI ENCODING Convolutional encoder setting in QPSK, OQPSK (SQPSK) mode :

 Single- 1 I+Q Single encoder common to I & Q Channels
 Dual – nI / nQ Separate encoders for I & Q Channels, n is the number of
parallel encoders and can be selected between 1 and 16.
See Section 1.6.1.5 for more details

VITERBI PUNCTURING Puncturing setting for I Channel in BPSK or UQPSK (AQPSK, AUQPSK,
AUSQPSK) mode or for both I & Q Channels in QPSK, OQPSK (SQPSK) mode :
 Off Puncturing disabled
 from reg. Puncturing scheme defined in registry.
 2/3 2/3 Viterbi
 ¾ (conv.1) 3/4 Viterbi (convention 1)
 ¾ (conv.2) 3/4 Viterbi (convention 2)
 4/5 4/5 Viterbi
 5/6(conv.1) 5/6 Viterbi (convention 1)
 5/6(conv.2) 5/6 Viterbi (convention 2)
 6/7 6/7 Viterbi
 7/8 (conv.1) 7/8 Viterbi (convention 1)
 7/8 (conv.2) 7/8 Viterbi (convention 2)
 1/4 Esrin 1/4 Viterbi (ESA / ESRIN type)

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VITERBI PUNCTURING Q Puncturing setting for Q Channel in UQPSK (AQPSK, AUQPSK, AUSQPSK)
mode :
 Off Puncturing disabled
 from reg. Puncturing scheme defined in registry.
 2/3 2/3 Viterbi
 ¾ (conv.1) 3/4 Viterbi (convention 1)
 ¾ (conv.2) 3/4 Viterbi (convention 2)
 4/5 4/5 Viterbi
 5/6(conv.1) 5/6 Viterbi (convention 1)
 5/6(conv.2) 5/6 Viterbi (convention 2)
 6/7 6/7 Viterbi
 7/8 (conv.1) 7/8 Viterbi (convention 1)
 7/8 (conv.2) 7/8 Viterbi (convention 2)
 1/4 Esrin 1/4 Viterbi (ESA / ESRIN type)

4.5.8.3.2 DVB TRANSPORT LAYER SETTING

DVB TRANSPORT LAYER Enable or Disable the DVB Transport Layer.

4.5.8.3.3 CCSDS SETTING

CADU SYNC WORD Enable or Disable the synchronization word inside the data. Essentially used with
simulated pseudo-random data.

CADU SW SIZE Selection of the size of the synchronization word.

CADU FRAME SIZE Selection of the size of the frame.

REED SOLOMON 223 Enable or Disable the CCSDS Reed Solomon encoder RS(223,255).

REED SOLOMON 239 Enable or Disable the Reed Solomon encoder RS(239,255).

SCRAMBLING Set the randomization operation to ON or OFF.

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4.5.8.3.4 LDPC SETTING

LDPC Enable or Disable the LDPC encoding.

4.5.8.3.5 BYTES FORMAT

LSB FIRST Enable or Disable the LSB-first byte formatting in the simulated data..

4.5.8.3.6 TCM SETTING

TCM ENCODER 4D-TCM encoder for 8-PSK modulation mode :

 Off TCM OFF
 2.00/3 4D-TCM rate 2
 2.25/3 Not Implemented today
 2.50/3 4D-TCM rate 2.5
 2.75/3 4D-TCM rate 2.75

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4.5.8.4 “Physical Layer” Window

Figure 137 : Test Modulator : Physical layer Window for SCCC and DVB-S2 standard

This window is used only with DVB-S2 or SCCC transmission standards.

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4.5.8.4.1 CONTROL

MODE Selection of the standardmodulation mode :

 OFF Normal modulation mode
 VHR E/O DVB-S2 Very High Rate DVB-S2 modulation satandard
 SCCC SCCC modulation standard

VCM Enable or not the VCM mode: Automatic detection of the current modulation

VCM FILE If VCM mode is enabled, the modulation and coding modes sequence is
described inside a simulation ASCII file. This field allows to select the file
number

MODULATION If VCM mode is disabled, select the demodulation mode

 QPSK
 8PSK
 16APSK
 32APSK
 64APSK

RATE If VCM mode is disabled, select the coding rate (DVB-S2 and SCCC standard)

PILOTS Enable or not the insertion of pilots indide the frames (DVB-S2 and SCCC
standard)

SHORT FRAME Enable or not the transmission of short frames (DVB-S2 standard only)

PL SCRAMBLING Enable or not the randomization of the frames (DVB-S2 and SCCC standard)

GAMMA 1 Radius ratio 1 for 16APSK, 32APSK and 64APSK

GAMMA 2 Radius ratio 2 for 32APSK and 64APSK

GAMMA 3 Radius ratio 3 for 64APSK

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4.5.9 Playback Windows

4.5.9.1 “Global” Window

Figure 138 : Playback : Global Window

4.5.9.1.1 CONFIGURATION AND CONTROL

Parameters in this window are described in PLBK

To start the replay, the HDR must be set in “Acquisition” mode.

START TIME Allows to define an automatic starting date for the replay.
Must be selected to be active.

STOP TIME Allows to define an automatic stop date for the replay.
Must be selected to be active.

Manual start of the replay.

Manual stop of the replay.

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BIT RATE Selects the bit rate of the playback only used in “Data+Clock” mode.
Important: In “Test modulator” mode, the bit rate of the playback is the bit
rate set in the test modulator window.

MEMORY ALLOCATION Allows to allocate a fixed part of the available memory to the playback function
FOR PLAYBACK when the selection box Auto is disabled. The recommended operating mode is to
enable the Auto mode.

MODE Select the playback mode:

 Off Playback OFF
 Soft Mode Specific Project
 Data + Clock Playback at the ECL outputs of the demodulators
 Test Modulator Playback at IF level using the test modulator
Important: Before selecting a playback mode (“Test Modulator” or “Data +
Clock”) the playback function must be connected to the test modulator (test
modulator Global Window – Field: Operating Mode = Playback), or to the
Demodulator outputs (Demodulator Global Window – Field: Output Mode =
Playback Merge or Playback Split 2).

4.5.9.1.2 STATUS
Status and alarms in this window are described in PLBK

The status field is divided into two parts:

A general status line gives the status of the operation: “Ready to start” or “Play in progress, waiting for stop”.

A bar-graph gives in real-time the level of the current playback as a percentage of the consumed data from the
selected file.

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4.5.9.2 “File” Window

Figure 139 : Playback : File Window in Report TM mode (By date)

Figure 140 : Playback : File Window in Report TM mode (By number)

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Figure 141 : Playback : File Window in Playback Data File mode

Figure 142 : Playback : File Window in BER File mode

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Figure 143 : Playback : File Window in Recorded Frames mode

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4.5.9.2.1 CONFIGURATION

OPERATING MODE Select the source of the data for the replay:
 Report TM: Selects recorded data from a previous satellite pass (from the
recorded report file of the pass – refer to “From report” command)
 Playback Data from File: Selects data recorded inside a User-defined file
 Playback Data from Directory: Selects data recorded inside a set of User-
defined files recorded inside one directory
 Rec Frames by date: Selects data CADUs by dates
 BER file : Selects a PRN code or a data simulation file

FRAME LENGTH Selects the length of the data frames for the playback (synchronization word
included).

64-BIT ALIGN Allows to indicate that TM blocks of the file(s) to be replayed are 64-BIT aligned.

DATE FIELD Allows to indicate that a date field (8-bytes word) is inserted in the TM block of the
file(s) to be replayed.

STATUS FIELD Allows to indicate that a status field (8-bytes word) is inserted in the TM block of the
file(s) to be replayed.

SPARE Allows to indicate if other spare 8-bytes words are inserted in the TM block of the
file(s) to be replayed. Number of words from 0 to 8.

LOOP ON FILE Enable or disable the loop replay on the selected file.

DRU NUMBER A to H selection of the DRU from where the replayed data are extracted.

FIRST CADU Date of the first CADU to replay (only in “Rec Frames by date” mode)

LAST CADU Date of the last CADU to replay (only in “Rec Frames by date” rmode)

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4.5.9.2.2 FILE SELECTION

With “Report TM” mode:

CHANNEL Selection of the Recording channel (DRU-A, B, C, …H) where the pass report file
has to be selected.
 DRU-A to DRU-H

REPORT NUMBER Selection of the report number: 1 to N. Can be selected directly by clinking in the
Storage report and TM files Window

LINE Selection of a specific line (a specific file) inside the selected pass report : 0 to N.
Can be selected directly by clinking in the Storage report and TM files Window

Allows to open the Storage report and TM files Window :

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With “Report TM” mode:

CONTROLLER Selection of the Controller for the replay.

PARTITION Selection of the Partition for the replay.

FILE NBR. Selection of the file number for the replay: 1 to N. The file must be recorded in the
“PLAYBACK” directory of the selected partition.

With “BER File” mode:

MODE BER measurement mode (simulated data for BER analyzis) :

 File Simulated data from a file on the disk
 PseudoDxx Pseudo random data, using from PN generator xx
(where xx = 10, 11, 15 or 23. See Section 3.6.2.1)

FILE NUMBER Selection of the simulation number: 1 to N.

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4.5.10 Logging Windows

4.5.10.1 “Data Logging Control” Window
For details on the data logging function, refer to section 3.8.

To control the data logging function, in the upper toolbar click on . This operation opens the data logging
control window :

Figure 144 : Logging status Window

4.5.10.1.1 CONTROL
START / STOP Start or stop the data logging in manual mode.

AUTOMATIC LOG If selected, the recording starts automatically with the Acquisition mode. In this
case the parameters are recorded in the file number 0 for TMA, TMB, TMC and
TMD.

CONFIGURATION FILE Select the number of the configuration file used for the current data logging
operation

CHOOSE CHANNELS Select the channel(s) TMA, TMB, TMC and/or TMD for the current logging
operation.

Open the editor window to configure a new configuration file (see next section).

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4.5.10.1.2 STATUS

The status field can take the following values: Inactive, Running or Automatic. In case of a non valid
configuration file number, Error is reported in this status field.

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4.5.10.2 “Data Logging Editor” Window

Note that the data logging edition can be performed only in local mode.

For details on the data logging editor function, refer to section 3.8.

To edit an already existing or a new logging configuration file, click on in the previous data logging control
window to open the following data logging editor window :

Figure 145 : Logging editor Window

CHANNEL Select the channel: ChannelA, ChannelB, ChannelC or ChannelD on which

the logging configuration file applies.

CONFIGURATION FILE Select the number of the configuration file to edit: 0 to 100

LOG NAME Enter a general label associated with the logging file (this label will appear
inside the data logging text file).

PERIOD Select a period (in seconds) for periodical recording.

MAX DURATION If 0, the recording will stop only by clicking on the stop button in the control
window. If a value is set (in seconds), the recording will stop at the end of this
delay even is the stop button has not been clicked.

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PARAMETER LABEL Enter a label for the parameter to log (this label will appear inside the data
logging text file).

COMPONENT AND Select the effective HDR control parameter or status by entering its component
OFFSET number (hexadecimal format) and offset (hexadecimal or decimal format) as
defined in the STI document.

LOGGING TYPE Select the logging type associated with the selected parameter
 Periodic Logging
 Log on Transition
 Log on Variation

VALUE TYPE Select the logging format for the value of the selected parameter:
 Unsigned Integer
 Signed Integer
 Hexadecimal
 Float
 Double float

STATE VALUE In “Log on Transition” mode, defined the status labels associated with the
actual status values (these label will appear inside the data logging text file).

Save the current parameter definition in the current configuration file.

Delete the selected parameter from the current configuration file.

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4.5.11 Licenses and Basic Menus

The following table shows the hardware limitations for each basic menu of the demodulator:

BASIC
INGESTION
MENU
DEMODULATOR # 1 DEMODULATOR # 2
1 5 1 5
NBR. Max. SR A/UQPSK FIR Coding MAX. SR A/UQPSK FIR Coding DPU NUMBER

2 2
1 240 NO YES TCM 2.5/3 240 NO YES TCM 2.5/3 2 x FS

RS DVB RS DVB

2 240 NO YES LDPC 7/8 Not available 1 x FS

3 3
3 240 NO YES Viterbi 1/2 240 NO YES Viterbi 1/2 2 x FS

V.35 V.35

RS (223,255) RS (223,255)

RS(6,10) CRC RS(6,10) CRC

3 3
4 240 NO YES Viterbi 1/2 240 NO YES Viterbi 1/2 2 x FS

V.35 V.35

RS (239,255) RS (239,255)

RS(6,10) CRC RS(6,10) CRC

3 3
5 2x240 YES YES Viterbi 1/2 2x240 YES YES Viterbi 1/2 4 x FS

64 600 NO YES 1/4 Viterbi (ESRIN) Not available 1 x FS

RS (223,255)

Soft bit output

7 360 NO YES 1/2, Parallel Not available 1 x FS

3
Fast Viterbi

RS (223,255)

Soft bit output

2 2
8 240 NO YES TCM 2.00/3 240 NO YES TCM 2.00/3 2 x FS

RS DVB RS DVB

2
9 360 NO YES Fast TCM 2.5/3 Not available 1 x FS

RS DVB

Soft bit output

2
10 360 NO YES Fast TCM 2.00/3 Not available 1 x FS
RS DVB

Soft bit output

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11 240 NO YES 1/2 Viterbi 240 NO YES 1/2 Viterbi 4 x FS

RS (223,255) RS (223,255)
and De-randomizer and De-randomizer

Worldview type Worldview type

OQPSK/8PSK VCM OQPSK/8PSK VCM

2
12 360 NO YES Fast TCM 2.5/3 Not available 1 x FS

RS (239,255)

Soft bit output

4 2
13 600 NO YES Fast TCM 2.5/3 Not available 1 x FS

RS (239,255)
Soft bit output

14 Reserved for future development

15 240 NO YES LDPC 1/2 Not Available 1 x FS

(4096 bits)

16 360 NO YES RS (223,255) Not Available 8 x FS

17 360 NO YES Coder on Optional Not Available 1 x FS

Extension board

Soft bit output

18 4 600 NO YES Coder on Optional Not Available 1 x FS

Extanesion board

Soft bit output

19 4 300 NO YES LDPC 7/8 Not Available 1 x FS

Soft bit output

20 4 300 NO YES LDPC 1/2 Not Available 1 x FS

(4096 bits)

Soft bit output

21 240 NO YES LDPC 1/2 Not Available 1 x FS

(1024 bits)

22 4 300 NO YES LDPC 1/2 Not Available 1 x FS

(1024 bits)
Soft bit output

23 4 300 NO YES 1/2, and Parallel Not Available 1 x FS

Fast Viterbi
RS (223,255)

Soft bit output

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24 240 NO YES TCM 2.5/3 240 NO YES TCM 2.5/3 2 x FS

RS (239,255) RS (239,255)
RS(6,10) CRC RS(6,10) CRC

25 360 NO YES SCCC / DVB-S2 Not Available 1 x FS

VCM

26 4 600 NO YES SCCC / DVB-S2 Not Available 1 x FS

VCM

27 4 200 YES YES 1/2 Viterbi RS Not Available 2 x FS

(223,255)

28 4 600 NO YES Fast TCM 2.5/3 Not Available 1 x FS

RS DVB

Soft bit output

29 4 300 NO YES 1/2 Parallel Not Available 1 x FS

Fast Viterbi

RS (239,255)

Soft bit output

30 6 NA NA NA RS (223,255) NA NA NA RS (223,255) 2 x FS
RS(6,10) CRC RS(6,10) CRC

31 6 NA NA NA RS (239,255) NA NA NA RS (239,255) 2 x FS

RS(6,10) CRC RS(6,10) CRC

32 240 NO YES Combining (DMU1 + Not Available 1 x FS

DMU3) ½ Viterbi

RS(223,255)

RS(6,10) CRC

33 240 NO YES 1/2 Viterbi 240 NO YES 1/2 Viterbi 2 x FS

+ V.35 XDEAF V.35

XDEAF RS (223,255) RS (223,255)

RS(6,10) CRC RS(6,10) CRC

34 240 NO YES TCM 2.25/3 240 NO YES TCM 2.25/3 2 x FS

RS (239,255) RS (239,255)

RS(6,10) CRC RS(6,10) CRC

35 240 NO YES TCM 2.75/3 240 NO YES TCM 2.75/3 2 x FS

RS (239,255) RS (239,255)

RS(6,10) CRC RS(6,10) CRC

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36 360 NO YES Viterbi 1/4 Not Available 1 x FS

RS (223,255)
Soft bit output

37 240 NO YES Viterbi 1/2 240 NO YES Viterbi 1/2 4 x FS

RS (223,255) RS (223,255)

38 4 600 NO YES 1/2 and parallel Not Available 1 x FS

fast Viterbi

Soft bit output

RS(223, 255)

39 4 600 NO YES 1/2 and parallel Not Available 1 x FS

fast Viterbi

Soft bit output

RS(239, 255)

40 120 NO YES Combining (DMU1 + Not Available 1 x FS

DMU3) LDPC 7/8

41 240 NO YES Combining (DMU1 + Not Available 1 x FS

DMU3) TCM 2.5/3

RS(239,255)

42 8 300 NO YES LDPC 7/8 Not Available 1 x FS

Soft bit output

43 240 NO YES Dual LDPC 7/8 Not Available 2 x FS

44 8 300 NO YES LDPC 7/8 Not Available 1 x FS

Soft bit output

45 7 240 NO YES 240 NO YES 2 x FS

46 7 240 NO YES RS (239,255) 240 NO YES RS (239,255) 2 x FS

RS(6,10) CRC RS(6,10) CRC

47 7 240 NO YES ½ Viterbi 240 NO YES ½ Viterbi 2 x FS

RS (223,255) RS (223,255)

RS(6,10) CRC RS(6,10) CRC

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48 7 240 NO YES TCM 2.5/3 240 NO YES TCM 2.5/3 2 x FS

RS (239,255) RS (239,255)
RS(6,10) CRC RS(6,10) CRC

49 7 360 NO YES No Decoder 360 NO YES No Decoder No DPU

3
50 240 YES YES Viterbi 1/2 Not Available 2 x FS

RS (223,255)

3 3
51 240 NO YES Viterbi 1/2 240 NO YES Viterbi 1/2 2 x FS

RS (239,255) RS (239,255)

RS(6,10) CRC RS(6,10) CRC

52 9 360 NO YES RS (223,255) Not Available 8 x FS

53 240 NO YES TCM 2.5/3 Not Available 1 X FS

+
RS (239,255)
XDEAF

54 240 NO YES TCM 2/3 Not Available 1 X FS

+
RS (239,255)
XDEAF

55 240 NO YES TCM 2/3 Not Available 1 X FS

+
RS (223,255)
XDEAF

56 240 NO YES TCM 2.5/3 Not Available 1 X FS

+
RS (223,255)
XDEAF

Table 16 : The basic demodulator menus of the CORTEX HDR

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Note 1: Maximum Symbol Rate of the demodulator (Msps). Refer to the following tables which give the maximum
Bit Rates measured at the demodulator input for different demodulation and decoding schemes.

Note 2: Maximum Bit Rates at the input of the TCM decoder are given in the following tables .

Note 3: Maximum Bit Rates at the input of the Viterbi decoder are given in the following tables.

Note 4: Menus 6, 13, 18,19, 20, 22, 23, 26, 27, 28, 29, 38 and 39 are available with 1.2 GHz IF input.

Note 5: FIR capabilities are menu dependent:

Menus 1 to 5 : up to 26 direct taps (16 bits) or 8 crossed taps (8 bits), symmetric or asymmetric.

Menu 6: up to 8 direct or crossed taps (8 bits), symmetric or asymmetric.

Menu 7: up to 26 direct taps (16 bits) or 8 crossed taps (8 bits), asymmetric only.

Note 6: Menus 30 and 31 are available with DPU inputs (Data + Clock) . The input bit rate is limited to 350 Mbps.
Note 7: Menus 45 to 49 are customers menus with specific I/O (Refer to the specific DTU documents).
Note 8: Menus 42 and 44 are customers menus with 1.2 GHz IF inputs.

Note 9: Enhanced 16QAM demodulation.

The following table shows the hardware limitations for each basic menu of the test modulator:

Basic UQPSK 16QAM High rate Parallel Data Byte Output 1 Filtering Doppler DVBS2
1
Menu modulation modulation modulation generation Simulation SCCC

> 310 Msps

1 Not available YES Not available Not available Not available Not available Not available Not available

2 YES Not available Not available Not available Not available Not available Not available Not available

3 Not available YES YES Not available Not available Not available Not available Not available

4 Not available YES Not available Not available YES Not available Not available Not available

5 Not available YES Not available YES Not available Not available Not available Not available

6 Not available YES Not available Not available Not available YES Not available Not available

7 Not available YES Not available Not available Not available Not available YES Not available

8 Not available YES YES Not available Not available Not available Not available YES

9 Not available YES Not available Not available Not available YES Not available YES

101 Specific Menu (reserved)

111 Specific Menu (reserved)

Table 17 : The basic test modulator menus of the CORTEX HDR

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Note 1: Available for specific projects (refer to specific DTU document).

The following table gives the hardware menus available with the Extension Board (option):

Basic Menu Nbr. LDPC 7/8 LDPC 1/2 LDPC 2/3

1 Available Not available Not available

2 Not available Available with information block length Not available

k = 4096 bits (4K)

3 Not available Not available Available with information block length

k = 4096 bits (4K)

4 Not available Available with information block length Not available

k = 1024 bits (1K)

5 Not available Not available Available with information block length

k = 1024 bits (1K)

6 Not available Available with information block length Not available

k = 16384 bits (16K)

Table 18 : The basic menus of the Extension board (LDPC decoder)

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The following table gives the maximum performances of the decoders:

Viterbi decoding mode Maximum Bit rate at the input Maximum Bit rate at the input

wiith Demodulator menus with high rate Demodulator menus

# 3, 4, 5, 11, 27, 32, 33, 37 # 7, 23, 29, 38, 39

Viterbi ½ single 240 Mbps 1160 Mbps

Viterbi ½ dual 440 Mbps 1160 Mbps

Viterbi ½ parallel 2 x I – 2 x Q N.A. 360 Mbps

Viterbi ½ parallel 3 x I – 3 x Q N.A. 540 Mbps

Viterbi ½ parallel  4 x I – 4 x Q N.A. > 600 Mbps

Viterbi ¼ (ESRIN) 240 Mbps (menus #6 and #36 only) N.A.

Table 19 : Limitations of the Viterbi decoder

Remark: For Punctured Viterbi codes the maximum bit rate is equal to the maximum bit rate of the Viterbi ½
multiplied by the puncturing rate.

TCM decoder Demodulator menu Maximum Bit rate at the input

TCM 2.5/3 (5/6) # 1, 24, 34 360 Mbps

High rate TCM 2.5/3 (5/6) # 9, 12, 13 1500 Mbps

TCM 2/3 #8 360 Mbps

High rate TCM 2/3 # 10 1500 Mbps

TCM 2.75/3 # 35 360 Mbps

Viterbi ¼ (ESRIN) 240 Mbps (menus #6 and #36 only) N.A.

Table 20 : Limitations of the TCM decoder

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RS decoder Demodulator menu Maximum Bit rate at the input

RS DVB # 1, 8 360 Mbps

High rate RS DVB # 9, 10, 28 960 Mbps

RS (255, 223) # 3, 30, 32, 33, 37, 38 950 Mbps

High rate RS (255, 223) # 6, 23, 36 1900 Mbps

RS (255, 239) # 4, 24, 29, 31, 34, 35, 39 950 Mbps

High rate RS (255, 239) # 12, 13 1900 Mbps

Specific Satellite RS #11 700 Mbps

Table 21 : Limitations of the Reed Solomon decoder

Remark: The previous tables give the intrinsic performance of each decoder versus the selected menus and not
the performance of the overall demodulation channel for a specific demodulation mode and a specific decoding
scheme. The following table gives some example of achievable performances:

Modulation Dual demodulator Menu Decoding Maximum Bit rate at the

input of the demodulator

QPSK YES 3 CCSDS Reed Solomon > 470 Mbps

QPSK NO 7 CCSDS Reed Solomon > 640 Mbps

QPSK NO 7 Viterbi ½ parallel 15 x I – 15 x Q > 640 Mbps

8 PSK YES 3 CCSDS Reed Solomon > 719 Mbps

8 PSK YES 1 TCM + RS DVB > 359 Mbps

8 PSK NO 7 CCSDS Reed Solomon > 959 Mbps

8 PSK NO 9 TCM + RS DVB > 1 Gbps

8 PSK NO 2 LDPC > 700 Mbps

Table 22 : Examples of maximum Bit Rates @ 720 MHz IF input

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To check which licenses are mounted in the machine, position the mouse cursor on the Function status fields of
the GUI or select the “Information” Window in the CORETX HDR top-level Global Window to have an overall
view. This view takes into account the available licenses and the capabilities of the current basic menu.

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5. MAINTENANCE
PROCEDURES

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5.1 GENERAL
5.1.1 Mechanical Inspection and Cleaning
It is recommended to take the following precautions to get the best performance from the system :

 Do not carry out any dust-producing work in the room housing the CORTEX HDR. Clean the air filters regularly
to avoid electronic components overheating.

 Use only alcohol or a water-based cleaner on the front and rear panels of equipment. Other solvents may
damage the keys, LCD and markings.

 Perform a regular operating check on the fan units (check for any abnormal temperature rise, check the air flow
at the air exhaust). The system is not designed for permanent operation without ventilation.

 Preventive maintenance: it is recommended to change the Pentium cooling fan every 3 years.

5.1.2 Handling Precautions

WARNING:

SOME OF THE HARDWARE COMPONENTS USE CMOS TECHNOLOGY AND CAN BE DAMAGED

BY ELECTROSTATIC DISCHARGE FROM YOUR CLOTHES OR BODY.

ALWAYS USE AN ANTI-STATIC BRACELET WHEN WORKING ON THE CORTEX

TO REPLACE A BOARD OR COMPONENT.

 Never remove a board from the CORTEX HDR without switching it off first and removing the power cord !

 When a module has been removed from the chassis, it is essential to handle and store it with care. It is
particularly important to ensure that it is not exposed to electrostatic shocks.

 Certain precautions must also be taken when reinstalling a board in the chassis : when plugging the board into
the PCI bus connectors, never force it; screw the board strip attaching screws back into the frame; reinstall the
connector locking screws. Only then may the CORTEX HDR be switched back on.

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5.1.3 CPU Load Considerations

ZDS DOES NOT WARRANTY CORTEX HDR PERFORMANCE

IF ADDITIONAL SOFTWARE IS LOADED / EXECUTED ON THE MACHINE.

5.1.4 Software Loading

Avoid using floppy disks from unidentified sources. The presence of a virus may severely affect the performance of
the equipment or crash the software.

5.2 FUNCTIONAL INVESTIGATION

The following check-list can be followed for checking that the CORTEX HDR functions correctly :

 Demodulator check : signal acquisition and demodulation.

 Viterbi decoder check (if the Viterbi license is supplied).

 Demodulator output ports.

5.2.1 Demodulator Check

Apply a modulated RF signal (input level between –10 and –50 dBm) to the Demodulator board and verify
the acquisition and demodulation process :

1. If the IF level status is lower than 50 dBm, check the RF connecting cable. Check also that the IF input
port is correctly programmed (Nominal or Alternate IF).

2. Check the correctness of the Demodulator status : Carrier Offset, BR Offset, PLL locked, Bit
Synchronizer Locked.

3. Check that the displayed constellation is the expected one and remains stable (see Figure 106) :

 Four points on a circle for QPSK, OQPSK (SQPSK) and UQPSK (AQPSK, AUQPSK, AUSQPSK)
modulations.

 Two points on the abscissa axis for BPSK modulation.

 Eight points on a circle for 8PSK modulations

4. Check that the Eb/No status is correct.

If the Demodulator fails to lock, verify the setting of the unit.

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5.2.2 Viterbi Check

1. Apply an RF signal with Viterbi encoded data and verify the acquisition and demodulation process (see
previous section).

2. Check the Viterbi Lock / Unlock status.

3. Check that the Viterbi BER status is in accordance with the estimated Eb/No status.

4. If the Viterbi fails to decode, check the setting of the Viterbi decoder : single or dual Viterbi mode, G2
inverted, etc…

5.2.3 Demodulator Output Ports

Once the Demodulator and the Viterbi decoder (if any) are locked, check that the Demodulator output signals are
formatted as expected by the Ingestion System. In case of problem (wrong BER measured by the Data Ingestion
System), check that :

1. The output ports setting is correct : Output Clock, I/Q polarity, Normal or I&Q merged, Output mode. If
the problem remains, try different setting.

2. The PCM code is correct (NRZ-M, DNRZ, …).

3. The hardware connections to the Data Ingestion System are correct.

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5.2.4 Interpretation of the Vector Display

 Low IF input level (-73 dBm). No signal at Demodulator input

 I/Q display : random noise

 Incorrect IF setting (signal = QPSK 720 MHz. Demodulator setting = 721 MHz)

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 Incorrect bit rate setting (signal = QPSK 50 Mbps. Demodulator setting : 47 Mbps). Matched filter
inefficient.

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 QPSK input signal with unwanted MSK modulation appearing as phase

noise on the I/Q display

 Incorrect matched filter setting (input signal = RRC, Roll-off 0.3.

Demodulator setting : I & D) provoking noise-looking inter-symbol
interferences.

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 Dual 50 Mbps QPSK signals at 720 and 770 MHz (adjacent channel
interferences).

 Dual 50 Mbps QPSK signals at 720 and 770 MHz. Limited interferences thanks to an RRC filter
(Roll-off 0.1) on the Demodulator.

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 Reception of an un-modulated carrier.

 Demodulator locked to a heavily affected IF signal (Eb/No close to 0).

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5.3 HARDWARE INVESTIGATION & REPAIR

5.3.1 LED Indicators

5.3.1.1 Test Modulator Board

One LED indicator is located on the front panel of the board :

HW Turns to green and flashes at 1-PPS to show that the hardware is correct.
Unlit (or high rate flashing) in the case of Test Modulator board or CPU board failure.

5.3.1.2 Demodulator Board

One LED indicator is located on the front panel of the board :

HW Turns to green and flashes at 1 PPS to show that the hardware is correct.
Unlit (or high rate flashing) in the case of Demodulator board or CPU board failure.

5.3.1.3 CPU Board

Refer to Annex 4.

5.3.2 IPMIMonitor Tool. Temperature Alarm

The CPU board has several sensors for monitoring the Pentium processors and board temperature.

These sensors are permanently monitored by a dedicated software tool IPMIMonitor. To run this software, click
on START -> PROGRAM -> IPMIMonitor -> IPMIMonitor.

Check the three following status in the list :

STATUS NAME : TYPICAL VALUE @ 22°C AMBIENT : ALARM THRESHOLD :

Baseboard Temp. 34 °C 52 °C
Processor 1 Temp. 43 °C 72 °C
Processor 2 Temp. 43 °C 72 °C
These alarms are reported to the remote monitoring clients via the Global CORTEX Monitoring table (Annex 1, STI
100013_<product name>, Table 6, offset 41) and at the CORTEX GUI (bottom status bar. See section 4.3.5.5).

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In case of temperature alarm :

 Immediately shutdown and switch off the chassis to avoid any damage to the hardware.

 Verify that the air exhaust system of the housing rack works properly,

 Verify that the air intake and exhaust grids are clear. Important : a free rack space must be provided
above and below the chassis,

 Check the cooling fans on both sides of the chassis, at the rear panel of the chassis (power supply
module) and on both CPU processors.

 Return the chassis to ZDS or its maintenance representative if the problem cannot be fixed on site.

5.3.3 PC Workstation Maintenance

Refer to Annex 4 for detailed instructions on how to change :

 The power supply module

 The fan units

 The disk drives : floppy, hard disk and CD ROM

 The display assembly

 The keyboard/trackball.

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5.4 SOFTWARE UPGRADE & INSTALLATION

The CORTEX HDR software is supplied in the form of Compact Disks (CD ROM) :

 Windows OS for re-installing the operating system in the case of disk failure.
 HDR software. The CD ROM contains the Signal Processing Software (SPS), Monitoring & Control Software
(MCS), Demodulator board software (disk-resident part only) and the user documentation.

5.4.1 Loading or Upgrading the IN-SNEC Software

Strictly follow the procedure described on the back of the reference CD ROM.

5.4.2 Complete Software Re-installation

In the case of disk failure, complete software re-installation will be required :

1. Load Windows Operating System (procedure described at the back of the CD ROM).

2. Load the HDR software (procedure described on the back of the CD ROM).

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6. SATELLITES
CONFIGURATION
EXAMPLES

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Next table is a non-exhaustive list of in-orbit satellites with their main downlink configuration parameters :
modulation, bit rate, PCM code, Viterbi mode, output mode.

These parameters can be entered manually on the CORTEX HDR or, more easily, by loading the MCS file
indicated in the left column. These MCS files can be found in :

C:\Program Files\IN-SNEC\CrtxMcs\Default\Config

Reminder : procedure for configuring the CORTEX HDR from an MCS file :

1. Click on FILE, CLOSE. If necessary, save the current configuration to the active MCS document.

2. Click on FILE, OPEN. Select a new MCS document in the list and click on OK to load it. The configuration
status turns to (unless the new MCS document is strictly identical to the previous one).

3. Enable the configuration mode if necessary (click on in the lower toolbar and enter the Configuration
password).

4. Reconfigure the unit by clicking on . The configuration status turns to .

WARNING :

SATELLITE INFORMATION LISTED IN THIS SECTION IS NOT CONTRACTUAL.

THE OPERATOR SHOULD KNOW THE DETAILED FEATURES OF THE TRACKED SATELLITE

AND PROGRAM THE CORTEX HDR ACCORDINGLY.

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Satellite Bit rate Modulation Viterbi Output mode Basic

Mode Menu
+ MCS Document
to be loaded

Adeos II I : 30 Mbps UQPSK : 6dB OFF I channel A 5

(or ¼
Adeos2.mcs Q : 30 Mbps Q channel B
AUSQPSK)

NRZ-M

AKARI 8.388608 Mbps QPSK Dual Normal 3

Akari.mcs NRZ-M

Alos 138.76 Mbps QPSK OFF Merge 3

Alos.mcs DNRZ

Alsat 65 Mbps 8PSK OFF Merge 1

Alsat2.mcs TCM 2.00/3

Aqua DB 15 Mbps OQPSK OFF Merge 3

AquaDB.mcs NRZ-M

Aqua DP 150 Mbps OQPSK OFF Merge 3

AquaDP.mcs NRZ-M

Aqua DP & DB 15 Mbps OQPSK OFF Merge 3

150 Mbps
AquaDP_DB.mcs NRZ-M

ATV 6 Mbps OQPSK OFF Merge 3

ATV.mcs NRZ-M

Aura DP & DB 15 Mbps OQPSK OFF Merge 3

150 Mbps
AuraDP_DB.mcs NRZ-M

CBERS 53 Mbps QPSK OFF Normal 3

CBERS.mcs DNRZ

Corriolis 1 51.2 Mbps OQPSK OFF Merge 3

Corriolis1.mcs NRZ-M

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Corriolis 2 102.4 Mbps OQPSK Dual Merge 3

Corriolis2.mcs NRZ-M

Corriolis2_FS.mcs

Cosmo 155 Mbps QPSK OFF Normal 3

Cosmo.mcs DNRZ

Cryosat 100 Mbps QPSK OFF Normal 3

Cryosat.mcs DNRZ

Demeter 16 Mbps 8PSK OFF Merge 1

Demeter.mcs TCM 2.00/3

Envisat 100 Mbps QPSK OFF Merge 3

Envisat_Asar.mcs DNRZ

Envisat 100 Mbps QPSK OFF Normal 3

Envisat_Meris.mcs DNRZ

Envisat 100 Mbps QPSK OFF Merge 3

Envisat_Meris_Asar.mcs DNRZ

EO1 105 Mbps QPSK OFF Merge or 3

Normal
EO1merge.mcs DNRZ
or Both
EO1nonmerge.mcs
depend on
EO1merge_nomerge.mcs
mcs file

EROS 87.5 Mbps QPSK OFF Merge 3

EROS.mcs DNRZ

ERS-1 105 Mbps QPSK OFF Merge or 3

normal depend
ERS1merge.mcs DNRZ
on mode
& ERS1nonmerge.mcs

Feng Yun 3 124 Mbps QPSK Dual Normal 3

FengYun3_DPT_HRTP.mcs DNRZ Rate 3/4

FengYun3_DPT_HRTP_FS.mcs 37.4 Mbps Rate 1/2

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Feng Yun 3 5.6 Mbps QPSK Dual Normal 3

FengYun3_HRPT_MPT_FS.mcs DNRZ Rate 3/4

37.4 Mbps Rate 1/2

Formosat 2 120 Mbps QPSK OFF Normal 3

Formosat-2.mcs DNRZ

GOES-R 150 Mbps OQPSK OFF Normal 2

GOES-R.mcs NRZ-L

LDPC

GOSAT 138.76 Mbps OQPSK OFF Merge 3

Gosat.mcs NRZ-M

HY1 5.3232 Mbps QPSK OFF Merge 3

HY1.mcs DNRZ

HY3 105 Mbps QPSK Dual Normal 3

HY3.mcs DNRZ Rate 3/4

IceSat 40 Mbps OQPSK OFF Merge 3

Icesat.mcs NRZM

Icesat_fs.mcs

Ikonos 320 Mbps OQPSK OFF Merge 3

Ikonos.mcs NRZ-M

IRS-1C 42.4515 Mbps QPSK OFF Merge 3

IRS-1C_liss3.mcs DNRZ

IRS-1C 84.903 Mbps QPSK OFF Merge 3

IRS-1C_pan.mcs DNRZ

IRS-1D 42.4515 Mbps QPSK OFF Normal 3

IRS-1D_liss3.mcs DNRZ

IRS-1D 84.903 Mbps QPSK OFF Normal 3

IRS-1D_pan.mcs DNRZ

IRSP4 20.8 Mbps QPSK OFF Normal 3

IRSP4.mcs DNRZ

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IRSP5 84.903 Mbps QPSK OFF Normal 3

IRSP5.mcs DNRZ

IRSP6 105 Mbps QPSK OFF Normal 3

IRSP6.mcs DNRZ

JEM 100 Mbps QPSK Single Merge 3

JEM.mcs NRZ-M

JEM FORWARD 6 Mbps BPSK ON Normal 3

JEMFordward.mcs NRZ-M

Kompsat-2 320 Mbps OQPSK OFF Merge 3

Kompsat2.mcs NRZ-M

Landsat-5 I : 84.09 Mbps UQPSK : 6dB OFF I channel A 5

Landsat5.mcs Q : 15.06 Mbps NRZ-M Q channel B

Landsat-7 I : 74.914 Mbps UQPSK : 0dB OFF I channel A 5

(AQPSK)
Landsat7.mcs Q : 74.914 Mbps Q channel B
NRZ-L
Landsat7_FS.mcs

LRO HR MR 75 Mbps OQPSK Dual Merge 3

LRO_High_Medium.mcs 50 Mbps NRZ-M

LRO MR LR 50 Mbps OQPSK Dual Merge 3

LRO_Medium_Low.mcs 25 Mbps NRZ-M

Metop 70 Mbps QPSK OFF Merge 3

Metop.mcs NRZ-L
Metop_FS.mcs

Metop HRPT 4.6666 Mbps QPSK Single Normal 3

Metop_HRPT_FS.mcs NRZ-L

NPOES 300 Mbps OQPSK OFF Merge 3

NPOES.mcs NRZ-M
NPOES_FS.mcs

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NPP 300 Mbps OQPSK OFF Merge 3

NPP.mcs NRZ-M
NPP_FS.mcs

NRL-1 51.2 Mbps OQPSK OFF Merge 3

NRL1.mcs NRZ-M

NRL-2 102.4 Mbps OQPSK Dual Merge 3

NRL2.mcs NRZ-M

OFEC 103 Mbps QPSK OFF Merge 3

OFEC.mcs DNRZ

Oryx 125.414 Mbps QPSK Dual Normal 3

Oryx.mcs NRZ-M

PLEIADES 199.954 Mbps 8PSK OFF Normal 1

Pleiades.mcs TCM 2.50/3

PROBA 2 Mbps BPSK ON Normal 3

PROBA.mcs NRZ-L
PROBA_FS.mcs

QuickBird 320 Mbps OQPSK OFF Normal 3

QuickBird.mcs NRZ-M

RadarSat 105 Mbps QPSK OFF Merge 3

Radarsat.mcs DNRZ

RazakSat 30 Mbps QPSK OFF Normal 3

RazakSat.mcs DNRZ

RESURS-DK 153.6 Mbps QPSK OFF Normal 3

RESURS_DK.mcs NRZ-L

SAC-C 6.606 Mbps BPSK ON Merge 3

SAC-C.mcs NRZ-M

SAC-C_FS.mcs

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SDO 300 Mbps OQPSK Dual Merge 3

sdo.mcs NRZ-M
sdo_fsrs.mcs

SICH 2 61.44 Mbps OQPSK Dual Normal 3

SICH-2.mcs NRZ-M

SICH 3 320 Mbps OQPSK OFF Normal 3

SICH-3.mcs NRZ-M

SICH BPSK HR 61.44 Mbps BPSK OFF Normal 3

SICH-BPSK-HR.mcs NRZ-M

SICH BPSK LR 15.36 Mbps BPSK OFF Normal 3

SICH-BPSK-LR.mcs NRZ-M

SPOT-2 49.372 Mbps QPSK OFF Merge 3

SPOT2.mcs DNRZ

SPOT-4 49.372 Mbps QPSK OFF Merge 3

SPOT4.mcs DNRZ

SPOT-5 49.372 Mbps QPSK OFF Merge 3

spot5.mcs DNRZ
spot5_FS.mcs

SPOT VGT L band 1.0204 Mbps BPSK ON Normal 3

SPOT_VGT_LBand.mcs NRZ-M

SPOT VGT X band 3.4021 Mbps BPSK OFF Normal 3

SPOT_VGT_Band.mcs NRZ-M

SSTL BPSK 40 Mbps BPSK OFF Merge 3

SSTL-Bpsk.mcs NRZ-M

SSTL QPSK 80 Mbps QPSK Single Normal 3

SSTL-Qpsk.mcs NRZ-M

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Terra I : 26.250 Mbps UQPSK : 6dB I : ON I channel A 5

(or ¼
Terra.mcs Q : 13.125 Mbps Q : OFF Q channel B
AUSQPSK)
Terra_FS.mcs
MODIS is on
NRZ-M
channel A :
data1 + CLK

Terra High Rate 150 Mbps OQPSK I: 8 // decod. Merge 7

Terra_highdatarate.mcs NRZ-M Q: 8 //
decod.

TerraSARX 300 Mbps QPSK OFF Merge 3

TerraSARX.mcs DNRZ

TopSat BPSK 11.052 Mbps BPSK ON Normal 3

TopSat-BPSK.mcs NRZ-M

TopSat QPSK 22.104 Mbps QPSK Dual Normal 3

TopSat-BPSK.mcs NRZ-M

Worldview 2 400 Mbps OQPSK OFF Merge 3

Worldview2.mcs NRZ-M

DEAF

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7. ANNEX 1: CORTEX HDR

ETHERNET INTERFACE

ZODIAC DATA SYSTEMS PROPRIETARY Page A

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8. ANNEX 2:
DEMODULATOR BOARD

ZODIAC DATA SYSTEMS PROPRIETARY Page B

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9. ANNEX 3: TEST
MODULATOR BOARD

ZODIAC DATA SYSTEMS PROPRIETARY Page C

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10. ANNEX 4: PC-

COMPATIBLE
WORKSTATION

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11. ANNEX 5: PROJECT-

SPECIFIC DATA

ZODIAC DATA SYSTEMS PROPRIETARY Page E