18/19

1a)
Machine language is a low-level language made up of binary numbers or bits that a
computer can understand. It is also known as machine code or object code and is
extremely tough to comprehend. The only language that the computer understands is
machine language.

we use predefined words called mnemonics. Binary code instructions in low-level

language are replaced with mnemonics and operands in middle-level language. But the
computer cannot understand mnemonics, so we use a translator called Assembler to
translate mnemonics into machine language.

1b)
Multiple interrupt is an interrupt event which can occur while the processor is handling a
previous interrupt. For example − A program receiving data from a communication line
and printing result there is a possibility for communication interrupt to occur while
printer interrupt being processed.

2a)

Direct (register)

MOV AL,BL

Copy one register into another. This is easy to understand. The simulator does not
support this command. If you have to copy from one register to another, use a RAM
location or the stack to achieve the move.

format:

MOV destination,source

destination source example

register register mov ax,bx

register immediate mov ax,10h

register memory mov ax,es:[bx]

memory immediate mov aNumber,10h

memory register mov aDigit,ax

MOV copies the data in the source to the destination. The data can be either a byte or a
word. Sometimes this has to be explicitly stated when the assembler cannot determine
from the operands whether a byte or word is being referenced.

Each of the possible values for the destination and source is called an address. From
the above table it becomes apparent that there are a number of different addressing
modes (immediate, register, memory).

___________________________________________________

The contents of information are stored in Memory data register.

The Memory Data Register (MDR) or Memory Buffer Register (MBR) is the register of a
computer's control unit that contains the data to be stored in the computer storage (e.g.
RAM), or the data after a fetch from the computer storage.

A memory buffer register (MBR) or memory data register (MDR) is the register in a
computer's processor, or central processing unit, CPU, that stores the data being
transferred to and from the immediate access storage. It contains the copy of
designated memory locations specified by the memory address register.

In a computer, the Memory Address Register (MAR) is the CPU register that either
stores the memory address from which data will be fetched from the CPU, or the
address to which data will be sent and stored. In other words, MAR holds the memory
location of data that needs to be accessed.

A processor register (CPU register) is one of a small set of data holding places that are
part of the computer processor. A register may hold an instruction, a storage address, or
any kind of data (such as a bit sequence or individual characters). Some instructions
specify registers as part of the instruction.

2b)
Display ‘*’ 10 times each in new line (Use NEW_LINE Macro)
newline macro
mov ah, 02
mov dl, 10
int 21h
mov dl, 13
endm
.model small
.stack 100h
.code
main proc
mov cx, 10
pt: mov ah, 02
mov dl, '*'
int 21h
newline
dec cx
jnz pt
mov ah, 4ch
int 21h
main endp
end main
OR
DATA SEGMENT
STR1 DB "ENTER YOUR STRING HERE ->$" Microprocessor and Assembly
Language
STR3 DB "YOUR STRING IS ->$"
STR2 DB 80 DUP("$")
NEWLINE DB 10,13,"$"
N DB 10
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA,CS:CODE START:
MOV AX,DATA
MOV DS,AX
LEA SI,STR2
MOV CL,N
MOV AH,09H
LEA DX,STR1
INT 21H
MOV AH,0AH
MOV DX,SI
INT 21H
L1: MOV AH,09H
LEA DX,NEWLINE
INT 21H
MOV AH,09H
LEA DX,STR3
INT 21H
MOV AH,09H
LEA DX,STR2+2
INT 21H
LOOP L1
MOV AH,4CH
INT 21H
CODE ENDS
END START

2b)

3b)

The JMP instruction can be used for implementing loops. For example, the
following code snippet can be used for executing the loop-body 10 times.

MOV CL, 10 L1: <LOOP-BODY> DEC CL JNZ L1

The following code snippet illustrates the JMP instruction −

MOV AX, 00 ; Initializing AX to 0
MOV BX, 00 ; Initializing BX to 0
MOV CX, 01 ; Initializing CX to 1
L20:
ADD AX, 01 ; Increment AX
ADD BX, AX ; Add AX to BX
SHL CX, 1 ; shift left CX, this in turn doubles the CX value JMP
L20 ; repeats the statements

The processor instruction set, however, includes a group of loop

instructions for implementing iteration. The basic LOOP instruction has
the following syntax −

if( expression ) then << statements >> endif;

Assembly language, as usual, offers much more flexibility when dealing

with conditional statements. Consider the following C/C++ statement:

if( (( x < y ) && ( z > t )) || ( a != b ) ) stmt1;

A "brute force" approach to converting this statement into assembly
language might produce:

mov( x, eax );
cmp( eax, y );
setl( bl );
// Store X<Y in bl.
mov( z, eax );
cmp( eax, t );
setg( bh );
// Store Z > T in bh.
and( bh, bl );
// Put (X<Y) && (Z>T) into bl.
mov( a, eax );
cmp( eax, b );
setne( bh );
// Store A != B into bh.
or( bh, bl );
// Put (X<Y) && (Z>T) || (A!=B) into bl
je SkipStmt1;
// Branch if result is false (OR sets Z-Flag if false).

Find GCD of ra,rb, using 'while' loop

3C)

From the given question, the interrupt number is 21h.

IP is loaded from the address 21h*4=0084h,

CS is loaded from the address 21h*4+2=0086h

The new SP value at the start of ISR routine is =current SP value -

6=FFFCh-6=FFF6h
Explanation and detailed steps

When an interrupt occurs in 8086, the processor completes the execution

of the current instruction and goes for the execution of ISR(Interrupt
Service Routine) for handling the interrupt. The address of the
corresponding ISR routine is located in Interrupt Vector Table. The detailed
steps for handling an interrupt in 8086 is described below

1. Decrement stack pointer SP by 2

2. Push the value of the flag register to the stack

3.Decrement stack pointer SP by 2

4.Push the content of the CS register to stack

5.Decrement the stack pointer by 2

6.Push the content of the IP register to stack

7.Load IP register from the address 4*Interrupt number

8.Load CS register from the memory address 4*interrupt number+2

9. Reset Interrupt flag and Trap flag

10. Execute ISR routine

11. set Interrupt flag

12. Load IP register from stack top

13. Increment stack pointer by 2

14. Load CS register from stack top

15. Increment stack pointer by 2

16. Load Flag register from stack top

17. Increment stack pointer by 2

4a)
i) ROL : Rotate Left
The ROL instruction is an abbreviation for ‘Rotate Left’. This instruction rotates the
mentioned bits in the register to the left side one by one such that leftmost bit that is
being rotated is again stored as the rightmost bit in the register, and it is also stored in
the Carry Flag (CF).

While

SHL : Shift Left

The SHL instruction is an abbreviation for ‘Shift Left’. This instruction simply shifts the
mentioned bits in the register to the left side one by one by inserting the same number
(bits that are being shifted) of zeroes from the right end. The leftmost bit that is being
shifted is stored in the Carry Flag (CF).

ii)The reason is that offset ASC_TBL is calculated during translation - like being be
preprocessed- but, LEA is an actual processor instruction. you can't use the offset
instruction to get the addresses that aren't known before the compilation time.

The lea instruction places the address specified by its first operand into the register
specified by its second operand. Note, the contents of the memory location are not
loaded, only the effective address is computed and placed into the register.

While

iii)The NOT instruction implements the bitwise NOT operation. NOT operation reverses
the bits in an operand. The operand could be either in a register or in the memory.

While

NEG Changes the arithmetic sign of the contents of a general-purpose register and
places the result in another general-purpose register.

4b)

INT 21H will generate the software interrupt 0x21 (33 in decimal), causing the function
pointed to by the 34th vector in the interrupt table to be executed, which is typically an
MS-DOS API call.
4c)

Differences Between Isolated I/O and Memory Mapped I/O:

Isolated I/O No. Memory Mapped I/O

Isolated I/O uses separate memory 01 Memory mapped I/O uses memory
space. from the main memory.

Limited instructions can be used. 02 Any instruction which references to

Those are IN, OUT, INS, OUTS. memory can be used.

The addresses for Isolated I/O 03 Memory mapped I/O devices are
devices are called ports. treated as memory locations on
the memory map.

IORC & IOWC signals expands the 04 IORC & IOWC signals has no
circuitry. functions in this case which
reduces the circuitry.

Efficient I/O operations due to using 05 Inefficient I/O operations due to

separate bus using single bus for data and
addressing

Comparatively larger in size 06 Smaller in size

Uses complex internal logic 07 Common internal logic for memory

and I/O devices
 Slower operations 08 Faster operations

5a)

1. Since microprocessor is writing to the OUTPUT device the signal DT/R should be
high. It is because data transmission is taking place. This is indicated by pulling the
signal high after first clock cycle. During first clock cycle address of corresponding
output device will be latched. This is indicated by the ALE signal high during first clock
cycle.

2. Based on the output device M/IO signal also needs to be activated. If writing to IO
device it should be 0 and is indicated by pulling the signal down or if it is to memory
then pull it up

3. Pulling DEN signal down indicaated data is enabled at this time

5b)

Differentiate between minimum and maximum mode of opeartion of 8086

microprocessor. In minimum mode there can be only one processor i.e. 8086. In
maximum mode there can be multiple processors with 8086, like 8087 and 8089.
MN/¯MX is 1 to indicate minimum mode.

5c)

6a)

Specifications 80286 80386 80486

CPU Speed 6 to 25 MHz 12 to 40 MHz 16 to 100 MHz

Cores 1 1 1

RAM 16MB 4GB 4GB

Functional Units 4 6 9

Pipeline stages 3 3 5

Cache off chip 0 YES (Support) YES (Support)

Cache on chip 0 0 8 KB

Transistors 134,000 275,000 >1000000

6b)

6c)

80286 and up: IOPL (I/O privilege level) : It holds the privilege level at which your code
must be running in order to execute any I/O-related instructions.

NT – Nested task flag (bit D14) – When set, it indicates that one system task has
invoked another through a CALL instruction as opposed to a JMP. For multitasking this
can be manipulated to our advantage

7b)

Architecture of 80386

(i)80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit
operations in one cycle. It has a data and address bus of 32-bit each. Thus has the
ability to address 4 GB (or 232) of physical memory.

(ii)The Internal Architecture of 80386 is divided into 3 sections.

(a) Central processing unit, (b) Memory management unit, (c)Bus interface unit

(iii)The Memory management unit consist of a Segmentation unit and a Paging out.

(iv)Segmentation unit allows segments of size 4Gbytes at max.

(v)The Paging unit organizes the physical memory in terms of pages of 4kbytes size
each.

(v)The Segmentation unit provides a 4 level protection mechanism for protecting and
isolating the system code and data from those of the application program.

Technical Aspects of Pentium’s Memory Management Unit

Virtual Memory Management in Pentium

The memory management unit in Pentium is upward compatible with the 80386 and
80486 microprocessors. The linear address space for Pentium microprocessor is 4G
bytes that means from 0 to (232 – 1).
MMU translates the Virtual Address to Physical address in less than a single clock cycle
for a “HIT” and also it minimizes the cache fetch time for a “MISS”. CPU generates
logical address which are given to segmentation unit which produces linear address
which are then given to paging unit and thus paging unit generates physical address in
main memory. Hence, paging and segmentation units are sub forms of MMUs.

Logical to Physical Address Translation in Pentium

Pentium can run in both modes i.e. real or protected. Real mode does not allow
multi-tasking as there is no protection for one process to interfere with another whereas
in protected mode, each process runs in a separate code segment. Segments have
different privilege levels preventing the lower privilege process (such as an application)
to run a higher privilege one (e.g. Operating system). Pentium running in Protected
mode supports both segmentation and segmentation with paging.

Segmentation: Pentium

This process helps in dividing programs into logical blocks and then placing them in
different memory areas. This makes it possible to regulate access to critical sections of
the application and help identify bugs during the development process. It includes
several features like to define the exact location and size of each segment in memory
and set a specific privilege level to a segment which protects its content from
unauthorized access. [6]

Segment registers are now called segment selectors because they do not map directly
to a physical address but point to an entry of the descriptor table.

Pentium CPU has six 16 bit segment registers called SELECTORS. The logical address
consists of 16 bit of segment size and 32 bit offset. The below figure shows a
multi-segment model which uses the full capabilities of the segmentation mechanism to
provide hardware enforced protection of code, data structures, and programs and tasks.
This is supported by IA-32 architecture. Here, each program is given its own table of
segment descriptors and its own segments.
7C)

MyMacro2 MACRO

LOCAL label1,

label2

CMP AX, 2

JE label1

CMP AX, 3

JE label2

label1:

INC AX

label2:

ADD AX, 2

ENDM

ORG 100h

MyMacro2

MyMacro2

RET

CODE SEGMENT ASSUME CS:CODE FACT MACRO MOV BX,AX DEC BX BACK:
MUL BX DEC BX JNZ BACK ENDM START: MOV AX,7 FACT MOV AH,4CH INT
21H CODE ENDS END START
8a)

A thread is a basic unit of CPU utilization, consisting of a program counter, a stack, and
a set of registers, ( and a thread ID. ) Traditional ( heavyweight ) processes have a
single thread of control - There is one program counter, and one sequence of
instructions that can be carried out at any given time.

TurboMode (TM) is a form of dynamic voltage frequency scaling (DVFS). Unlike prior
applications of DVFS which de- crease CPU clock frequency and voltage to save power,
TM oper- ates in the opposite direction. Namely, TM increases CPU clock frequency in
the active cores when a multi-core processor has idle resources.

8b)
The Core i3 range is entirely dual core, while Core i5 and i7 processors have four
cores.It is difficult for an application to take advantage of the multicore system. Each
core is effectively its own processor – your PC would still work (slowly) with just one
core enabled.

19/20
1a)
A single processor system contains only one processor. So only one
process can be executed at a time and then the process is selected from
the ready queue. Most general purpose computers contain the single
processor systems as they are commonly in use.
A multicore processor is an integrated circuit that has two or more
processor cores attached for enhanced performance and reduced power
consumption. These processors also enable more efficient simultaneous
processing of multiple tasks, such as with parallel processing and
multithreading.

Assembly language is used to directly manipulate hardware, access

specialized processor instructions, or evaluate critical performance issues.
These languages are also used to leverage their speed advantage over high
level languages for time-sensitive activities such as high frequency trading.

1b)
Got it
1c)
The DUP operator is very often used in the declaration of arrays This
operator works with any of the data allocation directives. the count value
sets the number of times to repeat all values within the parentheses.
For example, the statement allocates the integer value 1 five times for a total of 5 bytes.:

The DUP Operator

barray BYTE 5 DUP (1)

The following examples show various ways for allocating data elements with the DUP operator:

Different uses of the DUP Operator

array DWORD 10 DUP (1) ;10 doublewords
initialized to 1
buffer BYTE 256 DUP (?) ;256-byte buffer
masks BYTE 20 DUP (040h, 020h, 04h, 02h) ;80-byte buffer with bit
masks
threed DWORD 5 DUP (5 DUP (5 DUP (0))) ;125
doublewords initialized to 0

2a)
2a

2b)
4a
2c)
3A)

The 8086 has four special segment registers: cs, ds, es, and ss. These stand for Code
Seg- ment, Data Segment, Extra Segment, and Stack Segment, respectively. These
registers are all 16 bits wide. They deal with selecting blocks (segments) of main
memory.

3c)
3c
4a)
Timing diagram\

4b)
4b
4c)
4c

S.No Interrupt Polling

1. When it comes to an interrupt, the When it comes to polling, the CPU

device informs the CPU that it needs its keeps on checking if the device
attention. needs attention.
 2. It is a hardware mechanism, not a It is a protocol and not a hardware
protocol. mechanism.

3. Here the system is functioned by an Here the system is serviced by a

interrupt handler. CPU.

4. It can occur at any time and moment. Here the CPU polls the system at
some particular intervals.

5. In the case of an interrupt, the In the case of polling, the

Interrupt-request line indicates that the command ready bit suggests the
device requires assistance. device requires service.

5a)

5b)
6c

6c)

7a)
A segmented memory model divides the system memory into groups of independent
segments referenced by pointers located in the segment registers. Each segment is
used to contain a specific type of data.

In 8086 microprocessor memory are divided into four parts which is known as the
segments. These segments are data segment, code segment, stack segment and extra
segment.

7b)
The program counter (PC) is a register that manages the memory address of the
instruction to be executed next. The address specified by the PC will be + n (+1 for a
1-word instruction and +2 for a 2-word instruction) each time one instruction is
executed.

7c)
Got it
8a)
Real mode, also called real address mode, is an operating mode of all x86-compatible
CPUs. The mode gets its name from the fact that addresses in real mode always
correspond to real locations in memory.
Protected mode is a mode of program operation in a computer with an Intel-based
microprocessor in which the program is restricted to addressing a specific contiguous
area of 640 kilobytes. Intel's original PC microprocessor, the 8088, provided a one
megabyte (1 Mbyte) random access memory (RAM).
In the 80386 microprocessor and later, virtual 8086 mode (also called virtual real mode,
V86-mode, or VM86) allows the execution of real mode applications that are incapable
of running directly in protected mode while the processor is running a protected mode
operating system.

8b)
The 80386DX Intel processor has a 32-bit external bus and a 32-bit address bus.
Memory access is faster with the DX Intel processor. The SX takes two fetches to get a
piece of memory, whereas the DX takes only one fetch. Also, the SX is limited to 16MB
of addressable memory, while the DX may have as much as 4GB.

8c)
 2020
2C)

3B)