Embedded System Programming

(RX63N-GR)
 Embedded programming

Chapter 1 Compiler for Embedded C Language

« Learning Goals »

 Understand the differences between general C language and embedded C

language.

 Understand the types and sizes of C language that can be used by RX

microcomputers.

 Understand the rules for storing arguments in RX microcomputers.

 Understand the handling of local variables in embedded C language.

 Understand the handling of global variables in embedded C language.

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1.1 Differences between general C language and

embedded C language
 Differences between general C language and embedded C language

General C language Embedded C language

Assumed to work on OS Not always assumed to work on OS
Assumed that the memory area used by The initialization of memory area used by
stack pointers and variables has been stack pointers and variables are basically
completely initialized initialized manually.
The specifications of functions are The specifications of functions may be
predefined. defined independently.
Memory allocation and initialization are Memory allocation and initialization are
performed by OS. basically performed manually.
Both data and programs are basically Basically data with initial values and
allocated on RAM. programs are allocated on ROM.
Standard functions are used. Standard functions are rarely used.

 Memory allocation
With the general C language, the location of variables on memory is basically determined by compiler. With the
embedded C language, you can independently specify the fine allocation in the unit of variable by using #pragma
extension description.

 The specifications of functions may be defined independently.

For example, you can independently define the function for power on process by using #pragma extension
description or the interrupt function by using _ _ interrupt modifier, allowing the embedded C compiler to let such
functions to behave differently than usual functions.

Examples)
#pragma entry (vect=0) void PowerON_Reset (void) { /* function processing */}
_ _interrupt (vect=vector number) void function name (void) { /* interrupt processing function main body */ }

 #pragma extension description

#pragma is the key word for compiler-dependent extension specification. #pragma extension description will be
described later.

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1.2 Language specification of compiler for RX

microcomputers (CC-RX)
 Compiler for RX microcomputers (CC-RX)
 C/C++ compiler for RX microcomputer (CC-RX) is designed for the development of
systems stored on ROM for embedded purposes. Therefore, the language specifications
contain the extended functions other than ANSI standard.

Items other than ANSI standard

Defined items of
ANSI standard
Structure of control statements, variable
declaration, function definitions, etc.

#pragma, embedded functions, etc.

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1.2.1 Types and sizes of variables

 Type definition of variables and functions

Types of variables and Size

Range of values
functions (bytes)
char 1 0 to 255
signed char 1 -128 to 127
short 2 -32768 to 32767
unsigned short 2 0 to 65535
int 4 -2147483648 to 2147483647
unsigned int 4 0 to 4294967295
long 4 -2147483648 to 2147483647
unsigned long 4 0 to 4294967295
long long 8 -9223372036854775808 to 9223372036854775807
unsigned long long 8 0 to 18446744073709551615
float 4 7.0064923216240862e-46f to 3.4028235677973364e+38f
double 8 4.9406564584124655e-324 to 1.7976931348623158e+308

 int type and short type

Confirm the size of int and short before starting your development. int depends on the compiler. With RX, the size is
4 bytes (32 bits). With RX, the size of short is 2 bytes (16 bits). Under the ANSI C standard, it merely stipulates by
the expression short <= int <= long that the size increases or stays the same in this order, and does not stipulate the
size of these types or the internal expression.

 char type
The default of char type (when unsigned or signed is not shown explicitly) is implementation dependent. Depending
on the CPU of microcomputer, the default of some is signed and, in some cases, you can select signed or unsigned.
You need to be very careful.

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1.2.2 Rules for storing arguments

 Allocated area for arguments
 Arguments are allocated to general registers R1 to R4 in the order of declaration, and
thereafter allocated to stacks.

Fig. 9.2 Rules on allocation to and release of stack frame

Stack Registers for storing arguments
↑ Lower address

Return PC

Argument area
Allocated area for arguments

[CCRXM]

 What is allocated to one general register is a variable with the length of 4 bytes or less such
as char and int.
 A variable with 4 bytes or longer (such as long long and double) will be handled by 2
general registers.

 A problem of argument storing in prototype declaration

 Argument storing without prototype declaration will not be guaranteed.
* Hereinafter the description where reference to "CC-RX Compiler User's Manual" is referred to will be denoted as [CCRXM]. 5

 Rules for storing arguments

When a C language program is translated to assembly language, as many arguments are allocated to registers as
possible to have the C language program work in a high speed. This is because using stacks will take time to read
from and write to memory. You should refrain from using many arguments. Since the number of registers varies with
microcomputers, the ways to allocate arguments to registers and the maximum number of allocation are varied. In
the case where debugging is done while confirming the result of translation from C language to assembly language,
or a program is created by both C language and assembly language, you need to take note of rules for storing
arguments.

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1.3 Handling of local variables

 Variables of integer type

 Basically variables of integer type are allocated to registers.
 When allocating to registers explicitly, register memory class must be designated.

 Variables with multiple elements such as struct and array

 The struct and union whose size is 16 bytes or less and a multiple of 4 are the objects of
passing on the registers and others are objects of passing on the stacks.
 Arrays are allocated to stacks.
 If using stacks is undesirable, the variables can be secured in static area by designating the
static memory class.

 What happens if initial values are set up for local variables of struct or array?
 Initial value setting will be executed each time the declared function is called.
 Initial values are secured also in the area other than stacks.

 Local variables
Local variables not using stacks but using registers will effectively improve the performance of programs with no
read and write actions from/to memory.

 register memory class

With regard to register memory class specifier, ANSI C describes
"when the identifier expressing the object is declared by memory class specifier register, it suggests that the access
to such object should be made as fast as possible. The range where such suggestion takes effect shall be defined
by implementation ."
Hence you cannot expect that the registers are always allocated to local variables just because register memory
class specifier is used. Pay special attention to the use of register memory class specifier.

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1.4 Handling of global variables

 Global variables or static variables with initial values

 These are allocated to both ROM and RAM, and the initial values will be copied from
ROM to RAM at the power-on reset.
 Since the initial values are allocated to ROM, the data area will be increased.

 Global variables without initial values

 They are allocated to RAM only, and the initial values will be set at 0 at power-on reset.
 Though they are not allocated to ROM, more instructions for initialization will be
required.

 Variables with const declaration

 The variables with const declaration will be allocated to ROM with initial values.

 Initialization of global variables without initial values

While the initial value of global variables without initial value is set to 0 under ANSI C, when any value other than 0
is to be set as the initial value, programmers need to issue instructions to initialize for each variable.

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End-of-chapter test -1.1-

Select the suitable words for the empty boxes [ ] from the Options and answer by
symbols.

Embedded C language does not always work on [ 1 ]. For this reason, memory
allocation and [ 2 ] will be basically done manually.
Since the rules for storing the arguments (area of allocating arguments) in embedded C
language is varied with microcomputers to microcomputers, special care needs to be paid
for rules for storing the arguments. For example, with the compiler for RX microcomputer
(CC-RX), the increased number of functions will cause the allocation to [ 3 ] rather than
to registers. Therefore the performance of program will be [ 4 ].
[ 5 ] with initial values are allocated to both ( 6 ) and RAM, and the initial values will be
copied from [ 6 ] to RAM at the power-on reset. [ 5 ] without initial values are allocated
RAM only, and the initial values will be set at [ 7 ] at the power-on reset.

<Options>
a. OS b. PC c. register
d. stack e. local variable f. global variable
g. ROM h. faster i. slower
j. initialization k. 0 l. 1
8

Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the differences between general C language and embedded C language.

 Explain the types and sizes of C language that can be used by RX

microcomputers.

 Explain the rules for storing arguments in RX microcomputers.

 Explain the handling of local variables in embedded C language.

 Explain the handling of global variable in embedded C language.

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 Embedded programming

Chapter 2 Execution of Program

« Learning Goals »

 Understand the allocation to memory area and section.

 Understand the designation related to stacks.

 Understand the access to processor status word (PSW).

 Understand the way for interrupt processing.

10

This chapter describes various measures, designations and processing that need to be performed before main
function required before the execution of embedded C language that are different from the execution of general C
language programs. Though the contents described here are based on the particular RX microcomputers that are
used in the exercise, the notion, terms, mechanism, description unique to compiler and those things provided by the
integrated development environment are largely common to many microcomputers with some variations.

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2.1 Allocation to memory area and section

 Section name definition of compiler for RX microcomputers (CC-RX)

 Compiler for RX microcomputers (CC-RX) sets up the section name definition as follows.
Section name Attributes Range
P Program code (instruction)
C Constant (with designation of const)
ROM portion (initial value) of static variables with initial values (initial values being
D
designated at declaration) ROM
C$DSEC Information on address and size of D section and R section
C$BSEC Information on address and size of B section
C$VECT Variable vector table
R RAM area of D section (the same size with D section)
B Static variables without initial values RAM
S Stack area

 Since section D is the ROM portion of variables with initial values, the initialization of
copying the initial values stored in ROM to RAM is necessary.
 According to ANSI language specification, section B even without initial values needs to set
the initial values to 0.

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 Variable vector table

The variable vector table is described in "7.4 Vector table" in details.

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2.2 Configuration of program

 Startup program prepared by CS+

 CS+ provides the following startup programs.
Table 8.1 List of programs generated in the integrated development environment

File names Contents

(a) resetprg.c Initial setup routine (reset vector function)

(b) intprg.c Definition of vector function
(c) vecttbl.c Fixed vector table *1
(d) dbsct.c Initialization processing for section (table)
(e) lowsrc.c Low level interface routine (C language portion)
(f) lowlvl.src Low level interface routine (Assembly language portion)
(g) sbrk.c Low level interface routine (sbrk function)
(h) typedefine.h Type definition header
(i) vect.h Header of vector function
(j) stacksct.h Setup of stack size
(k) lowsrc.h Low level interface routine (C language header)
(l) sbrk.h Low level interface routine (header of sbrk function)
[CCRXM]

 When a project is created, C language source files with the project name are created in
addition to startup program. In those files, main function is described.

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2.3 Initial setup routine (1)

 What is initial setup routine?

 To execute programs written in C language on a microcomputer, a program for storing into
ROM and starting up the user programs (main function) needs to be separately prepared.
This program is called initial setup routine.
 When a project is created by CS+, an initial setup routine resetprg.c is provided as one of
startup programs.

Initial setup routine Program of Program of

(resetprg.c) C language machine language
#pragma entry PowerON_Reset_PC main() 7001F0FF
{ FD68ECFB
void PowerON_Reset_PC(void) • EA0001FD

+
{ • 68E305C8
• • 060003FB
• } EE000001
• FD68E005
main(); Link 9F060000
•
•
}

This is a program that is executed from Executes program After resetting, executes
the address indicated by the program from main function. programs sequentially from
counter after reset and, upon initialization the address indicated by the
of variables, calls the main function. program counter. 13

 Initial setup routine

This function is executed before main function after power-on reset. With the compiler for RX microcomputer (CC-
RX), following processing is executed.
(i) Setup of stack pointer
(ii) Setup of interrupt table register (INTB)
(iii) Initialization of static variable area
(iv) Setup of processor status word (PSW)
(v) Others such as setup of control register and initialization of hardware

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2.3 Initial setup routine (2)

 Initial setup routine for RX microcomputer
 The function PowerOn_Reset_PC of initial setup routine for RX microcomputer is the
function to describe the procedure necessary before and after executing main function.
resetprg.c
Power On and Reset #include <machine.h>
#include "stacksct.h"
PowerON_Reset_PC #pragma entry PowerON_Reset_PC

Setting for interrupt void PowerON_Reset_PC(void)

table register {
set_intb(__sectop("C$VECT"));
Initialization of static
variable area
_INITSCT();
Initialization of PSW
register set_psw(PSW_init);

main();
main function calling
brk();
brkfunction calling }
stacksct.h
End #pragma stacksize su=0x100
#pragma stacksize si=0x300
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 brk function
After calling main function, user program will start working. In embedded systems, when main function is completed
in the state of power on, the control will never move to the next instruction. However, when such event should
happen, CPU will stop issuing instruction by using brk function.

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2.4 Designation related to stacks

 Initialization of stack
 For initialization of stack, entry function designation is used.
#pragma entry[(]< function name>[)]
The function designated by <function name> is treated as entry function.
With entry function, no output of register saving or return code will be executed by compiler.
When #pragma stacksize is declared, the initial setup code for stack pointer is outputted at the beginning
of function.

(1) The size of stack area is designated by stacksct.h.

#pragma stacksize su=0x100
#pragma stacksize si=0x300

(2) When PowerON_Reset_PC function is built, initial setup of stack pointer is expanded to
top of the function by assembly language codes.

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 Mixed mode display of CS+

#pragma entry PowerON_Reset_PC

_PowerON_Reset void PowerON_Reset_PC(void) Initial setup code
MVTC #00000508H,USP of stack pointer
MVTC #00000808H,ISP
{
set_intb(__sectop("C$VECT"));
MOV.L #-000FFE90H,R14
MVTC R14,INTB
_INITSCT();
BSR.A __INITSCT
MOV.L #010000H,R14
set_psw(PSW_init); // set Ubit & Ibit for PSW
MVTC R14,PSW
main();
BSR.A _main
brk();
BRK
RTS
}

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2.5 Access to processor status word (PSW)

(1) Method for accessing PSW

(i) To access PSW, following embedded function is used.
(ii) When built, special operation instructions in assembly language rather than function
call are directly developed.
(iii) When embedded function is used, inclusion of machine.h file will be necessary.

(2) Embedded function for accessing PSW

Setup to PSW set_psw (setup value) ; MOV.L #setup value,R14
MVTC R14,PSW
Reference to PSW variable = get_psw() ; MVFC PSW,R14
Interrupt permission setpsw_i() ; SETPSW I
Disabling of interrupt clrpsw_i() ; CLRPSW I

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 Include of machine.h
Since machine.h file is stored in the standard location to search by compiler CC-RX (the folder specified by
environment variable PATH),
#include <machine.h>
machine.h is enclosed by inequality sign "<" at left side and inequality sign ">" at right side.

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2.6 Way for interrupt processing

 Special nature of interrupt processing programs

 Interrupt processing programs always return by RTE instruction.
 Since an interrupt program must allow for being executed at any place, saving of registers
used in an interrupt program and return thereof must be secured.
 It is necessary to register the top address of interrupt processing program to vector.

 #pragma interrupt declaration

 When #pragma interrupt declaration is done for the function name that makes up the
interrupt program, the processing necessary for interrupt is added inside the function at
the building.
#pragma interrupt func (vect = vector number) <C language>
void func(){ .... }

Build

_func: <Assembly language>

PUSHM R1-R3 ; Registers used in the function is saved.
・・・
(R1, R2, R3 are used in the function.)
・・・
POPM R1-R3 ; Registers saved are returned.

RTE
17

 Registering the top address of interrupt processing program to vector

As shown in the slide, when some processing necessary for interrupt is added to a function to act as an interrupt
processing program and at the same time vector table is specified (vect= vector number) by #pragma interrupt
declaration, the address of such function (the top address of interrupt processing program) is registered to the
specified vector table number position in C$VECT section where variable vector table is allocated to (see "2.1
Memory allocation and section.").

 Setup of interrupt table register (INTB)

The top address of C$VECT section mentioned above needs to be set up at interrupt table register (INTB). This is
because when an interrupt is accepted, the value of PC is modified to the address in the area designated by INTB+
(the corresponding interrupt request vector number x 4). (See "7.3 Flow of RX63N interrupt actions.") Therefore
INTB must be set up before the permission of the interrupt (See "2.3 Initial setup routine (2).")

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2.7 Initialization of static variable area

 Initialization of static variable area

(i) The initialization of static variable area will require the information such as the top
address of the section and its size.
(ii) Such information is stored in two areas, C$DSEC and C$BSEC.
(iii) Based on these pieces of information, the static variable area is initialized.

 In the case of no OS
An initialization program written in assembly language is separately required.

 In the case of CS+ environment

The initialization program in the initial setup routine that is automatically generated by CS+
(_INITSC function) is used. (See "2.3 Initial setup routine (2).")

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End-of-chapter test -2.1 -

Select the suitable words for the empty boxes [ ] from the Options and answer by
symbols.
The C compiler for RX microcomputer manages the allocation of such items as
program code, constants and variables in the unit of [ 1 ]. [ 1 ] has varied allocation
memory areas depending on the name and attributes.
The integrated development environment CS+ prepares [ 2 ] at the time of generating
projects. While [ 2 ] consists of multiple files, [ 3 ] is the program executed at first at the
time of power on. The _INITSCT function contained in [ 3 ] initializes [ 4 ] area so that
C language program can use the data after main function.
The C compiler for RX microcomputer prepares [ 5 ] as the method for accessing
PSW. To use [ 5 ], you need to include [ 6 ]. Also, when interrupt processing function
declares [ 7 ], the processing necessary for interrupt will be added at the time of
building.

<Options>
a. startup program b. static variable c. dynamic variable
d. prolog program e. block f. section
g. iodefine.h h. machine.h i. HardwareSetup function
j. embedded function k. register function l. flag function
m. #pragma interrupt n. #pragma inline o. PowerON_Reset_PC function
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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the allocation to memory area and section.

 Explain the stack related designation.

 Explain the method to access the processor status word (PSW) from C language.

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Chapter 3 Outline of Exercise Board

« Learning Goals »

 Understand the outline of GR-SAKURA_eMboarD.

 Understand the basics necessary for exercise.

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3.1 Block diagram -1-

 Configuration of GR-SAKURA_eMboarD
 GR-SAKURA_eMboarD consists of CPU board (GR-SAKURA) and the extension board
(eMboarD).
 For the block diagram of RX63N, see p67 of RX63N User's Manual: Hardware.
 Block diagram of GR-SAKURA

Arduino compatible (CN7) Arduino compatible (CN8)

Extension connector (CN9) Extension connector (CN10)

LAN Clock
12MHz
Switch

JTAG (CN6)
RX63N
Clock
32kHz
USB Boot mode
changeover switch

5V power Extension connector (CN11)

supply Extension connector (CN13)
LED Extension connector (CN12)

Arduino compatible (CN14) Arduino compatible (CN15)

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3.1 Block diagram -2-

 Block diagram of eMboarD

Stepping motor RS232C CAN
Connector Connector Connector
connector connector connector
RS232C CAN Buzzer
changeover Termination
resistor

0 1 2 3 4 5 6 7 8 9 a b c d e f Optical
16x2 LCD Acceleration sensor
0 1 2 3 4 5 6 7 8 9 a b c d e f sensor
Temperature
sensor

Power switch
Power source LED
7 segment LED
12V power
supply
Connector
LED

Analog switch

GR-SAKURA

Volume Volume
Extension Extension
switchover switchover

Switch Switch
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3.2 Circuit diagrams

 eMboardD circuit diagram (outline)

 The diagram of eMboarD is shown at the end of the document. In the exercise, the control
program is created while confirming the diagram.

GR-SAKURA I 2C Analog Volume Sensor

switch

Switch Buzzer
UART Motor

LED

CAN
Power source circuit
LCD

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3.3 RX63N Manual

 Basic materials necessary for this exercise (to be presented by pdf)

 "RX63N Group User's Manual: Hardware"

 R01UH0041JJ0180 Rev.1.80 issued on April 25, 2014

 "RX Family User's Manual: Software"

 R01US0032JJ0120 Rev.1.20 issued on April 15, 2013

 "CC-RX Compiler User's Manual"

 R20UT3248JJ0108 Rev.1.08 issued on April 1, 2019

 In addition to above, more materials are stored in the folder. You are requested to see
them as necessary.

* The chapters hereafter will be described while doing the exercises. Exercise Volume: Read
Chapter 1 through Chapter 12 carefully.

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End-of-chapter test -3.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

GR-SAKURA_eMboarD consists of [ 1 ] (GR-SAKURA) and the [ 2 ]

(eMboarD).
On GR-SAKURA, [ 3 ] bit microcomputer RX63N from Renesas Electronics
and an oscillator of [ 4 ] MHz for the main clock are mounted.
On the extension board, such components as LED, switches, [ 5 ] that allows
display of 4 digits and [ 6 ] that allows display of 16 digits x 2 columns are
mounted. Also, [ 7 ] for asynchronous serial communication is mounted.

<Options>
a. CPU board b. extension board c. general purpose board
d. memory board e. 12 f. 16
g. 32 h. 64 i. 96
j. 7 segment LED k. color LED l. RS232C connector
m. touch panel n. LCD o. LAN connector

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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the outline of GR-SAKURA_eMboarD to be used in the exercise.

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Chapter 4 I/O Control Program

« Learning Goals »

 Understand the I/O control program using the general purpose I/O port of
RX63N.

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4.1 RX63N terminals (pins)

 What is a terminal (pin)?

 Terminal (pin) <=> physical wiring on a board <=> input/output port for sending/receiving
signals between equipment
 Types of terminals (pins)
 Terminals consist of power terminals, clock terminals, system control terminals and I/O
ports.

The layout diagram of terminals

(pins) for RX microcomputer can
be seen at the note portion.

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 Terminal (pin) allocation diagram (100 pin LQFP)

Though in the diagram shown below, each terminal (pin) has its own one name, most of terminals (pins) have
multiple functions
and have multiple terminal names.
Hereinafter, when "RX63N Group, RX631 Group Users' Manual, Hardware Edition, Rev. 1.80 2014.04, Renesas
Electronics Corporation“ is referred to, the manual name is described as [UMH].

RX63N Group
RX631 Group

(100 pin LQFP)

(top view)

Note: Pin allocation diagram shows power terminal and I/O port as well.
For the terminal configuration, see "Table 1.10 List of terminals by functions (100 pin LQFP)."
[UMH]
Table 1.9 Terminal allocation diagram (100 pin LQFP)

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4.2 I/O port for RX63N

 I/O port
 Most of I/O ports can be selected from
using as a general purpose I/O port, or
using as a peripheral function (built-in I/O terminal, bus and bus control terminal, interrupt input
terminal).
 At the initial state, I/O port is allocated to general purpose I/O port. (PMR=0x00)

 Registers of I/O ports

 The register can be set up by 1 bit as a unit or 8 bits as a I/O port
unit. Peripheral
function
 Port direction register (PDR)
 This register determines a terminal to be either inputted or General purpose I/O port
outputted. ("0": input "1": output)
 Port output data register (PODR) PDR
 This is a register to store the data to be outputted to terminals. Port direction register

("0": Low "1": High)

PODR
 Port input data register (PODR)
Port output data register
 This is a register to reflect the state of terminals.
PMR
("0": Low "1": High)
PIDR
 Port mode register (PMR) Port input data register
 This is a register to set up the terminal function of the port.
("0": used as general purpose I/O port "1": used for peripheral
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4.3 What is general purpose I/O port?

 General purpose I/O port

 General purpose I/O port is also called GPIO, and is a gate for digital signals that can be
used for both input and output.
 It is used for circuits that can be controlled only by High and Low of voltage such as LEDs
and switches.

Microcomputer

General purpose I/O port LED

Switch

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4.4 LED lighting circuit basics (1)

 LED circuit
 LED is a device that lights up by the flow of electric current. Connecting + (plus) of battery
to anode side and - (minus) to cathode side and applying electric current will light up the
LED. Resistor is inserted between battery and LED to restrict the electric current.

Physical Wiring Diagram Circuit diagrams

LED1
+ -
+3V
TLR114
LED1
-
A

R1 330
R1 330
K

TLR114

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 Anode
Anode is the electrode to which electric current flows from external circuit.

 Cathode (Kathode in German)

Cathode is the electrode from which electric current flows out to external circuit.

 Electric current limiting resistors

LED emits brighter light as more electric current is applied but each LED chip has the maximum electric current
value (maximum rated electric current IF) defined. The resistor to restrict the electric current below this value is
called electric current limiting resistor.

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4.4 LED lighting circuit basics (2)

 LED control circuit using a microcomputer

 Here we try to control LED by using the terminals of microcomputer (port) instead of
switches. By setting the state of port to either "High" or "Low," you can turn the light on and
off.

Low High
Port Port

Turning off Turning on

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4.4 LED lighting circuit basics (3)

 LED control circuit for GR-SAKURA

 Here we try to control LED by using the terminals of microcomputer (port) instead of
battery. There are 4 LEDs from D1 to D4 in GR-SAKURA.
 As it is clear from circuit diagram, D1 is connected to PA0 (PORTA0). Let's consider the
method to turn D1 on.

LED for users

330Ω×4 device

D4 D3 D2 D1

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4.5 RX63N port direction register

 Port direction register (PDR)

 PDR is a register to designate input or output of a port when the function of general
purpose I/O port is selected.
I/O port
Port direction register (PDR)
Peripheral
function
Addre ss

General purpose I/O port

PDR
Value after reset
Port direction register

Bit Symbol Bit name Function

Pm0 dire ction control bit 0: Input (It functions as input port.)
PODR
1: Output (It functions as output port.)
Pm1 dire ction control bit Port output data register
Pm2 dire ction control bit
PMR
Pm3 dire ction control bit

Pm4 dire ction control bit PIDR

Pm5 dire ction control bit
Port input data register
Pm6 dire ction control bit

Pm7 dire ction control bit

m=0 to 9, A to G, J
[UMH]

35

 PDR of PORTA
The PDR of PORTA connected to anode side of LED D1 is the address 0x0008C00A.
What value should be entered to set the bit 0 of PORTA to "output"?

Register Address Data

PORTA.PDR 0x0008C00A

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4.6 RX63N port output data register

 Port output data register (PODR)

 PODR is a register to store the output data for the terminal that is used as a general
purpose output port.
I/O port
Port output data register (PODR)
Peripheral
function
Addre ss

General purpose I/O port

PDR
Value after reset
Port direction register

Bit Symbol Bit name Function

Pm0 output data storage bit 0: Low output

PODR
1: High output
Pm1 output data storage bit Port output data register
PMR
Pm2 output data storage bit

Pm3 output data storage bit

Pm4 output data storage bit PIDR

Pm5 output data storage bit

Pm6 output data storage bit

Port input data register
Pm7 output data storage bit

m=0 to 9, A to G, J
[UMH]

36

 PODR of PORTA
The PODR of PORTA connected to LED D1 is the address 0x0008C02A.
What value should be entered to set the bit 0 of PORTA to "1"?

Register Address Data

PORTA.PODR 0x0008C02A

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4.7 Port control program (output)

 Program to turn on LED1

(i) Sets up the address of port to pointer variable.
(ii) Sets up the initial value of output data register for the port used and the direction register.
(iii) Turns on the LED.

void main(void)
{
/* variable declaration */
volatile char *porta_pdr =(char *)0x0008C00A;
volatile char *porta_podr=(char *)0x0008C02A;

/* port initialization */
*porta_podr = 0x00; /* Turn-off data is set at PORTA0 output data register. */
*porta_podr = 0x00; /* "1" (output) is set at PORTA0 direction register. */

/* Turn on LED */
*porta_podr=0x01; /* Turn-on data is set at PORTA0 output data register. */

while (1) {
/* termination loop */
}
}

37

 I/O register definition file

It takes time to search the manual and identify all addresses of registers each time. In CS+, iodefine.h that defines
I/O register is prepared.
In the program to turn on LED this time, the LED is turned off in the initialization once and then output setup is done.
While it is not of a problem with LED, it would be dangerous to activate by the output setup if such item as motor is
connected, and you should make it a rule to describe the program in the manner as stop setup -> output setup ->
activation setup.

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4.7.1 iodefine.h

 Defines I/O register.

 In CS+, iodefine.h that defines I/O register is prepared. This allows you to operate the
register by using the symbols of alphabets similar to the description of hardware manual.

struct st_porte { Excerpt of iodefine.h

union {
unsigned char BYTE;
struct {
unsigned char B7:1;
unsigned char B6:1;
unsigned char B5:1;
unsigned char B4:1;
unsigned char B3:1;
unsigned char B2:1;
unsigned char B1:1;
unsigned char B0:1;
} BIT;
} PDR;
・
・
・
define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)

I/O register control using PORTE.PDR.BYTE = 0xFF;

the structure description
38

 In the comment in iodefine.h file prepared by CC-RX compiler, "//" is used.

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4.7.2 Access to I/O register

 Program description using iodefine.h

 When you use iodefine.h by including, the source will have higher readability.
 If you rewrite the source of 4.6 Port control program (output) by using iodefine.h, the result
will be as follows.
#include "iodefine.h"

void main(void)
{
/* port initialization */
PORTA.PODR.BIT.B0 = 0; /* Turn-off data is set at PORTA0 output data register. */
PORTA.PDR.BIT.B0 = 1; /* "1" (output) is set at PORTA0 direction register. */

/* Turn on LED */
PORTA.PODR.BIT.B0 = 1; /* Turn-on data is set at PORTA0 output data register. */

while (1) {
/* termination loop */
}
}

-> "CS+ User's Guide" Program development procedure using CS+ <C language>

-> Practice
39

 Practice
By using the programming development procedure <C language> using CS+, let's create a project and execute a
program by entering the program of the slide.

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4.8 LED lighting circuit application

 LED control circuit using 2 ports

 This is the circuit to control LED by connecting GND side also to the terminal of
microcomputer (port). By setting the state of Port2 to either "High" or "Low," you can control
turning on and off of LED.

High High
Port1 Port1

Turning Turning
Port2 off Port2 on
High Low

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4.9 Current driven type driver

LED circuit of GR-SAKURA_eMboarD

 Since many of ports of microcomputers are voltage drive type and large current cannot
apply, the transistors are used as current driven type drivers.
 In LED circuit of GR-SAKURA_eMboarD, transistor arrays are embedded.
 Transistor array is a device in which multiple transistors are laid out.
 There are source type (large current flows out) and sink type (large current flows in) for
transistor array.

Source driver
LED1

10kΩ
RX63N High High A K
PORTE0

High Low
PORTJ3

-> Embedded programming (exercise problems)

Sink driver 1. Tips for exercises

-> Exercise 1
41

Model number, Pin connection

Overview
external view diagram
TBD62783 Pin connection diagram (top view)
Source type driver
About 500mA can flow out from
1 terminal.

TBD62083 Pin connection diagram (top view) Sink type driver

About 400mA can flow into 1
terminal.

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4.10 Switch input circuit

Switch circuit using general port

 SW3 is pulled up by resistor R9 and connected to bit 5 of PORT0. This indicates that
PORT05 terminal is at High when SW3 is not pressed and stays Low while SW3 is
pressed.

VCC

10kΩ
SW3

RX63N PORT05
GND

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4.11 RX63N port input data register

Port input data register (PIDR)

 PIDR register is a register to reflect the state of terminals used as general input port.
 By reading the PORTm.PIDR register, you can read the state of terminals regardless of the
values of PORTm.PDR register or PORTm.PMR.
I/O port
Port input data register (PIDR)
Peripheral functions
Addre ss

General purpose I/O port

PDR
Value after reset
Port direction register
Undefined

PODR
bit Symbol bit name Function

Pm0 bit 0: Low input

Output data register
Pm1 bit
1: High input
PMR
Pm2 bit

Pm3 bit
PIDR
Pm4 bit Input data register
Pm5 bit

Pm6 bit

Pm7 bit

m=0 to 9, A to G, J [UMH]

43

 PDR of PORT0
The PDR of PORT0 connected to SW3 is the address 0x0008C000.
What value should be entered to PORT0 direction register to set up the bit 5 of PORT0 to "input"?

Register Address Data

PORT0.PDR 0x0008C000

Note that after resetting RX63N, PDR is 0x00.

 PIDR of PORT0
The PIDR (input data register) of PORT0 connected to SW3 is the address 0x0008C040.
Predict the value of PIDR (input data register) of PORT0 when SW3 is not pressed.

Register Address Data

PORT0.PIDR 0x0008C040

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4.12 Port control program (input)

A program is created by using the definition of iodefine.h. The state of SW3 is

reflected to the variable switch3.

#include "iodefine.h"

void main(void)
{
/* variable setup */
volatile char switch3;

/* port initialization */
PORT0.PDR.BIT.B5 = 0;

while (1) {
/* SW1 reading */
switch3 = PORT0.PIDR.BIT.B5;
}
}

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4.13 Circuit of switch and LED control

Circuit of SW and LED

 Let's consider a program that turns off LED1 when SW3 is not pressed and turns on LED1
when SW3 is pressed.
RX63N
When the port is made
High, LED will turn on.

VCC
PORTE0
10kΩ
10kΩ

SW3
PORTJ3

GND PORT05

W hen the switch is The data bit of switch

pressed, the port will be When the port is made
status is inverted and High, LED will turn on.
Low.
output to LED.

-> Exercise 2
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4.14 Control using bit operation and shift operation

A control operation using bit operation or shift operation through BYTE access
rather than using bit field of I/O register defined by iodefine.h is also possible.

Set a specific bit.

 PORTE.PODR.BYTE |= 0x80;
 PORTE.PODR.BYTE |= 1 << 6;

Clear a specific bit.

 PORTE.PODR.BYTE &= ~0x20;
 PORTE.PODR.BYTE &= ~(1 << 4);

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End-of-chapter test -4.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

General I/O port is also called [ 1 ] and you can use it for both input and output
as the gate for [ 2 ] signals.
The general I/O port for RX63N is handled by the unit of [ 3 ] bits. Each port is
controlled by four registers, [ 4 ] (PDR), [ 5 ] (PODR), [ 6 ] (PIDR) and [ 7 ]
(PMR).

<Options>
a. peripheral I/O b. GPIO c. analog
d. digital e. port mode register f. 4
g. port input register h. port direction register i. 8
j. port output register k. 16 l. 32

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Answer Column

Correct
Question Answer
Answer

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End-of-chapter test -4.2-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

Source driver is a transistor array from which electric current can [ 1 ] and sink
driver is a transistor array to which electric current can [ 2 ].
To turn on LED1 in the circuit of bottom right, you need to set the output of
source driver at [ 3 ] by setting the terminal voltage of PORTE0 [ 4 ], while
you need to set the output of sink driver at [ 5 ] by setting the terminal voltage
of PORTJ3 [ 6 ]. Therefore, you should set [ 7 ] to port direction register of
PORTE0, [ 8 ] to port output data register, [ 9 ] to port direction register of
PORTJ3 and [ 10 ] to port output data register.
Source driver

Sink driver

<Options> (You can use one at multiple times.)

a. 0 b. 1 c. flow out
d. flow in e: high f: low
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Answer Column

Correct
Question Answer
Answer

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End-of-chapter test -4.3-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.
In the circuit of bottom right, the terminal of PORT05 is [ 1 ] when SW3 is not
pressed, and the terminal of PORT05 is [ 2 ] when SW3 is pressed.
In order to turn on LED when SW3 is pressed and turn off otherwise, the
program must read [ 3 ] of PORT05 and turn on when [ 4 ] and turn off when
[ 5 ].

<Options>
a. 0 b. 1 c. PODR
d. PIDR e: high f: low

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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the I/O control program that uses general I/O port of RX63N.

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Chapter 5 Timer Control Program

« Learning Goals »

 Understand the time control program that uses timer.

 Understand the mechanism of CMT (compare match timer) for RX63N

and the method of using it.

 Understand the clock setting for RX63N.

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5.1 Types of timers for RX63N

List of timers for RX63N

 On RX63N, following timers are mounted. In this chapter, "CMT (compare match timer)" is
described.

 TPUa (16-bit timer pulse unit)

 MTU2a (Multi-function pulse unit 2)
 PPG (Programmable pulse generator)
 TMR (8-bit timer)
 CMT (Compare match timer)
 RTCa (Realtime clock)
 WDTA (Watchdog timer)
 IWDTa (Independent watchdog timer)

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5.2 Clock

Clock
 Clock generates the timing for microcomputer to work.

*On GR-SAKURA, a clock with 12MHz is mounted. By the setting to use external
clock, the signal of 12MHz from the clock is input to the terminal of RX63N.

Waveform obtained from observing the

terminal of the clock by an oscilloscope

Item
Time

EXTAL Channel
Clock
12MHz
XTAL
Cursor 1

Cursor 2

GR-SAKURA

Clock

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5.3 Clock generation circuit

Count clock of timer
 Before using the timer, the setting of clock to be supplied to the timer is necessary.
 The waveform of 12MHz input from the clock (EXTAL) is multiplied and divided internally,
and is supplied to peripheral module as clean square wave.
 The count clock of timer is peripheral module clock PCLKB. In the exercises of this
training, 48MHz is used generally for setting.
The external clock XTAL (12MHz)
is multiplied by 16 by using the
setting of PLLCR.

Se le ctor
Syste m clock (ICLK)
To CPU, DM AC, DTC, ROM and RAM

Fre que ncy PLL Fre quency divider

divide r circuit
Se le ctor

Se le ctor

Se le ctor
De te c ting Peripheral module clock (PCLKA)
os c illa tion To ETHERC, EDMAC, DEU
s top
Peripheral module clock (PCLKB)
To peripheral modules other than
ETHERC, EDMAC, DEU

48MHz
M ain clock
Se le ctor

oscillator
M ain clock

12MHz

Se le ctor
Sub - clock
oscillator Sub -clock BCLK te rminal

Se le ctor
Exte rnal bus clock (BCLK)
High -speed To e xternal bus controller
on -chip
oscillator HOCO clock SDRAM clock (SDCLK)
To SDCLK te rminal

To be divided according to
Low -speed
setting and supplied to
on -chip
oscillator LOCO clock each clock [UMH]
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5.4 RX63N clock initial setup

External clock setup
 This shows the setup procedure for external clock of GR-SAKURA. RX63N operates on
low-speed on-chip oscillator (125kHz) at reset timing. It is switched over to external clock
for high-speed operation.
Start

Release of register write protection  The maximum operating frequency of RX63N is 100MHz,
while XTAL of GR-SAKURA is 12MHz. Since the setting of
Setup for clock terminals frequency division by 1 is prohibited when multiplier circuit
(PLL) is selected, the clock is multiplied by 16 once to
Oscillator weight control 192MHz and then frequency-divided by 2 to 96MHz which is
then supplied to ICLK (instruction clock: CPU clock).
Startup of main clock oscillator
 The clock used for timer is PCLKB (peripheral clock). The
Setup of PLL clock clock of 48MHz which is frequency-divided by 4 is supplied.

Setup of internal clock frequency-division ratio

 In the exercise problem, the clock initial setting program
PLL circuit connection (initBASE.c) which uses this mechanism is provided.

Stop of unnecessary clocks

Setup of register write protection

End
55

 Register write protection function

The register write protection function protects important registers from being rewritten easily.
When rewriting the protected register, setup for protect register (PRCR) is necessary to obtain permission for
writing. For the details, see Exercise volume of "11.2 Register write protection."

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5.5 Configuration of RX63N CMT (compare match timer)

Configuration of RX63N CMT (compare match timer)

 RX63N has a total of 4 channels inside consisting of 2 units (unit 0 and unit 1) of CMT
(compare match timer) that is built by 16 bit timer each. CMT has a 16-bit counter.

Control circuit Clock selection Control circuit Clock selection

Clock selection
Comparator

Comparator

Internal peripheral bus 2

Bus interface

Internal peripheral bus 2

Module bus

Bus interface

Unit 0
[UMH] Unit 1 56

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5.6 Operation of CMT (Compare match timer)

CMT (Compare match timer)

 CMT is a timer to measure the time.
 It applies the frequency-division to the peripheral module clock (PCLKB) supplied from the
clock and counts up.
 When the count matches CMCOR (compare match timer constant register), it sets the
interrupt request register of the controller.

CMT Interrupt controller

CMCOR (compare match
timer constant register) 1
Selection of count clock
(frequency-division) CMT interrupt request
register
Clock (IR)
Clock generation
circuit
CMCNT (counter)
PCBLKB
12MHz
48MHz

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5.7 Time calculation for compare match timer

1ms is measured by CNT0

 1ms is 1kHz. After applying frequency-division to PCLKB (48MHz) and counting, it detects
1kHz.
 The frequency-division of CMT is selected from 1/8, 1/32, 1/128 and 1/512.
48MHz/8 = 6000kHz Counting 6000 times yields 1kHz. … 
48MHz/32 = 1500kHz Counting 1500 times yields 1kHz. … 
48MHz/128 = 375kHz Counting 375 times yields 1kHz. … 
48MHz/512 = 93750Hz Cannot count 1kHz. … 

*For the count value, the value to be counted minus 1 should be set up.
(This is to notify the event at the next clock of the matching.)
Interrupt controller

CMCOR (compare match

timer constant register) 1

Selection of count clock CMT interrupt request

(frequency-division) register
Clock (IR)
Clock generation
circuit
CMCNT (counter)
PCBLKB
12MHz
48MHz

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5.8 Specifications of RX63N CMT (compare match timer)

Specifications of CMT
 The clock input to the timer is counted by CMCNT to measure the time. When the count
matches the value of CMCOR (the goal value), a compare match interrupt will develop, and
IR bit will turn to"1."

Value of CMCNT
(3) Compare match interrupt develops. -> IR is made to 1.

CMCOR

0000h

Time
(2) Matching of compare match
at CMCOR will reset the counter.

1
IR bit of CMT0
0

Processing Processing Processing

Program at each at each at each
defined time defined time defined time
59

 Specifications of CMT
(i) When frequency division clock is selected and start bit is set at"1," CMCNT counter will start counting up by
using the selected clock.
(ii) When the value of the CMCNT counter reaches that of the CMCOR register, the former will have "0000h."
(iii) At this timing, a compare match interrupt will develop and the corresponding interrupt status flag (IR) is set
at"1."
(iv) The CMCNT counter will restart counting up from "0000h."

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5.9 Initial setup of RX63N CMT(compare match timer)

Initial setup of compare match timer

 Prerequisite
 It is after the completion of setup for clock generating circuit.
 The setup value of the compare match timer to be used stays the initial value after the reset.
 Compare match is detected by polling.

Start

Release of the protection

Release of the module stop

Setup of the protection

Selection of count clock

Permission of compare match
interrupt

Counter initialization

Setting of cycle count

Clearing interrupt flag

Start counting

End
60

 Power consumption reduction function

Some of the peripheral modules of RX63N are at module stop status at the reset due to the power consumption
reduction function. For this reason, such module stop status needs to be released by module stop control register
before they are used. Details are described in Exercise volume of "11.3 Power consumption reduction function."

 Polling
Polling refers to the action in the programming processing to monitor at certain interval and to detect any changes in
signal or status.

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5.10 Control program for RX63N CMT(compare match timer)

The main program in the following exercise uses compare match timer CMT0 to
process by the standard time 1ms cycle. This will make the processing time clearer
and time control easier.

main *By making each processing by 1ms base, the combination will be
made more easily.
*The total of processing time needs to be standard time 1ms or less.
Initial setup It is important to write lean programs by considering the processing well.
of CNT0
1ms
NO
(only once
1ms elapsed?
IR=1?
at first)
1R setting 1R setting 1R setting
(1ms elapsed) (1ms elapsed) (1ms elapsed)
IR <- 0

Input processing Input processing

Data processing

Output processing

Input processing

Data processing

Output processing

Input processing

Data processing

Output processing
1ms
(2nd time
Data processing and after)

Output processing
-> Exercise 3
61

 By providing the reference time using the timer, time control becomes easy.
Generally 1ms cycle or 2ms cycle is often used, but the cycle may be set to longer period when there are much
contents of processing or sampling time can be prolonged.
In those cases where real-time property is demanded such as in communication or shorter sampling time is required
such as sound data, using interrupt can be a better solution. (-> Chapter 7)

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End-of-chapter test -5.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

Timer measures the time by [ 1 ] the basic clock. Since the clock for RX63N is
selected to [ 2 ] at the time of reset, switchover to external clock by initial
setup of program should be done and [ 3 ] of PLL and [ 4 ] for clock to be
supplied to each peripheral module need to be set up.
CMT (compare match timer) for RX63N measures the time by counting the
clock to be input to timer by using CMCNT. Comparing the clock count value
and the CMCOR that is set up, an interrupt will develop when they [ 5 ]. Since,
when the interrupt occurs, interrupt request flag (IR) will be [ 6 ], the time
control can be conducted by [ 7 ] in the program.

<Options>
a. frequency-division ratio b. counting c. multiplication ratio
d. larger e. smaller f. match
g. clear h. set i. sampling
j. polling k. interrupt l. reset
m. high-speed on-chip oscillator n. low-speed on-chip oscillator
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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the CMT (compare match timer) of RX63N.

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Chapter 6 Detection of Pressing Switches

« Learning Goals »

 Understand how to detect pressing of switches.

 Understand what chattering is.

 Understand how to remove chattering by software.

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6.1 Level sensing and edge sensing

Detecting the status change of switch
 The change of input signal at switch circuit can be identified by the status of the connected port.
 For the method to detect (sense) the status change, there are "level sensing" and "edge
sensing."
VCC

10kΩ RX63N
SW3

PORT05
GND

<Level sensing> <Edge sensing>

Port voltage Port voltage

High level

Falling Rising
edge edge

Low level
GND voltage
GND voltage
Time Time 65

 Detection of threshold level and signal changes

In digital circuits, the voltage above certain threshold is called High and the voltage below certain threshold is called
Low. Detecting this kind of level is called "level sensing."
It takes some time for the state of signal to change after being transmitted along the conducting wire.
The changing point of signal waveform is called edge, and the point of change from High level to Low level is called
falling edge while Low to High is called rising edge.
Detecting this edge is called edge sensing.

 Method for detecting (sensing) status change

(i) Level sensing
Judges the status of port directly.
(ii) Edge sensing
There are two methods to realize edge sensing. One is to search the point of change of "High to Low" and
"Low to High" by software through the use of input port.
Since this method is realized by polling, there will be some delay from execution of instruction. The other is to
detect the point of change of signal by hardware through the use of the interrupt signal.

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6.2 Detection of pressing switches

Detection of pressing switches

 Pressing of switches is detected by edge sensing.
 By using the flag that memorizes the status change of the edge and the processing state, a
mechanism is to be created to work only when the switch changes from OFF to ON.
Pressing at Pressing at
the first time 2nd time
Port voltage

GND voltage
Time

Status of
switch
OFF ON OFF ON
Edge
processing 0 1 0 1
flag
(i) Processing (i) Processing
when switch is when switch is
Program pressed Edge flag clear pressed
(ii) Edge flag (ii) Edge flag
setting setting 66

 Flag
As the memory location in a program to indicate that the processing has been completed, variables are prepared.
Since each of these variables uses the data "1"and"0" as the meaning of "set" and "clear" respectively, it is called
flag.

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6.3 Algorithm of detecting the pressing of switch

main

Initialization of the clock A

LED initialization
No
1ms elapsed?
Switch initialization
Yes
CMT0 initialization
Reading switch

No
Is switch pressed?

Yes Set edge processing

completion flag at 0.

Edge processing completed No

Is flag 0?

Yes

Processing

Set edge processing completion flag at 1.

-> Exercise 4a
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6.4 What is chattering?

What is chattering?
 It refers to the phenomenon whereby such items as movable contact point creates very fast
and fine vibration when the point moves to connected state or to disconnected state. It is
caused by the bouncing of contact point.
 The time duration varies with the type or structure of switches, but it lasts for the order of
100μsec to 10msec. The confirmation on specification or actual measurement is
necessary.
Voltage

GND voltage Time

 In the case of edge sensing, multiple events of edge sensing in a short period are detected,
which can cause malfunctions.
 There are solutions by hardware and by software to remove chattering.
68

 (Reference) Removing method by hardware

The signal is gradually changed using resistors and capacitors. After that, by using Schmidt trigger whose
thresholds vary between Low -> High and High -> Low, High and Low are determined.

VCC
R2

SW
(1) R1 (2) (3)
＋
C1

GND GND

(1) (2) (3)

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6.5 Removing chattering by software (1)

Removing chattering by software
 Read the status of switch at the interval longer than the duration of chattering.
 If the chattering period of switch is the order of milliseconds, there will be no impacts on man-
machine interface.

 The case where chattering occurs between a sampling and a sampling

Input port

Sampling

Determined data

 The case where chattering occurs before and after a sampling

Input port

Sampling

Determined data
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6.6 Algorithm of removing chattering (1)

 Read the status of switch at the interval longer than chattering time.
A

No
main 1ms elapsed?

Yes
Initialization of the clock No
Chattering time
elapsed?
LED initialization
Yes
Switch initialization
Reading switch

CMT0 initialization

No
Is switch pressed?

Yes Set edge processing

completion flag at 0.

Edge processing completed No

Is flag 0?

Yes

Processing

Set edge processing completion flag at 1.

-> Exercise 4b 70

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6.7 Removing chattering by software (2)

 Method to read the status of switch at the interval longer than the chattering time
 When a noise occurs, there can be a case where the switch status has wrongly been recognized to
have changed.

Noise
Input port

Sampling

Determined
data

 Under this method, the switch status is read by the interval longer than the chattering time
and the data is recognized to be the determined data only when the data of reading twice
match.
 Wrong detection cannot occur often even when noises occur.
Noise
Input port

Sampling

Determined
data

The status change will be reflected The status change will not take place because
because the data of reading twice match. the data of reading twice do not match. 71

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6.8 Algorithm of removing chattering (2)

 The processing takes place only when the switch data is the same as the previous time
(matching twice). A

No
main 1ms elapsed?

Yes
Initialization of the clock No
Chattering time
elapsed?
LED initialization
Yes
Switch initialization Reading switch

CMT0 initialization No
Is the status of switch the
same as the previous time?

A
Yes Save the current status
No of switch to memory.
Is switch pressed?

Yes Set edge processing

completion flag at 0.

Edge processing completed No

Is flag 0?

Yes

Processing

Set edge processing completion flag at 1.

-> Exercise 4c 72

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End-of-chapter test -6.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

For the method to detect [ sense ] the status change of switch, there are two
ways, [ 1 ] and [ 2 ].
[ 1 ] judges the status of port directly. [ 2 ] judges the change point of voltage.
The change point of voltage from High -> Low refers to [ 3 ] edge, and the
change point from Low -> High refers to [ 4 ] edge.
A switch is the device to create conduction by the contact of metal points. The
phenomenon whereby metal contact points bounce at the moment of contact is
called [ 5 ].
To avoid [ 5 ] by software, you need to apply sampling at the interval longer
than [ 5 ] time.

<Options>
a. sampling b. chattering c. polling
d. level sensing e. port sensing f. edge sensing
g. rising h. falling i. Schmitt trigger

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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain what the edge sensing for switch circuit is.

 Explain what chattering is.

 Explain the method to remove chattering by software.

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Chapter 7 Interrupt Control Program

« Learning Goals »

 Understand the exception handling.

 Understand the external terminal interrupt.

 Understand the peripheral module interrupt.

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7.1 RX63N exception handling

Exception handling
 Exception handling refers to the handling whereby CPU, when in the middle of executing a
usual program it encounters some event, suspends the execution of the program and
executes some other program.
Mechanism of executing exception handling
 The switchover to exception handling takes place by the mechanism whereby the top
address of a program is set up beforehand to the vector table and when some exception
occurs, the program counter is rewritten to such preset address.
RX63N exception handling
 With RX63N CPU, there are following exceptions.
 "Interrupt" is one of the exceptions.

Non-maskable interrupt Floating point exception

Reset Interrupt Unconditional trap

Undefined Privileged instruction

instruction exception Access exception exception
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7.2 Mechanism of interrupt

Interrupt is the mechanism whereby the processing currently executed is

suspended by the advent of interrupt causing factor and the interrupt program is
executed. After completion of the interrupt program, the suspended processing is
restarted from the point of suspension.

Main program Interrupt program

void main(void)
{ void Excep_ICU_IRQ13(void)
・
・ {
・ ・
・ ・ ・
} }

The interrupt causing factor and the interrupt processing program are linked by the
vector table. When an interrupt occurs, the interrupt processing program is started
by replacing the program counter (PC) by the address preregistered to the vector
table.
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7.3 RX63N vector table

The interrupt causing factor and the interrupt processing program are linked by the
vector table. When an interrupt occurs, the interrupt processing program is started
by replacing the program counter (PC) by the address preregistered to the vector
table.

There are two types of vector tables, fixed vector table and variable vector table.

 The fixed vector table is the one with its all allocated addresses being fixed. In the
addresses FFFFFF80h to FFFFFFFFh, each vector of privileged exception, access
exception, undefined instruction exception, floating point exception, non-maskable interrupt
and reset that are the object of exceptional processing for the system is allocated.
 The variable vector table is the one with its all allocated addresses allowing the
modification. In the area of 1024 bytes whose top address (IntBase) is shown by the
content of interrupt table register (INTB), each vector of unconditional trap and interrupt is
allocated.
 To the variable vector table, numbers (0 to 255) are assigned for each vector.
 With CC-RX, the top address of interrupt program is registered to the corresponding vector
of the variable vector table at the time of build by applying #pragma interrupt instruction to
interrupt function name handled as an interrupt program.

78

(Reserved area)

(Reserved area)

Privileged instruction exception

Access exception

(Reserved area)

Undefined instruction exception

(Reserved area)

Floating point exception

(Reserved area)

(Reserved area)

(Reserved area)

(Reserved area)

Non-maskable interrupt

Reset
[UMH]
Fig. 2.4 Fixed vector table

Order whereby
interrupt vectors
are allocated

[UMH]
Fig. 2.5 Variable vector table

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7.4 RX63N ICUb (interrupt controller)

RX63N ICUb (interrupt controller) accepts an interrupt from peripheral module or

external terminal and issues a request for interrupt to CPU.

IRRQn(n=0 to 15) ICUb

IRQ0 detector

External

Linking to vector number

..
interrupt ・

Terminal

IRQ15 Responding to interrupt Interrupt

requests from peripheral request
modules or IRQ0 through
IRQ15, interrupt requests
corresponding to vector
CPU
number are notified to
Interrupt
request CPU.

IE
Interrupt
Responding to an interrupt
permission bit request, an interrupt program
preregistered to the
corresponding vector number
Peripheral modules
is executed.

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7.5 Operational flow of RX63N interrupt (1)

Initial setup of interrupt

ICUb

Judgment of priority level

Linking to vector number

Comparison
(2) IEN is (4) I flag is set
set to "1." 1 to "1."
(1) IR is
set to "0."

IPL I
0000 1
PSW
0 1 0001

IR IEN IPR
CPU
Interrupt Interrupt Interrupt (3) IPR set
status flag request priority level
permission bit setting bit

80

 Interrupt requests
Interrupt requests are managed by IR, IER and IPR of ICUb (interrupt controller) and finally only one interrupt
request is issued to CPU.

 Setting of interrupt controller

For each interrupt, IR flag, IENj and IPR bit are provided.
When an interrupt is to be used, the IR flag of the corresponding interrupt is set at "0," IEN bit is set at "1" and IPR
bit is set at the interrupt priority order.

 State of PSW allowing the acceptance of interrupt request

To allow acceptance of an interrupt, the conditions
(i) IPL (processor interrupt priority level) of PSW is lower than IPR (interrupt priority level setup bit) that is requesting
the interrupt.
(ii) I bit of PSW is "1."
need to be met.

For this reason, when processing an interrupt, I bit of PSW needs to be set at "1."

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7.5 Operational flow of RX63N interrupt (2)

Occurrence of an interrupt

(2) Interrupt
ICUb priority level is
judged.

(3) Comparison
with IPL

Judgment of priority level

Linking to vector number

Comparison
1
Interrupt request
Occurrence of
an interrupt
(1) IR
becomes 1.
IPL I
0000 1
PSW
1 1 0001

IR IEN IPR
CPU
Interrupt Interrupt Interrupt
status flag request priority level
permission bit setting bit

81

 Occurrence of an interrupt
When an interrupt occurs, IR flag of interrupt controller is set.

 Judgment of interrupt priority level

When an interrupt occurs, it is judged if any other interrupt with higher priority has occurred.
As the result of judgment, if the interrupt has the highest priority among the interrupt requests and higher than IPL of
CPU, and the state of I flag is interrupt permission, then the interrupt processing will start.

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7.5 Operational flow of RX63N interrupt (3)

Execution of interrupt program (after interrupt (1) Replace the value of PC to the address
registered to the vector corresponding to
request being accepted) the accepted interrupt request.

Main program Interrupt program

(3) Save the value of
void main(void) PC PSW to stack.
{ void
・ Excep_ICU_IRQ13(void
) ISP Value of
・
{ PSW
・ Apply subtraction
・ Return
・ by -8.
・ address
}
・
(2) Save the return
} address to stack.

When an interrupt request occurs during the execution of main

IPL I
program and it is accepted, the (1) on-going processing is
0001 0
suspended and the control moves to the interrupt program.
PSW
Memory
(4) The value of IPR will
be that of the interrupt
CPU
being executed.
(5) Interrupt is
prohibited.

82

 Execution of interrupt program after interrupt request being accepted

At the time when the value of PC is changed, the processing of main program is suspended and thereafter the
interrupt program will operate (the operation of software).

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7.5 Operational flow of RX63N interrupt (4)

Execution of interrupt program (after interrupt

processing being completed) Restore the return address from the stack back to PC.

Main program Interrupt program

void main(void) PC
{ void
・ Excep_ICU_IRQ13(void
) ISP Value of
・
{ PSW
・
・ Return
・
・ address
}
・
} ... (2) Execute RTE instruction. Restore the value of PSW
from the stack.
(3)

Upon the completion of interrupt program processing,

IPL I
execute the RTE instruction at the exit of function and
0000 1
return to the suspended processing.
PSW
Memory
IPL is returned to the
CPU
original and I (interrupt
permission) bit will also
return to interrupt
permission state.
83

 Execution of RTE instruction

The instruction used to return from the interrupt program to the suspended main program is RTE instruction. The
operations all the way to the execution of RTE instruction are the operations of software. When RTE instruction is
executed, the hardware inside CPU will automatically operate as shown in the right side of the slide. And at the time
when the return address is returned to PC, the control is resumed to software.

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7.6 RX63N IRQ13 (external terminal interrupt)

IRQ is external terminal interrupt from the terminal.

 As the factors to cause external terminal interrupt for RX63N, there are "edge detection"
and "level detection."
RX63N

IRQ1

IRQ0

Edge detection: Level detection:

Interrupt request is recognized only when Interrupt request is recognized only
there is effective change of signals (selected when the level stays at "L" level for a
from falling edge, rising edge and both certain period.
falling and rising edges).

[Characteristics] [Characteristics]
• The response time to interrupt • The response time to interrupt
processing execution is fast. processing execution is slow.
• Weak at noises • Resistant to noises
• Clearance of request signal during
interrupt processing is necessary. 84

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7.7 RX63N IRQ13 (external terminal interrupt) control

We give it a try to use input port PORT05 of SW3 for external terminal interrupt.

VCC

RX63N
SW3 10kΩ

PORT05/
GND IRQ13

OFF
SW 3 PORT05/IRQ13
ON

1
IR bit of IRQ13
0

IRQ13 interrupt program Processing Processing

when SW3 is when SW3 is
pressed pressed

Main program Main

Main processing Main processing
processing
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7.8 Initial setup forRX63N IRQ13 (external terminal

interrupt)
Initial setup for IRQ13 interrupt
 Prerequisite
 The setup value of IRQ13 interrupt to be used stays at the initial value after the reset.

Start

MPC write-protect
register permitted to be written

P05 is set as IRQ13 input terminal

MPC write-protect
register prohibited to be written

Setup of IRQ13 detection

Clearing interrupt flag

Setup of interrupt priority level

Interrupt permission

End

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7.9 Control program for RX63N IRQ13 (external terminal

interrupt)

Interrupt control program

 Create an IRQ13 interrupt program independently from main program.

main IRQ13 interrupt

Initialization of the
clock Interrupt handling

LED initialization
RTE

Initialization of
interrupt

Infinite loop

-> Exercise 5
87

 Description of interrupt program

When the project is created by CS+, the empty interrupt processing function is provided to intprg.c, and the function
to become the interrupt function is designated to vect.h by using #pragma interrupt.
When a user describes an interrupt program, either one of following two must be selected.

(i) Describe in the corresponding interrupt function of intprg.c.

(ii) Comment out the corresponding interrupt function of intprg.c, create a function with the same name as the
corresponding function of intprg.c in arbitrary C language file and include vect.h at the top of the file.

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7.13 Timer interrupt control for RX63N

Timer interrupt control for RX63N

 Using the timer mounted on RX63N, you can issue an interrupt at some certain interval.

Value of CMCNT
(3) Compare match interrupt develops. -> IR is made to "1."

CMCOR

0000h

Time
(2) Matching of compare match at
CMCOR will reset the counter.

1
IR bit of CMT
0

CMT compare match Processing Processing Processing

Interrupt program at each at each at each
defined time defined time defined time

Main program Main

Main processing Main processing
processing
88

 Notes for timer interrupt

Though timer interrupt is handy, using multiple timer interrupts for controlling multiple time bands will make the
program difficult to understand.

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7.14 Initial setup of RX63N CMI1 (compare match)

interrupt
Initial setup of CMT1 interrupt
 Prerequisite
 The setup value of the CMI1 (compare match) interrupt to be used stays at the initial value after the
reset.
 Issue an interrupt at every 100ms.
main

Release of the protection

Release of the module stop

Setup of the protection

Selection of count clock
Permission of compare match
interrupt

Counter initialization

Setting of cycle count

Clearing interrupt flag

Setup of interrupt priority level

Interrupt permission

Start counting

End
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7.15 Control program for RX63N CMI1 (compare

match) interrupt

main

CMI1 (compare match) interrupt

Initialization of the
clock Timer interrupt processing

LED initialization RTE

CMT1
initialization

-> Exercise 6
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End-of-chapter Test -7.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

While CPU is executing a usual program, it can encounter some event and has
to suspend the execution of the program to execute some other program. This
kind of events are generally called [ 1 ] and the processing to respond this is
called [ 1 ] handling.
Interrupt is one of [ 1 ] cases.
When ICUb [ interrupt controller ] receives multiple interrupt requests from
peripheral modules or external interrupt terminals, it judges [ 2 ] by using the
setup value of [ 3 ]. Furthermore, by comparing [ 4 ] of PSW in CPU and [ 3 ]
in ICUb, when [ 3 ] > [ 4 ] and the flag of [ 5 ] is 1, an interrupt request is
issued to CPU.

<Options>
a. reset b. exception c. polling
d. IPR e. priority level f. IR
g. IPL h. D i. I
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Answer Column

Correct
Question Answer
Answer

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 Embedded programming

End-of-chapter test -7.2-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

When CPU receives an interrupt request while executing the main program, the
main program is [ 1 ] and the interrupt program is [ 2 ]. To execute the
interrupt program, it is necessary to preregister the top address of the interrupt
program to the corresponding address of the [ 3 ] table. When the interrupt
program is to be executed, the return address and [ 4 ] are saved to stack and
the top address of the interrupt program is set to program counter (PC).

<Options>
a. continued b. suspended c. executed
d. waiting e. ISP f. PSW
g. register h. memory i. vector

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Answer Column

Correct
Question Answer
Answer

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 Embedded programming

Summary

 Explain what exception handling of RX63N is.

 Explain the external terminal interrupt of RX63N.

 Explain the peripheral module interrupt of RX63N.

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Chapter 8 A/D Control Program

« Learning Goals »

 Understand the typical operating principles of A/D conversion.

 Understand the A/D conversion of RX63N.

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8.1 Mechanism of successive comparison type A/D converter

Operating principles of successive comparison type A/D converter
 By successive comparison between the analog signals inputted and the analog voltage
created internally for comparison, the values are determined sequentially.
 Input the analog signal.
 Set "1" to MSB of the successive comparison register. (Others are set to "0.")
 Convert the digital value of successive comparison register to analog voltage
internally (comparison value).
 Compare the large/small of input voltage value and comparison analog voltage
value.
(1) 1st time: Compare with
› When input voltage value > comparison analog voltage value, then 1.5V. b3 b2 b1 b0
MSB="1" is determined.
Result 0   
› When input voltage value < comparison analog voltage value, then
MSB="0" is determined.
 Thereafter, the same comparison is repeated to LSB.
(2) 2nd time: Compare with
3V 0.75V. b3 b2 b1 b0
Comparator Result 0 1  
－
Analog Successive
input comparison
register (3) 3rd time: Compare with
＋ 1.125V. b3 b2 b1 b0
(1)
(4) Result 0 1 1
1.2V 
(3)

Analog voltage for Result saving (2)

comparison register
(4) 4th time: Compare with
Output １
1.3125V. b3 b2 b1 b0
Result 0 1 1 0
0V Successive comparison
of small/large 95

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8.2 Configuration of RX63N S12ADa (12 bit A/D

converter)
Block diagram of S12ADa (12 bit A/D converter)

Interna l peripheral bus 2

Bus interface

comparison register
Successive
12 bit D/A

Interrup t signal

Comparator
Analog multiplexor

Control circuit Synchrono us trigger

(including decode
Sample & part)
hold circuit

Asynchro no us trigger

Temperature sensor output

Interna l reference power

[UMH]
Fig. 42.1 Block diagram of 12 bit A/D converter

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8.3 Specification of RX63N S12ADa (12 bit A/D

converter)
S12ADa (12 bit A/D converter) has 1 unit of successive comparison type 12 bit A/D
converter built in.
Table 42.1 Specification of 12 bit A/D converter
Item Contents
Number of units 1 unit
Input channel Max. 21 channels
Extension analog input Temperature sensor output, internal reference voltage (Note 3)
A/D conversion type Successive comparison type
Resolution 12 bit
Conversion time 1.0μs for channel (when A/D conversion clock ADCLK = 50MHz is working) (Note 4)
A/D conversion clock 4 types: PCLK, PCLK/2, PCLK/4, PCLK/8
(ADCLK)
Data register • For analog input: 21
• For temperature sensor: 1
• For internal reference voltage: 1
• The result of A/D conversion is retained by 12 bit A/D data register.
• In the addition mode, the result of A/D conversion is retained by 14 bit A/D data register.

Operation mode • Single scan mode:

The analog input of maximum 21 channels selected arbitrarily is A/D converted only once.
Temperature sensor output is A/D converted only once.
Internal reference voltage is A/D converted only once.
• Continuous scan mode: The analog input of maximum 21 channels selected arbitrarily is A/D
converted repeatedly. (Note 1)

A/D conversion starting • Software trigger

condition • Synchronous trigger
from MTU, TPU or TMR
• Asynchronous trigger
The start of A/D conversion by ADTRG0# terminal is enabled.

Function • Sample & hold function

• Function for variable number of sampling states
• A/D conversion value addition mode
Interrupt factors • At the completion of A/D conversion, scan completion interrupt request (S12AD10) is issued.
• DMAC and DTC can be started up by S12AD10 interrupt.
[UMH]
Function of reducing Setup to module stop status is possible. (Note 2)
power consumption

Note 1: When temperature sensor output or internal reference voltage is selected, do not use the continuous scan mode.
Note 2: After the release of module stop status, wait 10ms before starting A/D conversion.
Note 3: For internal reference voltage, see "51. Electric characteristics."
Note 4: It depends on such factors as channels, signal source impedance and AVCC voltage.
97

 A/D converter (S12ADa)

RX63N has 1 unit of successive comparison type 12 bit A/D converter built in.
You can select analog input of maximum 21 channels, temperature sensor output or internal reference voltage.
For the operation modes of A/D converter, there are two modes, one being single scan mode which converts only
once the analog inputs of maximum 21 channels selected arbitrarily in the order of the smaller channel number the
first, and the other being continuous scan mode which continuously converts the analog inputs of maximum 21
channels selected arbitrarily in the order of the smaller channel number the first.

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8.4 Initial setup of RX63N S12ADa (12 bit A/D converter)

Initial setup of S12ADa

 Prerequisite
 The setup value of S12ADa to be used stays at the initial value after the reset.

Start

Release of the protection

Release of the module stop

Setup of the protection

MPC write-protect
Register permitted to be written

P46 is set as A/D input terminal.

MPC write-protect
Register prohibited to be written

Set to the continuous scan mode

AD6 is set as the object of conversion.

Start A/D conversion.

-> Exercise 7
End
98

 Power consumption reduction function

Some of the peripheral modules of RX63N are at module stop status at the reset due to the power consumption
reduction function. For this reason, such module stop status needs to be released by module stop control register
before they are used. Details are described in Exercise volume of "11.3 Power consumption reduction function."

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End-of-chapter Test -8.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

The module that converts the signal inputted from [ 1 ] to [ 2 ] value is called
[ 3 ]. [ 3 ] of RX63N is [ 4 ] type and determines the value by comparing
with the internal voltage for comparison sequentially.
For RX63N, there are two types of converters, 10 bit A/D converter and 12 bit
A/D converter.
The [ 5 ] the number of bits is, the higher precision of conversion is available.

<Options>
a. digital b. analog c. A/D converter
d. D/A converter e. parallel comparison f. successive comparison
g. follow-up comparison h. smaller i. larger

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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the successive comparison type A/D converter.

 Explain the A/D conversion of RX63N.

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Chapter 9 PWM Control Program

« Learning Goals »

 Understand the Pulse Width Modulation (PWM).

 Understand the PWM using the timer of RX63N.

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9.1 What is PWM control?

PWM (Pulse Width Modulation) is

 Called “パルス幅変調” in Japanese, and is a control method whereby "H" and "L" of pulse
width is changed.
Duty ratio Pulse
 Cycle: time of "H" + "L"
 Pulse width: time of "H" Cycle
 Duty ratio: Pulse width
(Pulse width/cycle)*100 High
50%
Low

Cycle
Pulse width
High
25%

Low

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9.2 Application examples of PWM control

Voltage control for DC motor

 By applying PWM control to the voltage supplied to motor, the rotation speed of a motor can be changed.

Stop Rotation Stop Rotation Stop Rotation

Rotation speed: low Rotation speed: medium Rotation speed: high

Brightness control for LED

 By applying PWM control to the lighting time of LED, the brightness of LED can be changed.

Turning off Turning on Turning off Turning on Turning off Turning on

LED brightness: low (dark) LED brightness: medium (normal) LED brightness: high (bright) 103

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9.3 Configuration of RX63N MTU2a (Multi-function

timer pulse unit 2)
Block diagram of [Interrupt request signal]

MTU2a [Input output terminal]

Control logic
MTU3,4
[Input terminal]

[Clock input]

Module data bus

Interna l data bus

Control logic
Interna l clock:

Common
[A/D conversion start
request signal]

External clock:

[Interrupt request signal]

Control logic
MTU0 to 2

[Input output terminal]

[UMH]
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9.4 Specification of RX63N MTU2a (Multi-function

timer pulse unit 2)
RX63N MTU2a has PWM output function.
Table 23.1 Specification of MTU
Item Contents
Pulse input/output 16 at maximum
Pulse input 3
Count clock 8 or 7 types for each channel (MTU5 has 4 types)
Operations that can be set up [MTU0 to 4]
• Waveform output by compare matching
• Input capture function (noise filter setup function)
• Counter clear operation
• Simultaneous writing to multiple timer counters (TCNT)
• Simultaneous clear operation by compare-match/input-capture
• Synchronous input/output of registers by synchronized operations of counters
• PWM output of 12 phases at maximum available by combining synchronous
operations

[MTU0, 3, 4]
• Buffer operations can be set up.
• AC synchronous motor (brushless DC motor) driving mode using
complementary PWM and reset synchronous PWM can be set up, and two
types (chopping and level) of waveform output can be selected.

[MTU1, 2]
• Phase constant mode can be set up independently.
• Cascade connection operation
[MTU3, 4]
• Output of complementary PWM by continuous operations, and total 6 phases
from positive and negative of PWM 3 phases each are available.
[MTU5]
• Dead time compensation counter function
Complementary PWM mode • Interrupt at crest and trough of counter
• Thinning out function for conversion start trigger for A/D converter
Interrupt factors 28 types
Buffer operation Automatic transfer for register data
Trigger generation Output trigger for programmable pulse generator (PRG) can be generated.
Conversion start trigger for A/D converter can be generated.
Function of reducing power
consumption
Setup to module stop status is possible.
[UMH]

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9.5 PWM function of RX63N MTU2a (Multi-function

timer pulse unit 2)
PWM function of RX63N
 Some timers have the function of PWM output. With RX63N, following three timers have
PWM output function.
 TPUa (16-bit timer pulse unit)
 MTU2a (Multi-function pulse unit 2)
 TMR (8-bit timer)
 This chapter deals with PWM function of MTU2a (Multi-function timer pulse unit 2).

PWM1 mode of MTU2a

 In PWM1 mode of MTU2a, PWM output can be generated from MTIOCA terminal by using
TGRA and TGRB in pair.

Value of TCNT Counter clear by compare

match of TGRA

Time

[UMH]
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9.6 Initial setup of PWM output of RX63N MTU2a

(Multi-function timer pulse unit 2)
Initial setup for PWM1 mode of MTU2a
 Prerequisite
 The setup value of MTU2a to be used stays at the initial value after the reset.

Start A

Release of the protection Setting at PW M mode 1

Release of the module stop MTIOC4A output permission

MTIOC4C output permission
Setup of the protection
Setting of terminal function
MTIOC4A "H" at the initial "H" compare match
MPC write-protect
MTIOC4B "L" at the initial "H" compare match
Register permitted to be written
MTIOC4C "H" at the initial "H" compare match
Set PE1 and PE2 at MTU4A. MTIOC4D "L" at the initial "H" compare match

MPC write-protect Count initialization

Register prohibited to be written
Pulse width setting
PMR setting of PE1 and PE2 • Set the cycle at TGRA, set the pulse width initial value
at TGRB.
(To be used as peripheral function) • Set the cycle at TGRC, set the pulse width initial value
at TGRD.
TCR setting
• Count by PCLK/64. Start counting
• Count by falling edge.
• TCNT clear at matching with TGRA

End -> Exercise 8

A
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End-of-chapter test -9.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

The total time of High and Low of digital signal is called [ 1 ], the time of High
is called [ 2 ] and [ 2 ] divided by [ 1 ] is called [ 3 ].
The control method whereby the time of High and Low is changed while fixing
the [ 1 ] of digital signal is called [ 4 ].
[ 4 ] is often used for the speed control of [ 5 ].

<Options>
a. frequency b. cycle c. pulse width
d. duty ratio e. frequency ratio f. pulse ratio
g. PWM control h. PAM control i. PDM control
j. stepping motor l. DC motor

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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain what PWM is.

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Chapter 10 Communication Control Program

« Learning Goals »

 Understand the start-stop synchronous serial communication.

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10.1 Mechanism of start-stop synchronous serial

communication
Start-stop synchronous serial communication
 In the start-stop synchronous serial communication, the character information of one
character (*1) is sandwiched by "start bit" meaning the start and "stop bit" meaning the stop
before sending. A "parity bit" to check if the data has been sent correctly can be added.
The communication device used for this method is called UART (Universal Asynchronous
Receiver/Transmitter).

Example of communication format

Data length: 8 bits
MSB LSB
Parity: None
Stop bit: 1 bit The character sent "x" 0 1 0 1 1 0 0 1

start bit "0" 0

stop bit "1" 1

MSB LSB

1 0 1 0 1 1 0 0 1 0

Transmitting Receiving
side side
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 Parity bit
In the start-stop synchronous serial communications, since there is no error correction function and error of 2 bits or
more cannot be detected, the error check is only conducted at the higher communication layer and it is often the
case that transmission with "no parity bit" is conducted.

 Bit rate (communication speed)

How many bits of data a second is sent/received is expressed by the unit of bps (bits per second).
As the communication speed, there are such types as 9600bps, 19200bps, 38400bps, 57600bps and 115200bps.

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10.2 Configuration of RX63N SCIc (serial

communications interface)
Block diagram of SCIc Register for
transmission data
Register for

Internal peripheral bus 2

received data

Bus interface
Module data bus

Baud rate
generator

Interrupt factors at sending/receiving

TEI: Transmission completion
TXI: Transmission data empty
Occurrence of
parity error
Clock
RXI: Receiving data full
Parity check Sending/receiving
control

Exte rnal clock

Receive shift register Bit rate register

Received data register Serial extension mode register
Transmit shift register Noise filter setting register
Transmit data register I2C mode register1
Serial mode register I2C mode register2
Serial control register I2C mode register3
Serial status register I2C status register
Smart card mode register SPI mode register
[UMH]
Fig. 35.1 Block diagram of SCI0 to SCI4, SCI7 to SCI11

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 Operations of SCI at the time of serial data transmission

See "RX63N Group User's Manual: Hardware"
and "35.3.6 Transmission of serial data (start-stop synchronous mode)."

 Operations of SCI at the time of serial data receiving

See "RX63N Group User's Manual: Hardware"
and "35.3.7 Reception of serial data (start-stop synchronous mode)."

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10.3 Specification of RX63N SCIc (serial

communication interface)
The peripheral module that can perform start-stop synchronous communication in
RX63N is SCI.
Table 35.1 Specifications of SCIc (1/2)

Item Contents
Serial communication method • Start-stop synchronous method
• Clock synchronization method
• Smart card interface
• Simple l2C bus
• Simple SPI bus
Transmission speed By the use of embedded baud generator, any bit rate can be set up.
Full duplex communication Transmission part: Continuous transmission by double-buffer configuration is
possible.
Receiving part: Continuous reception by double-buffer configuration is possible.
Input output terminal See Table 35.4 to 35.6.
Data transmission Selection between LSB first/MSB first is possible (Note 1).
Interrupt factors Transmission completion, Transmission data empty, Receiving data full,
Receiving error, Start-condition/restart-condition/Stop-condition generation
completion (For simple l2C mode)
Function of reducing power consumption Setting to module stop status for each channel is possible.
Start-stop Data length 7 bits/8 bits
synchronous mode Transmission stop bit 1 bit /2 bits
Parity function Even parity/odd parity/no parity
Receiving error detection Parity error, overrun error, framing error
function
Hardware flow control Sending/receiving control using CTSn terminal and RTSn terminal is possible.
Break detection Break can be detected by reading RXDn terminal level directly in case of framing
error.
Clock source Selectable from internal clock and external clock
Transfer rate clock input from TMR (SCI5, SCI6) is possible.
Multi-processor Serial communication function among multiple processors
communications function
Noise reduction The signal paths from input on the RXDn terminals incorporate digital noise
filters.
Clock synchronization Data length 8 bits
mode Receiving error detection Overrun errors
Hardware flow control Sending/receiving control using CTSn terminal and RTSn terminal is possible. [UMH]

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 Data length
For the data length of RX63N SCIc, you can select 7 bits or 8 bits.

 Transmission stop bit

For the transmission stop bit of RX63N, you can select 1 bit or 2 bits.

 Parity function
For the parity function of RX63N SCIc, you can select from even parity, odd parity and no parity.

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10.4 Initial setting of RX63N SCIc (serial

communication interface)
Prerequisite of initial setting for SCIc
 The setup value of SCIc to be used stays at the initial value after the reset.

Start

Release of the protection A

Release of the module stop
Setting of RXI2 interrupt request
Setting of the protection Setting of TXI2 interrupt request
Setting of TEI2 interrupt request
MPC write-protect
Register permitted to be written RXI2 priority level setting
TXI2 priority level setting
P50 is set at TXD2. TEI2 priority level setting
P52 is set at RXD2.

MPC write-protect RXI2 interrupt permitted

Register prohibited to be written TXI2 interrupt permitted
TEI2 interrupt permitted
P50, P52 used in peripheral functions
Sending/receiving permitted
Setting of communication format

Setting of baud rate

End

A
-> Exercise 9
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End-of-chapter test -10.1-

Select the suitable words for the empty boxes [ ] from the Options and answer
by symbols.

In start-stop synchronous serial communication, the communication is

conducted by matching the timing at both transmission side and receiving side.
The data transmission speed in this case is called [ 1 ] and to indicate how
many [ 2 ] of data is transmitted in a second, the unit [ 3 ] is used.
The shortest data that can be sent/received by SCI of RX63N is start bit [ 4 ]
bit, data [ 5 ] bit, parity bit [ 6 ] bit and stop bit [ 7 ] bit, altogether [ 8 ] bits.

<Options>
a. bps b. kbps c. Mgps
d. byte rate e. bit rate f. bit
g. byte h. 0 i. 1
j. 2 k. 7 l. 8
m. 9 n. 10 o. 11
p. 12 q. 13 r. 14
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Answer Column

Correct
Question Answer
Answer

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Summary

 Explain the start-stop synchronous serial communication.

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