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24AA024/24LC024/24AA025/24LC025
2K I2C™ Serial EEPROM
Device Selection Table Description

Part Max Temp. Write The Microchip Technology Inc. 24AA024/24LC024/

VCC Range 24AA025/24LC025 is a 2 Kbit Serial Electrically
Number Clock Range Protect
Erasable PROM with a voltage range of 1.8V to 5.5V.
24AA024 1.8V - 5.5V 400 KHz(1) I Yes The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
24AA025 1.8V - 5.5V 400 KHz(1) I No
design permits operation with typical standby and
24LC024 2.5V - 5.5V 400 KHz I Yes active currents of only 1 µA and 1 mA, respectively.
The device has a page write capability for up to 16
24LC025 2.5V - 5.5V 400 KHz I No bytes of data. Functional address lines allow the
Note 1: 100 KHz for VCC < 2.5V connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
Features is available in the standard 8-pin PDIP, 8-pin SOIC
• Single supply with operation from 1.8V to 5.5V (150 mil), TSSOP and MSOP packages.
• Low-power CMOS technology Package Types
- 1 mA active current typical PDIP/SOIC
- 1 µA standby current typical at 5.5V A0 1 8 VCC

24XX025
24XX024
• Organized as a single block of 256 bytes (256 x 8)
A1 2 7 WP*
• Hardware write protection for entire array
(24XX024) A2 3 6 SCL
• 2-wire serial interface bus, I2C™ compatible
VSS 4 5 SDA
• 100 kHz and 400 kHz clock compatibility
• Page write buffer for up to 16 bytes TSSOP/MSOP
1 8
24XX025
• Self-timed write cycle (including auto-erase) A0 24XX024 VCC
• 10 ms max. write cycle time A1 2 7 WP*
• Address lines allow up to eight devices on bus A2 3 6 SCL
VSS 4 5 SDA
• 1,000,000 erase/write cycles
• ESD protection > 4,000V
• Data retention > 200 years Block Diagram
• 8-pin PDIP, SOIC, TSSOP and MSOP packages A0 A1 A2 WP*
HV Generator
• Available for extended temperature ranges
- Industrial (I): -40°C to +85°C I/O Memory
Control Control
Logic EEPROM
Pin Function Table Logic XDEC
Array

Name Function
SDA SCL
VSS Ground
Write-Protect
SDA Serial Data VCC Circuitry
YDEC
SCL Serial Clock VSS
VCC 1.8V to 5.5V Power Supply Sense Amp.
A0, A1, A2 Chip Selects R/W Control

WP Hardware Write-Protect (24LC024)

Note: *WP pin available only on 24XX024. This pin

has no internal connection on 24XX025.

 2004 Microchip Technology Inc. DS21210G-page 1

24AA024/24LC024/24AA025/24LC025
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply across the VCC = 1.8V to 5.5V
specified operating ranges unless Industrial (I): TA = -40°C to +85°C
otherwise noted.
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage VIH 0.7 VCC — V —
Low-level input voltage VIL — 0.3 VCC V —
Hysteresis of Schmitt Trigger inputs VHYS 0.05 VCC — V (Note)
Low-level output voltage VOL — 0.40 V IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current ILI — ±1 µA VIN = 0.1V to 5.5V, WP = VSS
Output leakage current ILO — ±1 µA VOUT = 0.1V to 5.5V
Pin capacitance (all inputs/outputs) CIN, COUT — 10 pF VCC = 5.0V (Note)
TA = 25°C, f = 1 MHz
Operating current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
Standby current ICCS — 1 µA VCC = 5.5V, SDA = SCL = VCC
WP = VSS, A0, A1, A2 = VSS
Note: This parameter is periodically sampled and not 100% tested.

DS21210G-page 2  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
TABLE 1-2: AC CHARACTERISTICS
All parameters apply across the specified VCC = 1.8V to 5.5V
operating ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C

Vcc = 2.5V - 5.5V

STD MODE
Parameter Symbol FAST MODE Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK — 100 — 400 kHz —
Clock high time THIGH 4000 — 600 — ns —
Clock low time TLOW 4700 — 1300 — ns —
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns —
Stop condition setup time TSU:STO 4000 — 600 — ns —
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH TOF — 250 20 +0.1 250 ns (Note 1), CB ≤ 100 pF
minimum to VIL maximum CB
Input filter spike suppression TSP — 50 — 50 ns (Note 3)
(SDA and SCL pins)
Write-cycle time TWC — 10 — 10 ms Byte or Page mode
Endurance 1M — 1M — cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at
www.microchip.com.

FIGURE 1-1: BUS TIMING DATA

THIGH
TF TR

SCL
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
SDA
THD:STA
IN TSP

TBUF
TAA
SDA
OUT

 2004 Microchip Technology Inc. DS21210G-page 3

24AA024/24LC024/24AA025/24LC025
2.0 PIN DESCRIPTIONS 3.0 FUNCTIONAL DESCRIPTION
The 24AA024/24LC024/24AA025/24LC025 supports
2.1 SDA Serial Data a bidirectional, 2-wire bus and data transmission
SDA is a bidirectional pin used to transfer addresses protocol. A device that sends data onto the bus is
and data into and out of the device. It is an open-drain defined as transmitter, while a device receiving data
terminal, therefore the SDA bus requires a pull-up is defined as receiver. The bus has to be controlled
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for by a master device which generates the serial clock
400 kHz). (SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
For normal data transfer, SDA is allowed to change 24LC024/24AA025/24LC025 works as slave. Both
only during SCL low. Changes during SCL high are master and slave can operate as transmitter or
reserved for indicating the Start and Stop conditions. receiver, but the master device determines which
mode is activated.
2.2 SCL Serial Clock
The SCL input is used to synchronize the data transfer
from and to the device.

2.3 A0, A1, A2

The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either VCC or VSS.

2.4 WP (24XX024 Only)

WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.

2.5 Noise Protection

The 24AA024/24LC024/24AA025/24LC025 employs a
VCC threshold detector circuit which disables the inter-
nal erase/write logic if the VCC is below 1.5 volts at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.

DS21210G-page 4  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
4.0 BUS CHARACTERISTICS The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
The following bus protocol has been defined: clock pulse.
• Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and
is not busy. terminated with a Stop condition. The number of the
• During data transfer, the data line must remain data bytes transferred between the Start and Stop
stable whenever the clock line is high. Changes in conditions is determined by the master device and is,
the data line while the clock line is high will be theoretically, unlimited, (though only the last sixteen will
interpreted as a Start or Stop condition. be stored when performing a write operation). When an
Accordingly, the following bus conditions have been overwrite does occur, it will replace data in a first-in
defined (Figure 4-1). first-out fashion.

4.1 Bus Not Busy (A) 4.5 Acknowledge

Both data and clock lines remain high. Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
4.2 Start Data Transfer (B) pulse which is associated with this Acknowledge bit.
A high-to-low transition of the SDA line while the clock Note: The 24AA024/24LC024/24AA025/
(SCL) is high determines a Start condition. All 24LC025 does not generate any
commands must be preceded by a Start condition. Acknowledge bits if an internal
programming cycle is in progress.
4.3 Stop Data Transfer (C) The device that acknowledges has to pull down the SDA
A low-to-high transition of the SDA line while the clock line during the acknowledge clock pulse in such a way
(SCL) is high determines a Stop condition. All that the SDA line is stable low during the high period of
operations must be ended with a Stop condition. the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
4.4 Data Valid (D) an Acknowledge bit on the last byte that has been
The state of the data line represents valid data when, clocked out of the slave. In this case, the slave must
after a Start condition, the data line is stable for the leave the data line high to enable the master to generate
duration of the high period of the clock signal. the Stop condition (Figure 4-2).

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

SCL (A) (B) (C) (D) (C) (A)

SDA

Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change

FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge
Bit

SCL 1 2 3 4 5 6 7 8 9 1 2 3

SDA Data from transmitter Data from transmitter

Transmitter must release the SDA line at this point allowing Receiver must release the SDA line at this
the Receiver to pull the SDA line low to acknowledge the point so the Transmitter can continue
previous eight bits of data. sending data.

 2004 Microchip Technology Inc. DS21210G-page 5

24AA024/24LC024/24AA025/24LC025
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT
A control byte is the first byte received following the Read/Write Bit
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For Chip Select
Control Code Bits
the 24AA024/24LC024/24AA025/24LC025, this is set
as ‘1010’ binary for read and write operations. The next
three bits of the control byte are the Chip Select bits S 1 0 1 0 A2 A1 A0 R/W ACK
(A2, A1, A0). The Chip Select bits allow the use of up
to eight 24AA024/24LC024/24AA025/24LC025 Slave Address
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control Start Bit Acknowledge Bit
byte must correspond to the logic levels on the corre-
sponding A2, A1 and A0 pins for the device to respond.
These bits are in effect the three Most Significant bits of 5.1 Contiguous Addressing Across
the word address. Multiple Devices
The last bit of the control byte defines the operation to The Chip Select bits A2, A1 and A0 can be used to
be performed. When set to a one, a read operation is expand the contiguous address space for up to 16K bits
selected. When set to a zero, a write operation is by adding up to eight 24AA024/24LC024/24AA025/
selected. Following the Start condition, the 24AA024/ 24LC025 devices on the same bus. In this case, soft-
24LC024/24AA025/24LC025 monitors the SDA bus ware can use A0 of the control byte as address bit A8,
checking the control byte being transmitted. Upon A1 as address bit A9 and A2 as address bit A10. It is
receiving a ‘1010’ code and appropriate Chip Select not possible to sequentially read across device
bits, the slave device outputs an Acknowledge signal boundaries.
on the SDA line. Depending on the state of the R/W bit,
the 24AA024/24LC024/24AA025/24LC025 will select a
read or write operation.

DS21210G-page 6  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
6.0 WRITE OPERATIONS The higher-order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
6.1 Byte Write
address counter will roll over and the previously
Following the Start signal from the master, the device received data will be overwritten. As with the byte-write
code(4 bits), the Chip Select bits (3 bits) and the R/W operation, once the Stop condition is received, an
bit (which is a logic-low) is placed onto the bus by the internal write cycle will begin (Figure 6-2). If an attempt
master transmitter. The device will acknowledge this is made to write to the protected portion of the array
control byte during the ninth clock pulse. The next byte when the hardware write protection has been enabled,
transmitted by the master is the word address and will the device will acknowledge the command but no data
be written into the address pointer of the 24AA024/ will be written. The write cycle time must be observed
24LC024/24AA025/24LC025. After receiving another even if write protection is enabled.
Acknowledge signal from the 24AA024/24LC024/
24AA025/24LC025, the master device will transmit the Note: Page write operations are limited to writing
data word to be written into the addressed memory bytes within a single physical page,
location. The 24AA024/24LC024/24AA025/24LC025 regardless of the number of bytes
acknowledges again and the master generates a Stop actually being written. Physical page
condition. This initiates the internal write cycle and, dur- boundaries start at addresses that are
ing this time, the 24AA024/24LC024/24AA025/ integer multiples of the page buffer size (or
24LC025 will not generate Acknowledge signals ‘page size’) and end at addresses that are
(Figure 6-1). If an attempt is made to write to the integer multiples of [page size - 1]. If a
protected portion of the array when the hardware write Page Write command attempts to write
protection (24XX024 only) has been enabled, the across a physical page boundary, the
device will acknowledge the command but no data will result is that the data wraps around to the
be written. The write cycle time must be observed even beginning of the current page (overwriting
if write protection is enabled. data previously stored there), instead of
being written to the next page, as might be
6.2 Page Write expected. It is therefore necessary for the
application software to prevent page write
The write control byte, word address and the first data operations that would attempt to cross a
byte are transmitted to the 24AA024/24LC024/ page boundary.
24AA025/24LC025 in the same way as in a byte write.
However, instead of generating a Stop condition, the 6.3 Write Protection
master transmits up to 15 additional data bytes to the
24AA024/24LC024/24AA025/24LC025, which are The WP pin (available on 24XX024 only) must be tied
temporarily stored in the on-chip page buffer and will be to VCC or VSS. If tied to VCC, the entire array will be
written into the memory once the master has transmit- write-protected. If the WP pin is tied to VSS, write
ted a Stop condition. Upon receipt of each word, the operations to all address locations are allowed.
four lower-order address pointer bits are internally
incremented by one.

FIGURE 6-1: BYTE WRITE

S S
BUS ACTIVITY T
A CONTROL WORD T
BYTE ADDRESS DATA O
MASTER R
T P
SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 6-2: PAGE WRITE

S
BUS ACTIVITY T S
MASTER A CONTROL WORD T
R BYTE ADDRESS (n) DATA (n) DATA (n +1) DATA (n + 15) O
T P
SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

 2004 Microchip Technology Inc. DS21210G-page 7

24AA024/24LC024/24AA025/24LC025
7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus Send
throughput). Once the Stop condition for a Write Write Command
command has been issued from the master, the device
initiates the internally-timed write cycle, with ACK
polling being initiated immediately. This involves the Send Stop
master sending a Start condition followed by the control Condition to
byte for a Write command (R/W = 0). If the device is still Initiate Write Cycle
busy with the write cycle, no ACK will be returned. If no
ACK is returned, the Start bit and control byte must be
re-sent. If the cycle is complete, the device will return
Send Start
the ACK and the master can then proceed with the next
Read or Write command. See Figure 7-1 for a flow
diagram of this operation.
Send Control Byte
with R/W = 0

Did Device No
Acknowledge
(ACK = 0)?

Yes

Next
Operation

DS21210G-page 8  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
8.0 READ OPERATIONS sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
Read operations are initiated in the same way as write but not before the internal address pointer is set. The
operations, with the exception that the R/W bit of the master then issues the control byte again, but with the
slave address is set to ‘1’. There are three basic types R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/
of read operations: current address read, random read 24LC025 will then issue an acknowledge and transmits
and sequential read. the eight bit data word. The master will not acknowl-
edge the transfer but does generate a Stop condition
8.1 Current Address Read and the 24AA024/24LC024/24AA025/24LC025 dis-
continues transmission (Figure 8-2). After this com-
The 24AA024/24LC024/24AA025/24LC025 contains mand, the internal address counter will point to the
an address counter that maintains the address of the address location following the one that was just read.
last word accessed, internally incremented by one.
Therefore, if the previous read access was to address
n, the next current address read operation would
8.3 Sequential Read
access data from address n + 1. Upon receipt of the Sequential reads are initiated in the same way as a
slave address with the R/W bit set to ‘1’, the 24AA024/ random read except that after the 24AA024/24LC024/
24LC024/24AA025/24LC025 issues an acknowledge 24AA025/24LC025 transmits the first data byte, the
and transmits the 8-bit data word. The master will not master issues an acknowledge (as opposed to a Stop
acknowledge the transfer but does generate a Stop condition in a random read). This directs the 24AA024/
condition and the 24AA024/24LC024/24AA025/ 24LC024/24AA025/24LC025 to transmit the next
24LC025 discontinues transmission (Figure 8-1). sequentially-addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24AA024/24LC024/
8.2 Random Read 24AA025/24LC025 contains an internal address
Random read operations allow the master to access pointer that is incremented by one upon completion of
any memory location in a random manner. To perform each operation. This address pointer allows the entire
this type of read operation, the word address must first memory contents to be serially read during one
be set. This is accomplished by sending the word operation. The internal address pointer will
address to the 24AA024/24LC024/24AA025/24LC025 automatically roll over from address 0FFh to address
as part of a write operation. Once the word address is 000h.

FIGURE 8-1: CURRENT ADDRESS READ

S
T S
BUS ACTIVITY A CONTROL T
MASTER R BYTE DATA O
T P
SDA LINE S P
A N
BUS ACTIVITY C O
K A
C
K

 2004 Microchip Technology Inc. DS21210G-page 9

24AA024/24LC024/24AA025/24LC025
FIGURE 8-2: RANDOM READ
S S
BUS ACTIVITY T T S
MASTER A CONTROL WORD A CONTROL DATA (n) T
R BYTE ADDRESS (n) R BYTE O
T T P
S S P
SDA LINE
A A A N
C C C O
K K K A
BUS ACTIVITY
C
K

FIGURE 8-3: SEQUENTIAL READ

S
BUS ACTIVITY CONTROL T
MASTER BYTE DATA (n) DATA (n + 1) DATA (n + 2) DATA (n + X) O
P
SDA LINE P
A A A A N
C C C C O
BUS ACTIVITY K K K K A
C
K

DS21210G-page 10  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

XXXXXXXX 24LC024
T/XXXNNN I/P13F
YYWW 0319

8-Lead SOIC (150 mil) Example:

XXXXXXXX 24LC024
T/XXYYWW I/SN0319
NNN 13F

8-Lead TSSOP Example:

Part TSSOP
Number Marking Code
XXXX 4L24
24AA024 4A24
TYWW I319
24LC024 L24
NNN 13F
24AA025 4A25
24LC025 L25

8-Lead MSOP Example:

Part MSOP
Number Marking Code
XXXXT 4L24I
24AA024 4A24I
YWWNNN 31913F
24LC024 4L24I
24AA025 4A25I
24LC025 4L25I

Legend: XX...X Customer specific information*

T Temperature grade
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

* Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

 2004 Microchip Technology Inc. DS21210G-page 11

24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

n 1

A A2

L
c
A1

β B1
p
eB B

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

DS21210G-page 12  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E1

D
2

B n 1

h α
45°

c
A A2

φ
β L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .050 1.27
Overall Height A .053 .061 .069 1.35 1.55 1.75
Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55
Standoff § A1 .004 .007 .010 0.10 0.18 0.25
Overall Width E .228 .237 .244 5.79 6.02 6.20
Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99
Overall Length D .189 .193 .197 4.80 4.90 5.00
Chamfer Distance h .010 .015 .020 0.25 0.38 0.51
Foot Length L .019 .025 .030 0.48 0.62 0.76
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .008 .009 .010 0.20 0.23 0.25
Lead Width B .013 .017 .020 0.33 0.42 0.51
Mold Draft Angle Top α 0 12 15 0 12 15
Mold Draft Angle Bottom β 0 12 15 0 12 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

 2004 Microchip Technology Inc. DS21210G-page 13

24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E1

D
2

1
n
B

α
A

φ A1 A2

β
L

Units INCHES MILLIMETERS*

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .026 0.65
Overall Height A .043 1.10
Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Overall Width E .246 .251 .256 6.25 6.38 6.50
Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50
Molded Package Length D .114 .118 .122 2.90 3.00 3.10
Foot Length L .020 .024 .028 0.50 0.60 0.70
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .007 .010 .012 0.19 0.25 0.30
Mold Draft Angle Top α 0 5 10 0 5 10
Mold Draft Angle Bottom β 0 5 10 0 5 10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086

DS21210G-page 14  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E1

D
2
B
n 1

A A2
c
φ
A1

(F) L
β

Units INCHES MILLIMETERS*

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 8 8
Pitch p .026 BSC 0.65 BSC
Overall Height A - - .043 - - 1.10
Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95
Standoff A1 .000 - .006 0.00 - 0.15
Overall Width E .193 TYP. 4.90 BSC
Molded Package Width E1 .118 BSC 3.00 BSC
Overall Length D .118 BSC 3.00 BSC
Foot Length L .016 .024 .031 0.40 0.60 0.80
Footprint (Reference) F .037 REF 0.95 REF
Foot Angle φ 0° - 8° 0° - 8°
Lead Thickness c .003 .006 .009 0.08 - 0.23
Lead Width B .009 .012 .016 0.22 - 0.40
Mold Draft Angle Top α 5°5° - 15° 5° - 15°
-
Mold Draft Angle Bottom β 5°5° - 15° 5° - 15°
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111

 2004 Microchip Technology Inc. DS21210G-page 15

24AA024/24LC024/24AA025/24LC025
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Added part number 24AA025 to document.
Correction to Section 1.0, Ambient Temperature.

DS21210G-page 16  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
ON-LINE SUPPORT SYSTEMS INFORMATION AND
Microchip provides on-line support on the Microchip UPGRADE HOT LINE
World Wide Web site. The Systems Information and Upgrade Line provides
The web site is used by Microchip as a means to make system users a listing of the latest versions of all of
files and information easily available to customers. To Microchip's development systems software products.
view the site, the user must have access to the Internet Plus, this line provides information on how customers
and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line
Internet Explorer. Files are also available for FTP Numbers are:
download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site 042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events

 2004 Microchip Technology Inc. DS21210G-page 17

24AA024/24LC024/24AA025/24LC025
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 24AA024/24LC024/24AA025/24LC025 Literature Number: DS21210G

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21210G-page 18  2004 Microchip Technology Inc.

 24AA024/24LC024/24AA025/24LC025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX Examples:

a) 24AA024-I/P: Industrial Temperature,
Device Temperature Package
1.8V, PDIP Package
Range
b) 24AA024-I/SN: Industrial Temperature,
1.8V, SOIC Package
Device: 24AA024: 1.8V, 2 Kbit Addressable Serial EEPROM with c) 24AA025T-I/ST: Industrial Temperature,
WP pin. 1.8V, TSSOP Package, Tape and Reel,
24AA024T:1.8V, 2 Kbit Addressable Serial EEPROM
no WP
(Tape and Reel) with WP pin.
24LC024: 2.5V, 2 Kbit Addressable Serial EEPROM with d) 24LC024-I/P: Industrial Temperature,
WP pin. 2.5V, PDIP Package
24LC024T:2.5V, 2 Kbit Addressable Serial EEPROM
e) 24LC024-I/MS: Industrial Temperature,
(Tape and Reel) with WP pin.
24AA025: 1.8V, 2 Kbit Addressable Serial EEPROM with 2.5V, MSOP Package, Tape and Reel
no WP pin. f) 24LC025-T-I/SN: Industrial Temperature,
24AA025T:1.8V, 2 Kbit Addressable Serial EEPROM 2.5V, SOIC Package, Tape and Reel, No
(Tape and Reel) with no WP pin.
24LC025: 2.5V, 2 Kbit Addressable Serial EEPROM WP
(Tape and Reel) with no WP pin.
24LC025T:2.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with no WP pin.

Temperature Range: I = -40°C to +85°C

Package: P = Plastic DIP, (300 mil Body), 8-lead

SN = Plastic SOIC, (150 mil Body)
ST = TSSOP, 8-lead
MS = MSOP, 8-lead

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2004 Microchip Technology Inc. DS21210G-page 19

24AA024/24LC024/24AA025/24LC025
NOTES:

DS21210G-page 20  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
No representation or warranty is given and no liability is
registered trademarks of Microchip Technology Incorporated
assumed by Microchip Technology Incorporated with respect
in the U.S.A. and other countries.
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
use or otherwise. Use of Microchip’s products as critical SmartSensor and The Embedded Control Solutions Company
components in life support systems is not authorized except are registered trademarks of Microchip Technology
with express written approval by Microchip. No licenses are Incorporated in the U.S.A.
conveyed, implicitly or otherwise, under any intellectual Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
property rights. dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc. DS21210G-page 21

 WORLDWIDE SALES AND SERVICE
AMERICAS China - Beijing Korea
Unit 706B 168-1, Youngbo Bldg. 3 Floor
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Tel: 905-673-0699 Netherlands
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Fax: 905-673-6509 P. A. De Biesbosch 14
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Fax: 61-2-9868-6755 Tel: 44-118-921-5869
Fax: 44-118-921-5820

02/17/04

DS21210G-page 22  2004 Microchip Technology Inc.