504 L. KIRASAMUTHRANON, J. KOSEEYAPORN, P.

WARDKEIN, QPSK MODULATOR WITH CONTINUOUS PHASE AND FAST …

QPSK Modulator with Continuous Phase

and Fast Response Based on Phase-Locked Loop
Lerson KIRASAMUTHRANON, Jeerasuda KOSEEYAPORN, Paramote WARDKEIN
Dept. of Telecommunications Engineering, Faculty of Engineering,
King Mongkut’s Institute of Technology Ladkrabang (KMITL), Ladkrabang, Bangkok, 10520, Thailand

[email protected]

Submitted December 4, 2016 / Accepted February 24, 2017

Abstract. Among M-phase shift keying (M-PSK) schemes, Among the PSK variants, QPSK modulation is one of the
quadrature phase-shift keying (QPSK) is used most often most popular ones, and four different phases are assigned
because of its efficient bandwidth consumption. However, for it: i.e., 45°, 135°, −135°, and −45°.
in comparison with minimum-shift keying, which has con-
tinuous phase transitions, QPSK requires a higher band- In general, M-PSK digital phase modulation involves
width to transmit a signal. This article focuses on the phase a signal of the form s(t) = Acos(ωct – ϕn), where ϕn is one of
transitions in QPSK signals, and a QPSK modulator based the M-PSK phases. This expression can be rewritten as
on a phase-locked loop (PLL) is proposed. The PLL circuit s(t) = an cos(ωct) + bn sin(ωct), where an = Acos ϕn and
in the proposed system differs from that of conventional bn = Asin ϕn. It can be seen that the key factors for control-
PLL circuits because a three-input XOR gate and a sum- ling the phase of the M-PSK signal are an and bn, which are
ming circuit are used. With these additional components, the voltage levels corresponding to each set of digital data
the proposed PLL provides a continuous phase change in bits (n bits/set). For example, in the case of 2 bits/set,
the QPSK signal. Consequently, the required bandwidth for M = 22 = 4, which is equivalent to QPSK modulation;
transmitting the QPSK signal when using the proposed hence, four possible two-bit combinations (00, 01, 10, 11)
circuit is less than that for a conventional QPSK signal are converted to analogue voltage levels by using a D/A
with a discontinuous phase. The analytical results for the converter to generate the associated an and bn. Finally,
proposed system in the time domain agree well with the a phase-modulated signal is obtained.
experimental and simulation results of the circuit. Both the This basic principle for generating a QPSK signal has
theoretical and experimental results thus confirm that the led to many modulation techniques, such as QPSK modu-
proposed technique can be realized in real-world applica- lation using FPGA [8], [9], VLSI [10] or CMOS [11–14].
tions. All these techniques are based on the application of the
aforementioned basic principle by using modern technol-
ogy. Some limitations exist such as applicable frequencies,
Keywords power consumption, unsupported electronic components,
and high cost. In 2007, a QPSK modulating circuit that
QPSK, Phase Locked Loop (PLL), phase shift controls the gain of a phase-locked loop (PLL) to shift the
phase was proposed, along with external circuits [15].
However, the reference frequency used for the PLL in this
1. Introduction approach is fairly low; as a result, it cannot be implemented
using current technology. In addition, the requirement of
Digital modulation currently plays a vital role in external circuits also increases the level of complexity of
communication systems such as satellite communication this technique. Furthermore, the continuous phase change
[1–4], television broadcasting, asymmetrical digital sub- in the PSK signal owing to the operation of the PLL is not
scriber lines (ADSL) [5], and mobile communication [6], mentioned in the study. In [16], a QPSK modulating circuit
[7]. This is because digital modulation provides high secu- constructed with basic electronic components (e.g., op-
rity, is not subject to interfering noise, and requires less amps, D flip-flops, inverters, and BJTs) was proposed. This
bandwidth than analogue modulation. Various types of structure not only is complex but also lacks flexibility ow-
digital modulation exist, including amplitude shift keying ing to the mandatory requirement of a 90° phase difference
(ASK), frequency shift keying (FSK) and phase shift key- in the input signals.
ing (PSK). In PSK modulation, the phase of the output It is well known that the phase in a QPSK signal is
signal is shifted from the reference phase according to the discontinuous, which results in signal components of high
input data bit. There are multiple variants of PSK, such as frequency; thus, QPSK signals require a high bandwidth
binary phase-shift keying (BPSK), quadrature phase-shift for transmission. The bandwidth required can be reduced
keying (QPSK) and M-phase shift keying (M-PSK). by using minimum-shift keying (MSK) [17], which is

DOI: 10.13164/re.2017.0504 CIRCUITS

RADIOENGINEERING, VOL. 26, NO. 2, JUNE 2017 505

known as continuous phase shift keying. There are no relatively simple, the associated mathematical analysis,
phase discontinuities because the frequency changes occur which involves many elements, can become complicated.
at the carrier’s zero-crossing points. Therefore, MSK re- A block diagram of a conventional PLL is shown in
quires less bandwidth than QPSK. However, it should be Fig. 1(a). The reference signal and the output signal from
noted that an MSK signal uses more than one frequency for the voltage-controlled oscillator (VCO) are fed into the
signal transmission, whereas a QPSK signal uses only one phase detector. The output from the phase detector is
frequency. passed through the loop filter and then applied to the VCO.
In this paper, a technique for generating a QPSK sig-
nal based on a PLL circuit is proposed. Given that the PLL
has a natural response every time the parameters in the 2.1 Conventional Phase-Locked Loops
system are changed, the outputs of the PLL (the QPSK In this section, a brief overview of conventional
signal) has a continuous phase change and a constant fre- PLLs, which consist of a phase detector (PD), a low-pass
quency. Hence, this technique requires less bandwidth than filter (LPF), a VCO, and an integrator, is presented. The
conventional QPSK and uses only one constant frequency, notation used in the figures is as follows:
unlike MSK, which uses multiple frequencies. In the de-
modulation process, the principle of demodulating conven- ϕi(s):Laplace transform of the input function ϕi(t)
tional QPSK signals can be applied to the proposed ap- ϕo(s):Laplace transform of the output function ϕo(t)
proach. Although the demodulation process necessarily ϕd(s):Laplace transform of the phase error ϕd(t)
starts after the phase transition in the modulated signal is VL(s):Laplace transform of the loop filter output vL(t)
complete, this is not important because the phase transition ωo(s):Laplace transform of the frequency output of the
time of the modulated signal is constant. In addition, the VCO ωo(t)
phase transition time can be adjusted by modifying the cut- F(s): Transfer function of the loop filter
off frequency of the low-pass filter. I(s): Transfer function of the integrator
ω r: Running frequency of the VCO
kd: Gain of the phase detector
2. Principles A: Gain of the loop filter
B: Sensitivity of the VCO
A PLL is a control system that generates an output
signal whose phase is related to the phase of the input C: Gain of the integrator
signal. Although the basic concepts of PLL operation are D: A constant, where D=A×B×C

(a)

(b)

(c)
Fig. 1. Block diagrams of different PLLs: (a) Block diagram of a conventional PLL. (b) Block diagram of a PLL with gain control.
(c) Block diagram of a PLL with a summing circuit.
506 L. KIRASAMUTHRANON, J. KOSEEYAPORN, P. WARDKEIN, QPSK MODULATOR WITH CONTINUOUS PHASE AND FAST …

The aim of conventional PLL analysis is to obtain the From (8), the solutions are m1 = –D and m2 =
complete solution ϕo(t) of the system. From Fig. 1(a), the –(ωc + D), and thus the solution of the natural response is
relationship of the parameters in the system can be written
C1 C2
as on  t    . (9)
 exp  Dt  exp  c  D  t 
o  s   F  s  I  s  Bkd i  s   F  s  I  s  Bkd o  s   I  s  r . (1)
s
Next, the forced response ϕof (t) will be analyzed from
Substituting the transfer function of the loop filter, the second-order differential equation. Let the input signal
F(s) = A/(1 + Gs), and the transfer function of the of the system ϕi (t) be a linear function of time, given as
integrator, I(s) = C/s, in (1) yields
i  t   i t  i (10)
Cr
Gs o  s   so  s   Do  s   Di  s  
2
 CGr . (2) where ωi is the reference frequency and θi is the initial
s
phase of the input signal. Then, ϕof (t) can be expressed in
By taking the inverse Laplace transform of both sides of the following form
(2), it becomes a second-order differential equation.
of (t )  at  b (11)
d o  t  do  t 
2

G   Do  t   Di  t   Cr u  t   CGr  t  . where a and b are constants. Replacing ϕi (t) and ϕof (t) in
dt 2 dt
(3) with (10) and (11) yields
(3a)
Cr  i
In reality, all systems have the causality property. For of  t   i t  i  . (12)
this system, t in (3a) is said to be greater than zero ( t  0 ), D
and applying this property to (3a) gives rise to (3b). Thus, the complete response is
Gd o  t  d o  t 
2
 C1   C  i 
  Do  t   Di  t   Cr . (3b) o  t   
C2
   t  i  r
dt 2 dt 
 exp  Dt  exp  c  D  t    i  . (13)
  D 
From (3b), the solution for ϕo(t) can be determined by
solving the differential equation. In general, ϕo(t) is com- From (13), the process of the PLL can be described as
posed of two parts: a homogeneous solution (the natural follows: when a proper input is fed to the PLL, the system
response ϕon(t)) and a particular solution (the forced re- will reach the “steady-state” mode if the natural response is
sponse ϕof(t)). The natural response can be found from the zero. It should be noted that parameters of the PLL (e.g., all
second-order differential equation when there is no input gains in the PLL and the cut-off frequency) have an effect
applied to the system, on the time required to reach the steady state. When the
PLL is in the steady state, its output is
d 2 on (t ) d on (t )
G   Don (t )  0 . (4) C  r  i
d t2 dt o  t   i t   i  . (14)
D
From (4), the characteristic equation is given by (5), and
By comparing the reference signal in (10) with the
the solutions of (5) are expressed in (6).
output in (14), it can be seen that the angular frequency of
Gm 2  m  D  0 , (5) the reference signal is equal to that of the output signal, but
the phase is shifted, as given by
1  1  4GD
m1,2  . (6) i  Cr
2G d  t   . (15)
D
In the transfer function of the loop filter, ωc is specified as
the cut-off frequency. Hence, the relationship equation The shifted phase depends on the angular frequency
of the reference signal and all gains in the system. It should
between G and ωr is defined as G = 1/ ωr, and (6) can be
be noted that a QPSK modulator using this technique was
rewritten as
presented in [15].
c c 4D
m1,2    1 . (7)
2 2 c 2.2 QPSK Modulator Based on a PLL with
By using the Taylor series a Gain Control
x x 2 x3 According to the analysis shown in the previous sub-
1  x  1     ... for x  1 and x   4 D c , section, the phase of the output signal can be controlled by
2 8 16
(7) can be rewritten as the system gain. However, it is fairly difficult to change the
gain of a conventional PLL, and the PLL may not be able
c c  2 D . (8) to reach its locking state as a result of any change made to
m1,2    the system. Therefore, the simplest way to shift the phase
2 2
of the signal is by adding a gain controller between the
RADIOENGINEERING, VOL. 26, NO. 2, JUNE 2017 507

phase detector and the low-pass filter or between the low- As shown in (18), the DC level M, which is used for
pass filter and the VCO, as shown in the block diagram of phase shifting, has no effect on the natural response, as
the PLL with gain control in Fig. 1(b). In this figure, it opposed to the case when a PLL with a gain control is
should be noted that k1 is a gain constant that is placed used. In addition, the time between phase changes is
between the phase detector and the loop filter and that k2 is always constant; as a result, the demodulation procedure
a gain constant that is placed between the loop filter and when using this technique can be easily managed. Further-
the VCO. The PLL system is analyzed using Fig. 1(b); the more, the phase-shifting speed can also be controlled by
complete response is calculated as in (16) and the phase adjusting the cut-off frequency of the low-pass filter. How-
difference is calculated as in (17). ever, only two phase positions can be obtained. Therefore,
to achieve the other two phase shift positions, phase
 C1 C2  reversing is required, which will be discussed in the next
o  t     
 exp  k1k2 Dt  exp  c  k1k2 D  t   section.
  (16)
 Cr  i 
 i t  i  , 2.4 π-Radian Phase Shifting Based on the
 k1k2 D 
Data Bit
i  Cr
d  t   . (17) In this subsection, the theory for adapting operations
k1k2 D
for π-radian phase shifting based on the data bit of the
From (16) and (17), reference [15] shows that the phase detector is described. In a conventional PLL, the
output phase can be correctly shifted to two positions: π/4 phase detector has two input signals (a reference signal
and 3π/4 radians, and that additional circuits are required to ϕi (t) and its output signal ϕo (t)), and can detect phase dif-
shift the phase to –π/4 and –3π/4 radians. The natural re- ferences ranging from 0 to π radians.
sponse that occurs for each instance of phase shifting Hence, in a three-input phase detector based on an
causes continuous phase shift modulation. The benefits of XOR gate, as shown in Fig. 2(a), two inputs are used to
such a modulation system are decreased bandwidth usage detect the phase difference between two signals, while the
and high-order harmonic component prevention. However, other input is used for π-radian phase shifting. The truth
the gain required for shifting from π/4 to 3π/4 is not the table is given in Tab. 1, and it can be seen that when the
same for shifting from 3π/4 to π/4. For this reason, the data bit is in the low state (L), the three-input phase detec-
natural response occurring for each instance of phase
shifting is definitely not equal. Because of the gain varia-
tion required for the different phase changes, the non-per-
sistent natural response of the QPSK-PLL modulation with
a gain control circuit causes demodulation difficulty. To
control phase changes so that the natural response is con- (a)
sistent and to reduce complexity of demodulation, the PLL
structure has been improved, as presented in the following
section.

2.3 QPSK Modulator Based on a PLL with

a Summing Circuit
Another method for generating the QPSK signal is to
place a summing circuit between the low pass-filter and the
VCO, as depicted in Fig. 1(c). A DC level, M, is employed
to obtain the desired phase shift. This technique also pro- (b)
vides a continuous phase shift in the QPSK signal. The Fig. 2. Phase detector based on an XOR gate:
complete response of the system is given by (a) Three-input phase detector based on an XOR gate.
(b) Three-input phase detector timing diagram.
 C1 C2 
o  t      Data bit i  t  o  t  d  t 
 exp  Dt  exp  c  D  t  
  (18) L L L L
 Cr  i  BCM  L L H H
 i t  i  D . L H L H
  L H H L
Equation (18) shows that the DC level can control the H L L H
H L H L
output phase shift, which results in
H H L L
i  Cr  BCM H H H H
d  t   . (19)
D Tab. 1. Truth table of a 3-input XOR gate.
508 L. KIRASAMUTHRANON, J. KOSEEYAPORN, P. WARDKEIN, QPSK MODULATOR WITH CONTINUOUS PHASE AND FAST …

tor will operate in the same manner as the conventional phase detector, is employed to control the phase detector
phase detector. However, when the data bit is in the high output, either inverting or non-inverting for the low state or
state (H), this phase detector’s output is the inverse of the the high state, respectively. The designed modulation code
output of the low state (L). The relationship between the is given in Tab. 2.
input signals of the phase detector is demonstrated in
Fig. 2(b). From Fig. 2(b), the duty cycle when the data bit
is L and H can be expressed as (20) and (21), respectively. 4. Experimental and Simulation
Duty cycle d  t   
tp
, (20) Results
T
tp
Duty cycle d  t    1  . (21) 4.1 Relationship between the DC Level and
T the Phase Shift of the QPSK Signal
With this principle, the proposed PLL can shift the An experiment using the proposed technique was
phase by π radians, and this principle can be used to gener- conducted to verify that this technique can be implemented
ate a QPSK signal with a PLL. The next section will de- in real-world applications. The experimental setup and the
scribe the proposed QPSK modulator, which is based on results are presented in this subsection. A circuit based on
a summing circuit, and the adaptation of the operation of the proposed PLL is illustrated in Fig. 4(a). It is composed
the phase detector by using the data bit. of a three-input phase detector based on an XOR gate,
a summing circuit, a low-pass filter (with its cut-off fre-
quency at 5.89 kHz), and a voltage-controlled oscillator
3. Proposed QPSK Modulator using the XR2206 integrated circuit (which generates
a signal whose maximum frequency is 86.73 kHz and has
As it is clear from the previous subsections, one ad- a gain of −17 kHz/V). The relationship between the DC
vantage of a QPSK modulator based on a PLL with level M and the phase shift was first examined in this ex-
a summing circuit is that the QPSK signal produced has periment. The data bit D1 was set to 0 (the low state), the
a continuous phase change, thus requiring less bandwidth reference signal frequency was set to 70 kHz, and the infor-
than that of conventional QPSK transmissions. Moreover, mation signal of the summing circuit was set to be a DC
demodulation when using this QPSK modulating technique signal. The obtained phase shift output in accordance with
is less complex compared to that when the QPSK modula-
tor based on a PLL with gain control is used, because of the
constant phase shifting. In addition, the phase detector
based on a three-input XOR gate provides full-range phase
shifting. Hence, a new QPSK modulator is proposed, as
depicted in Fig. 3. As shown in the figure, the input data
bits are used as the switching control signal and the input
signal of the phase detector. Thus, the D/A component is
not required in this system. The data bits D0 and D0 are
used as the switching control signals for S0 and S1, respec-
tively. The data bit D1, which is also an input signal of the
(a)

380

360

340
Phase shifter output (Degree)

320

300

280

260

240

220

200

Fig. 3. Proposed QPSK modulator. 180

-.5 0.0 .5 1.0 1.5 2.0

Phase shift D1 D0 S1 S0 DC. Input (V)

-3π/4 L L OFF ON (b)

–π/4 L H ON OFF Fig. 4. Experimental circuit and its phase shift results:
π/4 H L OFF ON (a) Experimental circuit for verifying the relationship
3π/4 H H ON OFF between the information signal and the phase shift
output. (b) Phase shift of the output signal versus the
Tab. 2. The designed modulation code. DC input voltage of the proposed QPSK modulator.
RADIOENGINEERING, VOL. 26, NO. 2, JUNE 2017 509

the input DC level M is demonstrated in Fig. 4(b). It can be

seen that for DC input voltage levels varying from −0.02 V
to 1.32 V, the output signal phase is shifted from –3π/4 to
–π/4 radians.

4.2 QPSK Modulating Signal

The experimental setup for the proposed QPSK mod- (a)
ulator circuit illustrated in Fig. 3 is described in this sec-
tion. The D0 and D0 data bits are used to control switches
S0 and S1, respectively. The D1 data bit is the input of the
phase detector. In addition, two DC levels, M1 and M2, are
set as −0.02 V and 1.32 V, respectively, to obtain phase
shifts of –3π/4 radians (225°) and –π/4 radians (315°). The
resulting QPSK signals for –3π/4, –π/4, π/4 and 3π/4 phase
shifts are shown in Fig. 5.
(b)
Fig. 6. Example of the continuously changing phase of the
QPSK signal: (a) Phase changing from 3π/4 radians to
π/4 radians (experimental results). (b) Phase changing
from 3π/4 radians to π/4 radians (simulation results).

For each change in the data bits, the natural response

is conclusively removed, and the system reaches the steady
state as the phase of the QPSK signal simultaneously
reaches the specified value. Because of the continuous
(a) phase shift characteristic of the proposed modulator, no
high-frequency harmonics occur, and less bandwidth is
required than for a conventional QPSK modulator. Figure 6
shows an example of the output phase changing from 3π/4
radians to π/4 radians.
In addition, the proposed technique was verified by
computer simulation using MATLAB/Simulink. The sim-
ulation results obtained for an example phase change are
shown in Fig. 6(b).
(b)
4.3 Reducing Phase-Shifting Time by
Changing the Filter’s Cut-Off Frequency
According to the analysis and experimental results, it
can be seen that the generated QPSK signal has a continu-
ous phase shift when the input data bit is changed. The
phase-shifting time can be reduced without affecting the
system output by adjusting the cut-off frequency of the
low-pass filter in (18). As observed in (18), the cut-off
(c) frequency of the low-pass filter affects only the natural
response. Hence, making the natural response vanish
quickly makes the phase-shifting process faster as well. In
other words, phase-shifting time is directly proportional to
convergence time to the steady state of the natural re-
sponse. However, in practice, the complete phase-shifting
process is unknown. To determine the completion time of
the phase-shifting process, the output of the loop filter must
be considered, because the phase-shifting process is truly
complete only when the output of the loop filter is in the
(d) steady state.
Fig. 5. Resulting QPSK signals: (a) For a phase shift of
In the experiment and the simulation, phase shifts
–3π/4 radians. (b) For a phase shift of –π/4 radians.
(c) For a phase shift of π/4 radians. (d) For a phase from –3π/4 radians to –π/4 radians were obtained when the
shift of 3π/4 radians. cut-off frequency was set to 37,037 rad/s, 50,000 rad/s, and
510 L. KIRASAMUTHRANON, J. KOSEEYAPORN, P. WARDKEIN, QPSK MODULATOR WITH CONTINUOUS PHASE AND FAST …

From this subfigure, it can be seen that an increase in the

cut-off frequency can decrease the time it takes for the
filter output to reach the steady-state (thus reducing phase-
shifting time). As a result, the system will be able to
increase the transmission bit rate.

4.4 Power Spectral Densities for Conventional

QPSK, QPSK from PLL with a Gain
Control and QPSK from PLL with a Sum-
(a)
ming Circuit
The simulation results for comparing the power spec-
tral densities (PSDs) obtained from conventional QPSK,
QPSK from PLL with gain control, and QPSK from PLL
with a summing circuit are shown in Fig. 8. The theoretical
analysis and the experimental results coherently show that
the proposed QPSK modulator provides continuous phase
change, which directly affects the PSD of the signal. From
Fig. 8(a), it can be seen that the main lobe and the first
nulls of the conventional QPSK spectrum occur at the same
(b)
frequencies as that of the spectra of QPSK from PLL with
a summing circuit and the QPSK from PLL with a gain
Fig. 7. Experimental and simulation results for different cut- control. However, the difference between the null and peak
off frequencies: (a) Phase transition of the QPSK
signal for a cut-off frequency of 37,037 rad/s. of its side lobe Ψ is greater than that of the proposed QPSK
(b) Simulation results of the LPF output for cut-off based on PPL σ. This shows that most of the proposed
frequencies of 37,037 rad/s, 50,000 rad/s and QPSK signal is contained within the main lobe of the spec-
100,000 rad/s. trum, resulting in a lower bandwidth than that of conven-
100,000 rad/s. Figure 7(a) shows an example of phase tional QPSK. The spectrums of the bandpass filter outputs
transition of the QPSK signal for a cut-off frequency of can be compared in Fig. 8(b) when the frequency range of
37,037 rad/s. In this subfigure, the top, middle, and bottom the bandpass filter used in the simulation is placed between
traces are the data, the low-pass filter output, and the QPSK 63.7-76.3 kHz. According to Fig. 8(b), the spectrum of the
signal and its reference signal, respectively. In addition, the filtered QPSK from PLL with summing shows the superior
simulation results for the low-pass filter outputs for the null and peak of the sidelobe than that of the conventional
three different cut-off frequencies are shown in Fig. 7(b). QPSK.

(a)

(b)
Fig. 8. The comparison of PSDs obtained from different modulation techniques: (a) The spectrum of QPSK signals before filtering.
(b) The spectrum of QPSK signals after filtering.
RADIOENGINEERING, VOL. 26, NO. 2, JUNE 2017 511

5. Error Analysis In (22), Ad is the amplitude of the PWM signal from

the XOR gate, tp is the time for which the signal is high, T
An analysis of phase error in the QPSK signal is pre- is the total period of the signal, and ω0 is the angular fre-
sented in this section. Generally, phase detectors, especially quency of ϕd (t). Therefore, the relationship between tp and
XOR gates, generate an output in the form of a pulse-width the DC component of vPWM(t) can be rewritten as
modulated (PWM) signal, as exemplified in Fig. 9(a).
Hence, the phase difference resulting from the phase de- Tkd d  t 
tp  (23)
tector is directly proportional to the DC component of the Ad
PWM signal [18], as expressed by the following equation.
where kd is the gain of the phase detector. Substituting (23)
vPWM  t   in (22) yields (24).
Ad t p vPWM  t   kd d  t  


  n sin  n t   n sin  n  t  t  .

Ad  1 1  .(22)


0 0 p
T
1  Tkd d  t     (24)
n 1
Ad 
1 

  n sin  n t   n sin  n
0 0 t 
Ad
  .
n 1      
After vPWM(t) passes through the low-pass filter, the
magnitude and phase responses are (25) and (26),
respectively.

vo   1
 , (25)
(a) vi   1   c 
2

 
 vo   arctan   (26)
 c 
where vi is the magnitude of the input signal, vo is the mag-
nitude of the output signal, vo is the output phase, and ωc
(b) is the low-pass filter’s cut-off frequency. The low-pass
Fig. 9. Error analysis of fluctuating-output of LPF that affects filter output for the input signal vPWM(t) is thus expressed in
phase shifting of QPSK signal: (a) Realization of the
1   n0 c   n0 c ,
2
phase detector output. (b) Illustration of the second (27). By using the approximation
term of equation (28) using computer simulation. (27) can be rewritten as (28).
v L  t   kd d  t  
 
 
Ad   1 1   n0   1 1   Tkd d  t    n0    (27)
 
 n 1  n
sin  n0t  arctan      sin  n0  t 
   arctan    ,
 c   n Ad  c   
2 2
 n0    n0    
 1   1   
  c   c  
Ad c  1   n   1   Tk   t    n   
vL  t   kd d  t  
0
n sin  n0t  arctan  0    2 sin  n0  t  d d
     arctan  0   .
 (28)
 c   n  c   
2
n 1     Ad 
2c
By considering (28), it is clear that the first term is the DC phase error  error  =
. (30)
component kdϕd(t) and that the second term is a triangular 0
signal with asymmetric slopes, as illustrated in Fig. 9(b). As shown in (30), the phase error is proportional to
From (28) and Fig. 9(b), the minimum and maximum error the low-pass filter’s cut-off frequency. A technique to
voltage range is found to lie between –Adωc/πω0 and eliminate this phase error is currently under investigation.
+Adωc/πω0. The magnitude of the error voltage is thus
expressed in (29). The PLL can support a maximum phase
shift of π radians, corresponding to the highest output 5.1 Phase Noise
voltage of the low pass filter, Ad. Hence, according to (29), Phase noise in the proposed QPSK modulator, which
the magnitude of the phase error can be expressed by (30). is caused by the phase error signal or the amplitude fluctu-
Ad c ation of the VCO input signal as described in (28), can be
Verror  , (29) measured by considering the power spectral density S(ω) of
0 the periodic phase error signal expressed in (31):
512 L. KIRASAMUTHRANON, J. KOSEEYAPORN, P. WARDKEIN, QPSK MODULATOR WITH CONTINUOUS PHASE AND FAST …

 
 n t 
S     cn    n0  S     4d     n0  .
2
(31) 2
sin 2  0 p (34)
n  n   2 
where cn is the magnitude of the spectrum, and ω0 is the According to the transfer function of the low-pass
angular frequency of the signal. The phase error signal is filter described in (25), the PSD can be expressed by (35)
the low-pass filter output signal, and the magnitude of the
2
spectrum cn is calculated from coefficients an and bn of vo  
the phase detector output signal as described in (32). So     S   
vi  
cn  an2  bn2    n t 
2
(35)
 
4 A sin  0 p 
2
 (32)
2 1   2      n .
 2A
 
  2A
sin  n0t p      cos  n0t p   1  .

1   c 
2   nT 0 
 0
 
 nT 0   nT 0
n 
  
 
By letting d = 2A/(nTω0) and because sin2(θ/2) =
½ (1 – cosθ), (32) can be rewritten as (33). Thus, the phase noise can be described as (36)

 n t  phase noise  10 log  S0    

cn  2d sin  0 p  . (33)
 2     n t 
2

  
4 A sin  0 p   (36)
 1   2      n  .
By substituting (33) into (31), the PSD can be
expressed as (34).
 10 log  2   nT 0 
 0 
1     n 
  
 
  c    

According to (36), phase noise charts, such as the

ones presented in Fig. 10, can be generated, showing the
inverse proportionality between the phase noise and the
duty cycle tp. As can be seen, the more the duty cycle is the
less phase noise in the QPSK signal of the proposed
scheme.

5.2 Error Vector Magnitude (EVM)

(a)
The concept of error vector magnitude (EVM) is
explained in this subsection. An error vector is a vector in
the I-Q plane between the error point (Ierror, Qerror) and the
ideal constellation point (In, Qn), which can be calculated
from the expression of QPSK as shown in (37):
s  t   A cos c t   n  (37)

which can be rewritten as (38)

s  t   A cos n  cos c t   A sin n  sin c t  . (38)
(b)
Hence, the ideal constellation point can be described by
(39) and (40) as follows
I n  A cos  n  , (39)
Qn  A sin  n  . (40)

Likewise, the error point (Ierror, Qerror) of the proposed

QPSK technique can be described by (41) and (42)
I error  A cos  error  , (41)

(c) Qerror  A sin  error  . (42)

Fig. 10. Phase noise charts for different duty cycle values.
(a) Phase noise for a duty cycle of 20%. (b) Phase
From (30), the calculated phase error (θerror) is directly
noise for a duty cycle of 50%. (c) Phase noise for proportional to the LPF's cut-off frequency, which affects
a duty cycle of 80%. to the EVM.
RADIOENGINEERING, VOL. 26, NO. 2, JUNE 2017 513

Conference (IMOC). Belem (Brazil), November 2009, p. 282–285.

 I 
3
 I n    Qerror  Qn 
2 2
DOI: 10.1109/IMOC.2009.5427582
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. (43) [3] CARTIER, N., HUSSONNOIS, M., TRANIER, B., et al. X-band

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modulation. IEEE Communications Magazine, 1979, vol. 17, Jeerasuda KOSEEYAPORN graduated M.S. and Ph.D.
no. 4, p. 14–22. DOI: 10.1109/MCOM.1979.1089999
degrees in Electrical Engineering from Vanderbilt Univer-
[18] SUN, J. Pulse-Width Modulation. Chapter in Dynamics and sity, Nashville, TN, USA, in 1999 and 2003, respectively.
Control of Switched Electronic Systems. Springer Science & She is now an associate professor of Telecommunications
Business Media, 2012, 1st ed., p. 25–61.
Engineering Department, Faculty of Engineering,
(KMITL), Thailand. Her current research interests include
analog circuits in telecommunication systems and digital
signal processing.
About the Authors …
Paramote WARDKEIN received his M.E. and D.Eng.
Lerson KIRASAMUTHRANON received B.Eng and degree in Electrical Engineering from King Mongkut’s
M.S. degree in Telecommunication Engineering from King Institute of Technology Ladkrabang (KMITL), Bangkok,
Mongkut’s Institute of Technology Ladkrabang (KMITL), Thailand, in 1990 and 1997, respectively. He is now an
Bangkok, Thailand, in 2009 and 2012. He is currently pur- associate professor of Telecommunications Engineering
suing his Ph.D. degree at the same institute in the area of Department, Faculty of Engineering, (KMITL), Thailand.
telecommunication engineering. His current research inter- His current research interests include not only the field of
ests include signal processing and control system. signal processing but also analog-digital communications.