Unit . Analog Electronics Contents (s. | Topic | Page No. 1. Diodes and their Applications... a4 2. BIT, FET and their Biasing Circuit seisernaenn 422 3. Small Signal Analys 433 4, Operational Amplifiers se ABS 5 Oscillators and Feedback Amplifiers...... ne 454 6. Miscellaneous. 458Diodes and their Applications 14 12 13 14 18 Figure shows an electronic votage regulator. The zener diode may be assumed to require a minimum current of 25™mA for satisfactory operations, The value of Rrequired for satistactory voltage regulation ofthe circuits Kov F100 [1901 : 2 Marks} ‘The depletion region (ot) space charge region (or) transition region ina semiconductor p-n junction lode has (@) electrons and holes (©) postive ions and electrons (©) positive and negative ions (@) negative ions and holes [1996 : 1 Mark] ‘As temperature is increased, the voltage across a diode carying a constant current (@) increases (©) decreases (©) remains constant (@) may increase or decrease depending upon the doping levels in the junction [1999 : 1 Mark] The mobility of an electron in a conductor expressed in terms of (@) cmeN-sec © cmv (b) omisec (@) omsec [1999 : 1 Mark] ‘A diode whose terminal characteristics are reiaieg 8 p= 1, 7, where /, is the reverse saturation current and Vis thermal voltage (= 25 mV). is biased at n= 2 mA, Its dynamic resistance is @ 2a (o) 1250 © 9a (@ 10a WwW 18 The forward resistance of the diode shown n figure is 5 Qand the remaining parameters are same as. those of ideal diode, The DC components of the source currentis Vin A © Sox ©) Sone Yn 2p © Joonde ( Sonya (2002 : 1 Mark] The cutin voltage of both zener diode D, and D ‘shown in figure is 0.7 V, while breakdown voltage ‘of the zener is 3.3 V and reverse break down of D ig SV. The other parameters can be assumed to be the same as those ofan ideal diode. The values of the peak output voltage (V,) are (@) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle (©) 4 Vin the positive half cycle and § V in the negative halt cycle. (6) 8.3 V in the both positive and negative halt cycle. (@) 4 Vin the both-positive and negative halt oycie 1a. “Wy 4 ratenc()10 nos kav 1 L [2002 : 1 Mark] Inthe single-phase diode bridge rectfer shown in figure, the load resistor is R= 602. The source voltage is V= 200 sin at, where w = 2n x 60 radi.‘The power dissipated in the load resistor Ris 6! 2 ee > | : 2 «nw 2 @ anw [2002 : 2 Marks] 1.9 Avoltage signal 10 sin wtis applied to the circuit with ideal diodes, as shown in figure. The maximum, and minimum values of the output waveform V,, of the circuit are respectively 1010 a (@ #4Vand-7V [2003 : 2 Marks] 1.10 The current through the Zener diode in figure is 2240 ve23aV Ry (@) 33mA (©) 2ma (b) 3.3mA (a) Oma [2004 1 Mark] 1.11 Assuming that the diodes are ideal in figure, the ccurrent in diode D, is bo ho I sv > av (a) ama (0) 5ma () Oma (@) -3ma [2004 : 2 Marks} 1.12 Assume that D, and D, in figure are ideal diodes. The value of current Fis, 210 1m (c) 7 | Ezka (a) Oma (0) O.5mA fc) 1mA (a) 2ma (2005 : 1 Mark] 1.13 What ae the states ofthe three ideal diodes ofthe cercuit shown infigure? a0 OT {@) 0,0N, 0, OFF 0, OFF (©) 0, OFF, 0, ON, D, OFF (©) D,ON, 0, OFF, DON (0) 0,0FF,D,0N, 0,0N [2006 : 1 Mark] 1.14 Assuming the diodes D, and D, of the circuit shown in figure to be ideal ones, the transfor characteristics of the circuit willbeva tn @ o) © ba vo @ ot ey, io [2008 : 2 Marks} 1.18 The three-terminal linear voltage regulator is connected toa 10 load resistor as shown in the figure. If Vis 10 V, what is the power dissipated inthe transistor? ene ha Zr-100 “ ener $00 ° (@ o6w (o) 24w ( 42w @ 54w [2007 : 1 Mark] 1.16 The equivalent circuits ofa diode, during forward biased and reverse biased conditions, are shown inthe igure pale ae opts oe @ sosnat ©) ov Zou 17 Hf euch a diode is used in clipper circuit of figure Given above, the output voltage (V) ofthe circuit will be [2008 : 1 Mark) Inthe voltage doubler circuit shown in the figure, the switch 'S is closed at t= 0, Assuming diodes ‘D, and D; tobe ideal, load resistance tobe infinite and initial capacitor voltages to be zero, The steady state voltage across capacitors C, and C, wate x 0 sinar : 2 am AE © tvs E Row ©) Vey ©) Va =5V, Va" 10V (8) Ve =5Y, Vig=10V {2008 : 2 Marks}1.18 Assuming that the diodes in the given circuit are ideal, the voltage V, is eT Fr tev baile (@ 4v 5V (© 75¥ (@) 1212v [2010 : 1 Mark] 1.19 The transistor used in the circult shown below has ‘a Pof 20 and /pgqis negligible. Ifthe forward voltage drop of diode is 0.7 V, then the current through collector will be (@) 168mA (0) 108mA (©) 2054mA —(d)_5.36mA [2011 : 2 Marks) 1.20 Aciippercitcuitis shown below Assuming forward voltage drops ofthe diodes to be 0.7 \, the input-output transter characteristics of the circuits @) () ——a v, [2011 : 2 Marks] 1.21 The bv characteristics of the diode in the circuit given below are: z ie} Goo v207V OA v () 10V uv © wv [1991 : 1 Mark) 2.2. Inthe transistor circuit shown in figure. Collector a ground voltage is +20 V. Which of the folowing Is the probable cause of rror? mov aia (@) Collector emitter terminals shorted (b) Emitter to ground connection open (©) 10k82 resistor open (@) Collector base terminals shorted [1994 1 Mark] 2.8 One the applications of current mirror is, (@) output currentiimiting (b) obtaining a very high current gain (©) current feedback (4) tomperature stabilized biasing [1998 : 1 Mark) 24 25 26 a7 28 ANPN Sitransistor is meant forlow-current audio ampiiication. Match its following characteristics against their values, Characteristics Values ©) Vea @ ory ©) Venas (9) o2v © Vern ® ev ©) sv [1998 : 2 Marks) The enhancement typo n-channel MOSFET is reprovented by symbol eal @ fe ) =z l= eal © —4 [1999 Inthe circulto figure, the value ofthe base current Igwillbe 1 Mark] wv (@) OWA (©) 182A (©) 267pA (@) 40uA [2000 : 2 Marks} ‘An channel JFET having a pinch-ot voltage (V,) of 5 V shows transconductance (g,) of 1 maN when the applied Gate to source voltage (Ve) is 3. ts maximum transconductance (mma) @) 18 (&) 20 © 25 @ 30 {2001 : 2 Marks} The variation of dain current with gate-o-source voltage (/p~ Vas characteristic) of a MOSFET is shown in figure. The MOSFET isVor a (@) ann-channel depletion mode device (©) ann-channel enhancement mode device (©) anp-channel depletion mode device (@ anp-channel enhancement mode device [2003 : 1 Mark] 2.9 Inthe circuit of figure, assume that the transistor thas pg =99.and Vgg = 0.7 V. The value of collector ‘current /c of the transistor is approximately 3310 te 330 Rv oe 33k0 (@) [3313.3] ma (©) [3.343.3+0.33)] mA (©) [3.3133] ma (© [33163 +3.3)] mA [2003 : 1 Mark] 2.10 Forthe n-channel enhancement MOSFET shown in figure, the threshold voltage V, = 2V. The drain current /p of the MOSFET is 4 mA when the drain resistance Apis 1 KO. Ifthe value of Rpisincreased t0.4k0, drain current /,willbecome tay 1 Em L_ (®) 20ma ( 10mA (@) 28ma (©) 1.4ma, 2.11 Two perfectly matched silicon transistors are connected as shown in igure. The value of the current is (@) OmA (0) 43 ma, (b) 23ma (@) 73mA [2004 1 Mark] 2.12 The transconductance 9,0! the transistor shown in igureis 10mS. The value of the input resistance Ryis bcd — 1010 ng cae wei B50 (a) 100k2 ~—() 83K (©) 50k (0) 25a [2004 : 2 Marks} 2.13 The value of F for which the PMOS transistor in figure wil be biased in linear region is f F aglim (a) 2209 (b) 470 (c) 6802 (d) 120092.14 Assume that the n-channel MOSFET shown in the figure is ideal, and that its thereshold voltage is. +1.0 Vthe voltage V,, between nodes a and bis ta. rT (@ 5v tv © 2v @ ov [2005 : 1 Mark) 2.15 The common emitter ampifer shown in the figure is biased using a 1 mA ideal current source. The approximate base current value is Yeo=8¥ 1OpA 1000 nA [2005 : 2 Marks) Statement for common data Questions (2.16 and 2.17) Assume that the threshold voltage of the n-channel MOSFET shown in figure is +0.75 V. The output characteristics of the MOSFET are also shown. (@) oa ©) (© 100nA @) R= 10%0 Moa 7 055 4 008) Vert) 2.16 The transconductance of the MOSFET is. (@ 075ms ——(b) 1S (© 2ms (@) toms, [2005 : 2 Marks) 2.17 The voltage gain of the ampli is. @ +5 @) 75 © +10 @ -10 [2005 : 2 Marks) 2.18 Consider the circuit shown in figure. If the B of the transistor is 30 and Jogo i$ 20 nA and the input voltage is +5 V, the transistor would be ‘operating in 22K 2 vi ke) 10080 (a) saturation region (0) activeregion (6) breakdownregion (A) cutoff region [2006 : 2 Marks) 2.19 The common emitter forward current gain of the transistor shown is B-= 100. tka.‘The transistor is operating in {a) saturation region (©) cutottregion (c) reverse active region (@) forward activeregion, [2007 : 1 Mark] 2.20 Two porfectly matched silicon transistor are connected as shown in the figure. Assuming the Botthe tansisiros to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current ris asa (@) Oma (b) 3.6mA (©) 43a, (@) 8:7mA [2008 : 2 Marks) 2.21. Thettsnisstor crcut shown uses asilcon transistor With Vag = 0.7 V,Je-= Je and a de current gain of 100. The value of V, ie rey sco (@) 465V ©) sv © 63v (@) 7238 [2010 : 2 Marks} 2.22 The vollage gain A, of the circuit shown below is @ |Al=200 JA|=100 © |Al=20 @ |A|=10 [2012 : 2 Marks] 2.23 The transistor in the given circuit should always bo in active region, Take Verua = 0-2 V. Vee = 0.7 V ‘The maximum value of Rin Q which can beused, [2014 : 1 Mark, Set-2] 2.24 Inthe given circuit. the silicon transistor has B= 75 and a collector voltage V=9V. Then the ratio of Rand Acie ay as Re [2015 : 1 Mark, Set-1] 2.26 In the following circuit, the transistor is in active mode and V,,= 2V. Toget V-=4V, we replace FR, with A. Then the ratio A/a 18 sv Ve [2018 : 1 Mark, Set-2}2.26 When a bipolar junction transistor is operating in the saturation mode, which one of the following statements is TRUE about the state of collector- base (CB) and the base-emitter (BE) junctions? {(@) The CB junctions is forward biased and the BBE junction is reverse biased, (©) The CB junctions is reverse biased and the BE junction is forward biased (© Both the CB and BE junctions are forward biased, (@) Both the CB and BE junctions are reverse biased, [2015 : 1 Mark, Set-2} 2.27 A transistor circuit is given below. The Zener lode breakdown vottage is §.3 Vas shown below. Take base to emitter voltage drop to be 0.6 V. The value of the current gain fis rove osmal sav) sna [2016 : 1 Mark, Set-1] 2.28 The circuit shown In the figure uses matched transistor with a thermal voltage V,= 25 mV. The base currents ofthe transistors are negligible. The value ofthe resistance A in k® that is required to provide 1 mA bias current for the differential ampilier block shown is. (Give the anawer up to one decimal place.) = Dare sat na [2017 : 2 Marks, Set-1) 2.29 Forte circuit shown inthe igure below, tis given that Vor = YB. The transistor has B= 29 and Vge = 0.7 V when the B-E junction is forward biased fe pez For this citcuit, the value of A/F is (a) 43 (©) @ (©) 121 © 12 [2017 : 2 Marks, Sot-2] 2.80 In the circuit shown in the figure, the bipolar junction transistor (BJT) has @ current gain 8 = 100. The base-emitter voltage drop Is a constant, Vge= 0.7 V. The value of te Thevenin equivalent resistance A, (in Q) as shown in the figure is (upto 2 decimal places) 1040 [2018 : 2 Marks) 2.31 The enhancement type MOSFET in the circuit below operates according to the square law. H,Cq,= 100 WAV, the threshold voltage (V,) is 500 m\. Ignore channel length modulation. The ‘output voltage Vag is(@ av (b) 500m (8) Vog> Voi Vag S Vo. Mp (© 100mv (6) 600mv (0) Von < Voy: Vag 2 Voy ~ Vo [2019 : 2 Marks] (©) Vog> Vii Yao? Vge~ Ve 2.82 Given, V,,{s the gate-source voltage, Vj isthe (O) Vas < Vani Vas $ Vos Mn (2019: 1M drain source voltage, and V,, is the threshold vottage of an enhancement ype NMOS transistor, the conditions for transistor to be biased in saturation are or BJT, FET and their Biasing Circuits 24 (©) 22 (o) 23 ) 25 (a) 26 (b) 27 () 28 (c) 29 (b) 210 (0) 21160) 212d) 243 ) 214(¢) 215 (o) 216 (o) 2.17) 2.18 (b) 2.19 d) 2.20 (bo) 2.21 (@) 2.22 (d) 2.28 (2232) 2.24 (105.13) 2,25 (0.75) 2.26 (c) 2.27 (19) 2.28 (1727) 2.29 (d) 2.90 (90.09) 231 ) 2.32 (©)Small Signal Analysis 3.1. Inthe transistor amplifier shown in figure, the ratio (@) increases (©) decreases Cf small signal voltage gain, when the emitter (6) isunatfectes —_(¢)_dropsto zero [2001 : 1 Mark} tesistoris bypassed by the capacitor'C, to when it Is not bypassed. (Assuming of simplified approximate h-parameter model for transistor) is Mee R ie i j}—ow, vo c se @1 @) h (1+ Me Fe @ 14 fhe A Ne d [1996 : 1 Mark) 3.2 Inthe single stage trancistor amplifier circuit shown in figure, the capacitor C,is removed thon the ac smal signal midband voltage gain ofthe amplifier ca : yw RE 7 7 {+ (EEEEIIEN smatt signal Analysis 3.1 @) 32 (b) 3.3 (d) The magnitude of the mid-band voltage gain of the circuit shown in figure is (assuming fh, of the transistor tobe 100) 3.3 ox ps tt—*M6 ng 100 “i 101 © 4 ©) 10 oa (@) 100 [2014 : 1 Mark, Set-1]Operational Amplifiers 4.1. An ideal op-amp is used to make an inverting amplifier. The two input terminals of the op-amp are atthe same potential because (@) the two input terminals are directly shorted internal, (©) the inputimpedance of he op-amp is infinity (6) the open-toop gain of the op-amp is infinity (@) CMBR is infinity. [1992 : 1 Mark] 4.2. The circult shown in igure is excited by the input wave form shown, Sketch the wave form of the output, Assume all the components are ideal [1992 : 2 Marks) 4.3. Given figure, shows @ non-inverting op-amp ‘summer with V; = 2V and V, = =1 V the output voltage V = a ro" [1904 : 1 Mark} 4.4. The commen mode voltage of @ unity gain (voltage follower) op-amp butter in terms of Its output voltage Vis [1995 : 4 Mark] 48 47 48 Let the magnitude of the gain in the inverting ‘op-amp circuit shown be x with switch S, open When the switch is closed, the magnitude of gain becames. (a) x2 (o) = (0) 2 (a) -2 [1996 : 1 Mark) ‘A non-inverting op-amp ampilier is shown in figure. The output voltage is. 20 2+ nt@o00 to Sao) sito (©) 2sintoor (@ noneot these [1996 : 1 Mark] ‘A major advantage of active filers is that they canbe realized without using @ opamps (©) inductors © resistors (8) copacitors [1997 : 1 Mark} Match the following Circuits:Me P High-pass fiter Comparator S. Low-pass iter [1998 : 2 Marks) 4.9 The feedback factor forthe circuit shown in figure 100 7 [tw — ook a Na 8 9 © 0 © 3 1 1 5 o [2000 : 1 Mark} 4.10 The circuit shown in figure uses an idesl op-amp working with +5 V and -5 V power supplies. The output voltage Vy is equal to sha (@) +5v @+Vv () Vv (9) -1V [2000 : + Mark] 4.11. An op-amp having a slew rate of 62.8 V/usec is connected in a voltage follower configuration. if the maximum amplitude of the input sinusoidal is 10 Volts, then the minimum frequency at which the slew rate limited distortion would set in the ‘output is (a) 1MHz (b) 628M (©) 10MHz (0) 62.8MHz [2001 : 2 Marks) 4.12 For the circuit of figure with an ideal operational ampitier, the maximum phase shift of the output Va with reference to the input Vis : é" t. ae relate Bie mae [2003 : 1 Mark] 418 smn ee cpr ng et the gain V,4/p for the circuit shown in figure is tha toKa. 1a aa ves M% @-1 (©) -20 (©) ~100 (@ -120 [2003-04 : 2 Marks] 4.14 The input resistance Ry, (= VI.) ofthe circuit in figure isV@ + 100KQ =) ~ 100K (0) +1MaQ— (@) -1 Ma | [2004 @ Markl ‘4.15. Consider the inverting amplifier, using an ideal operational amplifier shown in the figure. The designer wishes to realize the input resistance ‘seen by the small-signal source to be as large as possible, while keeping the voltage gain between =10 and -25. The upper limit on Ais 1 MQ. The value of R should be 5 tow f (ob) 1MQ (@) 40K [2005 : 2 Marks) (2) Infinity (©) 100kQ, 4.16 In the given figure, ifthe input is a sinusoidal signal, the output will appear as shown in 447 © @ Les [2005 : 2 Marks} For a given sinusoidal input voltage, the voltage waveform at point Pof the clamper circuit shown in figure wil be DN © 7h (@ o7v. “Vv oe [2006 : 1 Mark}4.18 A relaxation oscillator is made using OPAMP as shown in figure. The supply voltages of fhe OPAMP are = 12 V. The voltage waveform at point P will 7 - 5 iE ° + o_o of ye | «LF © o 4 +o 10] oY TN [2006 : 2 Marks] 4.19 The circuit shown in the figure is. R vt my Load w (2) avottage source wih votage Ta (0) avotage sec winotage My rR +P, (©) acurrent source with current (8, ecurentsouc wou Abe- [2007 : 1 Mark] 4.20 Theswitch Sinthe crcuitolthe gue isinialy closed, itis opened at ime t= 0. Yournay neglect the Zener 0? wt 7 4 oot ov (@) It makes a transition trom -5 V to +5 V at 12.98 ys (©) It makes a transition from -5 V to + 5 V at = 257 us (6) It makes a transition from +5 V to -§ V at t= 12.98 ys (d) Mt makes a transition trom + 5 V 10-5 V at S7 us [2007 : 2 Marks) 4.21 The block diagrams of two of half wave rectifiers are shown in the figure with the transfer Ccharacterstics of the rectifiers. itis desired to make full wave rectifer using above ‘wo hall-wave rectifiers. The resultant circutt will be Pe o “dy, ATL. Itis desired to make full wave reciier using above two half-wave rectifiers. The resultants circuit will be@ % ©) Yt (©) @ vo [2008 : 2 Marks) ‘Statement for Linked Answer Questions(4.22 and 4.23): ‘A general iter circuit is shown in the figure: R, ite f, é 2% "ER 4.22 It, = R= Ryand Ry =A, = Ag the circuit acts (@) allpass iter (b) band pass fiter (©) high pass fiter (4). low pass fiter 4.23 The output ofthe filter in Q.4.22 is given to the circutt shown in figure. “The gains reqeuncy characteristic ofthe output (vwillbe ain [2008 : 2 Marks} 4.24 Thenatureot feedbackin the opamp circuit shown (@) Current Current feedback (©) Votage - Voltage feedback (©) Current - Voltage feeaback (@) Voltage Current feedback [2009 : 1 Mark] 4,25 The following circuit has A = 10 kM, C= 10 pF. ‘The input voltage is a sinusoid at 50 Hz with an rms value of 10 \. Under ideal conattions, the current, from the source is4.26 427 (@) 10rmA\eading by 90° (©) 20nmA leading by 90° (©) 10mAleading by 90° (@) 10RmAlagging by 90° [2009 : 2 Marks) ‘Transformer and emitter follower can both be used forimpedance matching at te output of an audio amplifier The basic reationship between te input power P, and output power P,,. in both the cases is @) Py, = Pay for both transformer and emitter ‘ollower (©) Py > Pay for both transformer and emitter ‘lower (©) Ps, < Pag for transformer and P,, emitter folower (@) Py, = Pay for transformer and P,, < Pay for ‘emitter folower Pag for [209 : ‘An ideal opamp circuit and its input waveform are shown in the figures. The output waveform of this circuit will be Marks) q -1 -| va - : (b) q se - i epee © ot. ‘ sl “y o i i co yas [2009 : 2 Marks) 4.28 Given thatthe op-amp is ideal, the ulputvotage wis + (@ 4v (© 75V @) ) 6v 1212v [2010 : 1 Mark) 4.29 Alow-pass fiter with a cut-of frequency of 30 Hz is cascaded with a high-pass fiter with a cut-off frequency of 20 Hz. The resultant system of fiters will function as {@) anal-pass titer (©) anallstop fiter (c) aband stop (band-reject) titer (@) aband-pas fiter [2011 : 4 Mark)4.30 For the circuit shown below, 4.31 The circuit shown is a (@) low pass fter With fag = 1 rR" 1 (©) high pass iter with oa = rads 1 (©) low pass iter with ag = Fiavadls 1 (©) high pass fier with beo= TET AyGTas Hye [2012 : 2 Marks) 4.32 In the circult shown below what is the ouiput ‘voltage (V,,)ifa/slicon transistor @and an ideal ‘op-amp are used? Bs (@) -15V (07 (+07v () +15V TT] {2019 : 4 Mark] © “ay pev 4.33 Inthe circuit shown below the op-amps are ideal. Then Vain vor 8 yo tio i oY ois 2 P>> a | “pe a © —9 how nv vn = 1a! Tav (2011: + Mark) wa we on (@) 10 [2013 : 2 Marks)4.34 Given that the op-ampsin the figure are ideal, the output voltage Vis ar Me (a) (Y,~¥4) 2(y-%) w@ 4s) Zl (iyevy [2014 2 Marks, Set-1] 4.35 In the figure shown, assume the op-amp to be ideal. Which of the alternatives gives the correct Yoo) Bode plots for the transfer function ig) ? vs ) behea. soli © beet “| . / [2014 : 2 Marks, Set-1] @ gag 4.36 An operational amplifier circults is shown in the figure. Ry ‘The output of the crcut for a given input vis © (+B @ -( 2) (+R) 4.97 The transfer characteristic of the op-amp circuit shown in figure is (OV OV Pe A Re R [2014 : 1 Mark, Set-3]| — } oO T o i [2014 : 2 Marks, Set-3] 4.38 Consider the circuit shown in the figure. In this, circuit A= 1 KA, and C= 1 wF The input voltage is sinusoidal with a frequency of 50 Hz, represented as a phasor with magnitude V, and phase angle 0 radian as shown in the figure. The output voltage Is represented as a phasor with magnitude V, and phase angle 8 radian. What is the value of the output phase angle 6 (in radian) ‘elative to the phase engle of the input voltage? oe wo we (o) we (8) -W2 [2018 : 1 Mark, Sot-1], ‘4.39 The op-emp shown in the figure has a finte gain ‘A= 1000 and an infinite input resistance. A step- voltage V, = 1 mV is appliod at the input at time ‘0 as shown, Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage Vis (a) 1001 © 10 tt @4 [2018 : 2 Marks, Set-1] 4.40 The operational amplifier shown in the figure is Ideal, The input voltage (in Volt) is Vj=2sin(2x x 20000. The amplitude of the output voltage V,fin Vol) is _ [2015 : 1 Mark, Set-2) 4.41 The filters F1 and F2 having characteristics as ‘shown in figure (a) and (b) are connected as shown in figure (c). DXA, fry a — f 7‘The cutoff frequencies of F1 and F2are f,and , 4.45 For the circuit shown below, taking the opamp as respectively If < f, the resultant circuit exhibits, idea, the output votage V, in terms of he input the characteristic ofa voltages ¥, V, and V, is (@) Band-passtiter (6) Bandt-stop fiter ae (©) Allpass titer (@) High-@iiter [2015 : 1 Mark, Set-2) ae Yee 4.42 The saturation voltage of the ideal op-amp shown A cae aaa below is 210 V. The output voltage Vy of the prea c Yn folowing circut in he steady state 49 ¢ ia yo o. (@) 18, +72V,-Vy wey () 24,+8%-9\%, (©) 72V,+18V,-V, > —en (@ eV,+2v,-9% (“a3 i (2018: 2 Marks, Set2} 4.48 The approximate transfer characteristic for the a circuit shown below with an ideal operational amplifier and diode wil be oar (a) square wave of period 0.55 ms (0) triangular wave of period 0.55 ms (6) square wave of period 0.25 ms (2) triangular wave of period 0.25 me [2015 : 2 Marks, Set-2] 4.43 Otthe four characteristics given below, which are the major requirements for an instrumentation ampliior? P._ High common mode rejection ratio @ Q. Highinputimpedance iaiiauiatal eines R. Hightinearty S._ High outputimpedance (8) P.Qand Ronly (b) Pand R only (©) P.QandSonly (d) Q,RandS only [2015 : 1 Mark, Sot-1] 4.44 The circuit shown below is an example of a [2017 : 2 Marks, Set-1] = 4.47 For the circuit shown below, assume that the (@) low passtiter_(b) band pass fiter OPAMP is ideal. Which one of the following is (© high pass iter (4) notch fiter TRUE?5 2% o 28 w -2% Fy © Zz @ 24 Pe (au'8 1 Mark) 4.49 Inthe cicut below, the operational aor t ideal; = TO mV and Y= 80 nV he output vetiage (is @) %e=5v, 100 se [2017 : 2 Marks, Set-2) 101m 4.48, Thep-amp showin he Hgureis dea. The input is Impedance Vee hen adance ¥/,© glven By = sora “ (@) 400mV——() S00mV (©) eoomy =) 100mv + [2010 : 2 Marks} . EXINIIZ operational Amplifiers 41 943 (1) 45 @) 46 @ 47 © 49 ( 4101) 4110) 4120 4.139 (cd) 4.14 (b) 4.15 (6) 4.16 (0) 4.17 (d) 4.18 (a) 4.19 (5) 4.20) 4.21 (b) 4.22 (c) 4.23 (d) 4.24 (bo) 4.25(d) 4.26 (cd) 4.27 (d) 4.28 (b) 4.29 (d) 4.30 (d) 4.31 (b) 4.32 (0) 4.33 (©) 4.34(b) 4.35 (a) 4.36 (d) 4.37 (c) 4.38 (4) 4.39 (d) 4.40 (1.245) 441 (0) 4.42(a) 4.43 (2) 4.44 (a) 4.45 (dc) 4.46 (a) 4.47 (c) 4.48 (b) 4.49 (a)Oscillators and Feedback Amplifiers 6.1 Ina common emitter ampilir, the unbypassed ‘emitter resistance provides (a) voltage-shunt feedback (0) current-series feedback (6) negative-voltage feedback (@) positive-current feedback [1992 : 1 Mark] 5.2 AWein bridge oscillator is shown in figure. Which of the following statements are true, iff is the frequency of oscilation? tea, C= Lr f= 1H (©) For 1 akac-1, C= TF, (©) The gainof the op-amp stage should be less than two for proper operation. (@) The gain of op-amp should be three for proper operation. [1993 : 1 Mark] 5.3 Given figure shows a two stage small signal transistor feedback amplifier Match the defectve component (listed on the left hand side below) with its probable effect on the circuit (sted on the right nand side), 5.4 85 56 ust Capacitor ©, is open Capacitor C; is open Capacitor C, is open goo Fo, is shorted stl Allde vetages normal, Vjincrease marginally. Collector of TR, at Ve. Vo All de voltages normal, gain of 2% stage decrease V, decrease. 8. Alldde voltage normal, Vo = 0. T. All de voltage normal, overall gain of the amplifier increases, V,increase. U. Nochange por [1994 : 1 Mark] A practical AC sinusoidal oscillator is built using 2 positive feedback amplifier witha closed loop gain slightly less than unity. TruefFalse) [1994 : 1 Mark] ‘An op-amp has an open-loop gain of 10° and an open loop upper cut-off frequency of 10 Hz. If this op-amp is connected ae an ampiitior with a closed loop gain af 100, then the new upper cut off frequency is (@) 10H (©) 100H2 (6) 10kHz (6) 100KH2 [2001 : 1 Mark] For the oscillator circuit shown in figure, the ‘expression forthe time period of oscillations can bbe given by (whore «87 58 59 @ ting (b) 2rin3 © tin2 (a) 2tin2 [2001 : 2 Marks) ‘The output voltage (V,) of the schit tigger shown ln figure swings between +15 V and -15V, Assume that the operational ampifier is ideal. The output will change from +15 V to ~15 V when the instantaneous value of the input sine wave is, 00K V,= 10sinato Ye 10x 2ka (a) 5 Vin the positive slope only. (©) 5 Vin the negative slope only {(¢) 5 Vin the postive and nogative slopes. (@) 3V in the positive and negative slopes. [2002 : 2 Marks} ‘The feedback used in the circuit shown in figure can be classified as (a) shunt-series feedback (©) shunt-shunt feedback {c) series-shunt feedback (G) series-sories teodback [2004 : 1 Mark} The typical frequency response of a two-stage direct coupled voltage amplifier is as shown in (@) sain Frequency (team Frequency (©) {ai aaa Freeney (0) (Gein Frequency [2008 : 2 Marks) 5.10 In the feedback network shown below, if the feedback factor kis increased, then a Vou (@) the input impedance increases and output impedance decreases, (©) the input impedance increases and output impedance also increases. (c) the input impedance decreases and output impedance also decreases. (@) the input impedance decreases and output impedance increases. [2013 : 1 Mark) 5.11 Inthe Wien Bridge oscillator circuit shown in igure, the bridge is balanced when@ BF o B-& © B-8.2 ope ROR FRGRG [2014 : 1 Mark, Sot-1) 5.12 Anoecilator cxcuit using dea op-amp and diodes fg shown in the figure ww J i [EERIE ocittators and Feedback Amplifiers 5.1 &) 62 WRG 54 55 (© 6.13 6.14 56 “The time duration for +ve part ofthe cycle is At, and for-ve partis Alp, The value of © 7 wil be. [2014 : 2 Marks, Set-2] Anhysteresie type TTL inverter is used to realize ‘an ogcilatorn the circuit shown in the igure. wey It the lower and upper trigger level voltages are (0.9V and 1.7, the period (in ms), for which output is LOW, is [2014 : 2 Marks, Set-3} A current controlled current source (CCCS) has ‘aninput impedance of 10Aand output impedance ‘f 100 KO When this CCS is used in a negative feedback closed loop with a loop gain of 9, the closed loop cutput impedance is (@ 109 () 100k (©) 1000ka. (@ 10a [2010 : 1 Mark} ©) 57 @ 58 &) 59 ©) 5.10 (a) 6.11 (6) 5.12 (08) 5.13 (063)5.14 (©)Miscellaneous 61 The circuit of figure shows a §65 Timer IC connected as an astable mutivibrator. The value of the capacitor C is 10 nF. The values of the resistors Rand Aator a frequency of 10kHzand a duly cycle of 0.75 for the output voltage waveform are Re e: ¥ (@) Ry 962k, Ry = 362K 3.62 KO, Ay =7.25 KO 7.2540, Ry = 362K0 (8) Ry= 72540, Ry = 72540 [2003 : 2 Marks] 6.2" In the Schmitt vigger circuit shown in figure, if Voeay = 021 V, the outputlogic tow lvel (Ves (@ 125 ©) (©) 2504 1.35V (@ 500Vv [2004 : 2 Marks} es" a4 The input signal ¥, shown in the figure is a1 kHz square wave voltage that alternates between +7 V ‘and ~7 V with a 60% duty cycle. Both transistors have the same current gain. which is large. The Circuit detivers power tothe load resistor R. What le the efficioney ofthis eicuit for the given input? choose the closest answer. sv -wvs = @) 16% tb) 55% © 60% (@) 92% [2007 : 2 Marks} IC 555 in the figure is configured as an astable rmultwibrator. It is enabled to oscilate at '= 0 by applying ahigh input to pin 4. The pin des |: 1 and8~supply;24rigger; 4-reset; 6-threshold T-discharge. The waveform appearing across the capacitor starting from f= 0, as observed on a storage CRO is 10%|65 66 ©) ) [2007 : 2 Marks} ‘The truth able of a maneshot shown nthe figures is given in the table below. ‘Two monoshots, one positive edge triggered and ther negative edge triggered, are connected ‘shown in the figure. The pulse widths of the two ‘monoshot outputs, Q, and Q, are and Toy, and Toye respectively. py x[y [eye off injar| **] Be Theta) ved i “Tme(s) ° 100 200300400 evel) ‘The element connected between a and b could te (2) «—pt—b © —4-— ‘The trequency and the duty cycle ofthe signal at Q, will respectively be 1 Tom ne Tox Tas Tex tg it 4 Tore. OT Ta Tay 0” Tay Toe (©) f= @e [2008 : 2 Marks] The following circuit has a source voltage V, as showin the graph. The current through the citcut i also shown, eee g rEma 7 (© s—t¢-—» @ 7 “Two monashot multvbrator, one positive edge triggered (M,) and another negative edge triggered (Mare connected as shownin gute [2009 : 1 Mark) “sv 10a: oa ‘Themoroshots M, and M, when tiggered produce pulses of width T, and T, respectively, where T, > Tp: The steady state output voltage V, of the circuits =@ © vo 6 ® | cy [2014 : 2 Marks Not in the GATE-2018 syllabus. Miscellaneous ‘ 61 ©) 62 &) 63 () 64 @) 65 (@) 66 (@) 67 ()