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CTS Assignment

This document contains questions about clock tree synthesis (CTS) and clock routing. It asks about inputs and outputs of CTS, clock skew, buffer vs clock buffer characteristics, metal layers used for clock routing, impacts of setup and hold violations, differentiating global and local skew, maximum frequency calculation for a sample design, and running two CTS experiments varying buffer types and routing rules to capture metrics.

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Sachin Singh
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63 views3 pages

CTS Assignment

This document contains questions about clock tree synthesis (CTS) and clock routing. It asks about inputs and outputs of CTS, clock skew, buffer vs clock buffer characteristics, metal layers used for clock routing, impacts of setup and hold violations, differentiating global and local skew, maximum frequency calculation for a sample design, and running two CTS experiments varying buffer types and routing rules to capture metrics.

Uploaded by

Sachin Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Answer below questions in 1-2 sentences

1) What is CTS? Explain clock behavior before-CTS and after-CTS?


2) What are the inputs to CTS step?
3) What is Insertion Delay or latency of clock tree?
4) What is clock-skew. How does skew impact timing?
5) How do you pick clock slew/transition target for the clock tree in your design.
6) What is the difference between normal buffer and clock buffer?
7) Which metal layers in a given metal stack are used for clock routing and Why?
8) Suppose you missed fixing a setup violation and found it post silicon. What is the impact. What would you want to do
now.
9) Suppose you missed fixing a hold violation and found it post silicon. What is the impact. What would you want to do
now.
10) Why don't we perform Hold analysis before CTS?
11) Differentiate b/w global and local skews
12) Assume that we time a design for setup and hold with clock period defined as 1ns and see setup and hold WNS of
+200 ps and +150 ps respectively for a single cycle timing path(not multicycle path or half-cycle path). Now if the SDC is
updated such that the new clock frequency is 1.5GHz and then if the design is timed again, what are the new setup and
hold WNS you would see in the design.
13) Note the below design with 3 flipflops. Consider propagated clock and answer the questions below. Clock tree is
denoted using green colored lines.
Assume the following
input delay on input port IN1 = 250 ps
input delay on input port IN2 = 800 ps
output delay on output port OUT = 250 ps
C1 is combinational delay = 50 ps
C2 is combinational delay = 250 ps
CLK Setup time of FF1 = 250 ps & Hold time of FF1 = 300 ps
A

B
Setup time of FF2 = 250 ps & Hold time of FF2 = 300 ps
Setup time of FF3 = 250 ps & Hold time of FF3 = 300 ps
CK-Q delay of FF1 = 250 ps
CK-Q delay of FF2 = 250 ps
CK-Q delay of FF3 = 250 ps
Delay of clock buffer chain “A” = 600 ps
Delay of clock buffer chain “B” = 50ps

Question 1 : What is the maximum frequency this design can operate at ?


Question 2 : Given that the clock frequency is set to 1GHz, What is the setup WNS of this design?
Question 3 : Does this design have any hold violations. If yes, how many hold violations ? what is the worst hold
slack ?
Question 14 : Please find the lab assignment details below. You will have to do 2 different CTS experiments(Only clock tree synthesis
and clock routing to be done. No timing optimization to be done) using the placed database you used in your lab and capture output
reports in the attached excel book. For each of the experiments, use M5 & M6 as clock routing layers. Clock cells to be used in each
case/experiment are given below.

Case 1 : Use only clock INVERTER cells with all drive strengths and route the clock tree with double width and double spacing routing
rules
Case 2 : Use only clock BUFFER cells with all drive strengths and route the clock tree with double width and triple spacing routing
rules

You will be running 2 different runs. Capture the following metrics from each run

• Inst Count

• Buf/Inv Count

• Congestion number post Clock routing

• Insertion Delay

• Skew

• Clock-Cell Count

• No.of Levels in the clock tree

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