EVALUATION KIT AVAILABLE

MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

General Description Benefits and Features

The MAX14920/MAX14921 battery measurement analog S High Accuracy
front-end devices accurately sample cell voltages and  ±0.5mV (max) Cell Voltage Error
provide level shifting for primary/secondary battery packs  Simultaneous Cell Voltage Sampling
up to 16 cells/+65V (max). The MAX14920 monitors up
 Self-Calibration
to 12 cells, while the MAX14921 monitors up to 16 cells.
Both devices simultaneously sample all cell voltages, S Integrated Diagnostics
allowing accurate state-of-charge and source-resistance  Open-Wire and Short Fault Detection
determination. All cell voltages are level shifted to ground  Undervoltage/Overvoltage Warning
reference with unity gain, simplifying external ADC data
 Thermal Shutdown
conversion.
S High Flexibility
The devices have a low-noise, low-offset amplifier that
buffers differential voltages of up to +5V, allowing moni- SPI Interface

toring of all common lithium-ion (Li+) cell technologies. 12-Cell and 16-Cell Versions

The resulting cell voltage error is Q0.5mV. +6V Minimum (3 Cells) Operation

The devices’ high accuracy make them ideal for monitoring +0.5V to +4.5V Cell Voltage Range

cell chemistries with very flat discharge curves, such as Integrated Cell-Balancing FET Drivers

lithium-metal phosphate. Integrated 5V LDO

Passive-cell balancing is supported by external FET S Low Power
drivers. Integrated diagnostics in the devices allow
 1µA Shutdown Mode
open-wire detection and undervoltage/overvoltage
alarms. The devices are controlled by a daisy-chainable  1µA/10µA Cell Current Draw
SPI interface.
The MAX14920 is available in a 64-pin (10mm x 10mm)
TQFP package with an exposed pad. The MAX14921 is Ordering Information appears at end of data sheet.
available in an 80-pin (12mm x 12mm) TQFP package.
Both devices are specified over the -40°C to +85°C Functional Diagram appears at end of data sheet.
extended temperature range.

Applications
Industrial Battery Backup Systems
Telecom Battery Backup Systems
Energy Storage Packs
e-Transportation Energy Packs

For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6496; Rev 3; 3/15
 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to AGND.) (MAX14921 only)........................-0.3V to (VCV(m** - 1) + 0.3V)
VP ..........................................................................-0.3V to +70V BA1.......................................................... -0.3V to (VCV1 + 0.3V)
LDOIN ............................................... (VA - 0.3V) to (VP + 0.3V) BA2–BA12......(VCV(n* - 1) - 0.3V) to min((VCVn* + 0.3V) or +6V)
VA ............................................................................-0.3V to +6V BA2–BA16 (MAX14921 only).............(VCV(m** - 1) - 0.3V) to min
VL .........................................................................-0.3V to +5.5V .((VCVm** + 0.3V) or +6V)
CV0, DGND...........................................................-0.3V to +0.3V AOUT, T1, T2, T3......................................... -0.3V to (VA + 0.3V)
SCLK, SDI, CS, EN...................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
SDO, SAMPL................................................ -0.3V to (VL + 0.3V) 64-Pin TQFP-EP (derate 31.3mW/°C above +70°C)...2508mW
CV1...........................................................................-0.3V to +6V 80-Pin TQFP (derate 23.3mW/°C above +70°C).........1860mW
CV2–CV12..............................(VCV(n* - 1) - 0.3V) to (VP + 0.3V) Operating Temperature Range........................... -40NC to +85°C
CT1–CT12..................................... -0.3V to (VCV1–VCV12 + 0.3V) Maximum Junction Temperature......................................+150°C
CB2–CB12........................................ -0.3V to (VCV(n* - 1) + 0.3V) Storage Temperature Range............................. -65NC to +150°C
CV2–CV16 Lead Temperature (soldering, 10s).................................+300°C
(MAX14921 only)............... (VCV(m** - 1) - 0.3V) to (VP + 0.3V) Soldering Temperature (reflow).......................................+260°C
CT1–CT16 *n = 2–12
(MAX14921 only).......................-0.3V to (VCV1–VCV16 + 0.3V) **m = 2–16
CB2–CB16

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

Junction-to-Ambient Thermal Resistance (qJA) Junction-to-Case Thermal Resistance (qJC)
64-Pin TQFP-EP..........................................................31.9°C/W 64-Pin TQFP-EP...............................................................1°C/W
80-Pin TQFP...................................................................43°C/W 80-Pin TQFP.....................................................................8°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

DC ELECTRICAL CHARACTERISTICS
(VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES
VP Supply Voltage VP +6 +65 V
IP_OFF EN = low or LOPW = 1 1
VP Supply Current FA
IP_ON EN = high 65 150
LDOIN Supply Voltage VLDOIN +6 +65 V
ILDOIN_OFF EN = low, IA = 0A 75 125
LDOIN Supply Current FA
ILDOIN_ON EN = high, IA = 0A 350 500
VA Analog Supply Voltage VA VA supply externally, VA = VLDOIN +4.75 +5 +5.25 V
IA_OFF EN = low, VA = VLDOIN 50 75
VA Analog Supply Current FA
IA_ON EN = high, VA = VLDOIN 350 450
VL Supply Voltage VL +1.62 +5.5 V
All logic inputs static, held at logic-low
VL Supply Current IL 2.5 5 FA
or logic-high

Maxim Integrated   2

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

DC ELECTRICAL CHARACTERISTICS (continued)
(VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VP UVLO UV_VPVTH VP rising +6 V
UVLO Hysteresis UV_VPHYST 200 mV
LDOIN UVLO UV_LDOINVT VLDOIN rising +5.25 +6 V
VA UVLO UV_VAVTH VA rising +4.7 V
VL UVLO UV_VLVTH VL rising +1.6 V
LDO Output Voltage VA_LDO_OUT 0 < ILOAD < 10mA +4.75 +5 +5.25 V
ANALOG INPUTS (T1, T2, T3)
Input Signal Range VT Reference to AGND 0 VA V
On-Resistance RONA 200 I
T_ route to buffer amplifier -1 +1
Input Leakage Current IT_LEAK FA
T_ route to AOUT -1 +1
CAPACITOR INPUTS (CT_)
Capacitor Discharge Current ILT_ Hold phase, SAMPL = low -1 +1 FA
ANALOG INPUTS (CV_)
Differential Input Signal Range
VDn VCVn – VCVn-1 (Note 3) +0.5 +4.5 V
for Guaranteed Accuracy
CV1 Input Voltage Range VCV1 0 +5 V
CV2–CV12 Input Voltage Range
VCVn n ≥ 2, VCVn ≥ VCVn-1 (Note 3) +1.5 +65 V
(MAX14920)
CV2–CV16 Input Voltage Range
VCVm m ≥ 2, VCVm ≥ VCVm-1 (Note 3) +1.5 +65 V
(MAX14921)
ILS_ During sampling phase -1 +1
ILH_ During holding phase -1 +10
Input Leakage Current FA
ILC_ During calibration -1 +10
ILD_ During diagnostics, DIAG = 1 10
BA_ active, VCVn - VCVn-1 = +4.5V
Balancing Input Current ILB_ 6.5 12 mA
(Note 3)
VCVn > +2V, ISINK = 2mA (Note 3) 80 150
RSAMPLE
VCVn > +1.5V, ISINK = 1mA (Note 3) 90
Sample Switch On-Resistance I
VCVn > +2V, ISINK = 2mA (Note 3)
RSWCAL 800 16,000
during charge injection error calibration
An undervoltage sets the associated SPI
Cell Undervoltage Threshold UV_VCVTH +1.4 +1.5 +1.6 V
Cn bit
An overvoltage sets the associated SPI
Cell Overvoltage Threshold OV_VCVTH VA V
Cn bit

Maxim Integrated   3

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

DC ELECTRICAL CHARACTERISTICS (continued)
(VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ANALOG OUTPUT (AOUT)
Output Signal Range VAOUT Reference to AGND +0.3 VA - 0.3 V
VAOUT = +3.3V, after self-calibration
Amplifier Offset Voltage VOFFSET Q50 Q100 FV
(Note 5)
Temperature Offset Drift If not recalibrated Q1.5 FV/°C
Gain A_V Gain = VAOUT/VD 1 V/V
Output Error VO_ERR (Note 4) -0.5 +0.5 mV
Amplifier Gain Error VGAIN_ERR ROUT = 100kI, VD = 2V to 4.5V (Note 6) -0.2 +0.2 mV
[SC0, SC1, SC2, SC3] MAX14920 VP/12
VP Monitor Voltage VPMON V
= [0, 0, 1, 1] MAX14921 VP/16
[SC0, SC1, SC2, SC3] =
VP Monitor Accuracy VPMONA -0.25 0 +2.5 %
[0, 0, 1, 1]
CHARGE-BALANCE DRIVERS (BA_)
IBA_ = 30µA, VCV(n) - VCV(n - 1) = +3.3V VCV(n - 1)
Output Low VBAL VCV(n - 1) V
(Note 3) + 0.9
IBA_ = -30µA, VCV(n) - VCV(n - 1) = +3.3V
Output High VBAH VCV(n) - 1.5 VCV(n) V
(Note 3)
Pulldown Resistance RPDWN 10.5 14.8 21.5 kI
LOGIC OUTPUT (SDO)
Output Low Voltage VOL ISINK = 10mA +0.4 V
Output High Voltage VOH ISOURCE = 0.5mA VL - 0.25 V
Output Leakage Current IL VCS = VL -1 +1 FA
LOGIC INPUTS (SDI, SCLK, EN, SAMPL)
VL < +2.3V 0.2 x VL
Input Low Voltage VIL V
+2.3V < VL < +5.5V 0.3 x VL
VL < +2.3V 0.8 x VL
Input High Voltage VHL V
+2.3V < VL < +5.5V 0.7 x VL
Input Leakage Current IL -1 +1 FA
DYNAMIC CHARACTERISTICS
Measured between channels with
AOUT Settling Time tSET +4V signal change. Settling to Q1mV 5 Fs
accuracy, CLOAD = 100pF (Figure 1)
CSAMPLE = 1FF, during charge injection
Sampling Time tSAMPL 40 ms
error calibration
Delay from SMPLB set to 1 or SAMPL
Holding Delay Time tHD 0.5 Fs
falling edge to holding of all cell voltages

Maxim Integrated   4

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

DC ELECTRICAL CHARACTERISTICS (continued)
(VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Delay from SMPLB set to 1 or SAMPL
Level-Shifting Delay Time tLS_DELAY falling edge to shifting of all cell voltages 25 50 Fs
to ground and available for reading
AOUT Voltage-Droop Time tDROOP Droop to -1mV (Figure 2) 1 ms
Measured between T_ input selection
T_ Settling Time tTS and AOUT settling to +1mV accuracy, 5 Fs
CLOAD = 100pF, SC2 = 1
T_ Turn-On Delay Time tTD 0.2 Fs
Measured between VP/12 (MAX14920),
VP/16 (MAX14921) input selection and
VP Settling Time tVPS 25 60 Fs
AOUT, settling to 2.5%,
CLOAD = 100pF, SC3 = 1
Self-Calibration Time 8 ms
THERMAL DETECTION
Thermal Shutdown +140 °C
Thermal-Shutdown Hysteresis 15 °C
SPI TIMINGS (Figure 3)
SDI to SCLK Setup tDS 50 ns
SDI to SCLK Hold tDH 12 ns
SCLK to SDO Valid tDO 100 ns
CS Fall to SDO Enable tDV 100 ns
CS Rise to SDO Disable tTR 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0 ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Note 4: Output error VO_ERR is the difference between the input cell difference voltage (VD = VCV(n) - VCV(n - 1)) and the
output voltage VAOUT. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli-
fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output
error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the
Measurement Accuracy section for a detailed explanation).
Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after
power-up phase, it is suggested to run self-calibration on a regular basis to get best performance
(see the Buffer Amplifier Offset Calibration section for a detailed explanation).
Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error.

Maxim Integrated   5

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Timing Diagrams
tSET

CS

SCLK

SDI C1 C2 C3 C4 C16 T1 T2 T3 OT

AOUT

0V
*n = 1–12 (MAX14920) AND n = 1–16 (MAX14921)

Figure 1. AOUT Delay from SPI Select

tDROOP tSAMPL

SAMPL

VCVn*
1mV

AOUT

*n = 1–12 (MAX14920) and n = 1–16 (MAX14921)

Figure 2. AOUT Voltage-Droop Time

CS

tCSS tCH tCSH

tCL

SCLK

tDS
tDH

SDI

tDO tTR
tDV

SDO

Figure 3. SPI Timing

Maxim Integrated   6

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Typical Operating Characteristics

(VCVn - VCV(n - 1) = +3.3V (where n = 1–12 (MAX14920) and n = 1–16 (MAX14921)), TA = +25°C, unless otherwise noted.)

LDO OUTPUT VOLTAGE CHANGE

IP vs. VP IP vs. TEMPERATURE vs. LOAD CURRENT
60 60 0.5
MAX14920 toc01

MAX14920 toc02

MAX14920 toc03
SAMPLE MODE SAMPLE MODE VP = 10V
LDO DISABLED LDO DISABLED 0.4
50 50

CHANGE IN OUTPUT VOLTAGE (%)

0.3
0.2
40 40
TA = +85°C 0.1
TA = +25°C VP = 65V VP = 24V VP = 6V
IP (µA)

IP (µA)

30 TA = -40°C 30 0
-0.1
20 20
-0.2
-0.3
10 10
-0.4
0 0 -0.5
5 25 45 65 -40 -15 10 35 60 85 0 2 4 6 8 10
VP (V) TA (°C) IOUT (mA)

VAOUT SETTLING TIME VAOUT DROOP TIME

VOLTAGE ERROR vs. CELL VOLTAGE vs. TEMPERATURE vs. TEMPERATURE
0.4 6 5.0
MAX14920 toc05

MAX14920 toc06
MAX14920 toc04

VCVn-1 = 40V
4.5
0.3
5
4.0
VAOUT SETTLING TIME (µs)

0.2
VAOUT DROOP TIME (ms)

3.5
4
0.1 3.0
ERROR (mV)

VCVn-1 = 60V VCVn-1 = 20V

0 3 2.5
2.0
-0.1 VCVn-1 = 0V 2
1.5
-0.2 VCVn - VCVn-1 = 1.5V
VP = 24V 1.0 CSAMPLE = 1µF
1
-0.3 SETTLE TO 1mV 0.5 VCVn - VCVn-1 = 1.5V
tSAMPLE = 4ms VP = 24V
-0.4 0 0
0.5 1.5 2.5 3.5 4.5 -40 -15 10 35 60 85 -40 -15 10 35 60 85
CELL VOLTAGE (V) TA (°C) TA (°C)

VL SUPPLY CURRENT
T_ ON-RESISTANCE vs. VT_ VBAn - VCVn-1 vs. IBAn vs. TEMPERATURE
200 3.5 5.0
MAX14920 toc07

MAX14920 toc08

MAX14920 toc09

SAMPL = VL
180 4.5
3.0
160 4.0
VL SUPPLY CURRENT (µA)

2.5 VOH VL = 5V
140 3.5
VBAn - VCVn-1 (V)

120 3.0
2.0
RON (I)

100 2.5 VL = 3.3V

1.5
80 2.0
60 1.0 1.5 VL = 1.8V
40 1.0
0.5
20 IT_ = 0.1mA VCVn - VCVn-1 = 3.3V 0.5
0 0 0
0 1 2 3 4 5 0 1 2 3 4 5 -40 -15 10 35 60 85
VT_ (V) IBAn (mA) TA (°C)

Maxim Integrated   7

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Configurations

TOP VIEW

CV4
CB5

CV5
CB6

CV6
CB7

CV7
CB8
BA4

CT5
BA5

CT6
BA6

CT7

CT8
BA7
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

CT4 49 32 BA8
CB4 50 31 CV8
CV3 51 30 CB9
BA3 52 29 CT9
CT3 53 28 BA9
CB3 54 27 CV9
CV2 55 26 CB10
BA2 56 MAX14920 25 CT10
CT2 57 24 BA10
CB2 58 23 CV10
CV1 59 22 CB11
BA1 60 21 CT11
CT1 61 20 BA11
CV0 62 *EP 19 CV11
EN 63 18 CB12
CS 64 + 17 CT12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK
SDI
SDO
SAMPL
VL
DGND
T3
T2
T1
AOUT
AGND
VA
LDOIN
VP
CV12
BA12

64 TQFP-EP
(10mm x 10mm)
*CONNECT EP TO GND

Maxim Integrated   8

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Configurations (continued)

TOP VIEW

CB10
CT10
CV5
CB6

CV6
CB7

CV7
CB8

CV8
CB9

CV9
BA5

CT6
BA6

CT7
BA7

CT8
BA8

CT9
BA9
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

CT5 61 40 BA10
CB5 62 39 CV10
CV4 63 38 CB11
BA4 64 37 CT11
CT4 65 36 BA11
CB4 66 35 CV11
CV3 67 34 CB12
BA3 68 33 CT12
CT3 69 32 BA12
CB3 70 MAX14921 31 CV12
CV2 71 30 CB13
BA2 72 29 CT13
CT2 73 28 BA13
CB2 74 27 CV13
CV1 75 26 CB14
BA1 76 25 CT14
CT1 77 24 BA14
CV0 78 23 CV14
EN 79 22 CB15
CS 80 21 CT15
+

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SCLK
SDI
SDO
SAMPL
VL
DGND
T3
T2
T1
AOUT
AGND
VA
LDOIN
VP
CV16
BA16
CT16
CB16
CV15
BA15

80 TQFP
(12mm x 12mm)

Maxim Integrated   9

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Description

PIN
MAX14920 MAX14921 NAME FUNCTION
(64 TQFP-EP) (80 TQFP)
1 1 SCLK SPI Clock Input
2 2 SDI SPI Data Line Input
3 3 SDO SPI Data Line Output
Sample Control Input. Voltages at CV_ inputs are tracked when SAMPL is logic-
4 4 SAMPL high. When SAMPL transitions from high to low, the differential voltages on CV_ are
held internally and made ready for readout at the AOUT output.
Logic Supply Input. Bypass VL to DGND with a 0.1FF capacitor as close as
5 5 VL
possible to the device.
6 6 DGND Digital Ground
Single-Ended Voltage Input. T3 can be connected to a temperature sensor or other
7 7 T3
analog voltage.
Single-Ended Voltage Input. T2 can be connected to a temperature sensor or other
8 8 T2
analog voltage.
Single-Ended Voltage Input. T1 can be connected to a temperature sensor or other
9 9 T1
analog voltage.
10 10 AOUT Buffered Amplifier Output. The AOUT output voltage is relative to CV0.
Analog Ground. AGND is a low-noise ground. Connect CV0 to AGND. Connect
11 11 AGND
DGND to AGND.
+5V LDO Output. Bypass VA to AGND with a 1FF capacitor as close as possible to
12 12 VA
the device.
+5V LDO Power Supply. Connect LDOIN to VP to enable the LDO. Connect LDOIN
13 13 LDOIN
to VA to disable the LDO and use an external +5V supply.
Power Supply. Connect to the highest voltage of the battery cell stack. Bypass VP to
14 14 VP
AGND with a 0.1FF capacitor as close as possible to the device.
Cell Voltage Input 12. Connect CV12 to cell anode/cathode. Connect CV12 to the
15 31 CV12
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 12. Connect BA12 to the gate of the external
16 32 BA12
n-channel FET. Leave BA12 unconnected if not used.
Sampling Capacitor 12 High Terminal. CT12 internally connects to CV12 when
17 33 CT12 SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave
CT12 unconnected if not used.
Sampling Capacitor 12 Low Terminal. CB12 internally connects to CV11 when
18 34 CB12 SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave
CB12 unconnected if not used.
Cell Voltage Input 11. Connect CV11 to cell anode/cathode. Connect CV12 to the
19 35 CV11
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 11. Connect BA11 to the gate of the external
20 36 BA11
n-channel FET. Leave BA11 unconnected if not used.

Maxim Integrated   10

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Description (continued)

PIN
MAX14920 MAX14921 NAME FUNCTION
(64 TQFP-EP) (80 TQFP)
Sampling Capacitor 11 High Terminal. CT11 internally connects to CV11 when
21 37 CT11 SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave
CT11 unconnected if not used.
Sampling Capacitor 11 Low Terminal. CB11 internally connects to CV10 when
22 38 CB11 SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave
CB11 unconnected if not used.
Cell Voltage Input 10. Connect CV10 to cell anode/cathode. Connect CV10 to the
23 39 CV10
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 10. Connect BA10 to the gate of the external
24 40 BA10
n-channel FET. Leave BA10 unconnected if not used.
Sampling Capacitor 10 High Terminal. CT10 internally connects to CV10 when
25 41 CT10 SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave
CT10 unconnected if not used.
Sampling Capacitor 10 Low Terminal. CB10 internally connects to CV9 when
26 42 CB10 SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave
CB10 unconnected if not used.
Cell Voltage Input 9. Connect CV9 to cell anode/cathode. Connect CV9 to the
27 43 CV9
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 9. Connect BA9 to the gate of the external
28 44 BA9
n-channel FET. Leave BA9 unconnected if not used.
Sampling Capacitor 9 High Terminal. CT9 internally connects to CV9 when
29 45 CT9 SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CT9
unconnected if not used.
Sampling Capacitor 9 Low Terminal. CB9 internally connects to CV8 when
30 46 CB9 SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CB9
unconnected if not used.
Cell Voltage Input 8. Connect CV8 to cell anode/cathode. Connect CV8 to the
31 47 CV8
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 8. Connect BA8 to the gate of the external
32 48 BA8
n-channel FET. Leave BA8 unconnected if not used.
Sampling Capacitor 8 High Terminal. CT8 internally connects to CV8 when
33 49 CT8 SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CT8
unconnected if not used.
Sampling Capacitor 8 Low Terminal. CB8 internally connects to CV7 when
34 50 CB8 SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CB8
unconnected if not used.
Cell Voltage Input 7. Connect CV7 to cell anode/cathode. Connect CV7 to the
35 51 CV7
highest voltage of the battery cell stack if not used.

Maxim Integrated   11

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Description (continued)

PIN
MAX14920 MAX14921 NAME FUNCTION
(64 TQFP-EP) (80 TQFP)
Cell-Balancing Gate Driver Output 7. Connect BA7 to the gate of the external
36 52 BA7
n-channel FET. Leave BA7 unconnected if not used.
Sampling Capacitor 7 High Terminal. CT7 internally connects to CV7 when
37 53 CT7 SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CT7
unconnected if not used.
Sampling Capacitor 7 Low Terminal. CB7 internally connects to CV6 when
38 54 CB7 SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CB7
unconnected if not used.
Cell Voltage Input 6. Connect CV6 to cell anode/cathode. Connect CV6 to the
39 55 CV6
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 6. Connect BA6 to the gate of the external
40 56 BA6
n-channel FET. Leave BA6 unconnected if not used.
Sampling Capacitor 6 High Terminal. CT6 internally connects to CV6 when
41 57 CT6 SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CT6
unconnected if not used.
Sampling Capacitor 6 Low Terminal. CB6 internally connects to CV7 when
42 58 CB6 SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CB6
unconnected if not used.
Cell Voltage Input 5. Connect CV5 to cell anode/cathode. Connect CV5 to the
43 59 CV5
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 5. Connect BA5 to the gate of the external
44 60 BA5
n-channel FET. Leave BA5 unconnected if not used.
Sampling Capacitor 5 High Terminal. CT5 internally connects to CV5 when
45 61 CT5 SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CT5
unconnected if not used.
Sampling Capacitor 5 Low Terminal. CB5 internally connects to CV4 when
46 62 CB5 SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CB5
unconnected if not used.
Cell Voltage Input 4. Connect CV4 to cell anode/cathode. Connect CV4 to the
47 63 CV4
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 4. Connect BA4 to the gate of the external
48 64 BA4
n-channel FET. Leave BA4 unconnected if not used.
Sampling Capacitor 4 High Terminal. CT4 internally connects to CV4 when
49 65 CT4 SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CT4
unconnected if not used.
Sampling Capacitor 4 Low Terminal. CB4 internally connects to CV3 when
50 66 CB4 SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CB4
unconnected if not used.

Maxim Integrated   12

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Description (continued)

PIN
MAX14920 MAX14921 NAME FUNCTION
(64 TQFP-EP) (80 TQFP)
Cell Voltage Input 3. Connect CV3 to cell anode/cathode. Connect CV3 to the
51 67 CV3
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 3. Connect BA3 to the gate of the external
52 68 BA3
n-channel FET. Leave BA3 unconnected if not used.
Sampling Capacitor 3 High Terminal. CT3 internally connects to CV3 when
53 69 CT3 SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CT3
unconnected if not used.
Sampling Capacitor 3 Low Terminal. CB3 internally connects to CV2 when
54 70 CB3 SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CB3
unconnected if not used.
Cell Voltage Input 2. Connect CV2 to cell anode/cathode. Connect CV2 to the
55 71 CV2
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 2. Connect BA2 to the gate of the external
56 72 BA2
n-channel FET. Leave BA2 unconnected if not used.
Sampling Capacitor 2 High Terminal. CT2 internally connects to CV2 when
57 73 CT2 SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CT2
unconnected if not used.
Sampling Capacitor 2 Low Terminal. CB2 internally connects to CV1 when
58 74 CB2 SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CB2
unconnected if not used.
59 75 CV1 Cell Voltage Input 1. Connect CV1 to cell anode/cathode.
Cell-Balancing Gate Driver Output 1. Connect BA1 to the gate of the external
60 76 BA1
n-channel FET. Leave BA1 unconnected if not used.
Sampling Capacitor Connection 1 High Terminal. CT1 internally connects to CV1
61 77 CT1 when SAMPL is logic-high. Connect a 1FF capacitor between CT1 and CV0.
Leave CT1 unconnected if not used.
62 78 CV0 Cell Voltage Input 0. Connect CV0 to AGND.
Enable Input. Drive EN low to put the device into shutdown mode and reset the SPI
63 79 EN registers. The +5V LDO remains active in the shutdown mode. Drive EN high for
normal operation.
64 80 CS SPI Chip-Select Input. Active low.
Cell Voltage Input 16. Connect CV16 to cell anode/cathode. Connect CV16 to the
— 15 CV16
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 16. Connect BA16 to the gate of the external
— 16 BA16
n-channel FET. Leave BA16 unconnected if not used.
Sampling Capacitor Connection 16 High Terminal. CT16 internally connects to
— 17 CT16 CV16 when SAMPL is logic-high. Connect a1FF capacitor between CT16 and CB16.
Leave CT16 unconnected if not used.

Maxim Integrated   13

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Pin Description (continued)

PIN
MAX14920 MAX14921 NAME FUNCTION
(64 TQFP-EP) (80 TQFP)
Sampling Capacitor Connection 16 Low Terminal. CB16 internally connects to CV15
— 18 CB16 when SAMPL is logic-high. Connect a 1FF capacitor between CT16 and CB16. Leave
CB16 unconnected if not used.
Cell Voltage Input 15. Connect CV15 to cell anode/cathode. Connect CV15 to the highest
— 19 CV15
voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 15. Connect BA15 to the gate of the external
— 20 BA15
n-channel FET. Leave BA15 unconnected if not used.
Sampling Capacitor Connection 15 High Terminal. CT15 internally connects to CV15
— 21 CT15 when SAMPL is logic-high. Connect a 1FF capacitor between CT15 and CB15. Leave
CT15 unconnected if not used.
Sampling Capacitor Connection 15 Low Terminal. CB15 internally connects to CV14
— 22 CB15 when SAMPL is logic-high. Connect a 1FF capacitor between CT15 and CB15. Leave
CB15 unconnected if not used.
Cell Voltage Input 14. Connect CV14 to cell anode/cathode. Connect CV14 to the highest
— 23 CV14
voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 14. Connect BA14 to the gate of the external
— 24 BA14
n-channel FET. Leave BA14 unconnected if not used.
Sampling Capacitor Connection 14 High Terminal. CT14 internally connects to CV14
— 25 CT14 when SAMPL is logic-high. Connect a 1FF capacitor between CT14 and CB14. Leave
CT14 unconnected if not used.
Sampling Capacitor Connection 14 Low Terminal. CB14 internally connects to CV13
— 26 CB14 when SAMPL is logic-high. Connect a 1FF capacitor between CT14 and CB14. Leave
CB14 unconnected if not used.
Cell Voltage Input 13. Connect CV13 to cell anode/cathode. Connect CV13 to the highest
— 27 CV13
voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 13. Connect BA13 to the gate of the external
— 28 BA13
n-channel FET. Leave BA13 unconnected if not used.
Sampling Capacitor Connection 13 High Terminal. CT13 internally connects to CV13
— 29 CT13 when SAMPL is logic-high. Connect a 1FF capacitor between CT13 and CB13. Leave
CT13 unconnected if not used.
Sampling Capacitor Connection 13 Low Terminal. CB13 internally connects to CV12
— 30 CB13 when SAMPL is logic-high. Connect a 1FF capacitor between CT13 and CB13. Leave
CB13 unconnected if not used.
— — EP Exposed Pad (MAX14920 Only). Connect EP to AGND.

Maxim Integrated   14

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Detailed Description left away or their value reduced: First connect the battery
pack's bottom (B-) and top (B+) terminals to the BMS elec-
The MAX14920/MAX14921 analog front-end devices are
tronics' AGND/CV0 and VP/CVT pins - then connect all of
used in multicell battery measurement systems to monitor
the remaining intermediary cell connections to the CV_ pins.
primary/secondary battery packs up to 16 cells/+65V (max).
The devices perform the signal conditioning required for Consider the sampling switches’ on-resistance of 150I
enabling accurate cell voltage measurement. Both devices (max) when calculating the filter and settling times. Using
simultaneously sample all cell voltages, allowing accurate 3kW protection resistors in series with the CV_ pin together
state-of-charge and source-resistance determination, even with 1µF sampling capacitors, the RC settling time from
under transient load current conditions. The cell voltage mea- 0V to within 200µV of a possible 4.5V cell voltage is about
surements are shifted down to ground reference with unity 60ms. If shorter sampling times are required, smaller
gain, simplifying external ADC data conversion. The devices sampling capacitors can be used, but note the effect of
enable passive cell balancing through drivers that control increased charge injection errors. The sampling capaci-
external discharge FETs. tors only discharge minimally during the hold phase, and if
the battery's load is nearly static, the cell voltages will only
A high-accuracy, low-offset amplifier buffers differential volt-
change minimally between successive samples, resulting
ages up to +5V for monitoring of the common rechargeable
in much reduced settling times. In the holding phase, each
cell technologies such as lithium-ion (Li+). The resulting cell
capacitor’s voltage can be independently routed to the ana-
measurement errors from the devices are below Q0.5mV
log AOUT output under SPI control.
(max). The devices’ high accuracy make them ideal for
monitoring cell chemistries with very flat discharge curves, Voltage Readout
such as a lithium-metal phosphate cell. Diagnostics detect When the SMPLB bit is set high, or when the SAMPL input
open-wire and short conditions, and warn about overvolt- is driven low, the sampling switches are opened after 0.5Fs
age/undervoltage. (typ) and the cell voltages are held on the external sampling
The SPI interface is used for control and monitoring through capacitors. Within the time of tLS_DELAY < 50Fs (max),
a host controller. The SPI interface is daisy-chainable. Both the capacitors’ voltages are all shifted to ground reference.
devices can operate with a minimum of +6V total stack volt- Then the undervoltage/overvoltage monitoring of all cells is
age (typically equating to 3 cells). valid and the cell voltage is available for sequential readout
under SPI control. The SPI control can select the readout of
Voltage Sampling any cell voltages, in any order (Figure 5).
The voltages of all cells are tracked by the sampling capaci-
tors connected between the CTn and CBn pins (where n
= 1–12 (MAX14920) and n = 1–16 (MAX14921)), while the
SMPLB bit is set to 0 and the SAMPL input is driven high CSAMPLE

(Figure 4). When the SMPLB bit is set to 1, and the SAMPL
input transitions low, all cell voltages are simultaneously CTn* CBn*
sampled on their associated capacitors. The voltages are
RLIM
held by the capacitors while the SMPLB bit is 1, or the CVn*
SAMPL pin is held low. When sample and holding is con-
trolled by the SAMPL input, set the SMPLB bit to 0. When CVn* - 1
sample and hold is controlled by the SMPLB bit, keep the
RLIM
SAMPL input high.
MAX14920
In sample phase selecting any cell voltage (ECS = 1), AOUT
MAX14921
equals VP/12 (MAX14920) or VP/16 (MAX14921).
In order to allow random connection of the battery cells to
SAMPL SMPLB
the BMS electronics, 3kW resistors must be placed in series
with the CV_ inputs for protection, as shown in Figure 11.
These protection resistors are not needed on CV0 and CVT,
where CVT refers to CVn pins connected to the battery's
*n = 1–12 (MAX14920) and n = 1–16 (MAX14921)
top (B+) terminal. Only if the following connection sequence
can be guaranteed, all of the protection resistors can be
Figure 4. Voltage Sampling

Maxim Integrated   15

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

SAMPLE PHASE HOLD PHASE

tSAMPL

HOLD LEVEL
SETTLING
DELAY SHIFT

tD_H tD_LS SELECT tSET CONVERT SELECT tSET CONVERT SELECT CONVERT SELECT tSET CONVERT
CELL a CELL a CELL b CELL b CELL c CELL m CELL n CELL n

= VOLTAGE READY
= SPI ACTIVITY
= ADC CONVERSION

Figure 5. SPI Control Cells Voltage Readout

With the ECS bit set to 1, a selected cell’s voltage appears at For example, with 1FF sampling capacitors and an ADC
the AOUT output according to the cell selection (as defined conversion rate > 20kHz, VERR_LEAK is less than 1mV. Cells
by the SC_ cell select bits). A low-leakage, low-noise, low- with a higher common-mode voltage have a higher leakage.
offset amplifier buffers the capacitor charge and provides To reduce the voltage drift over time, start sequential voltage
the high-accuracy AOUT analog output. After a settling time readout from the highest cell in the stack first.
of tSET, from the rising edge of the CS signal, the voltage is The buffer amplifier errors are nondeterministic in nature,
available at AOUT with specified accuracy. An ADC can then and vary from chip to chip. They are also affected by tem-
sample and convert the AOUT voltage. The AOUT output perature. The buffer amplifier offset error can be calibrated
voltage droops over time due to capacitor discharge. The out through an internal offset-calibration function. This
droop time for 1mV of change is larger than tDROOP (> calibration is automatically performed at power-up. The
CSAMPLE /ICT_LEAK). calibration can also be initiated under SPI control. Due to
Measurement Accuracy temperature drifts over time, it is best done on a regular
The accuracy of cell-voltage measurement (i.e., the differ- basis. Once the buffer amplifier offset is calibrated out, the
ence of the AOUT voltage relative to the cell voltages) is total error of the buffer is below 0.3mV. After power-up, if the
determined by four factors: devices do not calibrate regularly, a temperature offset drift
1) Sampling Time relative to the RC setting time of Q1.5FV/NC can occur.
2) Held voltage droop due to leakage on the CT_ pins The level shifting is subject to deterministic errors due to
3) Internal buffer amplifier’s voltage errors charge injection by parasitic PCB-related capacitance on
4) Capacitive level-shifting circuit error the CT_ pins. The charge-injected sampling error can be
The CT_ leakage (1FA, max) is a current that mainly comes calculated as follows:
from the CV_ pin and increases with temperature.
CPAR
Neglecting the PCB leakage across the sampling capaci- VERR_CHARGE_INJECTION = x VCVn
tance, the voltage drift error is given by: CSAMPLE
I CT_LEAK where:
VERR_LEAK = x t READOUT
C SAMPLE CPAR is the parasitic capacitance of the CTn pin, where
where: n = 1–12 (MAX14920) and n = 1–16 (MAX14921)
CSAMPLE is the sampling capacitor
CSAMPLE is the sampling capacitance VCVn is the voltage of the CTn pin with respect to
ICT_LEAK is the leakage current on the CT_ pin AGND, where n = 1–12 (MAX14920) and n = 1–16
tREADOUT is the delay between hold starts and readout (MAX14921)
of the cell voltage

Maxim Integrated   16

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

If VERR__CHARGE_INJECTION is large enough to affect the
OUTPUT ERROR vs. CT_ VOLTAGE toc01 required 1mV accuracy, this calibration method provides
2.5
CTPARASITIC = 3pF a measurement of the parasitic capacitance on each
CT_ pin so the microcontroller can use this to correct
2.0
VERR_INJECTION in its readings.
CSAMPLE = 0.1µF
A simple way to correct cell voltages is to store the ADC
OUTPUT ERROR (mV)

1.5
data of each cell obtained during calibration (i.e., error
values), divided by 128, and subtract these from the
1.0
subsequently measured cell voltages.
CSAMPLE = 1µF Note that the charge injection errors only depend on the
0.5
parasitic capacitance of the CTn pin and the common
mode voltage. The parasitic capacitance is PCB layout
0.0
0 10 20 30 40 50 60 70 dependent and does not change from board to board.
VCT (V)
Buffer Amplifier Offset Calibration
Figure 6. Charge Injection Error Voltage for 3pF Parasitic On power-up, the devices automatically go through a
Capacitance self-calibration phase to minimize the internal buffer’s
offset voltage. In addition, the offset voltage can be cali-
Figure 6 shows the charge-injected sampling error for brated out at any time under host control. Offset calibra-
1pF of parasitic capacitance in worst-case conditions for tion is configurable by setting the [ECS, SC0, SC1, SC2,
a 100nF and 1FF sampling capacitor if charge injection SC3] bits to [0, 1, 0, 0] and is initiated on the low to high
error correction is not employed. CS transition in sampling phase. This offset-calibration
Minimizing the parasitic capacitance on the CT_ pins to procedure takes 8ms to complete. The AOUT output is
a few picofarads, with a sampling capacitor of 1FF, is high impedance during this period. No regular cell volt-
enough to achieve output error below 1mV target. age measurement can be taken during this time period.
However, the SPI operates normally when communicat-
Alternatively, if a sampling capacitor lower than 1FF or a
ing with other devices (e.g., in daisy-chain mode). So
parasitic capacitance of more than 15pF are present, these
as not to affect calibration, do not take measurement
errors can be calibrated out to achieve a < 1mV accuracy
and keep the devices in sample mode (ECS = 0, SC2
level through a calibration procedure for each cell. These
= 0, SMPLB = 0). After power-up, if the devices do not
per-cell errors are simply subtracted from every cell volt-
calibrate regularly, a temperature offset drift of Q1.5FV/°C
age measurement (see the Parasitic Capacitance Charge
can occur.
Injection Error Calibration section).
Monitoring Less Than 12/16 Cells
Parasitic Capacitance Charge
The devices can monitor from 3 (VP > +6V) to 12/16
Injection Error Calibration
cells (VP < +65V). When monitoring less than the maxi-
This calibration is performed with all cells connected
mum number of possible cells per device, connect the
to the CV_ terminals. Setting the [ECS, SC0, SC1, SC2,
most negative cell stack voltage to the bottom of the
SC3] bits to [0, 0, 0, 0, 0] configures the devices for
voltage input string (CV0). The unused CV_ inputs at
parasitic capacitance charge-injection error calibration.
the top of the string should be shorted together and
During the sampling phase, every sampling capacitor’s connected to VP. Leave the unused BA_, CT_ , and CB_
CTn and CBn terminals are shorted together by internal pins unconnected.
calibration switches (RSWCAL = 800I typ), so that only
the parasitic capacitance is charged to the cell’s common- Reading Total Cell Stack Voltage
mode voltage VCVn, where n = 1–12 (MAX14920) and n Besides monitoring the individual cell voltages, the
= 1–16 (MAX14921). devices can monitor the total voltage of the cell stack.
An internal resistive voltage-divider between VP and
The subsequent cell voltage readout sequence
AGND divides the stack voltage by 12 (MAX14920) or 16
then shows the value of VERR_CHARGE_INJECTION
(MAX14921). This provides a way to quickly determine
for each cell at AOUT, multiplied by 128.
the state of the total battery pack, as well as the average

Maxim Integrated   17

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

voltage of all cells. The settling time of AOUT is 60Fs. To CB1 is the first bit expected from the controller and C1 is
read out the total cell stack voltage, set the [ECS, SC0, the first bit that the devices sent to the controller. The SDO
SC1, SC2, SC3] bits to [0, 0, 0, 1, 1]. The total cell stack data changes on the falling edge of the SCLK signals. The
voltage can be read during the sample or hold phase. devices sample the SDI data on the rising edge of SCLK.
SPI Serial Interface SPI Configuration/Control Bits
Control of the devices is done through a 24-bit SPI inter- The configuration/control bits allow enabling of the
face. The controller sends the serial data to the devices charge-balance switches, sampling and holding of all
through the SDI input. The devices simultaneously send the cell voltages, selecting the cell for voltage output,
out monitoring data at the SDO output. This scheme selecting the T_ input channels, and enabling diagnos-
allows daisy-chained operation with other daisy-chain- tics mode. Table 1 describes the bits that the devices
able devices, such as ADC converters. Figure 7 shows receive from the host controller for configuration and
the serial bit sequence. control through SDI.

CS

SCLK

SDI X CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 CB16 ECS SC0 SC1 SC2 SC3 SMPLB DIAG LOPW X

SDO C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 OP 0 OP 1 REV 0 REV 1 UV_VA UV_VP RDY OT X

Figure 7. SPI Serial Interface Bits

Table 1. SPI Configuration/Control Bits

NAME BITS ACCESS RESET DESCRIPTION
0: Set BA1 output low
CB1 0 W 0
1: Set BA1 output high
0: Set BA2 output low
CB2 1 W 0
1: Set BA2 output high
0: Set BA3 output low
CB3 2 W 0
1: Set BA3 output high
0: Set BA4 output low
CB4 3 W 0
1: Set BA4 output high
0: Set BA5 output low
CB5 4 W 0
1: Set BA5 output high
0: Set BA6 output low
CB6 5 W 0
1: Set BA6 output high
0: Set BA7 output low
CB7 6 W 0
1: Set BA7 output high
0: Set BA8 output low
CB8 7 W 0
1: Set BA8 output high

Maxim Integrated   18

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Table 1. SPI Configuration/Control Bits (continued)
NAME BITS ACCESS RESET DESCRIPTION
0: Set BA9 output low
CB9 8 R/W 0
1: Set BA9 output high
0: Set BA10 output low
CB10 9 R/W 0
1: Set BA10 output high
0: Set BA11 output low
CB11 10 R/W 0
1: Set BA11 output high
0: Set BA12 output low
CB12* 11 R/W 0
1: Set BA12 output high
0: Set BA13 output low
CB13* 12 R/W 0
1: Set BA13 output high
0: Set BA14 output low
CB14* 13 R/W 0
1: Set BA14 output high
0: Set BA15 output low
CB15* 14 R/W 0
1: Set BA15 output high
0: Set BA16 output low
CB16* 15 R/W 0
1: Set BA16 output high
0: Cell selection is disabled
ECS 16 R/W 0
1: Cell selection is enabled
[ECS, SC0, SC1, SC2, SC3]
SC0 17 R/W 0 1 – SC0, SC1, SC2, SC3: Selects the cell for voltage readout during hold phase.**
The selected cell voltage is routed to AOUT after the rising CS edge. See Table 2.
0 – 0, 0, 0, 0: AOUT is three-stated and sampling switches are configured for
SC1 18 R/W 0 parasitic capacitance error calibration.
0 – 1, 0, 0, 0: AOUT is three-stated and self-calibration of buffer amplifier offset
voltage is initiated after the following rising CS.
SC2 19 R/W 0 0 – SC0, SC1, 0, 1: Switches the T1, T2. T2 analog inputs directly to AOUT. See
Table 3.
0 – 0, 0, 1, 1: VP/12 (MAX14920) or VP/16 (MAX14921) voltage is routed to AOUT
SC3 20 R/W 0 on the next rising CS
0 – SC0, SC1, 1, 1: Routes and buffers the T1, T2. T3 to AOUT. See Table 3.
0: Device in sample phase if SAMPL input is logic-high
SMPLB 21 R/W 0
1: Device in hold phase
0: Normal operation
DIAG 22 R/W 0
1: Diagnostic enable, 10FA leakage is sunk on all CV_ inputs (CV0–CV16).
0: Normal operation
LOPW 23 R/W 0 1: Low-power mode enabled. Current into LDOIN is reduced to 125FA. Current
into VP is reduced to 1FA.
*Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920.
**For the MAX14920, if n > 12, VAOUT = 0V.

Maxim Integrated   19

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Table 2. Cell Selection
CELL SC0 SC1 SC2 SC3
1 0 0 0 0
2 1 0 0 0
3 0 1 0 0
4 1 1 0 0
5 0 0 1 0
6 1 0 1 0
7 0 1 1 0
8 1 1 1 0
9 0 0 0 1
10 1 0 0 1
11 0 1 0 1
12 1 1 0 1
13* 0 0 1 1
14* 1 0 1 1
15* 0 1 1 1
16* 1 1 1 1
*For MAX14921 only.

Table 3. Analog Input Selection

T_ SC0 SC1
T1 1 0
T2 0 1
T3 1 1

Maxim Integrated   20

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

SPI Monitoring Bits Flexible Logic Interface
The monitoring bits provide feedback of undervoltage The serial/parallel logic control interface logic levels can
conditions and thermal shutdown, as well as indication be defined to be in a range between +1.62V (min) and
when the devices are ready for operation after power-up. +5.5V (max). The voltage applied to the VL pin defines
Table 4 describes the diagnostics/monitoring bits that the logic levels. Choose the VL voltage to match the con-
the devices send back to the host controller through the troller and ADC’s I/O logic levels.
SDO output.

Table 4. SPI Monitoring Bits

NAME BITS ACCESS DESCRIPTION
C1 0 R 1: During hold phase if cell 1 voltage is below UV_VCVTH or above VA
C2 1 R 1: During hold phase if cell 2 voltage is below UV_VCVTH or above VA
C3 2 R 1: During hold phase if cell 3 voltage is below UV_VCVTH or above VA
C4 3 R 1: During hold phase if cell 4 voltage is below UV_VCVTH or above VA
C5 4 R 1: During hold phase if cell 5 voltage is below UV_VCVTH or above VA
C6 5 R 1: During hold phase if cell 6 voltage is below UV_VCVTH or above VA
C7 6 R 1: During hold phase if cell 7 voltage is below UV_VCVTH or above VA
C8 7 R 1: During hold phase if cell 8 voltage is below UV_VCVTH or above VA
C9 8 R 1: During hold phase if cell 9 voltage is below UV_VCVTH or above VA
C10 9 R 1: During hold phase if cell 10 voltage is below UV_VCVTH or above VA
C11 10 R 1: During hold phase if cell 11 voltage is below UV_VCVTH or above VA
C12* 11 R 1: During hold phase if cell 12 voltage is below UV_VCVTH or above VA
C13* 12 R 1: During hold phase if cell 13 voltage is below UV_VCVTH or above VA
C14* 13 R 1: During hold phase if cell 14 voltage is below UV_VCVTH or above VA
C15* 14 R 1: During hold phase if cell 15 voltage is below UV_VCVTH or above VA
C16* 15 R 1: During hold phase if cell 16 voltage is below UV_VCVTH or above VA

OP0 16 R Product identifying bits

MAX14921 (OP0 = 0, OP1 = 0)
OP1 17 R MAX14920 (OP0 = 1, OP1 = 0)
REV0 18 R Die version
REV1 19 R MAX14920/MAX14921 version bits
UV_VA 20 R 1: VA is below UV_VAVTH
UV_VP 21 R 1: VP is below UV_VPVTH. If LOPW = 1, VP UVLO circuit is disabled and this bit is always set to 1
1: Device is not ready to operate (power-up phase or buffer amplifier is in self-calibration
RDY 22 R
procedure)
OT 23 R 1: Device is in thermal shutdown
*Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920.

Maxim Integrated   21

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Linear Regulator Route the T_ inputs through the buffer to AOUT by setting
The internal linear regulator has LDOIN as its input volt- the SPI bits [ECS, SC0, SC1, SC2, SC3] = [0, b, a, 1, 1].
age and regulates this down to +5V Q5% at the VA output Route the T_ inputs directly to the AOUT output by setting
with a load current of 10mA (max). The LDO is automati- the bits [ECS, SC0, SC1, SC2, SC3 = [0, b, a, 0, 1]. Bits
cally enabled when LDOIN is above +5.5V. The internal a and b select one of the three T_ inputs or three-state
LDO is short-circuit protected with a current limit higher the AOUT output.
than 14mA (22mA, typ). An external +5V regulator can be
Three-Stating the AOUT Output
used instead of the internal one. When using an external
The AOUT output can be three-stated to share this pin
+5V regular, LDOIN must be connected to VA.
with other external signal sources, such as additional
Thermal Protection temperature sensors. Use the ECS and SC_ bits to three-
The devices have thermal shutdown to protect them state the AOUT output.
against thermal overheating. In thermal shutdown, the
Charge Balancing
LDO, amplifier, and charge-balance circuitry stop opera-
Enhancement-mode n-channel FETs can be connected
tion. The SPI interface is functional in thermal shutdown.
for passive balancing of cells. Select low on-resistance
Shutdown Mode FETs with a VT between 0.9V and half of the minimal cell
The devices can be placed into low standby-power voltage seen during cell balancing. Connect the FETs
shutdown mode through the LOPW bit. The internal LDO between each cell’s anode and cathode with a current-
remains on and the amplifier disabled, bringing the VP limiting resistor in the drain (Figure 9).
supply current down to 1FA (max). The charge-balancing FETs can be enabled through SPI
Analog/Temperature Inputs control. An internal 14.8kI (typ)/21.5kI (max) pulldown
The T1, T2, and T3 inputs are single-ended, CV0- resistor assures that the FET is normally switched off.
referenced, general-purpose analog inputs that are mul- When balancing is active, a leakage current of 5FA is
tiplexed to AOUT or to AOUT through a buffer (Figure 8). sunk from CV_. In addition, an internal balancing current
These inputs can be used for connection of temperature flowing from CVn to CVn - 1 of 10mA (max) is present,
sensors or for a current monitor. where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
The power dissipation created by the internal current
The total mux and switch series resistance is less than during balancing should be considered for total package
200I. In applications where the load current flowing to the power management. Resistors between the cells and
AOUT output is so high that significant errors are introduced the CVn inputs cause IR voltage drop due to the internal
due to series resistance in the voltage source and/or the 12mA(max) balance current. This results in measurement
signal path, use the buffer amplifier to improve accuracy. errors during balancing. Therefore, measuring cell volt-
ages during charge balancing is not meaningful.

CVn*
MAX14920
T1
AOUT RBAL MAX14921
T2 BAL
BUFFER
T3
CELLn* BAn*

14.8kI

SPI CONTROL CVn* - 1

*n = 1–12 (MAX14920) and n = 1–16 (MAX14921)

Figure 8. Analog/ Temperature Measurement Figure 9. Charge Balancing

Maxim Integrated   22

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Diagnostics Input-Voltage Clamping
The devices’ integrated diagnostics allow detection of The devices have internal ESD-protection diodes that
shorts between wires, as well as open-wire conditions of clamp input voltage lower than AGND or higher than VP
the CV_ pins. than VP (for CVn where n > 1) or 6V (for CV1) during a
Shorts between cell connections can be detected during fault condition. Connect 3kW series resistors (RLIM) to the
normal operation. The cell readout voltage results in ~0V inputs to limit the currents flowing through the forward-
or ~VA depending on where the short happens. In the biased diodes during fault conditions or hot plugging
case of shorts, the maximum currents flowing in/out of the (Figure 10). Sampling capacitors and balancing FETs
pins must be limited and overvoltages avoided, including must be chosen appropriately or protected with external
the external components (balancing FETs and sampling voltage clamps to survive such events.
capacitors).
Power Sequencing
Open-wire conditions between the CV_ inputs and the The VA and VL supplies can be applied at any sequence
cells can be detected in two different ways: with respect to each other and also independently of the
The first method of open-wire detection: VP and supplies CV_ inputs. The VP voltage has to con-
Set the DIAG bit to 1 while in the sampling phase. This nect to the highest voltage of the cell stack.
applies a leakage current of 10FA to the CVn inputs. If
CVn is unconnected, the leakage current starts discharg-
ing the sampling capacitor with a slew rate of ILEAK/
CSAMPLE (~10FA/1FF = 100mV/10ms) down to CVn - 1.
Two successive readouts show considerable cell voltage
change in case of an open wire. Alternatively, waiting for
a sampling time of ~300ms to 500ms reduces the cell
voltage to below the UV_VCVTH threshold voltage.
MAX14920
VP
First open-wire detection procedure: MAX14921
• Set DIAG bit to 1
• Wait > 0.5s before hold phase RLIM
CVn* CTn*
• Read out the Cn bit or the CVn voltage under SPI
control, where n = 1–12 (MAX14920) and n = 1–16 RBAL
(MAX14921)
The second method of open-wire detection: BAn* CSAMPLE
To check for a single open-wire connection, it is faster to
enable the balancing FET only on the selected cell during
RLIM
the sampling phase and then reading out the selected CVn*- 1 CBn*
cell voltage. If CVn is unconnected, the balancing FET
rapidly (time depends on the balancing resistance used)
shorts CVn to CVn - 1 and the readout phase shows ~0V
or CVn and a voltage higher than VA on CVn + 1. CV1

Second open-wire detection procedure:

• Set the BAn bit to 1
BA1
• Wait for a time of RBAL x CSAMPLE before switching
to the hold phase
• Route the CVn voltage to AOUT
CV0 AGND
• Repeat this procedure for all cells
During this procedure, the capacitors and external FETs
need to withstand a voltage equal to VCVn - VCVn-1,
*n = 1–12 (MAX14920) AND n = 1–16 (MAX14921)
where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).

Figure 10. Input-Voltage Clamp

Maxim Integrated   23

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Applications Information up to the cell voltages, or the initial samples are disregarded
until the monitored voltages stabilize to their final cell value.
Connecting the Battery Pack to the BMS The accuracy dependence on the capacitor values is deter-
When connecting the battery cells to the BMS electronics, mined by the discharge during the hold phase and by the
large inrush currents can flow through the CVn pins that errors introduced during level shifting (both were previously
charges capacitance present on the VP pin. These inrush described). By speeding up the readout of the cell voltages
currents must be limited to avoid damage. Connect 3kW during the hold phase, discharging is reduced. Note that
resistors in series with each CVn input pin, except the CV0 the last cell voltage being read out is most affected by dis-
and CVT/VP pins, as shown in Figure 11. CVT refers to the charging, due to its longer hold delay until being read out.
top CVn terminal, which would for example be CV16 in the Smaller capacitor values are prone to higher charge injec-
case of a 16S cell pack or CV10 in case of a 10S cell pack. tion errors caused by level-shifting. Both low-capacitance
Only if the following connection sequence of the BMS layout and charge injection error calibration compensation
electronics to the battery pack can be guaranteed, are the reduce these errors.
3kW protection resistors not required or their value can be Typical Application Circuit
reduced: FIrst connect the battery's bottom (B-) and top Figure 11 shows a high-accuracy measurement application
(B+) terminals to the BMS' AGND/CV0 and VP/CVT termi- based on an accurate 16-bit ADC, together with a high-qual-
nals, then connect the remaining CVn cells connections. ity voltage reference. The internal linear regulator is used for
Sampling Speed and Capacitor- supplying VA (+5V), and uses the SAMPL input for control-
Selection Considerations ling the cell voltage sample and hold times. Thermistors
Capacitor values of 1FF are recommended for achieving low are connected to the T1, T2, and T3 inputs to monitor three
charge injection errrors. In combination with 3kW current- temperatures.
limiting resistors, this results in sample and hold times in the If less absolute measurement accuracy is acceptable, an
order of 60ms. With 1FF capacitors and good PCB layout, ADC with internal reference, such as the MAX11163, can be
charge injection-error correction is normally not required. used. In applications where accuracy is not a critical factor,
If higher/lower sampling speeds are required, the sampling a microcontroller’s internal ADC may be adequate.
capacitors can be reduced and/or increased.
Multipack Applications
The cell sampling capacitors connected to the CT_ and CB_
In applications that require more than 12/16 cells to achieve
terminals affect:
higher voltages, multiple cell packs can be stacked. Each
• Speed of operation pack in the stack does not have to have the same number
• Cell readout accuracy of cells. A minimum of +6V or 3 cells can be monitored by
The smaller the sampling capacitor values, the lower their the devices.
RC time constant and hence the faster their charging time. In stacked packs, the sample signal can either be centrally
Therefore, for higher-speed operation, smaller capacitor controlled by a common signal for simultaneous sampling,
values can be selected. or the sample/hold can be initiated through SPI. Two cell
One application case can be when the cell voltages are packs stacked on one another can be interconnected
known to only vary by small amounts from one sample to through an SPI or other communication interface. The packs
the next. In this case, the sampling capacitors can be made can either have internal controllers or multiple packs can
smaller, as the sampling phases only need to charge the be controlled by one common controller. Internal controllers
capacitors by the charge lost during the previous level shift perform autonomous calibration and measurements, and
and hold phase, including the small change in cell voltage. allow an external controller to collect the data on demand.
See the Measurement Accuracy section for details on how This scheme is shown in Figure 12. To translate the inter-
to calculate the voltage drop due to these two factors. For pack communication signals between the differing common-
example, sampling capacitors of approximately 100nF can mode pack voltages, use opto-isolators, digital isolators, or
be adequate, thereby reducing the sampling phase by a digital ground level shifters (Figure 12).
factor of 10. If this technique is used, the initial sampling Layout Considerations
times, after initial power-up, either have to be made longer to Keep the PCB traces to the sampling capacitors as short as
allow the initially discharged sampling capacitors to charge possible and minimize parasitic capacitance between the
capacitor pins and the ground plane.

Maxim Integrated   24

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

1µF 1µF 1µF

CT16 CB16 CT15 CB15 CT14 CB14

LDOIN T_
VP
CV16

POWER-
SUPPLY
UNIT
BA16 VA
1µF
CV15
3kΩ
VL
MAX14920
1µF
MAX14921
VA
BA15
MAX6126
MAX11163 EXTERNAL REFERENCE
CV14 AOUT
16-BIT ADC
3kΩ

SAMPL
CV1
3kΩ SCLK
SDO
µC
SDI

BA1 CS
EN
CV0 DGND

AGND
CT1 CB2 CT2 CB3 CT3

1µF 1µF 1µF

Figure 11. Typical Application Circuit

Maxim Integrated   25

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

SDO CS CLK SDI

COMn VCCn

GND

VP MAX17501

VA
SPI2
MAX14920
MAX14921 ADC

SDO
SPI1
CONTROLLER
GND
SDI

MAX14850

COMn-1 VCCn-1

COM1 VCC1

GND

VP MAX17501

VA
SPI2
MAX14920
MAX14921 ADC

SDO
SPI1
CONTROLLER
GND
SDI

MAX14850

MOSI CS CLK MISO

CONTROLLER
GND VCC

Figure 12. Stacked Battery Pack Application Diagram Based on Daisy-Chained SPI

Maxim Integrated   26

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Functional Diagram

CB13*

CB14*

CB15*

CB16*
CT13*

CT14*

CT15*

CT16*
CB10

CB11

CB12
CT10

CT11

CT12
CB9
CT9
VP

CV16*
BA16*
MAX14920
CV15* MAX14921
BA15*
CV14* T1
BA14*
CV13* T2
BA13*
CV12 T3
BA12
CV11 LDOIN
+5V LDO
BA11
CV10 VA
BA10
CV9 AOUT
BA9
CV8 EN
SOURCE SELECT/
BA8 CALIBRATION
CV7
BA7
VL
CV6
BA6
CV5 SAMPL
BA5
CV4 CS
BA4
CV3 SCLK
SPI
BA3
CV2 SDI
BA2
CV1 SDO
BA1
CV0
DGND
AGND
CT1
CB1
CT2
CB2
CT3
CB3
CT4
CB4
CT5
CB5
CT6
CB6
CT7
CB7
CT8
CB8

*MAX14921 ONLY.

Maxim Integrated   27

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Ordering Information Package Information

For the latest package outline information and land patterns (foot-
PIN- prints), go to www.maximintegrated.com/packages. Note that a
PART CELLS TEMP RANGE
PACKAGE “+”, “#”, or “-” in the package code indicates RoHS status only.
MAX14920ECB+ 12 -40NC to +85NC 64 TQFP-EP* Package drawings may show a different suffix character, but the
MAX14921ECS+ 16 -40NC to +85NC 80 TQFP drawing pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

+Denotes a lead(Pb)-free/RoHS-compliant package.
TYPE CODE NO. PATTERN NO.
*EP = Exposed pad.
64 TQFP-EP C64E+10 21-0084 90-0329
80 TQFP C80+1 21-0072 —
Chip Information
PROCESS: BiCMOS

Maxim Integrated   28

 MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

Revision History

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 10/12 Initial release —
1 2/13 Removed future products asterisks from the MAX14920 28
Recommend the use of 3kW resistors in series with VCn for hot plug protection
2 6/14 16
The SDO logic VOL(max) spec has been changed from 0.9V to 0.4V.

Added 3kW resistors to Typical Application Circuit and updated TOCs, Electrical 1-4, 7, 10,
3 3/15
Characteristics table and applications information. 15-17, 22-25,

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 29
©  2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.