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Exam For Hardware Description Language

This document is a test exam for a course on digital logic and hardware description languages. It contains three sections - a cypher puzzle to solve, filling in blank spaces in a table, and short explanations of modeling in HDLs, simulation concepts, and the importance of HDLs. The cypher involves filling white squares with letters to solve clues and form words or phrases. The table focuses on topics like net types in Verilog, parts of number representation, and compiler directives. The elucidation section involves explaining the provided subjects in a structured way with content, correctness, and organization.

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Richards
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80 views2 pages

Exam For Hardware Description Language

This document is a test exam for a course on digital logic and hardware description languages. It contains three sections - a cypher puzzle to solve, filling in blank spaces in a table, and short explanations of modeling in HDLs, simulation concepts, and the importance of HDLs. The cypher involves filling white squares with letters to solve clues and form words or phrases. The table focuses on topics like net types in Verilog, parts of number representation, and compiler directives. The elucidation section involves explaining the provided subjects in a structured way with content, correctness, and organization.

Uploaded by

Richards
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SCORE

Course Code: CpE 314.1 CEAFA Date:


Term Exam: PRELIM EXAMINATION Instructor: ENGR. JOHN RICHARD MUSNI
Name: Yr. & Section:

I. CYPHER [15.PTS]
#commands.cypher{
Fill the white squares with letters, forming words or phrases, by solving clues, which lead to the
answers. If the answer has two phrases, fill an underscore (_) between the two phrases.
}

Across Down
3. It is a single character ' followed by one of the following 1. Describes how the modules reacts.
characters b, d, o and h, which stand for binary, decimal, octal and
hex, respectively.

5. This includes reg, integer, time, real, realtime. 2. A keyword from compiler directive that is used in text-macro
substitution.

6. A Interconnects logic gates and other modules. 4. A type of data that connects between structural elements.

8. A type of Hardware Description Language that is similar to 7. The industry's first unified hardware description and
Pascal. verification language.

11. A lexical element of verilog that requires a dollar sign as its 9. A lexical element that have to start with an alphabetic
beginning syntax keyword. character or underscore followed by alphanumeric or underscore
characters.

13. A text-based method for describing hardware to synthesis tool. 10. A keyword from compiler directive that is used to include files.

14. Developed by Gateway Design Automation as a proprietary 12. Employs a mathematical representation, or model, of a real
language for logic simulation in 1984. system in the form of a computer program.

15. The process of mixing several elements to produce something.

Record Code: CEAFA-IND-1.15.5


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SCORE

Course Code: CpE 314.1 CEAFA Date:


Term Exam: PRELIM EXAMINATION Instructor: ENGR. JOHN RICHARD MUSNI
Name: Yr. & Section:

II. LISTING SPACES [15.PTS]


#commands.listing_space{
Fill the blank spaces in the table based on the requirements. Each box is equivalent to 5 points if the
list is complete. If the list is incomplete, 3 points will be given, but no points will be given if the
spaces are blank.
}

Net Types Under Lexical Parts of Number Compiler Directives


Elements of Verilog Represenation


 

 

 

III. ELUCIDATION [15.PTS]

#commands.elucidation{
Explain the provided subject depending on your understanding. Each topic is worth 5 points.
The 5 points will be divided as follows:
Use the back of the paper.
Content: 2 points
Correctness: 2 points
Organization: 1 Point
}

A. Modeling in HDL
B. Concept of Simulation
C. Importance of HDL in the Computing Industry

Record Code: CEAFA-IND-1.15.5


Page 1 of 1

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