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Tutorial Active HDL

This document provides step-by-step instructions for using Aldec Active-HDL to design, simulate, synthesize, implement, and program a FPGA with a VHDL design for 2-input logic gates. The design is created and simulated in Active-HDL, then synthesized, implemented for a Spartan3 FPGA, and programmed onto the board using the generated bitstream file. Key steps include creating an Active-HDL workspace, adding the VHDL design module, performing functional simulation, running synthesis and implementation, generating a constraint file, and programming the FPGA with iMPACT.

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MEBM80
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© Attribution Non-Commercial (BY-NC)
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428 views

Tutorial Active HDL

This document provides step-by-step instructions for using Aldec Active-HDL to design, simulate, synthesize, implement, and program a FPGA with a VHDL design for 2-input logic gates. The design is created and simulated in Active-HDL, then synthesized, implemented for a Spartan3 FPGA, and programmed onto the board using the generated bitstream file. Key steps include creating an Active-HDL workspace, adding the VHDL design module, performing functional simulation, running synthesis and implementation, generating a constraint file, and programming the FPGA with iMPACT.

Uploaded by

MEBM80
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Aldec Active-HDL Tutorial Part 1

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Appendix A

Aldec Active-HDL Tutorial Part 1


Start the program by double-clicking the Active-HDL 7.1 icon on the desktop. Select Create new workspace and click OK.

Browse to the directory where you want to store the project, type gates for the workspace name and click OK.

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Appendix A

Select Create an Empty Design with Design Flow and click Next.

Click Flow Settings

Select HDL Synthesis

Select Xilinx ISE/WebPack 8.1 XST VHDL/Verilog

Press Select

Aldec Active-HDL Tutorial Part 1

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Select Implementation

Choose Xilinx ISE/WebPack 8.1 Press Select

Select Xilinx SPARTAN3 for Family

Click Ok

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Appendix A

Click Next

Type gatesA for the design name and click Next.

Click Finish.

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Click on HDE. Select VHDL and Click OK.

Click Next.

Type gates2 and click Next.

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Appendix A

Click New.

Type a.

Click New. Type b.

Click New. Type z. Click Out.

Set Array Indexes to 1:6.

Click Finish.

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This will generate a VHDL template with the input and output signals filled in. Add your name as author and type Behavior of 2-input gates as the description.

Note that the entity has been completed for you (see Listing 1.1 in Example 1).

2 Click Save

3 Click on + and then Right-click on gates2.vhd and select Compile

1 Type in these six assignment statements (see Listing 1 of Example 1)

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Appendix A

Click design flow and then Click options

Click here to select design

Select gates2.vhd and Click Ok

Click Choose, select gates2 as the top-level design, and click Add.

Click Ok

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Click Use Default Waveform

Click Ok Click functional simulation

The waveform window will automatically come up with the simulation already initialized. Make sure order is a, b, z (grab and drag if necessary). Right-click on a and select Stimulators.

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Appendix A

Select Clock and set Frequency to 25 MHz

Click Apply Click on b, select Clock and set Frequency to 50 MHz

Click Apply Click Close

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Set simulation time to 200 ns Click here to run simulation

Click + sign to show all elements of z. Print out the waveform by selecting File -> Print from the menu bar. Study the waveform for various magnifications. Click design flow

Click synthesis options

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Appendix A

Pull down menu and select gates2 for Top-level Unit.

Check VHDL Select 3S200ft256 for Device from pull down

Click Ok. Click synthesis

After synthesis is complete, click Close.

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Click Tools Click PACE Select File->New

Click Browse and select your gates2.vhd file

Click

Select Spartan3..XC3S200..FT256.

Click Ok.

Click Ok

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Appendix A

Type in the pin numbers for the two left-most slide switches for a and b and the six rightmost LEDs for the values of z(1:6).

Click Save and then click Ok Close the window Click implementation options

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Select 3s200ft256

Check VHDL Select Custom constraint

Browse and select the file gates2.ucf that you just created Click Ok. Select Translate and check Allow Unmatched LOC Constraints. Select BitStream and uncheck Do Not Run Bitgen.

Click Ok

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Appendix A

Click implementation

When implementation is complete click Close.

Click Analysis and click iMPACT options

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Select create a new project and click OK

Click Finish

Browse and locate gates2.bit, select it, and click Open.

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Appendix A

Click OK

Click Bypass to bypass Prom in the

Right-click the Spartan3 chip and select Program.

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Click OK.

After downloading the .bit file, Program Succeeded will be displayed. Close the iMPACT window and click Yes. Your program is now running on the board.

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