f133 User Manual v1.0
Uploaded by
William Whitef133 User Manual v1.0
Uploaded by
William WhiteF133
User Manual
Revision 1.0
May 24, 2021
Confidential
Revision History
Revision Date Author Description
1.0 May 24, 2021 AWA0330 Initial release version
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Contents
Revision History ....................................................................................................................................................................i
Contents ............................................................................................................................................................................... ii
1 About This Document ..................................................................................................................................................1
1.1 Purpose and Scope...............................................................................................................................................1
1.2 Intended Audience ...............................................................................................................................................1
1.3 Symbol Conventions.............................................................................................................................................1
1.3.1 Symbol Conventions.................................................................................................................................1
1.3.2 Table Content Conventions ......................................................................................................................1
1.3.3 Reset Value Conventions .........................................................................................................................1
1.3.4 Register Attributes ...................................................................................................................................2
1.3.5 Numerical System ....................................................................................................................................2
Contents ...............................................................................................................................................................................3
2 Product Description .....................................................................................................................................................4
2.1 Overview ..............................................................................................................................................................4
2.1.1 Device Difference .....................................................................................................................................4
2.2 Features ...............................................................................................................................................................4
2.2.1 CPU Architecture ......................................................................................................................................4
2.2.2 Memory SubSystem .................................................................................................................................4
2.2.3 Video Engine ............................................................................................................................................6
2.2.4 Video and Graphics ..................................................................................................................................6
2.2.5 Video Output ............................................................................................................................................8
2.2.6 Video Input...............................................................................................................................................9
2.2.7 System Peripherals...................................................................................................................................9
2.2.8 Audio Interfaces .................................................................................................................................... 12
2.2.9 Security System ..................................................................................................................................... 15
2.2.10 External Peripherals .............................................................................................................................. 16
2.2.11 Package ................................................................................................................................................. 22
2.3 Block Diagram ................................................................................................................................................... 22
Contents ............................................................................................................................................................................ 24
Figures ............................................................................................................................................................................... 27
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Tables ................................................................................................................................................................................ 29
3 System ....................................................................................................................................................................... 30
3.1 Memory Mapping ............................................................................................................................................. 30
3.2 RISC System ....................................................................................................................................................... 33
3.2.1 Overview ............................................................................................................................................... 33
3.2.2 Block Diagram ....................................................................................................................................... 33
3.2.3 Register List ........................................................................................................................................... 34
3.2.4 Register Description .............................................................................................................................. 35
3.3 Clock Controller Unit (CCU) ............................................................................................................................... 44
3.3.1 Overview ............................................................................................................................................... 44
3.3.2 Block Diagram ....................................................................................................................................... 44
3.3.3 Functional Description .......................................................................................................................... 45
3.3.4 Programming Guidelines....................................................................................................................... 50
3.3.5 Register List ........................................................................................................................................... 56
3.3.6 Register Description .............................................................................................................................. 59
3.4 BROM System.................................................................................................................................................. 144
3.4.1 Overview ............................................................................................................................................. 144
3.4.2 Functional Description ........................................................................................................................ 144
3.5 System Configuration ...................................................................................................................................... 152
3.5.1 Overview ............................................................................................................................................. 152
3.5.2 Register List ......................................................................................................................................... 152
3.5.3 Register Description ............................................................................................................................ 152
3.6 Timer ............................................................................................................................................................... 160
3.6.1 Overview ............................................................................................................................................. 160
3.6.2 Block Diagram ..................................................................................................................................... 161
3.6.3 Functional Description ........................................................................................................................ 161
3.6.4 Programming Guidelines..................................................................................................................... 165
3.6.5 Register List ......................................................................................................................................... 166
3.6.6 Register Description ............................................................................................................................ 167
3.7 High Speed Timer ............................................................................................................................................ 179
3.7.1 Overview ............................................................................................................................................. 179
3.7.2 Block Diagram ..................................................................................................................................... 179
3.7.3 Functional Description ........................................................................................................................ 179
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3.7.4 Programming Guidelines..................................................................................................................... 183
3.7.5 Register List ......................................................................................................................................... 183
3.7.6 Register Description ............................................................................................................................ 184
3.8 Platform-Level Interrupt Controller (PLIC) ...................................................................................................... 191
3.8.1 Overview ............................................................................................................................................. 191
3.8.2 Functional Description ........................................................................................................................ 191
3.8.3 Register List ......................................................................................................................................... 197
3.8.4 Register Description ............................................................................................................................ 198
3.9 Direct Memory Access Controller (DMAC)...................................................................................................... 202
3.9.1 Overview ............................................................................................................................................. 202
3.9.2 Block Diagram ..................................................................................................................................... 202
3.9.3 Functional Description ........................................................................................................................ 203
3.9.4 Programming Guidelines..................................................................................................................... 212
3.9.5 Register List ......................................................................................................................................... 215
3.9.6 Register Description ............................................................................................................................ 216
3.10 Thermal Sensor Controller (THS) .................................................................................................................... 236
3.10.1 Overview ............................................................................................................................................. 236
3.10.2 Block Diagram ..................................................................................................................................... 236
3.10.3 Functional Description ........................................................................................................................ 236
3.10.4 Programming Guidelines..................................................................................................................... 238
3.10.5 Register List ......................................................................................................................................... 240
3.10.6 Register Description ............................................................................................................................ 240
3.11 IOMMU ........................................................................................................................................................... 246
3.11.1 Overview ............................................................................................................................................. 246
3.11.2 Block Diagram ..................................................................................................................................... 246
3.11.3 Functional Description ........................................................................................................................ 247
3.11.4 Programming Guidelines..................................................................................................................... 257
3.11.5 Register List ......................................................................................................................................... 258
3.11.6 Register Description ............................................................................................................................ 262
3.12 RTC .................................................................................................................................................................. 332
3.12.1 Overview ............................................................................................................................................. 332
3.12.2 Block Diagram ..................................................................................................................................... 332
3.12.3 Functional Description ........................................................................................................................ 333
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3.12.4 Programming Guidelines..................................................................................................................... 337
3.12.5 Register List ......................................................................................................................................... 339
3.12.6 Register Description ............................................................................................................................ 340
Contents .......................................................................................................................................................................... 352
Figures ............................................................................................................................................................................. 353
4 Video and Graphics ................................................................................................................................................. 354
4.1 DE .................................................................................................................................................................... 354
4.2 DI ..................................................................................................................................................................... 356
4.3 G2D.................................................................................................................................................................. 357
4.4 Video Decoding ............................................................................................................................................... 358
4.4.1 Overview ............................................................................................................................................. 358
4.4.2 Block Diagram ..................................................................................................................................... 359
4.5 Video Encoding ............................................................................................................................................... 360
4.5.1 Overview ............................................................................................................................................. 360
4.5.2 Block Diagram ..................................................................................................................................... 360
Contents .......................................................................................................................................................................... 362
Figures ............................................................................................................................................................................. 363
Tables .............................................................................................................................................................................. 364
5 Video Output Interfaces.......................................................................................................................................... 365
5.1 TCON LCD ........................................................................................................................................................ 365
5.1.1 Overview ............................................................................................................................................. 365
5.1.2 Block Diagram ..................................................................................................................................... 366
5.1.3 Functional Description ........................................................................................................................ 366
5.1.4 Programming Guidelines..................................................................................................................... 378
5.1.5 Register List ......................................................................................................................................... 385
5.1.6 Register Description ............................................................................................................................ 387
5.2 TCON TV .......................................................................................................................................................... 420
5.2.1 Overview ............................................................................................................................................. 420
5.2.2 Functional Description ........................................................................................................................ 420
5.2.3 Register List ......................................................................................................................................... 420
5.2.4 Register Description ............................................................................................................................ 421
5.3 TV Encoder ...................................................................................................................................................... 433
5.3.1 Overview ............................................................................................................................................. 433
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5.3.2 Block Diagram ..................................................................................................................................... 433
5.3.3 Functional Description ........................................................................................................................ 433
5.3.4 Programming Guidelines..................................................................................................................... 435
5.3.5 Register List ......................................................................................................................................... 436
5.3.6 TVE_TOP Register Description ............................................................................................................ 438
5.3.7 TVE Register Description ..................................................................................................................... 442
5.4 MIPI DSI ........................................................................................................................................................... 462
5.4.1 Overview ............................................................................................................................................. 462
Contents .......................................................................................................................................................................... 463
Figures ............................................................................................................................................................................. 464
Tables .............................................................................................................................................................................. 465
6 Video Input Interfaces............................................................................................................................................. 467
6.1 CSIC ................................................................................................................................................................. 467
6.1.1 Overview ............................................................................................................................................. 467
6.1.2 Block Diagram ..................................................................................................................................... 467
6.1.3 Functional Description ........................................................................................................................ 468
6.1.4 Register List ......................................................................................................................................... 470
6.1.5 CCU Register Description .................................................................................................................... 474
6.1.6 CSIC Top Register Description ............................................................................................................. 475
6.1.7 Parser Register Description ................................................................................................................. 480
6.1.8 CSIC DMA Register Description ........................................................................................................... 501
6.2 TV Decoder ...................................................................................................................................................... 516
6.2.1 Overview ............................................................................................................................................. 516
6.2.2 Block Diagram ..................................................................................................................................... 516
6.2.3 Functional Description ........................................................................................................................ 517
6.2.4 Register List ......................................................................................................................................... 517
6.2.5 Register Description ............................................................................................................................ 519
Contents .......................................................................................................................................................................... 555
Figures ............................................................................................................................................................................. 556
Tables .............................................................................................................................................................................. 557
7 Memory................................................................................................................................................................... 558
7.1 SDRAM Controller (DRAMC) ........................................................................................................................... 558
7.2 SD/MMC Host Controller (SMHC) ................................................................................................................... 559
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7.2.1 Overview ............................................................................................................................................. 559
7.2.2 Block Diagram ..................................................................................................................................... 559
7.2.3 Functional Description ........................................................................................................................ 560
7.2.4 Programming Guidelines..................................................................................................................... 573
7.2.5 Register List ......................................................................................................................................... 578
7.2.6 Register Description ............................................................................................................................ 580
Contents .......................................................................................................................................................................... 611
Figures ............................................................................................................................................................................. 612
Tables .............................................................................................................................................................................. 614
8 Audio ....................................................................................................................................................................... 615
8.1 I2S/PCM........................................................................................................................................................... 615
8.1.1 Overview ............................................................................................................................................. 615
8.1.2 Block Diagram ..................................................................................................................................... 615
8.1.3 Functional Description ........................................................................................................................ 617
8.1.4 Programming Guidelines..................................................................................................................... 623
8.1.5 Register List ......................................................................................................................................... 625
8.1.6 Register Description ............................................................................................................................ 627
8.2 DMIC................................................................................................................................................................ 675
8.2.1 Overview ............................................................................................................................................. 675
8.2.2 Block Diagram ..................................................................................................................................... 675
8.2.3 Functional Description ........................................................................................................................ 675
8.2.4 Register List ......................................................................................................................................... 678
8.2.5 Register Description ............................................................................................................................ 678
8.3 OWA ................................................................................................................................................................ 693
8.3.1 Overview ............................................................................................................................................. 693
8.3.2 Block Diagram ..................................................................................................................................... 694
8.3.3 Functional Description ........................................................................................................................ 695
8.3.4 Register List ......................................................................................................................................... 702
8.3.5 Register Description ............................................................................................................................ 703
8.4 Audio Codec .................................................................................................................................................... 726
8.4.1 Overview ............................................................................................................................................. 726
8.4.2 Block Diagram ..................................................................................................................................... 727
8.4.3 Functional Description ........................................................................................................................ 727
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8.4.4 Programming Guidelines..................................................................................................................... 735
8.4.5 Register List ......................................................................................................................................... 736
8.4.6 Register Description ............................................................................................................................ 740
Contents .......................................................................................................................................................................... 815
Figures ............................................................................................................................................................................. 818
Tables .............................................................................................................................................................................. 822
9 Interfaces ................................................................................................................................................................ 824
9.1 TWI .................................................................................................................................................................. 824
9.1.1 Overview ............................................................................................................................................. 824
9.1.2 Block Diagram ..................................................................................................................................... 824
9.1.3 Functional Description ........................................................................................................................ 826
9.1.4 Programming Guidelines..................................................................................................................... 831
9.1.5 Register List ......................................................................................................................................... 834
9.1.6 Register Description ............................................................................................................................ 835
9.2 UART................................................................................................................................................................ 850
9.2.1 Overview ............................................................................................................................................. 850
9.2.2 Block Diagram ..................................................................................................................................... 850
9.2.3 Functional Description ........................................................................................................................ 851
9.2.4 Programming Guidelines..................................................................................................................... 857
9.2.5 Register List ......................................................................................................................................... 860
9.2.6 Register Description ............................................................................................................................ 862
9.3 SPI.................................................................................................................................................................... 891
9.3.1 Overview ............................................................................................................................................. 891
9.3.2 Block Diagram ..................................................................................................................................... 891
9.3.3 Functional Description ........................................................................................................................ 893
9.3.4 Programming Guidelines..................................................................................................................... 901
9.3.5 Register List ......................................................................................................................................... 904
9.3.6 Register Description ............................................................................................................................ 905
9.4 SPI_DBI ............................................................................................................................................................ 926
9.4.1 Overview ............................................................................................................................................. 926
9.4.2 Block Diagram ..................................................................................................................................... 926
9.4.3 Functional Description ........................................................................................................................ 928
9.4.4 Programming Guidelines..................................................................................................................... 948
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9.4.5 Register List ......................................................................................................................................... 956
9.4.6 Register Description ............................................................................................................................ 957
9.5 USB2.0 DRD ..................................................................................................................................................... 989
9.5.1 Overview ............................................................................................................................................. 989
9.5.2 Block Diagram ..................................................................................................................................... 990
9.5.3 Functional Description ........................................................................................................................ 990
9.6 USB2.0 HOST ................................................................................................................................................... 992
9.6.1 Overview ............................................................................................................................................. 992
9.6.2 Block Diagram ..................................................................................................................................... 992
9.6.3 Functional Description ........................................................................................................................ 993
9.6.4 Register List ......................................................................................................................................... 993
9.6.5 EHCI Register Description.................................................................................................................... 995
9.6.6 OHCI Register Description ................................................................................................................. 1012
9.7 GPIO .............................................................................................................................................................. 1034
9.7.1 Overview ........................................................................................................................................... 1034
9.7.2 Block Diagram ................................................................................................................................... 1034
9.7.3 Functional Description ...................................................................................................................... 1035
9.7.4 Register List ....................................................................................................................................... 1043
9.7.5 Register Description .......................................................................................................................... 1045
9.8 GPADC ........................................................................................................................................................... 1136
9.8.1 Overview ........................................................................................................................................... 1136
9.8.2 Block Diagram ................................................................................................................................... 1136
9.8.3 Functional Description ...................................................................................................................... 1137
9.8.4 Programming Guidelines................................................................................................................... 1138
9.8.5 Register List ....................................................................................................................................... 1140
9.8.6 Register Description .......................................................................................................................... 1141
9.9 TPADC............................................................................................................................................................ 1149
9.9.1 Overview ........................................................................................................................................... 1149
9.9.2 Functional Description ...................................................................................................................... 1149
9.9.3 Register List ....................................................................................................................................... 1155
9.9.4 Register Description .......................................................................................................................... 1156
9.10 PWM ............................................................................................................................................................. 1164
9.10.1 Overview ........................................................................................................................................... 1164
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9.10.2 Block Diagram ................................................................................................................................... 1164
9.10.3 Functional Description ...................................................................................................................... 1165
9.10.4 Programming Guidelines................................................................................................................... 1175
9.10.5 Register List ....................................................................................................................................... 1176
9.10.6 Register Description .......................................................................................................................... 1178
9.11 LEDC .............................................................................................................................................................. 1205
9.11.1 Overview ........................................................................................................................................... 1205
9.11.2 Block Diagram ................................................................................................................................... 1205
9.11.3 Functional Description ...................................................................................................................... 1206
9.11.4 Programming Guidelines................................................................................................................... 1210
9.11.5 Register List ....................................................................................................................................... 1215
9.11.6 Register Description .......................................................................................................................... 1215
9.12 EMAC ............................................................................................................................................................. 1226
9.12.1 Overview ........................................................................................................................................... 1226
9.12.2 Block Diagram ................................................................................................................................... 1226
9.12.3 Functional Description ...................................................................................................................... 1227
9.12.4 Programming Guidelines................................................................................................................... 1234
9.12.5 Register List ....................................................................................................................................... 1235
9.12.6 Register Description .......................................................................................................................... 1236
9.13 CIR Receiver .................................................................................................................................................. 1254
9.13.1 Overview ........................................................................................................................................... 1254
9.13.2 Block Diagram ................................................................................................................................... 1254
9.13.3 Functional Description ...................................................................................................................... 1255
9.13.4 Programming Guidelines................................................................................................................... 1259
9.13.5 Register List ....................................................................................................................................... 1260
9.13.6 Register Description .......................................................................................................................... 1260
9.14 CIR Transmitter ............................................................................................................................................. 1266
9.14.1 Overview ........................................................................................................................................... 1266
9.14.2 Block Diagram ................................................................................................................................... 1266
9.14.3 Functional Description ...................................................................................................................... 1267
9.14.4 Programming Guidelines................................................................................................................... 1269
9.14.5 Register List ....................................................................................................................................... 1270
9.14.6 Register Description .......................................................................................................................... 1270
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Contents ........................................................................................................................................................................ 1278
Figures ........................................................................................................................................................................... 1279
10 Security System ..................................................................................................................................................... 1280
10.1 Crypto Engine ................................................................................................................................................ 1280
10.1.1 Overview ........................................................................................................................................... 1280
10.1.2 Block Diagram ................................................................................................................................... 1281
10.1.3 Functional Description ...................................................................................................................... 1281
10.1.4 Programming Guidelines................................................................................................................... 1301
10.1.5 Register List ....................................................................................................................................... 1304
10.1.6 Register Description .......................................................................................................................... 1305
10.2 Security ID ..................................................................................................................................................... 1309
Appendix: Glossary ....................................................................................................................................................... 1310
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1 About This Document
1.1 Purpose and Scope
This document describes the features, logical structures, functions, operating modes, and related registers of
each module about F133. For details about the interface timings and related parameters, the pins, pin usages,
performance parameters, and package dimension, please refer to the F133_Datasheet.
1.2 Intended Audience
The document is intended for:
Design and maintenance personnel for electronics
Programmers in writing code or modifying the Allwinner provided code
1.3 Symbol Conventions
1.3.1 Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol Description
Indicates potential risk of injury or death exists if the instructions are not obeyed.
WARNING
Indicates potential risk of equipment damage, data loss, performance
CAUTION degradation, or unexpected results exists if the instructions are not obeyed.
Provides additional information to emphasize or supplement important points of
NOTE the main text.
1.3.2 Table Content Conventions
The table content conventions that may be found in this document are defined as follows.
Symbol Description
/ The cell is blank.
1.3.3 Reset Value Conventions
In the register definition tables:
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If other column value in a bit or multiple bits row is “/”, that this bit or these multiple bits are unused.
If the default value of a bit or multiple bits is “UDF”, that the default value is undefined.
1.3.4 Register Attributes
The register attributes that may be found in this document are defined as follows.
Symbol Description
R Read Only
R/W Read/Write
Read/Write-Automatic-Clear, clear the bit automatically when the operation of
R/WAC
complete. Writing 0 has no effect
R/WC Read/Write-Clear
R/W0C Read/Write 0 to Clear. Writing 1 has no effect
R/W1C Read/Write 1 to Clear. Writing 0 has no effect
R/W1S Read/Write 1 to Set. Writing 0 has no effect
W Write Only
1.3.5 Numerical System
The expressions of data capacity, frequency, and data rate are described as follows.
Type Symbol Value
1K 1024
Data capacity 1M 1,048,576
1G 1,073,741,824
1k 1000
Frequency, data rate 1M 1,000,000
1G 1,000,000,000
The expressions of addresses and data are described as follows.
Symbol Example Description
0x 0x0200, 0x79 Address or data in hexadecimal
0b 0b010, 0b00 000 111 Data or sequence in binary (register description is excluded.)
In data expression, X indicates 0 or 1.
X 00X, XX1 For example, 00X indicates 000 or 001 and XX1 indicates 001,
011, 101 or 111.
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Contents
2 Product Description .....................................................................................................................................................4
2.1 Overview ..............................................................................................................................................................4
2.1.1 Device Difference .....................................................................................................................................4
2.2 Features ...............................................................................................................................................................4
2.2.1 CPU Architecture ......................................................................................................................................4
2.2.2 Memory SubSystem .................................................................................................................................4
2.2.3 Video Engine ............................................................................................................................................6
2.2.4 Video and Graphics ..................................................................................................................................6
2.2.5 Video Output ............................................................................................................................................8
2.2.6 Video Input...............................................................................................................................................9
2.2.7 System Peripherals...................................................................................................................................9
2.2.8 Audio Interfaces .................................................................................................................................... 12
2.2.9 Security System ..................................................................................................................................... 15
2.2.10 External Peripherals .............................................................................................................................. 16
2.2.11 Package ................................................................................................................................................. 22
2.3 Block Diagram ................................................................................................................................................... 22
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2 Product Description
2.1 Overview
F133 is an advanced application processor designed for the video decoding platform. It integrates a 64-bit
processor with RISC CPU instruction architecture to provide the most efficient computing power. F133 supports
full format decoding such as H.265, H.264, MPEG-1/2/4, JPEG, VC1, and so on. And the independent hardware
encoder can encode in JPEG or MJPEG. Integrated multi ADCs/DACs and I2S/PCM/DMIC/OWA audio interfaces
can work seamlessly with the CPU to accelerate multimedia algorithms and provide the perfect voice
interaction solution. F133 supports rich display output interfaces to meet the requirements of the screen
display in differentiated markets. F133 can be used in network video machines, advertising machines, digital
photo frames, car MP5, and so on.
2.1.1 Device Difference
The F133 is configured with different sets of features in different devices. Table 2-1 shows the feature
differences across different devices.
Table 2-1 Device Feature Differences
Contents F133-A F133-B
CVBS IN No support Support
2.2 Features
2.2.1 CPU Architecture
RISC CPU
32 KB I-cache and 32 KB D-cache
2.2.2 Memory SubSystem
2.2.2.1 Boot ROM (BROM)
On-chip memory
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Supports system boot from the following devices:
- SD card
- eMMC
- SPI NOR Flash
- SPI NAND Flash
Supports mandatory upgrade process through USB and SD card
Supports GPIO pin and eFuse module to select the boot media type
2.2.2.2 SDRAM
Embedded with 64 MB DDR2
Supports clock frequency up to 533 MHz for DDR2
2.2.2.3 SMHC
Three SD/MMC host controller (SMHC) interfaces
The SMHC0 controls the devices that comply with the protocol Secure Digital Memory (SD mem-version
3.0)
The SMHC1 controls the device that complies with the protocol Secure Digital I/O (SDIO-version 3.0)
The SMHC2 controls the device that complies with the protocol Multimedia Card (eMMC-version 5.0)
Maximum performance:
- SDR mode 150 [email protected] V IO pad
- DDR mode 50 [email protected] V IO pad
- DDR mode 50 [email protected] V IO pad
Supports 1-bit or 4-bit data width
Supports block size of 1 to 65535 bytes
Internal 1024-Bytes RX FIFO and 1024-Bytes TX FIFO
Supports card insertion and removal interrupt
Supports hardware CRC generation and error detection
Supports descriptor-based internal DMA controller
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2.2.3 Video Engine
Video decoding
- H.265 [email protected] up to 1080p@60fps
- H.264 BP/MP/[email protected] up to 1080p@60fps
- H.263 BP up to 1080p@60fps
- MPEG-4 SP/ASP L5 up to 1080p@60fps
- MPEG-2 MP/HL up to 1080p@60fps
- MPEG-1 MP/HL up to 1080p@60fps
- Xvid up to 1080p@60fps
- Sorenson Spark up to 1080p@60fps
- WMV9/VC-1 SP/MP/AP up to 1080p@60fps
- MJPEG up to 1080p@30fps
Video encoding
- JPEG/MJPEG up to 1080p@60fps
- Supports input picture scaler up/down
2.2.4 Video and Graphics
2.2.4.1 Display Engine (DE)
Output size up to 2048 x 2048
Supports two alpha blending channels for main display and one channel for aux display
Supports four overlay layers in each channel, and has an independent scaler
Supports potter-duff compatible blending operation
Supports LBC buffer decoder
Supports dither output to TCON
Supports input format Semi-planar YUV422/YUV420/YUV411 and Planar YUV422/YUV420/YUV411,
ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565/palette
Supports SmartColor2.0 for excellent display experience
- Adaptive detail/edge enhancement
- Adaptive color enhancement
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- Adaptive contrast enhancement and fresh tone rectify
Supports write back for aux display
2.2.4.2 De-interlacer (DI)
Supports YUV420 (Planar/NV12/NV21) and YUV422 (Planar/NV16/NV61) data format
Supports video resolution from 32 x 32 to 2048 x 1280 pixel
Supports Inter-field interpolation/motion adaptive de-interlace method
Performance: module clock 600M for 1080p@60Hz YUV420
2.2.4.3 Graphic 2D (G2D)
Supports layer size up to 2048 x 2048 pixels
Supports pre-multiply alpha image data
Supports color key
Supports two pipes Porter-Duff alpha blending
Supports multiple video formats 4:2:0, 4:2:2, 4:1:1 and multiple pixel formats (8/16/24/32 bits graphics
layer)
Supports memory scan order option
Supports any format convert function
Supports 1/16× to 32× resize ratio
Supports 32-phase 8-tap horizontal anti-alias filter and 32-phase 4-tap vertical anti-alias filter
Supports window clip
Supports FillRectangle, BitBlit, StretchBlit and MaskBlit
Supports horizontal and vertical flip, clockwise 0/90/180/270 degree rotate for normal buffer
Supports horizontal flip, clockwise 0/90/270 degree rotate for LBC buffer
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2.2.5 Video Output
2.2.5.1 RGB and LVDS LCD
Supports RGB interface with DE/SYNC mode, up to 1920 x 1080@60fps
Supports serial RGB/dummy RGB interface, up to 800 x 480@60fps
Supports LVDS interface with dual link, up to 1920 x 1080@60fps
Supports LVDS interface with single link, up to 1366 x 768@60fps
Supports i8080 interface, up to 800 x 480@60fps
Supports BT656 interface for NTSC and PAL
RGB666 and RGB565 with dither function
Gamma correction with R/G/B channel independence
2.2.5.2 MIPI DSI
Compliance with MIPI DSI v1.01
Supports 4-lane MIPI DSI, up to 1280 x 720@60fps and 1920 x 1200@60fps resolution
Supports non-burst mode with sync pulse/sync event and burst mode
Supports pixel format: RGB888, RGB666, RGB666 loosely packed and RGB565
Supports continuous and non-continuous lane clock modes
Supports bidirectional communication of all generic commands in LP through data lane 0
Supports low power data transmission
Supports ULPS and escape modes
Hardware checksum capabilities
2.2.5.3 CVBS OUT
1-channel CVBS output
Supports NTSC and PAL format
Plug status auto detecting
10 bits DAC output
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2.2.6 Video Input
2.2.6.1 Parallel CSI
Supports 8-bit digital camera interface (RAW8/YUV422/YUV420)
Supports BT656, BT601 interface (YUV422)
Supports ITU-R BT.656 time-multiplexed format up to 2*1080p@30fps in DDR sample mode
Maximum pixel clock of 148.5 MHz
Supports de-interlacing for interlace video input
Supports conversion from YUV422 to YUV420, YUV422 to YUV400, YUV420 to YUV400
Supports horizontal and vertical flip
2.2.6.2 CVBS IN (Only for F133-B)
2-channel CVBS input and 1-channel CVBS decoder
Supports NTSC and PAL format
Supports YUV422/YUV420 format
With 1 channel 3D comb filter
Detection for signal locked and 625 lines
Programmable brightness, contrast, and saturation
10-bit video ADCs
2.2.7 System Peripherals
2.2.7.1 Timer
The timer module implements the timing and counting functions, which includes timer0, timer1,
watchdog, and audio video synchronization (AVS)
The timer0/timer1 is a 32-bit down counter. The timer0 and timer1 are completely consistent
The watchdog is used to transmit a reset signal to reset the entire system when an exception occurs in
the system
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The AVS is used to synchronize the audio and video. The AVS sub-block includes AVS0 and AVS1, which
are completely consistent
2.2.7.2 High Speed Timer (HSTimer)
The HSTimer module consists of HSTimer0 and HSTimer1. HSTimer0 and HSTimer1 are down counters that
implement timing and counting functions. They are completely consistent.
Configurable 56-bit down timer
Supports 5 prescale factors
The clock source is synchronized with AHB0 clock, much more accurate than other timers
Supports 2 working modes: periodic mode and single counting mode
Generates an interrupt when the count is decreased to 0
2.2.7.3 Platform-Level Interrupt Controller (PLIC)
Sampling, priority arbitration and distribution for external interrupt sources
The interrupt can be configured as machine mode and super user mode
Up to 256 interrupt source sampling, supporting level interrupt and pulse interrupt
32 levels of interrupt priority
Maintains independently the interrupt enable for each interrupt mode (machine/super user)
Maintains independently the interrupt threshold for each interrupt mode (machine/super user)
Configurable access permission for PLIC registers
2.2.7.4 DMAC
Up to 16-ch DMA
Provides 32 peripheral DMA requests for data reading and 32 peripheral DMA requests for data writing
Flexible data width of 8/16/32/64-bit
Programmable DMA burst length
Supports linear and IO address modes
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Supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral
Supports transfer with linked list
DRQ response includes waiting mode and handshake mode
DMA channel supports pause function
Memory devices support non-aligned transform
2.2.7.5 Clock Controller Unit (CCU)
8 PLLs
One on-chip RC oscillator
Supports one external 24 MHz DCXO and one external 32.768 kHz oscillator
Supports clock configuration and clock generation for corresponding modules
Supports software-controlled clock gating and software-controlled reset for corresponding modules
2.2.7.6 Thermal Sensor Controller (THS)
One thermal sensor located in CPU
Temperature accuracy: ±3°C from 0°C to +100°C, ±5°C from -25°C to +125°C
Averaging filter for thermal sensor reading
Supports over-temperature protection interrupt and over-temperature alarm interrupt
2.2.7.7 LDO Power
Integrated 2 LDOs (LDOA, LDOB)
LDOA: 1.8 V power output, LDOB: 1.35 V/1.5 V/1.8 V power output
LDOA for IO and analog module, LDOB for SDRAM
Input voltage is 2.4 V to 3.6 V
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2.2.7.8 RTC
Implements time counter and timing wakeup
Provides a 16-bit counter for counting day, 5-bit counter for counting hour, 6-bit counter for counting
minute, 6-bit counter for counting second
External connect a 32.768 kHz low-frequency oscillator for count clock
Timer frequency is 1 kHz
Configurable initial value by software anytime
Supports timing alarm, and generates interrupt and wakeup the external devices
8 general purpose registers for storing power-off information
2.2.7.9 I/O Memory Management Unit (IOMMU)
Supports virtual address to physical address mapping by hardware implementation
Supports VE, CSI, DE, G2D, DI parallel address mapping
Supports VE, CSI, DE, G2D, DI bypass function independently
Supports VE, CSI, DE, G2D, DI pre-fetch independently
Supports VE, CSI, DE, G2D, DI interrupt handing mechanism independently
Supports 2 levels TLB (level1 TLB for special using, and level2 TLB for sharing)
Supports TLB Fully cleared and Partially disabled
Supports trigger PTW behavior when TLB miss
Supports checking the permission
2.2.8 Audio Interfaces
2.2.8.1 Audio Codec
Two audio digital-to-analog converter (DAC) channels
- Supports 16-bit and 20-bit sample resolution
- 8 kHz to 192 kHz DAC sample rate
- 100 ± 2 dB SNR@A-weight, -85 ± 3 dB THD+N
One audio output:
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- One stereo headphone output: HPOUTL/R
Five audio analog-to-digital converter (ADC) channels
- Supports 16-bit and 20-bit sample resolution
- 8 kHz to 48 kHz ADC sample rate
- 95 ± 3dB SNR@A-weight, -80 ± 3dB THD+N
Three audio inputs:
- One differential microphone input: MICIN3P/3N, or one single-end microphone input: MICIN3P
- One stereo LINEIN input: LINEINL/R
- One stereo FMIN input: FMINL/R
Supports Dynamic Range Controller adjusting the DAC playback and ADC recording
One 128x20-bits FIFO for DAC data transmit, one 128x20-bits FIFO for ADC data receive
Programmable FIFO thresholds
Supports interrupts and DMA
Internal HPLDO output for HPVCC
Internal ALDO output for AVCC
2.2.8.2 I2S/PCM
Two I2S/PCM external interfaces (I2S1, I2S2) for connecting external power amplifier and MIC ADC
Compliant with standard Philips Inter-IC sound (I2S) bus specification
- Left-justified, Right-justified, PCM mode, and Time Division Multiplexing (TDM) format
- Programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)
Transmit and Receive data FIFOs
- Programmable FIFO thresholds
- 128 depth x 32-bit width TXFIFO and 64 depth x 32-bit width RXFIFO
Supports multiple function clock
- Clock up to 24.576 MHz Data Output of I2S/PCM in Master mode (Only if the IO PAD and Peripheral
I2S/PCM satisfy Timing Parameters)
- Clock up to 12.288 MHz Data Input of I2S/PCM in Master mode
Supports TX/RX DMA slave interface
Supports multiple application scenarios
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- Up to 16 channels (fs = 48 kHz) which has adjustable width from 8-bit to 32-bit
- Sample rate from 8 kHz to 384 kHz (CHAN = 2)
- 8-bit u-law and 8-bit A-law companded sample
Supports master/slave mode
2.2.8.3 DMIC
Supports maximum 8 digital PDM microphones
Supports sample rate from 8 kHz to 48 kHz
2.2.8.4 One Wire Audio (OWA)
One OWA TX and one OWA RX
Compliance with S/PDIF interface
IEC-60958 and IEC-61937 transmitter and receiver functionality
- IEC-60958 supports 16-bit, 20-bit, and 24-bit data formats
- IEC-61937 uses the IEC-60958 series for the conveying of non-linear PCM bit streams, each sub-frame
transmits 16-bit
TXFIFO and RXFIFO
- One 128×24bits TXFIFO and one 64×24bits RXFIFO for audio data transfer
- Programmable FIFO thresholds
Supports TX/RX DMA slave interface
Supports multiple function clock
- Separate clock for OWA TX and OWA RX
- The clock of TX function includes 24.576 MHz and 22.579 MHz frequency
- The clock of RX function includes 24.576*8MHz frequency
Supports hardware parity on TX/RX
- Hardware parity checking on the receiver
- Hardware parity generation on the transmitter
Supports channel status capture on the receiver
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Supports channel sample rate capture on the receiver
Supports insertion detection for the receiver
Supports channel status insertion for the transmitter
Supports interrupts and DMA
2.2.9 Security System
2.2.9.1 Crypto Engine (CE)
Supports Symmetrical algorithm for encryption and decryption: AES, DES, TDES
- Supports ECB, CBC, CTS, CTR, CFB, OFB mode for AES
- Supports 128/192/256-bit key for AES
- Supports ECB, CBC, CTR mode for DES/TDES
Supports Hash algorithm for tamper proofing: MD5, SHA, HMAC
- Supports SHA1, SHA224, SHA256, SHA384, SHA512 for SHA
- Supports HMAC-SHA1, HMAC-SHA256 for HMAC
- Supports multi-package mode for MD5/SHA1/SHA224/SHA256/SHA384/SHA512
Supports Asymmetrical algorithm for signature verification: RSA
- RSA supports 512/1024/2048-bit width
Supports 160-bit hardware PRNG with 175-bit seed
Supports 256-bit hardware TRNG
Internal DMA controller for data transfer with memory
2.2.9.2 Security ID (SID)
Supports 2 Kbits eFuse
Backup eFuse information by using SID_SRAM
Burning the key to the SID
Reading the key use status in the SID
Loading the key to the CE
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2.2.10 External Peripherals
2.2.10.1 USB DRD
One USB 2.0 DRD (USB0), with integrated USB 2.0 analog PHY
Complies with USB2.0 Specification
Supports USB Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s), and Low-Speed (LS, 1.5 Mbit/s)
- Supports only 1 USB Root port shared between EHCI and OHCI
Supports USB Device function
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s)
- Supports bi-directional endpoint0 (EP0) for Control transfer
- Up to 10 user-configurable endpoints (EP1+, EP1-, EP2+, EP2-, EP3+, EP3-, EP4+, EP4-, EP5+, EP5-) for
Bulk transfer, Isochronous transfer and Interrupt transfer
- Up to (8 KB + 64 Bytes) FIFO for all EPs (including EP0)
- Supports interface to an external Normal DMA controller for every EP
Supports an internal DMA controller for data transfer with memory
Supports High-Bandwidth Isochronous & Interrupt transfers
Automated splitting/combining of packets for Bulk transfers
Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral modes
Includes automatic ping capabilities
Soft connect/disconnect function
Performs all transaction scheduling in hardware
Power optimization and power management capabilities
Device and host controller share a 8K SRAM and a physical PHY
2.2.10.2 USB HOST
One USB 2.0 HOST (USB1), with integrated USB 2.0 analog PHY
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Complies with USB2.0 Specification
Supports USB2.0 Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) and Low-Speed (LS, 1.5 Mbit/s)
Device
- Supports only 1 USB Root port shared between EHCI and OHCI
An internal DMA Controller for data transfer with memory
2.2.10.3 EMAC
One EMAC interface for connecting external Ethernet PHY
10/100/1000 Mbit/s Ethernet port with RGMII and RMII interfaces
Compliant with IEEE 802.3-2002 standard
Supports both full-duplex and half-duplex operation
Provides the management data input/output (MDIO) interface for PHY device configuration and
management with configurable clock frequencies
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
Supports a variety of flexible address filtering modes
Separate 32-bit status returned for transmission and reception packets
Optimization for packet-oriented DMA transfers with frame delimiters
- Supports linked-list descriptor list structure
- Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each
descriptor can transfer up to 4 KB of data
- Comprehensive status reporting for normal operation and transfers with errors
4 KB TXFIFO for transmission packets and 16 KB RXFIFO for reception packets
Programmable interrupt options for different operational conditions
2.2.10.4 UART
Up to 6 UART controllers (UART0, UART1, UART2, UART3, UART4, UART5)
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UART0, UART4, UART5: 2-wire; UART1, UART2, UART3: 4-wire
Compatible with industry-standard 16450/16550 UARTs
Supports IrDA-compatible slow infrared (SIR) format
Two separate FIFOs: one is RX FIFO, and the other is TX FIFO
- Each of them is 64 bytes (For UART0)
- Each of them is 256 bytes (For UART1, UART2, UART3, UART4, and UART5)
The working reference clock is from the APB bus clock
- Speed up to 4 Mbit/s with 64 MHz APB clock
- Speed up to 1.5 Mbit/s with 24 MHz APB clock
5 to 8 data bits for RS-232 characters, or 9 bits RS-485 format
1, 1.5 or 2 stop bits
Programmable parity (even, odd, or no parity)
Supports TX/RX DMA slave controller interface
Supports software/hardware flow control
Supports RX DMA Master interface (Only for UART1)
Supports auto-flow by using CTS & RTS (Only for UART1/2/3)
2.2.10.5 Two Wire Interface (TWI)
Up to 4 TWI controllers (TWI0, TWI1, TWI2, TWI3)
Compliant with I2C bus standard
Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s)
Supports 7-bit and 10-bit device addressing modes
Supports master mode or slave mode
Master mode features:
- Supports the bus arbitration in the case of multiple master devices
- Supports clock synchronization and bit and byte waiting
- Supports packet transmission and DMA
Slave mode features:
- Interrupt on address detection
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The TWI controller includes one TWI engine and one TWI driver. And the TWI driver supports packet
transmission and DMA mode when TWI works in master mode
2.2.10.6 SPI and SPI_DBI
Up to 2 SPI controllers (SPI0, SPI1)
The SPI0 only supports SPI mode; The SPI1 supports SPI mode and display bus interface (DBI) mode
SPI mode:
- Full-duplex synchronous serial interface
- Master/slave configurable
- Mode0 to Mode3 are supported for both transmit and receive operations
- 8-bit wide by 64-entry FIFO for both transmit and receive data
- Polarity and phase of the Chip Select (SPI-CS) and SPI Clock (SPI-CLK) are configurable
- Supports 3-wire/4-wire SPI
- Supports programmable serial data frame length: 1-bit to 32-bit
- Supports Standard SPI, Dual-Output/Dual-Input SPI, Dual IO SPI, Quad-Output/Quad-Input SPI
DBI mode:
- Supports DBI Type C 3 Line/4 Line Interface Mode
- Supports 2 Data Lane Interface Mode
- Supports RGB111/444/565/666/888 video format
- Maximum resolution of RGB666 240 x 320@30Hz with single data lane
- Maximum resolution of RGB888 240 x 320@60Hz or 320 x 480@30Hz with dual data lane
- Supports Tearing effect
- Supports software flexible control video frame rate
2.2.10.7 CIR Receiver (CIR_RX)
One CIR_RX interface (IR-RX)
Full physical layer implementation
Supports NEC format infra data
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Supports CIR for remote control or wireless keyboard
64x8 bits FIFO for data buffer
Sample clock up to 1 MHz
2.2.10.8 CIR Transmitter (CIR_TX)
One CIR_TX interface (IR-TX)
Supports arbitrary wave generator
Configurable carrier frequency
Supports handshake mode and waiting mode of DMA
128 bytes FIFO for data buffer
2.2.10.9 PWM
Supports 8 independent PWM channels (PWM0 to PWM7)
- Supports PWM continuous mode output
- Supports PWM pulse mode output, and the pulse number is configurable
- Output frequency range: 0 to 24 MHz or 100 MHz
- Various duty-cycle: 0% to 100%
- Minimum resolution: 1/65536
Supports 4 complementary pairs output
- PWM01 pair (PWM0 + PWM1), PWM23 pair (PWM2 + PWM3), PWM45 pair (PWM4 + PWM5),
PWM67 pair (PWM6 + PWM7)
- Supports dead-zone generator, and the dead-zone time is configurable
Supports 4 group of PWM channel output for controlling stepping motors
- Supports any plural channels to form a group, and output the same duty-cycle pulse
- In group mode, the relative phase of the output waveform for each channel is configurable
Supports 8 channels capture input
- Supports rising edge detection and falling edge detection for input waveform pulse
- Supports pulse-width measurement for input waveform pulse
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2.2.10.10 General Purpose ADC (GPADC)
1-ch Successive approximation register (SAR) analog-to-digital converter (ADC)
12-bit sampling resolution and 8-bit precision
64 FIFO depth of data register
Power reference voltage: AVCC, analog input voltage range: 0 to AVCC
Maximum sampling frequency up to 1 MHz
Supports three operation modes: single conversion mode, continuous conversion mode, burst conversion
mode
2.2.10.11 Touch Panel ADC (TPADC)
12 bit SAR type A/D converter
Configurable sample frequency up to 1 MHz
One 32x12 FIFO for storing A/D conversion result
Supports DMA slave interface
Supports 4-wire resistive touch panel input detection
- Supports pen down detection with programmable sensitivity
- Supports single touch coordinate measurement
- Supports dual touch detection
- Supports touch pressure measurement with programmable threshold
- Supports median and averaging filter for noise reduction
- Supports X and Y coordinate exchange function
Supports Aux ADC with up to 4 channels
2.2.10.12 LEDC
LEDC is used to control the external intelligent control LED lamp
Configurable LED output high/low level width
Configurable LED reset time
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LEDC data supports DMA configuration mode and CPU configuration mode
Maximum 1024 LEDs serial connect
LED data transfer rate up to 800 kbit/s
2.2.11 Package
eLQFP128, 14 mm x 14 mm x 1.4 mm
2.3 Block Diagram
Figure 2-1 shows the system block diagram of the F133.
Figure 2-1 F133 System Block Diagram
Video Input RISC CPU Connectivity
CVBS IN USB2.0 DRD
I-cache 32 KB D-cache 32 KB
USB2.0 HOST
Parallel CSI
SDIO3.0
Video Output Display Engine Internal System SPI x2
(Supports SPI Nand/Nor Flash)
MIPI DSI DE CCU
TWI x4
RGB DI PLIC
UART x6
DMA
Dual link LVDS G2D
100M/1000M EMAC
Thermal Sensor
CVBS OUT Video Engine
Timer GPADC (1-ch)
Video Decoding
Audio H.265/H.264
High Speed Timer TPADC (4-ch)
Audio Codec Video Encoding
JPEG/MJPEG IOMMU PWM (8-ch)
I2S/PCM x2
Memory Security System LEDC
DMIC SIP 64 MB DDR2 Crypto Engine
CIR TX
OWA IN/OUT SD3.0/eMMC5.0 SID CIR RX
Note: F133-A does not support CVBS IN interface.
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Figure 2-2 shows the intelligent speaker solution of the F133.
Figure 2-2 F133 Intelligent Speaker Solution
SPEAKER SPEAKER
USB USB Analog
Power PA
Port Port KEYs Headphone
detection
WIFI/BT
HP HP
(XR819s) SDIO1 USB0 USB1 TPADC GPADC0
OUTL OUTR
UART1 LINEINL/R
SD Card SMHC0 FMINL/R
FM
SPI NOR/NAND SiP 64MB MICIN3N/P
SPI0/SMHC2
Flash DDR2
RISC CPU
24 MHz Internal TWI3
DCXO
Crystal Reset Circuit
PWM2
Thermal
32.768 kHz OSC RTC Sensor
Crystal 32K CIR-RX IR
5V
Adapter CVBS OUT TV
Internal
Charge IC LDO 1.8 V LDOs
I2S1–2 TWI2
Li-BAT DCDC 3.3 V Power UART0 TWI1 PWM3–6 PWM7 RGB/LVDS/DSI
Supply Panel
DCDC 0.9 V RGB/LVDS/
UART2–5 TWI0 PWM0–1
DSI
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Contents
3 System ....................................................................................................................................................................... 30
3.1 Memory Mapping ............................................................................................................................................. 30
3.2 RISC System ....................................................................................................................................................... 33
3.2.1 Overview ............................................................................................................................................... 33
3.2.2 Block Diagram ....................................................................................................................................... 33
3.2.3 Register List ........................................................................................................................................... 34
3.3 Clock Controller Unit (CCU) ............................................................................................................................... 44
3.3.1 Overview ............................................................................................................................................... 44
3.3.2 Block Diagram ....................................................................................................................................... 44
3.3.3 Functional Description .......................................................................................................................... 45
3.3.4 Programming Guidelines....................................................................................................................... 50
3.3.5 Register List ........................................................................................................................................... 56
3.3.6 Register Description .............................................................................................................................. 59
3.4 BROM System.................................................................................................................................................. 144
3.4.1 Overview ............................................................................................................................................. 144
3.4.2 Functional Description ........................................................................................................................ 144
3.5 System Configuration ...................................................................................................................................... 152
3.5.1 Overview ............................................................................................................................................. 152
3.5.2 Register List ......................................................................................................................................... 152
3.5.3 Register Description ............................................................................................................................ 152
3.6 Timer ............................................................................................................................................................... 160
3.6.1 Overview ............................................................................................................................................. 160
3.6.2 Block Diagram ..................................................................................................................................... 161
3.7 High Speed Timer ............................................................................................................................................ 179
3.7.1 Overview ............................................................................................................................................. 179
3.7.2 Block Diagram ..................................................................................................................................... 179
3.7.3 Functional Description ........................................................................................................................ 179
3.7.4 Programming Guidelines..................................................................................................................... 183
3.7.5 Register List ......................................................................................................................................... 183
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3.7.6 Register Description ............................................................................................................................ 184
3.8 Platform-Level Interrupt Controller (PLIC) ...................................................................................................... 191
3.8.1 Overview ............................................................................................................................................. 191
3.8.2 Functional Description ........................................................................................................................ 191
3.8.3 Register List ......................................................................................................................................... 197
3.8.4 Register Description ............................................................................................................................ 198
3.9 Direct Memory Access Controller (DMAC)...................................................................................................... 202
3.9.1 Overview ............................................................................................................................................. 202
3.9.2 Block Diagram ..................................................................................................................................... 202
3.9.3 Functional Description ........................................................................................................................ 203
3.9.4 Programming Guidelines..................................................................................................................... 212
3.9.5 Register List ......................................................................................................................................... 215
3.9.6 Register Description ............................................................................................................................ 216
3.10 Thermal Sensor Controller (THS) .................................................................................................................... 236
3.10.1 Overview ............................................................................................................................................. 236
3.10.2 Block Diagram ..................................................................................................................................... 236
3.10.3 Functional Description ........................................................................................................................ 236
3.10.4 Programming Guidelines..................................................................................................................... 238
3.10.5 Register List ......................................................................................................................................... 240
3.10.6 Register Description ............................................................................................................................ 240
3.11 IOMMU ........................................................................................................................................................... 246
3.11.1 Overview ............................................................................................................................................. 246
3.11.2 Block Diagram ..................................................................................................................................... 246
3.11.3 Functional Description ........................................................................................................................ 247
3.11.4 Programming Guidelines..................................................................................................................... 257
3.11.5 Register List ......................................................................................................................................... 258
3.11.6 Register Description ............................................................................................................................ 262
3.12 RTC .................................................................................................................................................................. 332
3.12.1 Overview ............................................................................................................................................. 332
3.12.2 Block Diagram ..................................................................................................................................... 332
3.12.3 Functional Description ........................................................................................................................ 333
3.12.4 Programming Guidelines..................................................................................................................... 337
3.12.5 Register List ......................................................................................................................................... 339
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3.12.6 Register Description ............................................................................................................................ 340
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Figures
Figure 3-1 RISC System Block Diagram................................................................................................................................ 34
Figure 3-2 CCU Block Diagram ............................................................................................................................................ 44
Figure 3-3 System Bus Tree ................................................................................................................................................. 45
Figure 3-4 Module Clock Generation .................................................................................................................................. 46
Figure 3-5 PLL Distribution .................................................................................................................................................. 47
Figure 3-6 BROM Process .................................................................................................................................................. 147
Figure 3-7 CPU0 Hotplug Process Diagram ....................................................................................................................... 148
Figure 3-8 Mandatory Upgrade Process ........................................................................................................................... 149
Figure 3-9 USB FEL Process ............................................................................................................................................... 150
Figure 3-10 Timer Block Diagram ...................................................................................................................................... 161
Figure 3-11 Block Diagram for the Timer .......................................................................................................................... 161
Figure 3-12 Block Diagram for the Watchdog ................................................................................................................... 163
Figure 3-13 Block Diagram for the AVS ............................................................................................................................. 165
Figure 3-14 HSTimer Block Diagram ................................................................................................................................. 179
Figure 3-15 Typical Application for HSTimer..................................................................................................................... 180
Figure 3-16 HSTimer Initialization Process........................................................................................................................ 182
Figure 3-17 DMAC Block Diagram ..................................................................................................................................... 202
Figure 3-18 DMAC Typical Application Diagram ............................................................................................................... 204
Figure 3-19 DMA Descriptor ............................................................................................................................................. 206
Figure 3-20 DMA Chain Transfer ....................................................................................................................................... 208
Figure 3-21 Workflow of the DMAC Handshake Mode .................................................................................................... 211
Figure 3-22 DMAC Transfer Process ................................................................................................................................. 213
Figure 3-23 THS Block Diagram ......................................................................................................................................... 236
Figure 3-24 Thermal Sensor Timing Requirement ............................................................................................................ 237
Figure 3-25 Thermal Sensor Controller Interrupt Source ................................................................................................. 237
Figure 3-26 THS Initial Process .......................................................................................................................................... 238
Figure 3-27 IOMMU Block Diagram .................................................................................................................................. 247
Figure 3-28 Internal Switch Process .................................................................................................................................. 251
Figure 3-29 VA-PA Switch Process .................................................................................................................................... 252
Figure 3-30 Invalid TLB Address Range ............................................................................................................................. 253
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Figure 3-31 Level1 Page Table Format .............................................................................................................................. 255
Figure 3-32 Level1 Page Table Format .............................................................................................................................. 255
Figure 3-33 Read/Write Permission Control ..................................................................................................................... 256
Figure 3-34 RTC Block Diagram ......................................................................................................................................... 333
Figure 3-35 RTC Application Diagram ............................................................................................................................... 334
Figure 3-36 RTC Clock Tree ............................................................................................................................................... 334
Figure 3-37 RTC Counter ................................................................................................................................................... 335
Figure 3-38 RTC 1 kHz Counter Step Structure ................................................................................................................. 336
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Tables
Table 3-1 PLL Typical Application ........................................................................................................................................ 48
Table 3-2 PLL Features ........................................................................................................................................................ 49
Table 3-3 Recommended Values for Configuration Factors of PLL_AUDIO1 ...................................................................... 51
Table 3-4 BOOT_MODE Setting......................................................................................................................................... 144
Table 3-5 GPIO Boot Select Configuration ........................................................................................................................ 145
Table 3-6 Groups of eFuse_Boot_Select ........................................................................................................................... 146
Table 3-7 eFuse Boot Select Setting .................................................................................................................................. 146
Table 3-8 Fast Boot Select Setting .................................................................................................................................... 151
Table 3-9 Interrupt Sources .............................................................................................................................................. 191
Table 3-10 DMAC Sub-blocks ............................................................................................................................................ 203
Table 3-11 DMA DRQ Type ............................................................................................................................................... 204
Table 3-12 Source/Destination Address Distribution ....................................................................................................... 207
Table 3-13 THS Information in the SID .............................................................................................................................. 238
Table 3-14 Correspondence Relation between Master and Module ............................................................................... 247
Table 3-15 Relation between ACI and Domain ................................................................................................................. 256
Table 3-16 RTC External Signals ........................................................................................................................................ 333
Table 3-17 RTC Counter Changing Range.......................................................................................................................... 336
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3 System
3.1 Memory Mapping
Module Address (It is for Cluster CPU) Size
BROM & SRAM
SRAM A1 0x0002 0000---0x0002 7FFF 32 KB
VE_SYS Related
VE 0x01C0 E000---0x01C0 FFFF 8 KB
SP0 (SYS Domain)
GPIO 0x0200 0000---0x0200 07FF 2 KB
PWM 0x0200 0C00---0x0200 0FFF 1 KB
CCU 0x0200 1000---0x0200 1FFF 4 KB
CIR_TX 0x0200 3000---0x0200 33FF 1 KB
LEDC 0x0200 8000---0x0200 83FF 1 KB
GPADC 0x0200 9000---0x0200 93FF 1 KB
THS 0x0200 9400---0x0200 97FF 1 KB
TPADC 0x0200 9C00---0x0200 9FFF 1 KB
IOMMU 0x0201 0000---0x0201 FFFF 64 KB
Audio Codec 0x0203 0000---0x0203 0FFF 4 KB
DMIC 0x0203 1000---0x0203 13FF 1 KB
I2S1 0x0203 3000---0x0203 3FFF 4 KB
I2S2 0x0203 4000---0x0203 4FFF 4 KB
OWA 0x0203 6000---0x0203 63FF 1 KB
TIMER 0x0205 0000---0x0205 0FFF 4 KB
SP1 (SYS Domain)
UART0 0x0250 0000---0x0250 03FF 1 KB
UART1 0x0250 0400---0x0250 07FF 1 KB
UART2 0x0250 0800---0x0250 0BFF 1 KB
UART3 0x0250 0C00---0x0250 0FFF 1 KB
UART4 0x0250 1000---0x0250 13FF 1 KB
UART5 0x0250 1400---0x0250 17FF 1 KB
TWI0 0x0250 2000---0x0250 23FF 1 KB
TWI1 0x0250 2400---0x0250 27FF 1 KB
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Module Address (It is for Cluster CPU) Size
TWI2 0x0250 2800---0x0250 2BFF 1 KB
TWI3 0x0250 2C00---0x0250 2FFF 1 KB
SH0 (SYS Domain)
SYSCTRL 0x0300 0000---0x0300 0FFF 4 KB
DMAC 0x0300 2000---0x0300 2FFF 4 KB
SID 0x0300 6000---0x0300 6FFF 4 KB
HSTIMER 0x0300 8000---0x0300 8FFF 4 KB
DCU 0x0301 0000---0x0301 FFFF 64 KB
CE_NS 0x0304 0000---0x0304 07FF 2 KB
CE_KEY_SRAM 0x0304 1000---0x0304 1FFF 4 KB (only CE access)
MSI+MEMC 0x0310 2000---0x0330 1FFF 2 MB
SH2 (SYS Domain)
SMHC0 0x0402 0000---0x0402 0FFF 4 KB
SMHC1 0x0402 1000---0x0402 1FFF 4 KB
SMHC2 0x0402 2000---0x0402 2FFF 4 KB
SPI0 0x0402 5000---0x0402 5FFF 4 KB
SPI1 0x0402 6000---0x0402 6FFF 4 KB
USB0 0x0410 0000---0x041F FFFF 1 MB
USB1 0x0420 0000---0x042F FFFF 1 MB
EMAC 0x0450 0000---0x0450 FFFF 64 KB
VIDEO_OUT_SYS Related (SYS Domain)
DE 0x0500 0000---0x053F FFFF 4 MB
DI 0x0540 0000---0x0540 FFFF 64 KB
G2D 0x0541 0000---0x0544 FFFF 256 KB
DSI 0x0545 0000---0x0545 1FFF 8 KB
DISPLAY_TOP 0x0546 0000---0x0546 0FFF 4 KB
TCON_LCD0 0x0546 1000---0x0546 1FFF 4 KB
TCON_TV0 0x0547 0000---0x0547 0FFF 4 KB
TVE_TOP 0x0560 0000---0x0560 3FFF 16 KB
TV Encoder 0x0560 4000---0x0560 7FFF 16 KB
VIDEO_IN_SYS Related (SYS Domain)
CSI 0x0580 0000---0x05BF FFFF 4 MB
TVD_TOP 0x05C0 0000---0x05C0 0FFF 4 KB
TV Decoder 0x05C0 1000---0x05C0 1FFF 4 KB
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Module Address (It is for Cluster CPU) Size
RISC_SYS Related (SYS Domain)
64 KB
RISC_BROM 0x0600 0000---0x0600 FFFF RISC Core accesses the brom address:
0x00000000---0x0000FFFF
RISC_CFG 0x0601 0000---0x0601 0FFF 4 KB
RISC_WDG 0x0601 1000---0x0601 1FFF 4 KB
RISC_TIMESTAMP 0x0601 2000---0x0601 2FFF 4 KB
APBS0
CIR_RX 0x0704 0000---0x0704 03FF 1 KB
AHBS
RTC 0x0709 0000---0x0709 03FF 1 KB
CPUX Related
CPU_SYS_CFG 0x0810 0000---0x0810 03FF 1 KB
TimeStamp_STA 0x0811 0000---0x0811 0FFF 4 KB
TimeStamp_CTRL 0x0812 0000---0x0812 0FFF 4 KB
IDC 0x0813 0000---0x0813 0FFF 4 KB
C0_CPUX_CFG 0x0901 0000---0x0901 03FF 1 KB
C0_CPUX_MBIST 0x0902 0000---0x0902 0FFF 4 KB
DRAM Space (SYS Domain)
DRAM SPACE 0x4000 0000---0xBFFF FFFF 2 GB
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3.2 RISC System
3.2.1 Overview
The RISC system includes RISC IP core and related peripheral devices (RISC_CFG, RISC_TIMESTAMP, Watchdog,
PSENSOR, BROM, and so on), which are interconnected by BUS Matrix.
The RISC system has the following features:
RISC 64GCV instruction architecture
The 5-level single engine executes the pipeline in sequence
Instruction and data cache of the first level Harvard, 32 KB I-cache + 32 KB D-cache, 64 B cacheline
Instruction high-cache can configure parity, and data high-cache can configure ECC or parity
Two-level TLB memory management unit to realize the virtual-real address translation and memory
management
Hardware automatic detection
Supports AXI4.0 128-bit master interface
Supports core-internal interrupt (CLINT) and interrupt controller (PLIC)
Floating-point process unit
Vector execution unit
3.2.2 Block Diagram
The following figure shows the block diagram of RISC system.
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Figure 3-1 RISC System Block Diagram
L4_CONN
AHB 32
GRAYDEC C906 P-SENSOR
AXI 128
0x4000_0000
AXI bridge AXI2MBUS GMB_TOP
0x0 128
X2H_AXI
X2H_AHB
AHB 32
AHB Matrix
AHB 32 AHB 32 AHB 32
AHB2APB
MSGBOX BROM(64KB)
RISCV_CFG WDG
GRAYENC TIMERSTAMP
AHB 32 GMB 128
riscv_clk 1GHz L4_CONN MSI
mclk 400MHz
hclk 200MHz MEMC
DDRPHY
3.2.3 Register List
Module Name Base Address
RISC_CFG 0x06010000
Register Name Offset Description
RISC_STA_ADD0_REG 0x0004 RISC Start Address0 Register
RISC_STA_ADD1_REG 0x0008 RISC Start Address1 Register
RF1P_CFG_REG 0x0010 RF1P Configuration Register
ROM_CFG_REG 0x001C ROM Configuration Register
WAKEUP_EN_REG 0x0020 Wakeup Enable Register
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Register Name Offset Description
WAKEUP_MASK0_REG 0x0024 Wakeup Mask0 Register
WAKEUP_MASK1_REG 0x0028 Wakeup Mask1 Register
WAKEUP_MASK2_REG 0x002C Wakeup Mask2 Register
WAKEUP_MASK3_REG 0x0030 Wakeup Mask3 Register
WAKEUP_MASK4_REG 0x0034 Wakeup Mask4 Register
TS_TMODE_SEL_REG 0x0040 Timestamp Test Mode Select Register
SRAM_ADDR_TWIST_REG 0x0044 SRAM Address Twist Register
WORK_MODE_REG 0x0048 Work Mode Register
RETITE_PC0_REG 0x0050 Retire PC0 Register
RETITE_PC1_REG 0x0054 Retire PC1 Register
IRQ_MODE0_REG 0x0060 IRQ Mode0 Register
IRQ_MODE1_REG 0x0064 IRQ Mode1 Register
IRQ_MODE2_REG 0x0068 IRQ Mode2 Register
IRQ_MODE3_REG 0x006C IRQ Mode3 Register
IRQ_MODE4_REG 0x0070 IRQ Mode4 Register
RISC_AXI_PMU_CTRL 0x0104 RISC AXI PMU Control Register
RISC_AXI_PMU_PRD 0x0108 RISC AXI PMU Period Register
RISC_AXI_PMU_LAT_RD 0x010C RISC AXI PMU Read Latency Register
RISC_AXI_PMU_LAT_WR 0x0110 RISC AXI PMU Write Latency Register
RISC_AXI_PMU_REQ_RD 0x0114 RISC AXI PMU Read Request Register
RISC_AXI_PMU_REQ_WR 0x0118 RISC AXI PMU Write Request Register
RISC_AXI_PMU_BW_RD 0x011C RISC AXI PMU Read Bandwidth Register
RISC_AXI_PMU_BW_WR 0x0120 RISC AXI PMU Write Bandwidth Register
3.2.4 Register Description
3.2.4.1 0x0004 RISC Start Address0 Register (Default Value: 0x0000_0000)
The 0x0004 register and 0x0008 register are grouped into a 40-bit address which is the running PC address
after RISC releases reset. Before releasing reset, this register should be configured. This register does support
dynamic configuration.
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Offset: 0x0004 Register Name: RISC_STA_ADD0_REG
Bit Read/Write Default/Hex Description
STA_ADD_L
31:0 R/W 0x00000000 Start Address Low 32-bit
The bit0 is fixed as 0 and can not be written.
3.2.4.2 0x0008 RISC Start Address1 Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: RISC_STA_ADD1_REG
Bit Read/Write Default/Hex Description
31:8 / / /
STA_ADD_H
7:0 R/W 0x00
Start Address High 8-bit.
3.2.4.3 0x0010 RF1P Configuration Register (Default Value: 0x0000_0013)
Offset: 0x0010 Register Name: RF1P_CFG_REG
Bit Read/Write Default/Hex Description
31:8 / / /
RF1P_CFG
7:0 R/W 0x13
RF1P Configuration
3.2.4.4 0x001C ROM Configuration Register (Default Value: 0x0000_0002)
Offset: 0x001C Register Name: ROM_CFG_REG
Bit Read/Write Default/Hex Description
31:8 / / /
ROM_CFG
7:0 R/W 0x02
ROM Configuration
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3.2.4.5 0x0020 Wakeup Enable Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: WAKEUP_EN_REG
Bit Read/Write Default/Hex Description
31:1 / / /
WP_EN
0 R/W 0x0
Wakeup Enable
3.2.4.6 0x0024 Wakeup Mask0 Register (Default Value: 0x0000_0000)
The 0x0024 to 0x0034 registers corresponds to the wakeup enable bits of 160 interrupts. These wakeup enable
bits are disabled by default. When some interrupt needs to be waken-up, the corresponding bit needs to be
set to 1.
Offset: 0x0024 Register Name: WAKEUP_MASK0_REG
Bit Read/Write Default/Hex Description
WP_MASK0
31:0 R/W 0x00000000
Wakeup Mask0
3.2.4.7 0x0028 Wakeup Mask1 Register (Default Value: 0x0000_0000)
The 0x0024 to 0x0034 registers corresponds to the wakeup enable bits of 160 interrupts. These wakeup enable
bits are disabled by default. When some interrupt needs to be waken-up, the corresponding bit needs to be
set to 1.
Offset: 0x0028 Register Name: WAKEUP_MASK1_REG
Bit Read/Write Default/Hex Description
WP_MASK1
31:0 R/W 0x00000000
Wakeup Mask1
3.2.4.8 0x002C Wakeup Mask2 Register (Default Value: 0x0000_0000)
The 0x0024 to 0x0034 registers corresponds to the wakeup enable bits of 160 interrupts. These wakeup enable
bits are disabled by default. When some interrupt needs to be waken-up, the corresponding bit needs to be
set to 1.
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Offset: 0x002C Register Name: WAKEUP_MASK2_REG
Bit Read/Write Default/Hex Description
WP_MASK2
31:0 R/W 0x00000000
Wakeup Mask2
3.2.4.9 0x0030 Wakeup Mask3 Register (Default Value: 0x0000_0000)
The 0x0024 to 0x0034 registers corresponds to the wakeup enable bits of 160 interrupts. These wakeup enable
bits are disabled by default. When some interrupt needs to be waken-up, the corresponding bit needs to be
set to 1.
Offset: 0x0030 Register Name: WAKEUP_MASK3_REG
Bit Read/Write Default/Hex Description
WP_MASK3
31:0 R/W 0x00000000
Wakeup Mask3
3.2.4.10 0x0034 Wakeup Mask4 Register (Default Value: 0x0000_0000)
The 0x0024 to 0x0034 registers corresponds to the wakeup enable bits of 160 interrupts. These wakeup enable
bits are disabled by default. When some interrupt needs to be waken-up, the corresponding bit needs to be
set to 1.
Offset: 0x0034 Register Name: WAKEUP_MASK4_REG
Bit Read/Write Default/Hex Description
WP_MASK4
31:0 R/W 0x00000000
Wakeup Mask4
3.2.4.11 0x0040 Timestamp Test Mode Select Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: TS_TMODE_SEL_REG
Bit Read/Write Default/Hex Description
31:1 / / /
TS_TEST_MODE_EN
Timestamp Test Mode Enable
0 R/W 0x0
0: Normal Mode
1: Test Mode
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3.2.4.12 0x0044 SRAM Address Twist Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: SRAM_ADDR_TWIST_REG
Bit Read/Write Default/Hex Description
SRAM_TS_KF
31:16 W UDF SRAM Twist Keyfield
The bit 0 can be written only if this key field is written by 0x16AA.
15:1 / / /
SRAM_ADDR_TS_FG.
SRAM Address Twist Flag.
When this bit is set up, the RISC_BROM area would become
0 R/W 0x0 invisible, and the start address of SRAM A1 would be twisted into
0x0, the original start address of SRAM A1 is 0x0002 0000. After
the address has been twisted, RISC reads data from 0x0002000
to 0x0002ffff as same as from 0x0 to 0xffff.
3.2.4.13 0x0048 Work Mode Register (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: WORK_MODE_REG
Bit Read/Write Default/Hex Description
31:2 / / /
WM_STA
Work Mode Status
00: Normal Mode
1:0 R 0x0
01: Low Power Mode
10: Debug Mode
11: Reserved
3.2.4.14 0x0050 Retire PC0 Register (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: RETITE_PC0_REG
Bit Read/Write Default/Hex Description
RT_PC_L
31:0 R 0x0 Retire PC[31:0]
It indicates the current retiring instruction PC[31:0].
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3.2.4.15 0x0054 Retire PC1 Register (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: RETITE_PC1_REG
Bit Read/Write Default/Hex Description
RT_SIG
Retire Signal
31 R 0x0
0: The current period has not the retired instruction
1: The current period has the retired instruction
30:8 / / /
RT_PC_H
7:0 R 0x0 Retire PC[39:31]
It indicates the current retiring instruction PC[39:31].
3.2.4.16 0x0060 IRQ Mode0 Register (Default Value: 0x0000_0000)
Offset: 0x0060 Register Name: IRQ_MODE0_REG
Bit Read/Write Default/Hex Description
IRQ_MD0
IRQ Mode0
31:0 R/W 0x00000000
0: High-level trigger
1: Rising edge trigger
3.2.4.17 0x0064 IRQ Mode1 Register (Default Value: 0x0000_0000)
Offset: 0x0064 Register Name: IRQ_MODE1_REG
Bit Read/Write Default/Hex Description
IRQ_MD1
IRQ Mode1
31:0 R/W 0x00000000
0: High-level trigger
1: Rising edge trigger
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3.2.4.18 0x0068 IRQ Mode2 Register (Default Value: 0x0000_0000)
Offset: 0x0068 Register Name: IRQ_MODE2_REG
Bit Read/Write Default/Hex Description
IRQ_MD2
IRQ Mode2
31:0 R/W 0x00000000
0: High-level trigger
1: Rising edge trigger
3.2.4.19 0x006C IRQ Mode3 Register (Default Value: 0x0000_0000)
Offset: 0x006C Register Name: IRQ_MODE3_REG
Bit Read/Write Default/Hex Description
IRQ_MD3
IRQ Mode3
31:0 R/W 0x00000000
0: High-level trigger
1: Rising edge trigger
3.2.4.20 0x0070 IRQ Mode4 Register (Default Value: 0x0000_0000)
Offset: 0x0070 Register Name: IRQ_MODE4_REG
Bit Read/Write Default/Hex Description
IRQ_MD4
IRQ Mode4
31:0 R/W 0x00000000
0: High-level trigger
1: Rising edge trigger
3.2.4.21 0x0104 RISC AXI PMU Control Register (Default Value: 0x0000_0000)
Offset: 0x0104 Register Name: RISC_AXI_PMU_CTRL
Bit Read/Write Default/Hex Description
31:2 / / /
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Offset: 0x0104 Register Name: RISC_AXI_PMU_CTRL
Bit Read/Write Default/Hex Description
PMU_CLR
PMU Clear
1 WC 0x0
0: No operation
1: PMU cleared
PMU_EN
PMU Enable
0 R/W 0x0
0: PMU disabled
1: PMU enabled
3.2.4.22 0x0108 RISC AXI PMU Period Register (Default Value: 0x0000_0000)
Offset: 0x0108 Register Name: RISC_AXI_PMU_PRD
Bit Read/Write Default/Hex Description
PRD
31:0 R/W 0x0 Monitor period
Suggest that the field is in units of 1 us (1 ms).
3.2.4.23 0x010C RISC AXI PMU Read Latency Register (Default Value: 0x0000_0000)
Offset: 0x10C Register Name: RISC_AXI_PMU_LAT_RD
Bit Read/Write Default/Hex Description
LAT_RD
31:0 R 0x0
Monitor the total latency of read-channel durning period
3.2.4.24 0x0110 RISC AXI PMU Write Latency Register (Default Value: 0x0000_0000)
Offset: 0x0110 Register Name: RISC_AXI_PMU_LAT_WR
Bit Read/Write Default/Hex Description
LAT_WR
31:0 R 0x0
Monitor the total latency of write-channel durning period
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3.2.4.25 0x0114 RISC AXI PMU Read Request Register (Default Value: 0x0000_0000)
Offset: 0x0114 Register Name: RISC_AXI_PMU_REQ_RD
Bit Read/Write Default/Hex Description
REQ_RD
31:0 R 0x0 Monitor the total command numbers of read-channel durning
period
3.2.4.26 0x0118 RISC AXI PMU Write Request Register (Default Value: 0x0000_0000)
Offset: 0x0118 Register Name: RISC_AXI_PMU_REQ_WR
Bit Read/Write Default/Hex Description
REQ_WR
31:0 R 0x0 Monitor the total command numbers of write-channel durning
period
3.2.4.27 0x011C RISC AXI PMU Read Bandwidth Register (Default Value: 0x0000_0000)
Offset: 0x011C Register Name: RISC_AXI_PMU_BW_RD
Bit Read/Write Default/Hex Description
BW_RD
31:0 R 0x0
Monitor the total data (KB) of read-channel durning period
3.2.4.28 0x0120 RISC AXI PMU Write Bandwidth Register (Default Value: 0x0000_0000)
Offset: 0x0120 Register Name: RISC_AXI_PMU_BW_WR
Bit Read/Write Default/Hex Description
BW_WR
31:0 R 0x0
Monitor the total data (KB) of write-channel durning period
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3.3 Clock Controller Unit (CCU)
3.3.1 Overview
The clock controller unit (CCU) controls the PLL configurations and most of the clock generation, division,
distribution, synchronization, and gating. The input signals of the CCU include the external clock for the
reference frequency (24 MHz). The outputs from the CCU are mostly clocks to other blocks in the system.
The CCU includes the following features:
8 PLLs
Bus source and divisions
Clock output control
Configuring modules clock
Bus clock gating
Bus software reset
3.3.2 Block Diagram
The following figure shows the functional block diagram of the CCU.
Figure 3-2 CCU Block Diagram
APB0
REG
CCU
Gating
BGR
Reset
DCXO 24 MHz
PLLs ...
CLK0 ...
CLK1 LEDC_CLK
... MUX GATE DIV
CPUX_CLK
CLKn
RC 16 MHz
External 32 KHz CLK_CTRL
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3.3.3 Functional Description
3.3.3.1 System Bus Tree
The system buses include advanced high-performance buses (AHBs), advanced peripheral buses (APBs), and
MBUS.
All devices mounted at the bus should use the related bus clocks, and the gating signals for the bus are from
the CCU module.
The following figure shows the diagram of the System Bus Tree.
Figure 3-3 System Bus Tree
AHB clock -SYSCTRL
-MSGBOX
-HSTimer
APB0 clock
AHB_DECODE(SLV0)—AHB0
AHB_DECODE(SLV1)—AHB1
AHB_DECODE(SLV2)—AHB2
APB_DECODE(SLV0)—APB0
APB_DECODE(SLV1)—APB1
-Timer -SID
-GPIO -DCU
APB1 clock -PWM -GIC
-CE -SMHC
-CCU -camera_subsys
-UART -MSI -SPI
MBUS clock -Audio_subsys -video_subsy
-TWI -------------------- -USBDRD
-INTC -display_subsys STBY_subsystem
-CPU_SUBSYS_CFG -EMAC
-OWA -RISC_subsys
-IR_TX -TSTAMP_STU
-GPADC -TSTAMP_CTRL
-IDC SYSRTC
-C0_CPUx_CFG (AON)
BROM -C0_CPUx_mbist
(APB:32bits) (APB:32bits) (AHB:32bits) (AHB:32bits) (AHB:32bits)
H2P_ASYNC H2P_ASYNC H2H_SYNC H2H_SYNC H2H_SYNC
SH04 SP00 SP01 SH00 SH02 SH03
L4_CONN (AHB)
PH02/PH03 PH05 PH06 PH04 SH01
(AHB:32bits) (AHB:32bits) (AHB:32bits) (AHB:32bits) (AHB:32bits)
AHB_DECODER
Display_subsys
TEST_SYS USB0
Camera_ SMHC0
RISC_subsys USB1
Video_ subsys DE (SDCard) SRAM
I/D cache: subsys DI DMAC SHMC1 CE (32 KB)
DCU SMHC2
32 KB G2D (SDIO)
D130 CVBSIN/ RBG/LVDS/DSI/ (eMMC)
BIST CSI CVBSOUT EMAC
Master
MBUS MBUS MBUS MBUS AHB AHB MBUS
(MBUS:64bits) (MBUS:64bits)
(MBUS:64bits) (MBUS:64bits)
(GMB:128bits) (3*MBUS:64bits) (2xAHB:32bits) (AHB:32bits)
(MBUS:128bits) (MBUS:64bits) (4xAHB:32bits)
L3_MAIN_CONNECT(MSI)
SMC
HIF_SYNC
(HIF:128bits)
DDRC
DDR_PHY
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3.3.3.2 Module Clock Generation
The following figure describes module clock generation.
Figure 3-4 Module Clock Generation
normal mux
cpupll peripll1x clkdiv3/3 peripll_div syscpus
ddrpll
vepll
clk mux video0pll 4x/2x/1x
peripll1x GATE div24 GATE emac_clck25m_fanout PAD
video1pll 4x/2x/1x
audio0pll8x
glitch free mux clk16m_rc clkdi3/8 ce_clk2m_rc ce
audio0pll4x ccu_clkdiv2 audio0pll2x
PLL
hosc div750 clk32k_hosc_d clk32k_hosc timer
dft mux ccu_clkdiv2 audio0pll1x
audio1pll_div2
apb0_clk GATE pclk_reg ccu
audio1pll_div5
occ occ in sys
peripll2x ccu_clkdiv2
ccu_clkdiv2 peripll1x hosc GATE dbgsys_clk_t
dbgsys_clk
test_clk
occ occ in ccu peripll_800m ccu_clkdiv2 periplldiv4
load
test_clk occ (sh0_hclk) ve
ve
hosc rstsyn/ccu/sdrctl/spi0-1
GATE usb_clk48m[1] clk32k
clk16m_rc clkdiv2xy clkdiv2y psi_clk hclk_occ ce/cpu_sys/dmac/hstimer/mbox/sh0/
periplldiv4 occ
USB48M peripll1x test_clk sysctl/spinlock/psi/sid
GEN
GATE usb_clk48m[0]
hosc
DIV4 clk_12m_usb hosc rstsyn/ccu
clk32k
psi_clk
clkdiv5xy clkdiv2y apb0_clk (sp0_pclk) dmic/i2s1-2/iommu/pwm/owa/timer/
occ
clk12m_usb0_s peripll1x test_clk gpio/sp0/irtx/tpadc/audiocodec/gpadc
hosc DIV2
clk_12m GATE usb_clk12m[0]
hosc rstsyn
clk32k
clk32k
clk16m_rc clkdiv5xy clkdiv2y apb1_clk (sp1_pclk)
psi_clk occ twi0-3/uart0-5/sp1
peripll1x test_clk
clk_12m_usb clk12m_usb1_s
ve/g2d
clk_12m
GATE usb_clk12m[1] hdr_clk
clk32k mbus_clk mclk
(ddr)
clk16m_rc occ ce/dmac/iommu/msi/cpu_sys
usb_clk_gen test_clk
BUS_CLK
hosc
peripll2x peripll1x
video0pll4x video0pll2x GATE clkdiv4 dsi_clk
video1pll4x GATE clkdiv5 de_clk de/dpss_de_logic occ
video1pll2x dsi
audio1pll_div2 audio1pll_div2 test_clk dsi
video0pll1x
peripll2x video0pll4x
video0pll4x video1pll1x
video1pll4x GATE clkdiv5 di_clk occ tcon_lcd
di video1pll4x GATE clkdiv4 clkdiv2y tconlcd_clk
audio1pll_div2 test_clk di
peripll2x
g2d audio1pll_div2
peripll2x
video0pll4x GATE clkdiv5 g2d_clk occ video0pll1x
video1pll4x g2d video0pll4x
audio1pll_div2 test_clk g2d
video1pll1x dpss_tv_logic
GATE clkdiv4 clkdiv2y tcontv_clk
video1pll4x
peripll2x
hosc audio1pll_div2
peripll2x GATE clkdiv4 clkdiv2y ce_clk
occ ce video0pll1x
peripll1x test_clk video0pll4x
video1pll1x CVBS OUT
GATE clkdiv4 clkdiv2y tve_clk
vepll
video1pll4x
GATE clkdiv5 ve_clk occ peripll2x
peripll2x ve audio1pll_div2
test_clk ve
hosc
video0pll1x
hosc GATE avs_clk timer GATE clkdiv5 tvd_clk CVBS IN
video1pll1x
peripll1x
hosc csi
peripll1x peripll2x
peripll2x GATE clkdiv4 clkdiv2y smhc0_clk sd0
video0pll2x GATE clkdiv4 csi_clk occ
audio1pll_div2 csi
video1pll2x test_clk csi
hosc
peripll1x hosc
GATE clkdiv4 clkdiv2y smhc1_clk sd1 peripll1x
peripll2x video0pll1x PAD
audio1pll_div2 GATE clkdiv5 csi_master_clk
video1pll1x
hosc audio1pll_div2
peripll1x audio1pll_div5
peripll2x GATE clkdiv4 clkdiv2y smhc2_clk sd2
peripll_800m hosc
audio1pll_div2 GATE tpadc_clk tpadc
audio0pll1x
hosc spi0
peripll1x
peripll2x GATE clkdiv4 clkdiv2y spi0_clk occ audio0pll1x
audio1pll_div2 spi0 audio1pll_div2 GATE clkdiv5 clkdiv2y audiocode1x_dac_clk adda
test_clk spi0
audio1pll_div5 audio1pll_div5
hosc spi1
peripll1x audio0pll1x
peripll2x GATE clkdiv4 clkdiv2y spi1_clk occ
audio1pll_div2 spi1 audio1pll_div2 GATE clkdiv5 clkdiv2y audiocode1x_adc_clk adda
audio1pll_div5 test_clk spi1
audio1pll_div5
hosc
GATE clkdiv4 clkdiv2y irtx_clk irtx hosc
peripll1x GATE clkdiv4 clkdiv2y ledc_clk ledc
peripll1x
audio0pll1x
audio0pll4x
audio1pll_div2 GATE clkdiv5 clkdiv2y owa_tx_clk owa audio0pll1x
audio1pll_div5 audio0pll4x GATE clkdiv5 clkdiv2y i2s1_clk i2s1
audio1pll_div2
peripll1x audio1pll_div5
audio1pll_div2 GATE clkdiv5 clkdiv2y owa_rx_clk occ audio0pll1x
audio1pll_div5 owa audio0pll4x
test_clk owa clkdiv5 i2s2
audio1pll_div2 GATE clkdiv2y i2s2_clk
audio1pll_div5
audio0pll1x audio0pll4x
audio1pll_div2 clkdiv5 dmic peripll1x
GATE clkdiv2y dmic_clk audio1pll_div2 GATE clkdiv5 clkdiv2y i2s2_asrc_clk occ
audio1pll_div5 i2s2
audio1pll_div5 test_clk i2s2
hosc
clk32k risc ddrpll
clk16m_rc audio1pll_div2
peripll_800m GATE clkdiv5xy risc_clk occ peripll2x GATE clkdiv2xy clkdiv2y dram_clk ddr
peripll1x
risc
risc
cpupll test_clk peripll_800m
audio1pll_div2
clk32k test_clk
1
irrx_clk irrx
GATE clkdiv5 clkdiv2y 0
clk_24m
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3.3.3.3 PLL Distribution
The following figure shows the block diagram of the PLL distribution.
Figure 3-5 PLL Distribution
USB0/1、CSI、Timer、GPIO、PWM、GPADC、AUDIO_CODEC
RISC CPU、RISC CPU_AXI、PSI、AHB、APB0、APB1、CE、AVS、SMHC0/1/2、SID、
EMAC、SPI0/1、IR_TX、DSI、TV Decoder、TPADC
DCXO 24 MHz
PLL_CPU RISC CPU
PLL_DDR DRAM、MBUS
DE、DI、G2D、CE、VE、SMHC0/1/2、SPI0/1、DSI、
PLL_PERI(2X)
TCON_LCD、TCON_TV、TV Encoder、CSI
PSI、AHB、APB0、APB1、CE、DI、SMHC0/1/2、SPI0/1、
PLL_PERI(1X)
IR_TX、I2S2_ASRC、TV Decoder、OWA_RX、DSI、RISC CPU
PLL_PERI_800M SMHC2、RISC CPU
PLL_VIDEO0(4X) DE、DI、G2D、TCON_LCD、TCON_TV、TV Encoder、RISC CPU
PLL_VIDEO0(1X) TCON_LCD、TCON_TV、TV Encoder、TV Decoder、CSI_MST
PLL_VIDEO1(4X) DE、DI、G2D、TCON_LCD、TCON_TV、TV Encoder、RISC CPU
PLL_VIDEO1(1X) TCON_LCD、TCON_TV、TV Encoder、TV Decoder、CSI_MST
PLL_VE VE
PLL_AUDIO0(1X) I2S1/2、OWA_TX、DMIC、AUDIO_CODEC、TPADC
PLL_AUDIO0(4X) I2S1/2、I2S2_ASRC、OWA_TX、DMIC、AUDIO_CODEC
DE、DI、G2D、SMHC0/1/2、SPI0/1、I2S1/2、I2S2_ASRC、
PLL_AUDIO1(DIV2) OWA_TX、OWA_RX、DMIC、AUDIO_CODEC、 RISC CPU、
TCON_LCD、TCON_TV、TV Encoder、CSI_MST
SPI0/1、I2S1/2、I2S2_ASRC、OWA_TX、OWA_RX、DMIC、
PLL_AUDIO1(DIV5)
AUDIO_CODEC、CSI_MST
External 32k
M
RISC CPU、RISC CPU_AXI、PSI、APB0、APB1、IR_TX、SMHC0/1、USB0/1、
RC16M U RTC_32K
X TIMER、GPIO、AUDIO_CODEC
/512
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Table 3-1 PLL Typical Application
PLL Type Application Module Notes
PLL_CPU RISC CPU Support DVFS
Support spread spectrum
PLL_DDR MBUS, SDRAM
No support linear FM
DE, DI, G2D, CE, VE, SMHC0/1/2, SPI0/1,
PLL_PERI(2X) DSI, TCON_LCD, TCON_TV, TV Encoder, No support dynamic FM
CSI
PSI, AHB, APB0, APB1, CE, DI,
PLL_PERI(1X) SMHC0/1/2, SPI0/1, IR_TX, I2S2_ASRC, No support dynamic FM
TV Decoder, OWA_RX, DSI, RISC CPU
PLL_PERI(800M) SMHC2, RISC CPU No support dynamic FM
DE, DI, G2D, TCON_LCD, TCON_TV,
PLL_VIDEO0(4X) No support DVFS
TV Encoder, RISC CPU
TCON_LCD, TCON_TV, TV Encoder,
PLL_VIDEO0(1X) No support DVFS
TV Decoder, CSI_MST
DE, DI, G2D, TCON_LCD, TCON_TV,
PLL_VIDEO1(4X) No support DVFS
TV Encoder, RISC CPU
TCON_LCD, TCON_TV, TV Encoder,
PLL_VIDEO1(1X) No support DVFS
TV Decoder, CSI_MST
PLL_VE VE No support dynamic FM
I2S1/2, OWA_TX, DMIC, AUDIO_CODEC,
PLL_AUDIO0 No support DVFS
TPADC
I2S1/2, I2S2_ASRC, OWA_TX, DMIC,
PLL_AUDIO0(4X) No support DVFS
AUDIO_CODEC
DE, DI, G2D, SMHC0/1/2, SPI0/1, I2S1/2,
I2S2_ASRC, OWA_TX, OWA_RX, DMIC,
PLL_AUDIO1(DIV2) No support DVFS
AUDIO_CODEC, RISC CPU, TCON_LCD,
TCON_TV, TV Encoder, CSI_MST
SPI0/1, I2S1/2, I2S2_ASRC, OWA_TX,
PLL_AUDIO1(DIV5) OWA_RX, DMIC, AUDIO_CODEC, No support DVFS
CSI_MST
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3.3.3.4 PLL Features
The following table shows the PLL features.
Table 3-2 PLL Features
Stable Operating Actual Operating Spread Linear Rate Lock
PLL Default Frequency Pk-Pk
Frequency Frequency Spectrum FM Control Time
288 MHz to 3.0 GHz
PLL_CPU 288 MHz to 1.8 GHz 408 MHz No Yes No < 200 ps 1.5 ms
(24*N)
24.576 MHz
180 MHz to 3.0 GHz 22.5792 MHz
PLL_AUDIO0 24.576 MHz Yes No No < 200 ps 500 us
(24MHz*N.x/M1/M0/P) 24.576*4 MHz
22.5792*4 MHz
Integer mode:
1/2x: 1.536 GHz
Fvco/Div 1/5x: 614.4 MHz
PLL_AUDIO1 180 MHz to 3.0 GHz Yes No No < 200 ps 500 us
(Div: 1–8) Decimal mode:
1/2x: 1.1179648 GHz
1/5x: 471.8592 MHz
180 MHz to 3.2 GHz Fvco/Div 1/2x: 1.2 GHz
PLL_PERI Yes No No < 200 ps 500 us
(24*N/M1/M0) (Div:1–8) 1/3x: 800 MHz
1x: 297 MHz
252 MHz to 3.0 GHz 192 MHz to
PLL_Video0(4X) 2x:594 MHz Yes No No < 200 ps 500 us
(24*N/M) 2400 MHz
4x:1188 MHz
1x: 297 MHz
252 MHz to 3.0 GHz
PLL_Video1(4X) 192 MHz to 2400 MHz 2x: 594 MHz Yes No No < 200 ps 500 us
(24*N/M)
4x: 1188 MHz
180 MHz to 3.0 GHz
PLL_VE 192 MHz to 600 MHz 432 MHz Yes No No < 200 ps 500 us
(24*N/M1/M0)
200 MHz to 800 MHz
( < 200 ps)
180 MHz to 3.0 GHz 800 MHz to 1.3 GHz
PLL_DDR 192 MHz to 2.0 GHz 432 MHz Yes No No 2 ms
(24*N/M1/M0) (< 140 ps)
1.3 GHz to 2.0 GHz
(< 100 ps)
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3.3.4 Programming Guidelines
3.3.4.1 Configuring the Frequency of PLL_CPUX
The frequency configuration formula of PLL_CPUX:
PLL_CPUX = 24 MHz*N/P
The parameter N is the frequency-doubling factor of PLL. The next parameter configuration can proceed after
the PLL relock. The parameter P is a digital post-frequency-division factor, which can be dynamically switched
in real-time, without affecting the normal work of PLL.
NOTE
PLL_CPUX supports dynamic frequency adjustment (modifying the value of N). However, for the system
stability, to configure the frequency of the PLL_CPUX from a higher value to a lower one, switch the clock
source of the CPU to another clock whose frequency is not higher than the current one first, and configure
PLL_CPUX to the target low frequency, and then switch the clock source of the CPU back to PLL_CPUX.
Follow the steps below to adjust the frequency of PLL_CPUX:
Step 1 Before you configure PLL_CPUX, switch the clock source of CPU to PLL_PERI(1X).
Step 2 Modify the parameters N and P of PLL_CPUX.
Step 3 Write the PLL Lock Enable bit (bit[29]) of PLL_CPU_CTRL_REG to 0 and then to 1.
Step 4 Wait for the Lock bit (bit[28]) of PLL_CPU_CTRL_REG to change to 1.
Step 5 Switch the clock source of the CPU to PLL_CPUX.
3.3.4.2 Configuring the Frequency of PLL_AUDIO
NOTE
PLL_AUDIO includes PLL_AUDIO0 and PLL_AUDIO1.
The frequency configuration formula of PLL_AUDIO:
PLL_AUDIO0 = 24 MHz*N/M0/M1/P/4
PLL_AUDIO1 = 24 MHz*N/M
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PLL_AUDIO does not support dynamic adjustment because changing any parameter of N, M0, M1, and P will
affect the normal work of PLL, and the PLL will need to be relocked.
Generally, PLL_AUDIO only needs two frequency points: 24.576*4 MHz or 22.5792*4 MHz. For these two
frequencies, there are usually special recommended matching factors. To implement the desired frequency
point of PLL_AUDIO, you need to use the decimal frequency-division function, so follow the steps below:
Step 1 Configure the N, M0, M1 and P factors.
Step 2 Configure PLL_AUDIOx Control Register[PLL_SDM_ENABLE] to 1.
Step 3 Configure PLL_AUDIOx Pattern0 Control Register to enable the digital spread spectrum.
Step 4 Write PLL_AUDIOx Control Register[Lock Enable] to 0 and then to 1.
Step 5 Wait for PLL_AUDIOx Control Register[Lock] to 1.
NOTE
When the P factor of PLL_AUDIO is an odd number, the clock output is an unequal-duty-cycle signal.
The recommended values for configuration factors of PLL_AUDIO1 are as follows.
Table 3-3 Recommended Values for Configuration Factors of PLL_AUDIO1
Frequency- PLL
Clock Source VCO Post Frequency- Actual Operating
Mode doubling Output Divisor Description
(MHz) (MHz) Division Frequency (MHz)
N (MHz)
4 384
8 192 Provide clock
2 1536 source for
16 96 peripherals
Integer
24 128 3072
divider ……
For audio-
5 614.4 25 24.576 related
modules
2 589.824
Provides clock
Decimal 3 393.216 source for
24 98.304 2359.296 2 1179.648
divider 6 196.608 peripheral
devices
12 98.304
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Frequency- PLL
Clock Source VCO Post Frequency- Actual Operating
Mode doubling Output Divisor Description
(MHz) (MHz) Division Frequency (MHz)
N (MHz)
For audio-
48 24.576 related
modules
5 471.8592
3.3.4.3 Configuring the Frequency of General PLLs
Step 1 Make sure the PLL is enabled. If not, refer to section 3.3.4.4 Enabling the PLL to enable the PLL.
Step 2 Configure the PLL_OUTPUT_ENABLE bit (bit[27]) of the PLL control register as 0 to disable the output
gate of the PLL because general PLLs are unavailable in the process of frequency modulation.
Step 3 Configure the N and M factors. (It is not suggested to configure M1 factor)
Step 4 Write the LOCK_ENABLE bit (bit[29]) of the PLL control register to 0 and then to 1.
Step 5 Wait for the LOCK bit (bit[28]) of the PLL control register to 1.
Step 6 Configure PLL_OUTPUT_ENABLE bit (bit[27]) of the PLL control register to 1.
3.3.4.4 Enabling the PLL
Follow the steps below to enable the PLL:
Step 1 Configure the N, M, and P factors of the PLL control register.
Step 2 Write the PLL_ENABLE bit and the LDO_EN bit of the PLL control register to 1, write the
PLL_OUTPUT_GATE bit of the PLL control register to 0.
Step 3 Write the LOCK_ENABLE bit of the PLL control register to 1.
Step 4 Wait for the status of the Lock to change to 1.
Step 5 Delay 20 us.
Step 6 Write the PLL_OUTPUT_GATE bit of the PLL control register to 1 and then the PLL will be available.
3.3.4.5 Disabling the PLL
Follow the steps below to disable the PLL:
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Step 1 Write the PLL_ENABLE bit (bit[31]) and the LDO_EN bit of the PLL control register to 0.
Step 2 Write the LOCK_ENABLE bit (bit[29]) of the PLL control register to 0.
CAUTION
In the normal use of PLLs, it is unsuggested to enable and disable the PLLs frequently. Turning on and off the
PLLs will cause mutual interference between PLLs, which will affect the stability of the system. When the
clock is unnecessary, you can write 0 to the PLL_OUTPUT_EN bit of the PLL control register to disable the
output gate of the PLL, instead of writing 0 to the Enable bit to disable the PLL.
3.3.4.6 Configuring Bus Clock
The bus clock supports dynamic switching, but the process of switching needs to follow the following two rules.
From a higher frequency to a lower frequency: switch the clock source first, and then set the frequency
division factor;
From a lower frequency to a higher frequency: configure the frequency division factor first, and then
switch the clock source.
3.3.4.7 Configuring Module Clock
For the Bus Gating Reset register of a module, the reset bit is de-asserted first, and then the clock gating bit is
enabled to avoid potential problems caused by the asynchronous release of the reset signal.
For all module clocks except the DDR clock, configure the clock source and frequency division factor first, and
then release the clock gating (that is, set to 1). For the configuration order of the clock source and frequency
division factor, follow the rules below:
With the increasing of the clock source frequency, configure the frequency division factor before the clock
source;
With the decreasing of the clock source frequency, configure the clock source before the frequency
division factor.
3.3.4.8 Implementing Spread Spectrum
The spread spectrum technology is to convert a narrowband signal into a wideband signal. It helps to reduce
the effect of electromagnetic interference (EMI) associated with the fundamental frequency of the signal.
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For the general PLL frequency, the calculation formula is as follows:
N 1 X
f 24MHz, 0 X 1
P M0 1 M1 1
Where,
P is the frequency division factor of module or PLL;
M0 is the post-frequency division factor of PLL;
M1 is the pre-frequency division factor of PLL;
N is the frequency doubling factor of PLL;
X is the amplitude coefficient of the spread spectrum.
The parameters N, P, M1, and M0 are for the frequency division.
When M1 = 0, M0 = 0, and P = 1 (no frequency division), the calculation formula of PLL frequency can be
simplified as follows:
f N 1 X 24MHz, 0 X 1
[ f1 , f2 ] N 1 [ X1 , X2 ] 24MHz
SDM_ BOT 217 X1
WAVE_STEP 217 X2 X1 /24MHz / PREQ 2
Where, SDM_BOT and WAVE_STEP are bits of the PLL pattern control register, and PREQ is the frequency of
the spread spectrum.
NOTE
Different PLLs have different calculate formulas, refer to the CTRL register of the corresponding PLL in
section 3.3.6 Register Description.
Configuration Procedure
Follow the steps below to implement the spread spectrum:
Step 1 Configure the control register of the corresponding PLL
a) Calculate the factor N and decimal value X according to the PLL frequency and PLL frequency
formula. Refer to the control register of the corresponding PLL (named PLL_xxx_CTRL_REG,
where xxx is the module name) in 3.3.6 Register Description for the corresponding PLL frequency
formula.
b) Write M0, M1, N, and PLL frequency to the PLL control register.
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c) Configure the SDM_Enable bit (bit[24]) of the PLL control register to 1 to enable the spread
spectrum function.
Step 2 Configure the pattern control register of the corresponding PLL
a) Calculate the SDM_BOT and WAVE_STEP of the pattern control register according to decimal
value X and spread spectrum frequency (the bit[18:17] of the PLL_PAT register)
b) Configure the spread spectrum mode (SPR_FREQ_MODE) to 2 or 3.
c) If the PLL_INPUT_DIV2 of the PLL control register is 1, configure the spread spectrum clock source
select bit (SDM_CLK_SEL) of the PLL pattern control register to 1. Otherwise, configure
SDM_CLK_SEL to the default value 0.
d) Write SDM_BOT, WAVE_STEP, PREQ, SPR_FREQ_MODE, and SDM_CLK_SEL to the PLL pattern
control register, and configure the SIG_DELT_PAT_EN bit (bit[31]) of this register to 1.
Step 3 Delay 20 us
Configuration Example
The following example shows how to configure the spread spectrum frequency as 605.3 MHz to 609.7 MHz.
If M1 = 0, M0 = 0, P = 1, according to the formula [ f1 , f2 ] N 1 [ X1 , X2 ] 24MHz , you can get:
[605.3, 609.7]
N 1 [ X1 , X2 ]
24
600 [5.3,9.7]
24
24 1 [5.3 / 24, 9.7/24]
Obviously,
N = 24, X1 = 5.3/24, X2 = 9.7/24
SDM_BOT = 217 * X1 = 0x7111
WAVE_STEP = 217 * (X2 – X1) /(24M/PREQ)*2 = 0x3f; PREQ = 31.5 kHz
If M0 = 1, M1=0, P = 1, then total frequency division factor is (M0 + 1) *1 = 2, so the actual output frequency of
PLL is 1212.1 MHz to 1219.4 MHz.
Similarly, you can get:
N = 49, X1 = 12.1/24, X2 = 19.4/24
Then calculate the values of SDM_BOT and WAVE_STEP according to the formulas, and follow the steps
described in Configuration Procedure.
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3.3.5 Register List
Module Name Base Address
CCU 0x02001000
Register Name Offset Description
PLL_CPU_CTRL_REG 0x0000 PLL_CPU Control Register
PLL_DDR_CTRL_REG 0x0010 PLL_DDR Control Register
PLL_PERI_CTRL_REG 0x0020 PLL_PERI Control Register
PLL_VIDEO0_CTRL_REG 0x0040 PLL_VIDEO0 Control Register
PLL_VIDEO1_CTRL_REG 0x0048 PLL_VIDEO1 Control Register
PLL_VE_CTRL_REG 0x0058 PLL_VE Control Register
PLL_AUDIO0_CTRL_REG 0x0078 PLL_AUDIO0 Control Register
PLL_AUDIO1_CTRL_REG 0x0080 PLL_AUDIO1 Control Register
PLL_DDR_PAT0_CTRL_REG 0x0110 PLL_DDR Pattern0 Control Register
PLL_DDR_PAT1_CTRL_REG 0x0114 PLL_DDR Pattern1 Control Register
PLL_PERI_PAT0_CTRL_REG 0x0120 PLL_PERI Pattern0 Control Register
PLL_PERI_PAT1_CTRL_REG 0x0124 PLL_PERI Pattern1 Control Register
PLL_VIDEO0_PAT0_CTRL_REG 0x0140 PLL_VIDEO0 Pattern0 Control Register
PLL_VIDEO0_PAT1_CTRL_REG 0x0144 PLL_VIDEO0 Pattern1 Control Register
PLL_VIDEO1_PAT0_CTRL_REG 0x0148 PLL_VIDEO1 Pattern0 Control Register
PLL_VIDEO1_PAT1_CTRL_REG 0x014C PLL_VIDEO1 Pattern1 Control Register
PLL_VE_PAT0_CTRL_REG 0x0158 PLL_VE Pattern0 Control Register
PLL_VE_PAT1_CTRL_REG 0x015C PLL_VE Pattern1 Control Register
PLL_AUDIO0_PAT0_CTRL_REG 0x0178 PLL_AUDIO0 Pattern0 Control Register
PLL_AUDIO0_PAT1_CTRL_REG 0x017C PLL_AUDIO0 Pattern1 Control Register
PLL_AUDIO1_PAT0_CTRL_REG 0x0180 PLL_AUDIO1 Pattern0 Control Register
PLL_AUDIO1_PAT1_CTRL_REG 0x0184 PLL_AUDIO1 Pattern1 Control Register
PLL_CPU_BIAS_REG 0x0300 PLL_CPU Bias Register
PLL_DDR_BIAS_REG 0x0310 PLL_DDR Bias Register
PLL_PERI_BIAS_REG 0x0320 PLL_PERI Bias Register
PLL_VIDEO0_BIAS_REG 0x0340 PLL_VIDEO0 Bias Register
PLL_VIDEO1_BIAS_REG 0x0348 PLL_VIDEO1 Bias Register
PLL_VE_BIAS_REG 0x0358 PLL_VE Bias Register
PLL_AUDIO0_BIAS_REG 0x0378 PLL_AUDIO0 Bias Register
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Register Name Offset Description
PLL_AUDIO1_BIAS_REG 0x0380 PLL_AUDIO1 Bias Register
PLL_CPU_TUN_REG 0x0400 PLL_CPU Tuning Register
CPU_AXI_CFG_REG 0x0500 CPU_AXI Configuration Register
CPU_GATING_REG 0x0504 CPU_GATING Configuration Register
PSI_CLK_REG 0x0510 PSI Clock Register
APB0_CLK_REG 0x0520 APB0 Clock Register
APB1_CLK_REG 0x0524 APB1 Clock Register
MBUS_CLK_REG 0x0540 MBUS Clock Register
DE_CLK_REG 0x0600 DE Clock Register
DE_BGR_REG 0x060C DE Bus Gating Reset Register
DI_CLK_REG 0x0620 DI Clock Register
DI_BGR_REG 0x062C DI Bus Gating Reset Register
G2D_CLK_REG 0x0630 G2D Clock Register
G2D_BGR_REG 0x063C G2D Bus Gating Reset Register
CE_CLK_REG 0x0680 CE Clock Register
CE_BGR_REG 0x068C CE Bus Gating Reset Register
VE_CLK_REG 0x0690 VE Clock Register
VE_BGR_REG 0x069C VE Bus Gating Reset Register
DMA_BGR_REG 0x070C DMA Bus Gating Reset Register
HSTIMER_BGR_REG 0x073C HSTIMER Bus Gating Reset Register
AVS_CLK_REG 0x0740 AVS Clock Register
DBGSYS_BGR_REG 0x078C DBGSYS Bus Gating Reset Register
PWM_BGR_REG 0x07AC PWM Bus Gating Reset Register
IOMMU_BGR_REG 0x07BC IOMMU Bus Gating Reset Register
DRAM_CLK_REG 0x0800 DRAM Clock Register
MBUS_MAT_CLK_GATING_REG 0x0804 MBUS Master Clock Gating Register
DRAM_BGR_REG 0x080C DRAM Bus Gating Reset Register
SMHC0_CLK_REG 0x0830 SMHC0 Clock Register
SMHC1_CLK_REG 0x0834 SMHC1 Clock Register
SMHC2_CLK_REG 0x0838 SMHC2 Clock Register
SMHC_BGR_REG 0x084C SMHC Bus Gating Reset Register
UART_BGR_REG 0x090C UART Bus Gating Reset Register
TWI_BGR_REG 0x091C TWI Bus Gating Reset Register
SPI0_CLK_REG 0x0940 SPI0 Clock Register
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Register Name Offset Description
SPI1_CLK_REG 0x0944 SPI1 Clock Register
SPI_BGR_REG 0x096C SPI Bus Gating Reset Register
EMAC_25M_CLK_REG 0x0970 EMAC_25M Clock Register
EMAC_BGR_REG 0x097C EMAC Bus Gating Reset Register
IRTX_CLK_REG 0x09C0 IRTX Clock Register
IRTX_BGR_REG 0x09CC IRTX Bus Gating Reset Register
GPADC_BGR_REG 0x09EC GPADC Bus Gating Reset Register
THS_BGR_REG 0x09FC THS Bus Gating Reset Register
I2S1_CLK_REG 0x0A14 I2S1 Clock Register
I2S2_CLK_REG 0x0A18 I2S2 Clock Register
I2S2_ASRC_CLK_REG 0x0A1C I2S2_ASRC Clock Register
I2S_BGR_REG 0x0A20 I2S Bus Gating Reset Register
OWA_TX_CLK_REG 0x0A24 OWA_TX Clock Register
OWA_RX_CLK_REG 0x0A28 OWA_RX Clock Register
OWA_BGR_REG 0x0A2C OWA Bus Gating Reset Register
DMIC_CLK_REG 0x0A40 DMIC Clock Register
DMIC_BGR_REG 0x0A4C DMIC Bus Gating Reset Register
AUDIO_CODEC_DAC_CLK_REG 0x0A50 AUDIO_CODEC_DAC Clock Register
AUDIO_CODEC_ADC_CLK_REG 0x0A54 AUDIO_CODEC_ADC Clock Register
AUDIO_CODEC_BGR_REG 0x0A5C AUDIO_CODEC Bus Gating Reset Register
USB0_CLK_REG 0x0A70 USB0 Clock Register
USB1_CLK_REG 0x0A74 USB1 Clock Register
USB_BGR_REG 0x0A8C USB Bus Gating Reset Register
DPSS_TOP_BGR_REG 0x0ABC DPSS_TOP Bus Gating Reset Register
DSI_CLK_REG 0x0B24 DSI Clock Register
DSI_BGR_REG 0x0B4C DSI Bus Gating Reset Register
TCONLCD_CLK_REG 0x0B60 TCONLCD Clock Register
TCONLCD_BGR_REG 0x0B7C TCONLCD Bus Gating Reset Register
TCONTV_CLK_REG 0x0B80 TCONTV Clock Register
TCONTV_BGR_REG 0x0B9C TCONTV Bus Gating Reset Register
LVDS_BGR_REG 0x0BAC LVDS Bus Gating Reset Register
TVE_CLK_REG 0x0BB0 TVE Clock Register
TVE_BGR_REG 0x0BBC TVE Bus Gating Reset Register
TVD_CLK_REG 0x0BC0 TVD Clock Register
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Register Name Offset Description
TVD_BGR_REG 0x0BDC TVD Bus Gating Reset Register
LEDC_CLK_REG 0x0BF0 LEDC Clock Register
LEDC_BGR_REG 0x0BFC LEDC Bus Gating Reset Register
CSI_CLK_REG 0x0C04 CSI Clock Register
CSI_MASTER_CLK_REG 0x0C08 CSI Master Clock Register
CSI_BGR_REG 0x0C1C CSI Bus Gating Reset Register
TPADC_CLK_REG 0x0C50 TPADC Clock Register
TPADC_BGR_REG 0x0C5C TPADC Bus Gating Reset Register
RISC_CLK_REG 0x0D00 RISC Clock Register
RISC_GATING_REG 0x0D04 RISC Gating Configuration Register
RISC_CFG_BGR_REG 0x0D0C RISC_CFG Bus Gating Reset Register
PLL_LOCK_DBG_CTRL_REG 0x0F04 PLL Lock Debug Control Register
FRE_DET_CTRL_REG 0x0F08 Frequency Detect Control Register
FRE_UP_LIM_REG 0x0F0C Frequency Up Limit Register
FRE_DOWN_LIM_REG 0x0F10 Frequency Down Limit Register
RISC_RST_REG 0x0F20 RISC LOCK RESET Register
CCU_FAN_GATE_REG 0x0F30 CCU FANOUT CLOCK GATE Register
CLK27M_FAN_REG 0x0F34 CLK27M FANOUT Register
PCLK_FAN_REG 0x0F38 PCLK FANOUT Register
CCU_FAN_REG 0x0F3C CCU FANOUT Register
3.3.6 Register Description
3.3.6.1 0x0000 PLL_CPU Control Register (Default Value: 0x4A00_1000)
Offset: 0x0000 Register Name: PLL_CPU_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
31 R/W 0x0
The PLL_CPU= InputFreq*N.
The PLL_CPU output frequency must be in the range from 200
MHz to 3 GHz. And the default value of PLL_CPUX is 408 MHz
when the crystal oscillator is 24 MHz.
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Offset: 0x0000 Register Name: PLL_CPU_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock Status
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of the PLL.
PLL_LOCK_TIME.
PLL Lock Time
26:24 R/W 0x2
The bit indicates the step amplitude from one frequency to
another.
23:16 / / /
PLL_N
PLL N
15:8 R/W 0x10 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
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Offset: 0x0000 Register Name: PLL_CPU_CTRL_REG
Bit Read/Write Default/Hex Description
4:2 / / /
PLL_M
PLL_M
1:0 R/W 0x0 M = PLL_FACTOR_M + 1
PLL_FACTOR_M is from 0 to 3.
Note: The M factor is only for testing.
3.3.6.2 0x0010 PLL_DDR Control Register (Default Value: 0x4800_2301)
Offset: 0x0010 Register Name: PLL_DDR_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
0: Disable
1: Enable
31 R/W 0x0
PLL_DDR = InputFreq*N/M1/M0.
The default value of PLL_DDR is 432 MHz when the crystal
oscillator is 24 MHz.
PLL_LDO_EN
LDO ENABLE
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of the PLL.
26:25 / / /
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Offset: 0x0010 Register Name: PLL_DDR_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0
0: Disable
1: Enable
23:16 / / /
PLL_N
PLL N
15:8 R/W 0x23 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M1
1 R/W 0x0
M1=PLL_INPUT_DIV2 + 1
PLL_INPUT_DIV2 is from 0 to 1.
PLL_OUTPUT_DIV2
PLL Output Div M0
0 R/W 0x1
M0=PLL_OUTPUT_DIV2 + 1
PLL_OUTPUT_DIV2 is from 0 to 1.
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3.3.6.3 0x0020 PLL_PERI Control Register (Default Value: 0x4821_6300)
Offset: 0x0020 Register Name: PLL_PERI_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
PLL_PERI(2X) = 24 MHz*N/M/P0
PLL_PERI(1X) = 24 MHz*N/M/P0/2
31 R/W 0x0 PLL_PERI(800M) = 24 MHz*N/M/P1.
When the crystal oscillator is 24 MHz, the default frequency of
PLL_PERI(2X) is 1.2 GHz, the default frequency of PLL_PERI(1X) is
600 MHz, and the default frequency of PLL_PERI(800M) is 800
MHz.
The output clock of PLL_PERI(2X) is fixed to 1.2 GHz and not
suggested to change the parameter.
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
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Offset: 0x0020 Register Name: PLL_PERI_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0 0: Disable
1: Enable
Enable spread spectrum and decimal division.
23 / / /
PLL_P1
PLL Output Div P1
22:20 R/W 0x2
P1=PLL_OUTPUT_DIV_P1 + 1
PLL_OUTPUT_DIV_P1 is from 0 to 7.
19 / / /
PLL_P0
PLL Output Div P0
18:16 R/W 0x1
P0=PLL_OUTPUT_DIV_P0 + 1
PLL_OUTPUT_DIV_P0 is from 0 to 7.
PLL_N
PLL N
15:8 R/W 0x63 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M
1 R/W 0x0
M1=PLL_INPUT_DIV2 + 1
PLL_INPUT_DIV2 is from 0 to 1.
0 / / /
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3.3.6.4 0x0040 PLL_VIDEO0 Control Register (Default Value: 0x4800_6203)
Offset: 0x0040 Register Name: PLL_VIDEO0_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
For application,
31 R/W 0x0
PLL_VIDEO0(4X)=InputFreq *N/M.
PLL_VIDEO0(2X)= InputFreq *N/M/2.
PLL_VIDEO0(1X)= InputFreq *N/M/4.
When the HOSC is 24 MHz, the default frequency of
PLL_VIDEO0(4X) is 1188 MHz.
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0
0: Disable
1: Enable
23:16 / / /
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Offset: 0x0040 Register Name: PLL_VIDEO0_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_N
PLL N
15:8 R/W 0x62 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M
1 R/W 0x1
M1=PLL_INPUT_DIV_M + 1
PLL_INPUT_DIV_M is from 0 to 1.
PLL_OUTPUT_DIV2
PLL Output Div D (The factor is only for testing)
0 R/W 0x1 M0=PLL_OUTPUT_DIV_D + 1
PLL_OUTPUT_DIV_D is from 0 to 1.
For test, PLL_VIDEO0(4X) =24MHz*N/M/D
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3.3.6.5 0x0048 PLL_VIDEO1 Control Register (Default Value: 0x4800_6203)
Offset: 0x0048 Register Name: PLL_VIDEO1_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
For application,
31 R/W 0x0
PLL_VIDEO1(4X)=InputFreq *N/M.
PLL_VIDEO1(2X)= InputFreq *N/M/2.
PLL_VIDEO1(1X)= InputFreq *N/M/4.
When the HOSC is 24 MHz, the default frequency of
PLL_VIDEO1(4X) is 1188 MHz.
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0
0: Disable
1: Enable
23:16 / / /
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Offset: 0x0048 Register Name: PLL_VIDEO1_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_FACTOR_N
PLL FACTOR N
15:8 R/W 0x62 N= PLL_FACTOR_N +1
PLL_FACTOR_N is from 0 to 254.
In application, PLL_FACTOR_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M
1 R/W 0x1
M1=PLL_INPUT_DIV_M + 1
PLL_INPUT_DIV_M is from 0 to 1.
PLL_OUTPUT_DIV2
PLL Output Div D.(The factor is only for testing)
0 R/W 0x1 M0=PLL_OUTPUT_DIV_D + 1
PLL_OUTPUT_DIV_D is from 0 to 1.
For test, PLL_VIDEO1(4X) =24MHz*N/M/D
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3.3.6.6 0x0058 PLL_VE Control Register (Default Value: 0x4800_2301)
Offset: 0x0058 Register Name: PLL_VE_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
31 R/W 0x0 1: Enable
PLL_VE = InputFreq*N/M1/M0.
When the HOSC is 24 MHz, the default frequency of PLL_VE is 432
MHz.
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
PLL_OUTPUT_GATE
PLL Output Gating Enable
27 R/W 0x1 0: Disable
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0
0: Disable
1: Enable
23:16 / / /
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Offset: 0x0058 Register Name: PLL_VE_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_N
PLL N
15:8 R/W 0x23 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M1
1 R/W 0x0
M1=PLL_INPUT_DIV2 + 1
PLL_INPUT_DIV2 is from 0 to 1.
PLL_OUTPUT_DIV2
PLL Output Div M0
0 R/W 0x1
M0=PLL_OUTPUT_DIV2 + 1
PLL_OUTPUT_DIV2 is from 0 to 1.
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3.3.6.7 0x0078 PLL_AUDIO0 Control Register (Default Value: 0x4814_5500)
Offset: 0x0078 Register Name: PLL_AUDIO0_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
PLL_AUDIO0(4X) = 24MHz*N/M1/M0/P
31 R/W 0x0 PLL_AUDIO0(2X) = (24MHz*N/M1/M0)/P/2
PLL_AUDIO0(1X) = (24MHz*N/M1/M0)/P/4
Note: 7.5≤N/M0/M1≤125 and 12≤N
The working frequency range of 24MHz*N/M0/M1 is from 180
MHz to 3.0 GHz.
The default frequency of PLL_AUDIO0(1X) is 24.5714 MHz.
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
PLL Lock
28 R 0x0 0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
Note: The bit is only valid when the bit29 is set to 1.
PLL_OUTPUT_GATE
0: Disable
27 R/W 0x1
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
PLL_SDM_EN
PLL SDM Enable
24 R/W 0x0 0: Disable
1: Enable
Enable spread spectrum and decimal division.
23:22 / / /
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Offset: 0x0078 Register Name: PLL_AUDIO0_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_P
PLL Post-div P
21:16 R/W 0x14
P= PLL_POST_DIV_P +1
PLL_POST_DIV_P is from 0 to 63.
PLL_N
PLL N
15:8 R/W 0x55 N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M1
1 R/W 0x0
M1=PLL_INPUT_DIV2 + 1
PLL_INPUT_DIV2 is from 0 to 1.
PLL_OUTPUT_DIV2
PLL Output Div M0
0 R/W 0x0
M0=PLL_OUTPUT_DIV2 + 1
PLL_OUTPUT_DIV2 is from 0 to 1.
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3.3.6.8 0x0080 PLL_AUDIO1 Control Register (Default Value: 0x4841_7F00)
Offset: 0x0080 Register Name: PLL_AUDIO1_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_EN
PLL Enable
0: Disable
1: Enable
PLL_AUDIO1 = 24MHz*N/M
PLL_AUDIO1(DIV2) = 24MHz*N/M/P0
31 R/W 0x0 PLL_AUDIO1(DIV5) = 24MHz*N/M/P1
The working frequency range of 24 MHz/M*N is from 180 MHz to
3.5 GHz.
The default frequency of PLL_AUDIO1 is 3072 MHz.
The default frequency of PLL_AUDIO1(DIV2) is 1536 MHz.
The default frequency of PLL_AUDIO1(DIV5) is 614.4 MHz (24.576
MHz*25).
PLL_LDO_EN
LDO Enable
30 R/W 0x1
0: Disable
1: Enable
LOCK_ENABLE
Lock Enable
29 R/W 0x0
0: Disable
1: Enable
LOCK
0: Unlocked
28 R 0x0
1: Locked (It indicates that the PLL has been stable.)
Note: The bit is only valid when the bit29 is set to 1.
PLL_OUTPUT_GATE
0: Disable
27 R/W 0x1
1: Enable
The bit is used to control the output enable of PLL.
26:25 / / /
PLL_SDM_EN
0: Disable
24 R/W 0x0
1: Enable
Enable spread spectrum and decimal division.
23 / / /
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Offset: 0x0080 Register Name: PLL_AUDIO1_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_P1
PLL Output Div P1
22:20 R/W 0x4
P1=PLL_OUTPUT_DIV_P1 + 1
PLL_OUTPUT_DIV_P1 is from 0 to 7.
19 / / /
PLL_P0
PLL Output Div P0
18:16 R/W 0x1
P0=PLL_OUTPUT_DIV_P0 + 1
PLL_OUTPUT_DIV_P0 is from 0 to 7.
PLL_N
PLL N
15:8 R/W 0x7F N= PLL_N +1
PLL_N is from 0 to 254.
In application, PLL_N shall be more than or equal to 12.
PLL_UNLOCK_MDSEL
PLL Unlock Level
7:6 R/W 0x0 00: 21-29 Clock Cycles
01: 22-28 Clock Cycles
1X: 20-30 Clock Cycles
PLL_LOCK_MDSEL
PLL Lock Level
5 R/W 0x0
0: 24-26 Clock Cycles
1: 23-27 Clock Cycles
4:2 / / /
PLL_INPUT_DIV2
PLL Input Div M
1 R/W 0x0
M=PLL_INPUT_DIV_M + 1
PLL_INPUT_DIV_M is from 0 to 1.
0 / / /
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3.3.6.9 0x0110 PLL_DDR Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0110 Register Name: PLL_DDR_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
3.3.6.10 0x0114 PLL_DDR Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x0114 Register Name: PLL_DDR_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
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Offset: 0x0114 Register Name: PLL_DDR_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.11 0x0120 PLL_PERI Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0120 Register Name: PLL_PERI_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
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3.3.6.12 0x0124 PLL_PERI Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x0124 Register Name: PLL_PERI_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.13 0x0140 PLL_VIDEO0 Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0140 Register Name: PLL_VIDEO0_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
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Offset: 0x0140 Register Name: PLL_VIDEO0_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
3.3.6.14 0x0144 PLL_VIDEO0 Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x0144 Register Name: PLL_VIDEO0_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.15 0x0148 PLL_VIDEO1 Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0148 Register Name: PLL_VIDEO1_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
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Offset: 0x0148 Register Name: PLL_VIDEO1_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
3.3.6.16 0x014C PLL_VIDEO1 Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x014C Register Name: PLL_VIDEO1_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
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Offset: 0x014C Register Name: PLL_VIDEO1_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.17 0x0158 PLL_VE Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0158 Register Name: PLL_VE_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
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3.3.6.18 0x015C PLL_VE Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x015C Register Name: PLL_VE_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.19 0x0178 PLL_AUDIO0 Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0178 Register Name: PLL_AUDIO0_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
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Offset: 0x0178 Register Name: PLL_AUDIO0_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
3.3.6.20 0x017C PLL_AUDIO0 Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x017C Register Name: PLL_AUDIO0_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.21 0x0180 PLL_AUDIO1 Pattern0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0180 Register Name: PLL_AUDIO1_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SIG_DELT_PAT_EN
31 R/W 0x0
Sigma-Delta Pattern Enable
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Offset: 0x0180 Register Name: PLL_AUDIO1_PAT0_CTRL_REG
Bit Read/Write Default/Hex Description
SPR_FREQ_MODE
Spread Frequency Mode
00: DC=0
30:29 R/W 0x0
01: DC=1
10: Triangular(1-bit)
11: Triangular(n-bit)
WAVE_STEP
28:20 R/W 0x0
Wave Step
SDM_CLK_SEL
SDM Clock Select
0: 24 MHz
19 R/W 0x0
1: 12 MHz
Note: When the PLL_INPUT_DIV2 is 1, the bit needs to be set to
1.
FREQ
Frequency
00: 31.5 kHz
18:17 R/W 0x0
01: 32 kHz
10: 32.5 kHz
11: 33 kHz
WAVE_BOT
16:0 R/W 0x0
Wave Bottom
3.3.6.22 0x0184 PLL_AUDIO1 Pattern1 Control Register (Default Value: 0x0000_0000)
Offset: 0x0184 Register Name: PLL_AUDIO1_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
DITHER_EN
24 R/W 0x0
Dither Enable
23:21 / / /
FRAC_EN
20 R/W 0x0
Fraction Enable
19:17 / / /
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Offset: 0x0184 Register Name: PLL_AUDIO1_PAT1_CTRL_REG
Bit Read/Write Default/Hex Description
FRAC_IN
16:0 R/W 0x0
Fraction In
3.3.6.23 0x0300 PLL_CPU Bias Register (Default Value: 0x8010_0000)
Offset: 0x0300 Register Name: PLL_CPU_BIAS_REG
Bit Read/Write Default/Hex Description
PLL_VCO_RST_IN
31 R/W 0x1
VCO reset in
30:21 / / /
PLL_CP
20:16 R/W 0x10
PLL current bias control
15:0 / / /
3.3.6.24 0x0310 PLL_DDR Bias Register (Default Value: 0x0003_0000)
Offset: 0x0310 Register Name: PLL_DDR_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
3.3.6.25 0x0320 PLL_PERI Bias Register (Default Value: 0x0003_0000)
Offset: 0x0320 Register Name: PLL_PERI_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
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3.3.6.26 0x0340 PLL_VIDEO0 Bias Register (Default Value: 0x0003_0000)
Offset: 0x0340 Register Name: PLL_VIDEO0_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
3.3.6.27 0x0348 PLL_VIDEO1 Bias Register (Default Value: 0x0003_0000)
Offset: 0x0348 Register Name: PLL_VIDEO1_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
3.3.6.28 0x0358 PLL_VE Bias Register (Default Value: 0x0003_0000)
Offset: 0x0358 Register Name: PLL_VE_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
3.3.6.29 0x0378 PLL_AUDIO0 Bias Register (Default Value: 0x0003_0000)
Offset: 0x0378 Register Name: PLL_AUDIO0_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
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Offset: 0x0378 Register Name: PLL_AUDIO0_BIAS_REG
Bit Read/Write Default/Hex Description
15:0 / / /
3.3.6.30 0x0380 PLL_AUDIO1 Bias Register (Default Value: 0x0003_0000)
Offset: 0x0380 Register Name: PLL_AUDIO1_BIAS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
PLL_CP
20:16 R/W 0x3
PLL bias control
15:0 / / /
3.3.6.31 0x0400 PLL_CPU Tuning Register (Default Value: 0x4440_4000)
Offset: 0x0400 Register Name: PLL_CPU_TUN_REG
Bit Read/Write Default/Hex Description
31 / / /
PLL_VCO
30:28 R/W 0x4
VCO range control
27 / / /
PLL_VCO_GAIN
26:24 R/W 0x4
KVCO gain control
23 / / /
PLL_CNT_INT
22:16 R/W 0x40
Counter initial control
PLL_REG_OD
15 R/W 0x0
PLL-REG-OD0 for verify
PLL_B_IN
14:8 R/W 0x40
PLL-B-IN [6:0] for verify
PLL_REG_OD1
7 R/W 0x0
PLL-REG-OD1 for verify
PLL_B_OUT
6:0 R 0x0
PLL-B-OUT [6:0] for verify
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3.3.6.32 0x0510 PSI Clock Register (Default Value: 0x0000_0000)
Offset: 0x0510 Register Name: PSI_CLK_REG
Bit Read/Write Default/Hex Description
31:26 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
001: CLK32K
25:24 R/W 0x0 010: CLK16M_RC
011: PLL_PERI(1X)
PSI_CLK = Clock Source/M/N.
Note: The clock select is lack of glitch switching and supports
dynamic configuration.
23:10 / / /
FACTOR_N
Factor N
00: 1
01: 2
9:8 R/W 0x0
10: 4
11: 8
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
7:2 / / /
FACTOR_M
Factor M.
M= FACTOR_M +1
1:0 R/W 0x0
FACTOR_M is from 0 to 3.
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
3.3.6.33 0x0520 APB0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0520 Register Name: APB0_CLK_REG
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x0520 Register Name: APB0_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
00: HOSC
01: CLK32K
25:24 R/W 0x0 10: PSI_CLK
11: PLL_PERI(1X)
APB0_CLK = Clock Source/M/N.
Note: The clock select is lack of glitch switching and supports
dynamic configuration.
23:10 / / /
FACTOR_N.
Factor N
00: 1
01: 2
9:8 R/W 0x0
10: 4
11: 8
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
7:5 / / /
FACTOR_M
Factor M
M = FACTOR_M+1
4:0 R/W 0x0
FACTOR_M is from 0 to 31.
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
3.3.6.34 0x0524 APB1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0524 Register Name: APB1_CLK_REG
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x0524 Register Name: APB1_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
00: HOSC
01: CLK32K
25:24 R/W 0x0 10: PSI_CLK
11: PLL_PERI(1X)
APB1_CLK = Clock Source/M/N.
Note: The clock select is lack of glitch switching and supports
dynamic configuration.
23:10 / / /
FACTOR_N
Factor N
00: 1
01: 2
9:8 R/W 0x0
10: 4
11: 8
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
7:5 / / /
FACTOR_M
Factor M
M = FACTOR_M+1
4:0 R/W 0x0
FACTOR_M is from 0 to 31.
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
3.3.6.35 0x0540 MBUS Clock Register (Default Value: 0xC000_0000)
Offset: 0x0540 Register Name: MBUS_CLK_REG
Bit Read/Write Default/Hex Description
31 / / /
MBUS_RST
MBUS Reset
30 R/W 0x1
0: Assert
1: De-assert
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Offset: 0x0540 Register Name: MBUS_CLK_REG
Bit Read/Write Default/Hex Description
29:0 / / /
NOTE
The MBUS clock is from the 4 frequency-division of PLL_DDR, and it has the same source with the DRAM clock.
3.3.6.36 0x0600 DE Clock Register (Default Value: 0xC000_0000)
Offset: 0x0600 Register Name: DE_CLK_REG
Bit Read/Write Default/Hex Description
DE_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
DE_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: PLL_PERI(2X)
26:24 R/W 0x0
001: PLL_VIDEO0(4X)
010: PLL_VIDEO1(4X)
011: PLL_AUDIO1(DIV2)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.37 0x060C DE Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x060C Register Name: DE_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
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Offset: 0x060C Register Name: DE_BGR_REG
Bit Read/Write Default/Hex Description
DE_RST
DE Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DE_GATING
DE Gating Clock
0 R/W 0x0
0: Mask
1: Pass
3.3.6.38 0x0620 DI Clock Register (Default Value: 0x0000_0000)
Offset: 0x0620 Register Name: DI_CLK_REG
Bit Read/Write Default/Hex Description
DI_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
DI_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: PLL_PERI(2X)
26:24 R/W 0x0
001: PLL_VIDEO0(4X)
010: PLL_VIDEO1(4X)
011: PLL_AUDIO1(DIV2)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M = FACTOR_M +1
FACTOR_M is from 0 to 31.
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3.3.6.39 0x062C DI Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x062C Register Name: DI_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
DI_RST
DI Reset
16 R/W 0x0
0: Assert
1: DE-assert
15:1 / / /
DI_GATING
DI Gating Clock
0 R/W 0x0
0: Mask
1: Pass
3.3.6.40 0x0630 G2D Clock Register (Default Value: 0x0000_0000)
Offset: 0x0630 Register Name: G2D_CLK_REG
Bit Read/Write Default/Hex Description
G2D_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
G2D_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: PLL_PERI(2X)
26:24 R/W 0x0
001: PLL_VIDEO0(4X)
010: PLL_VIDEO1(4X)
011: PLL_AUDIO1(DIV2)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
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3.3.6.41 0x063C G2D Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x063C Register Name: G2D_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
G2D_RST
G2D Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
G2D_GATING
G2D Gating Clock
0 R/W 0x0
0: Mask
1: Pass
3.3.6.42 0x0680 CE Clock Register (Default Value: 0x0000_0000)
Offset: 0x0680 Register Name: CE_CLK_REG
Bit Read/Write Default/Hex Description
CE_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
CE_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0 00: HOSC
01: PLL_PERI(2X)
10: PLL_PERI(1X)
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
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Offset: 0x0680 Register Name: CE_CLK_REG
Bit Read/Write Default/Hex Description
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.43 0x068C CE Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x068C Register Name: CE_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
CE_RST
CE Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
CE_GATING
CE Gating Clock
0 R/W 0x0
0: Mask
1: Pass
3.3.6.44 0x0690 VE Clock Register (Default Value: 0x0000_0000)
Offset: 0x0690 Register Name: VE_CLK_REG
Bit Read/Write Default/Hex Description
VE_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
VE_CLK = Clock Source/M.
30:25 / / /
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Offset: 0x0690 Register Name: VE_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
24 R/W 0x0
0: PLL_VE
1: PLL_PERI(2X)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.45 0x069C VE Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x069C Register Name: VE_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
VE_RST
VE Reset For VE_PROT
16 R/W 0x0
0: Assert
1: DE-assert
15:1 / / /
VE_GATING
Gating Clock For VE_PROT
0 R/W 0x0
0: Mask
1: Pass
3.3.6.46 0x070C DMA Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x070C Register Name: DMA_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
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Offset: 0x070C Register Name: DMA_BGR_REG
Bit Read/Write Default/Hex Description
DMA_RST
DMA Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DMA_GATING
DMA Gating Clock
0 R/W 0x0 0: Mask
1: Pass
Note: The working clock is from PSI_CLK.
3.3.6.47 0x073C HSTIMER Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x073C Register Name: HSTIMER_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
HSTIMER_RST
HSTIMER Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
HSTIMER_GATING
Gating Clock for HSTIMER
0 R/W 0x0
0: Mask
1: Pass
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3.3.6.48 0x0740 AVS Clock Register (Default Value: 0x0000_0000)
Offset: 0x0740 Register Name: AVS_CLK_REG
Bit Read/Write Default/Hex Description
AVS_CLK_GATING
Gating Clock
31 R/W 0x0 The AVS_CLK is from HOSC.
0: Clock is OFF
1: Clock is ON
30:0 / / /
3.3.6.49 0x078C DBGSYS Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x078C Register Name: DBGSYS_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
DBGSYS_RST
DBGSYS Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DBGSYS_GATING
Gating Clock for DBGSYS
0 R/W 0x0 The clock of DBGSYS is from HOSC.
0: Mask
1: Pass
3.3.6.50 0x07AC PWM Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x07AC Register Name: PWM_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
PWM_RST
PWM Reset
16 R/W 0x0
0: Assert
1: De-assert
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Offset: 0x07AC Register Name: PWM_BGR_REG
Bit Read/Write Default/Hex Description
15:1 / / /
PWM_GATING
Gating Clock for PWM
0 R/W 0x0
0: Mask
1: Pass
3.3.6.51 0x07BC IOMMU Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x07BC Register Name: IOMMU_BGR_REG
Bit Read/Write Default/Hex Description
31:1 / / /
IOMMU_GATING
Gating Clock for IOMMU
0 R/W 0x0
0: Mask
1: Pass
3.3.6.52 0x0800 DRAM Clock Register (Default Value: 0x8000_0000)
Offset: 0x0800 Register Name: DRAM_CLK_REG
Bit Read/Write Default/Hex Description
DRAM_CLK_GATING
Gating Clock
31 R/W 0x1 DRAM_CLK = Clock Source/M/N.
0: Clock is OFF
1: Clock is ON
30:28 / / /
SDRCLK_UPD
SDRCLK Configuration 0 Update
0: Invalid
1: Valid
27 R/WAC 0x0
Setting 1 will validate the bit. It will be automatically cleared after
the bit is valid.
Here supports dram req/ack signal. When dram_update is set to 1,
dram_clk_sel/dram_div2/dram_clk1 will be updated.
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Offset: 0x0800 Register Name: DRAM_CLK_REG
Bit Read/Write Default/Hex Description
DRAM_CLK_SEL
Clock Source Select
00: PLL_DDR
01: PLL_AUDIO1(DIV2)
26:24 R/W 0x0
10: PLL_PERI(2X)
11: PLL_PERI(800M)
Note: The clock select is lack of glitch switching and supports
dynamic configuration.
23:10 / / /
DRAM_DIV2
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:2 / / /
DRAM_DIV1
Factor M
M= FACTOR_M +1
1:0 R/W 0x0
FACTOR_M is from 0 to 3.
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
3.3.6.53 0x0804 MBUS Master Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x0804 Register Name: MBUS_MAT_CLK_GATING_REG
Bit Read/Write Default/Hex Description
31:12 / / /
RISC_MCLK_EN
Gating MBUS Clock For RISC
11 R/W 0x0
0: Mask
1: Pass
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Offset: 0x0804 Register Name: MBUS_MAT_CLK_GATING_REG
Bit Read/Write Default/Hex Description
G2D_MCLK_EN
Gating MBUS Clock For G2D
10 R/W 0x0
0: Mask
1: Pass
9 / / /
CSI_MCLK_EN
Gating MBUS Clock For CSI
8 R/W 0x0
0: Mask
1: Pass
TVIN_MCLK_EN
Gating MBUS Clock For TVIN
7 R/W 0x0
0: Mask
1: Pass
6:3 / / /
CE_MCLK_EN
Gating MBUS Clock For CE
2 R/W 0x0
0: Mask
1: Pass
VE_MCLK_EN
Gating MBUS Clock For VE
1 R/W 0x0
0: Mask
1: Pass
DMA_MCLK_EN
Gating MBUS Clock For DMA
0 R/W 0x0
0: Mask
1: Pass
3.3.6.54 0x080C DRAM Bus Gating Reset Register (Default Value: 0x0000_0001)
Offset: 0x080C Register Name: DRAM_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
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Offset: 0x080C Register Name: DRAM_BGR_REG
Bit Read/Write Default/Hex Description
DRAM_RST
DRAM Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DRAM_GATING
Gating Clock for DRAM
0 R/W 0x1
0: Mask
1: Pass
3.3.6.55 0x0830 SMHC0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0830 Register Name: SMHC0_CLK_REG
Bit Read/Write Default/Hex Description
SMHC0_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SMHC0_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
26:24 R/W 0x0 001: PLL_PERI(1X)
010: PLL_PERI(2X)
011: PLL_AUDIO1(DIV2)
Others: Reserved
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
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Offset: 0x0830 Register Name: SMHC0_CLK_REG
Bit Read/Write Default/Hex Description
FACTOR_M
Factor M
3:0 R/W 0x0
M = FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.56 0x0834 SMHC1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0834 Register Name: SMHC1_CLK_REG
Bit Read/Write Default/Hex Description
SMHC1_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
26:24 R/W 0x0 001: PLL_PERI(1X)
010: PLL_PERI(2X)
011: PLL_AUDIO1(DIV2)
Others: Reserved
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
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3.3.6.57 0x0838 SMHC2 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0838 Register Name: SMHC2_CLK_REG
Bit Read/Write Default/Hex Description
SMHC2_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
001: PLL_PERI(1X)
26:24 R/W 0x0
010: PLL_PERI(2X)
011: PLL_PERI(800M)
100: PLL_AUDIO1(DIV2)
Others: Reserved
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.58 0x084C SMHC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x084C Register Name: SMHC_BGR_REG
Bit Read/Write Default/Hex Description
31:19 / / /
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Offset: 0x084C Register Name: SMHC_BGR_REG
Bit Read/Write Default/Hex Description
SMHC2_RST
SMHC2 Reset
18 R/W 0x0
0: Assert
1: De-assert
SMHC1_RST
SMHC1 Reset
17 R/W 0x0
0: Assert
1: De-assert
SMHC0_RST
SMHC0 Reset
16 R/W 0x0
0: Assert
1: De-assert
15:3 / / /
SMHC2_GATING
Gating Clock for SMHC2
2 R/W 0x0
0: Mask
1: Pass
SMHC1_GATING
Gating Clock for SMHC1
1 R/W 0x0
0: Mask
1: Pass
SMHC0_GATING
Gating Clock for SMHC0
0 R/W 0x0
0: Mask
1: Pass
3.3.6.59 0x090C UART Bus Gating Reset Register (Default Value: 0x0000_0000)
NOTE
The clock of the UART is from APB1.
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Offset: 0x090C Register Name: UART_BGR_REG
Bit Read/Write Default/Hex Description
31:22 / / /
UART5_RST
UART5 Reset
21 R/W 0x0
0: Assert
1: De-assert
UART4_RST
UART4 Reset
20 R/W 0x0
0: Assert
1: De-assert
UART3_RST
UART3 Reset
19 R/W 0x0
0: Assert
1: De-assert
UART2_RST
UART2 Reset
18 R/W 0x0
0: Assert
1: De-assert
UART1_RST
UART1 Reset
17 R/W 0x0
0: Assert
1: De-assert
UART0_RST
UART0 Reset
16 R/W 0x0
0: Assert
1: De-assert
15:6 / / /
UART5_GATING
Gating Clock for UART5
5 R/W 0x0
0: Mask
1: Pass
UART4_GATING
Gating Clock for UART4
4 R/W 0x0
0: Mask
1: Pass
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Offset: 0x090C Register Name: UART_BGR_REG
Bit Read/Write Default/Hex Description
UART3_GATING
Gating Clock for UART3
3 R/W 0x0
0: Mask
1: Pass
UART2_GATING
Gating Clock for UART2
2 R/W 0x0
0: Mask
1: Pass
UART1_GATING
Gating Clock for UART1
1 R/W 0x0
0: Mask
1: Pass
UART0_GATING
Gating Clock for UART0
0 R/W 0x0
0: Mask
1: Pass
3.3.6.60 0x091C TWI Bus Gating Reset Register (Default Value: 0x0000_0000)
NOTE
The clock of the TWI is from APB1.
Offset: 0x091C Register Name: TWI_BGR_REG
Bit Read/Write Default/Hex Description
31:20 / / /
TWI3_RST
TWI3 Reset
19 R/W 0x0
0: Assert
1: De-assert
TWI2_RST
TWI2 Reset
18 R/W 0x0
0: Assert
1: De-assert
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Offset: 0x091C Register Name: TWI_BGR_REG
Bit Read/Write Default/Hex Description
TWI1_RST
TWI1 Reset
17 R/W 0x0
0: Assert
1: De-assert
TWI0_RST
TWI0 Reset
16 R/W 0x0
0: Assert
1: De-assert
15:4 / / /
TWI3_GATING
Gating Clock for TWI3
3 R/W 0x0
0: Mask
1: Pass
TWI2_GATING
Gating Clock for TWI2
2 R/W 0x0
0: Mask
1: Pass
TWI1_GATING
Gating Clock for TWI1
1 R/W 0x0
0: Mask
1: Pass
TWI0_GATING
Gating Clock for TWI0
0 R/W 0x0
0: Mask
1: Pass
3.3.6.61 0x0940 SPI0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0940 Register Name: SPI0_CLK_REG
Bit Read/Write Default/Hex Description
SPI0_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.
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Offset: 0x0940 Register Name: SPI0_CLK_REG
Bit Read/Write Default/Hex Description
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
001: PLL_PERI(1X)
26:24 R/W 0x0
010: PLL_PERI(2X)
011: PLL_AUDIO1(DIV2)
100: PLL_AUDIO1(DIV5)
Others: Reserved
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.62 0x0944 SPI1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0944 Register Name: SPI1_CLK_REG
Bit Read/Write Default/Hex Description
SCLK_GATING
Gating Special Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.
30:27 / / /
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Offset: 0x0944 Register Name: SPI1_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
000: HOSC
001: PLL_PERI(1X)
26:24 R/W 0x0
010: PLL_PERI(2X)
011: PLL_AUDIO1(DIV2)
100: PLL_AUDIO1(DIV5)
Others: /
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.63 0x096C SPI Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x096C Register Name: SPI_BGR_REG
Bit Read/Write Default/Hex Description
31:18 / / /
SPI1_RST
SPI1 Reset
17 R/W 0x0
0: Assert
1: De-assert
SPI0_RST
SPI0 Reset
16 R/W 0x0
0: Assert
1: De-assert
15:2 / / /
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Offset: 0x096C Register Name: SPI_BGR_REG
Bit Read/Write Default/Hex Description
SPI1_GATING
Gating Clock for SPI1
1 R/W 0x0
0: Mask
1: Pass
SPI0_GATING
Gating Clock for SPI0
0 R/W 0x0
0: Mask
1: Pass
3.3.6.64 0x0970 EMAC_25M Clock Register (Default: 0x0000_0000)
Offset: 0x0970 Register Name: EMAC_25M_CLK_REG
Bit Read/Write Default/Hex Description
EMAC_25M_CLK_GATING
Gating Special Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
CLK = PLL_PERI(1X)/24 = 25 MHz
EMAC_25M_CLK_SRC_GATING
Gating the Source Clock of Special Clock
30 R/W 0x0 It is for low power design.
0: Clock is OFF
1: Clock is ON
29:0 / / /
3.3.6.65 0x097C EMAC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x097C Register Name: EMAC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
EMAC_RST
EMAC Reset
16 R/W 0x0
0: Assert
1: De-assert
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Offset: 0x097C Register Name: EMAC_BGR_REG
Bit Read/Write Default/Hex Description
15:1 / / /
EMAC_GATING
Gating Clock for EMAC
0 R/W 0x0
0: Mask
1: Pass
3.3.6.66 0x09C0 IRTX Clock Register (Default: 0x0000_0000)
Offset: 0x09C0 Register Name: IRTX_CLK_REG
Bit Read/Write Default/Hex Description
IRTX_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
IRTX_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0
0: HOSC
1: PLL_PERI(1X)
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
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3.3.6.67 0x09CC IRTX Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x09CC Register Name: IRTX_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
IRTX_RST
IRTX Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
IRTX_GATING
Gating Clock for IRTX
0 R/W 0x0
0: Mask
1: Pass
3.3.6.68 0x09EC GPADC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x09EC Register Name: GPADC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
GPADC_RST
GPADC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
GPADC_GATING
Gating Clock For GPADC
0 R/W 0x0
0: Mask
1: Pass
3.3.6.69 0x09FC THS Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x09FC Register Name: THS_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
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Offset: 0x09FC Register Name: THS_BGR_REG
Bit Read/Write Default/Hex Description
THS_RST
THS Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
THS_GATING
Gating Clock For THS
0 R/W 0x0
0: Mask
1: Pass
3.3.6.70 0x0A14 I2S/PCM1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A14 Register Name: I2S/PCM1_CLK_REG
Bit Read/Write Default/Hex Description
I2S/PCM1_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
I2S/PCM1_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
00: PLL_AUDIO0(1X)
26:24 R/W 0x0
01: PLL_AUDIO0(4X)
10: PLL_AUDIO1(DIV2)
11: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
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Offset: 0x0A14 Register Name: I2S/PCM1_CLK_REG
Bit Read/Write Default/Hex Description
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.71 0x0A18 I2S/PCM2 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A18 Register Name: I2S/PCM2_CLK_REG
Bit Read/Write Default/Hex Description
I2S/PCM2_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
I2S/PCM2_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
00: PLL_AUDIO0(1X)
26:24 R/W 0x0
01: PLL_AUDIO0(4X)
10: PLL_AUDIO1(DIV2)
11: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
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3.3.6.72 0x0A1C I2S/PCM2_ASRC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A1C Register Name: I2S/PCM2_ASRC_CLK_REG
Bit Read/Write Default/Hex Description
I2S/PCM2_ASRC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
I2S/PCM2_ASRC_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
00: PLL_AUDIO0(4X)
26:24 R/W 0x0
01: PLL_PERI(1X)
10: PLL_AUDIO1(DIV2)
11: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M = FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.73 0x0A20 I2S/PCM Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0A20 Register Name: I2S/PCM_BGR_REG
Bit Read/Write Default/Hex Description
31:19 / / /
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Offset: 0x0A20 Register Name: I2S/PCM_BGR_REG
Bit Read/Write Default/Hex Description
I2S/PCM2_RST
I2S/PCM2 Reset
18 R/W 0x0
0: Assert
1: De-assert
I2S/PCM1_RST
I2S/PCM1 Reset
17 R/W 0x0
0: Assert
1: De-assert
16:3 / / /
I2S/PCM2_GATING
Gating Clock for I2S/PCM2
2 R/W 0x0
0: Mask
1: Pass
I2S/PCM1_GATING
Gating Clock for I2S/PCM1
1 R/W 0x0
0: Mask
1: Pass
0 / / /
3.3.6.74 0x0A24 OWA_TX Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A24 Register Name: OWA_TX_CLK_REG
Bit Read/Write Default/Hex Description
OWA_TX_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
OWA_TX_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
00: PLL_AUDIO0(1X)
26:24 R/W 0x0
01: PLL_AUDIO0(4X)
10: PLL_AUDIO1(DIV2)
11: PLL_AUDIO1(DIV5)
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Offset: 0x0A24 Register Name: OWA_TX_CLK_REG
Bit Read/Write Default/Hex Description
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.75 0x0A28 OWA_RX Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A28 Register Name: OWA_RX_CLK_REG
Bit Read/Write Default/Hex Description
OWA_RX_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
OWA_RX_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0 000: PLL_PERI(1X)
001: PLL_AUDIO1(DIV2)
010: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
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Offset: 0x0A28 Register Name: OWA_RX_CLK_REG
Bit Read/Write Default/Hex Description
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.76 0x0A2C OWA Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0A2C Register Name: OWA_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
OWA_RST
OWA Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
OWA_GATING
Gating Clock for OWA
0 R/W 0x0
0: Mask
1: Pass
3.3.6.77 0x0A40 DMIC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A40 Register Name: DMIC_CLK_REG
Bit Read/Write Default/Hex Description
DMIC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
DMIC_CLK = Clock Source/M/N.
30:27 / / /
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Offset: 0x0A40 Register Name: DMIC_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0 00: PLL_AUDIO0(1X)
01: PLL_AUDIO1(DIV2)
10: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.78 0x0A4C DMIC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0A4C Register Name: DMIC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
DMIC_RST
DMIC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DMIC_GATING
Gating Clock for DMIC
0 R/W 0x0
0: Mask
1: Pass
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3.3.6.79 0x0A50 AUDIO_CODEC_DAC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A50 Register Name: AUDIO_CODEC_DAC_CLK_REG
Bit Read/Write Default/Hex Description
AUDIO_CODEC_DAC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
AUDIO_CODEC_DAC_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SE
Clock Source Select
26:24 R/W 0x0 00: PLL_AUDIO0(1X)
01: PLL_AUDIO1(DIV2)
10: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.80 0x0A54 AUDIO_CODEC_ADC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A54 Register Name: AUDIO_CODEC_ADC_CLK_REG
Bit Read/Write Default/Hex Description
AUDIO_CODEC_ADC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
AUDIO_CODEC_ADC_CLK = Clock Source/M/N.
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Offset: 0x0A54 Register Name: AUDIO_CODEC_ADC_CLK_REG
Bit Read/Write Default/Hex Description
30:27 / / /
CLK_SRC_SE
Clock Source Select
26:24 R/W 0x0 00: PLL_AUDIO0(1X)
01: PLL_AUDIO1(DIV2)
10: PLL_AUDIO1(DIV5)
23:10 / / /
FACTOR_N
Factor N
00: /1
9:8 R/W 0x0
01: /2
10: /4
11: /8
7:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.81 0x0A5C AUDIO_CODEC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0A5C Register Name: AUDIO_CODEC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
AUDIO_CODEC_RST
AUDIO_CODEC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
AUDIO_CODEC_GATING
Gating Clock For AUDIO_CODEC
0 R/W 0x0
0: Mask
1: Pass
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3.3.6.82 0x0A70 USB0 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A70 Register Name: USB0_CLK_REG
Bit Read/Write Default/Hex Description
USB0_CLKEN
Gating Special Clock For OHCI0
31 R/W 0x0
0: Clock is OFF
1: Clock is ON
USBPHY0_RSTN
USB PHY0 Reset
30 R/W 0x0
0: Assert
1: De-assert
29:26 / / /
USB0_CLK12M_SEL
OHCI0 12M Source Select
00: 12M divided from 48 MHz
25:24 R/W 0x0
01: 12M divided from 24 MHz
10: RTC_32K
11: /
23:0 / / /
3.3.6.83 0x0A74 USB1 Clock Register (Default Value: 0x0000_0000)
Offset: 0x0A74 Register Name: USB1_CLK_REG
Bit Read/Write Default/Hex Description
USB1_CLKEN
Gating Special Clock For OHCI1
31 R/W 0x0
0: Clock is OFF
1: Clock is ON
USBPHY1_RSTN
USB PHY1 Reset
30 R/W 0x0
0: Assert
1: De-assert
29:26 / / /
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Offset: 0x0A74 Register Name: USB1_CLK_REG
Bit Read/Write Default/Hex Description
USB1_CLK12M_SEL
OHCI0 12M Source Select
00: 12M divided from 48 MHz
25:24 R/W 0x0
01: 12M divided from 24 MHz
10: RTC_32K
11: /
23:0 / / /
3.3.6.84 0x0A8C USB Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0A8C Register Name: USB_BGR_REG
Bit Read/Write Default/Hex Description
31:25 / / /
USBDRD0_RST
USBDRD0 Reset
24 R/W 0x0
0: Assert
1: De-assert
23:22 / / /
USBEHCI1_RST
USBEHCI1 Reset
21 R/W 0x0
0: Assert
1: De-assert
USBEHCI0_RST
USBEHCI0 Reset
20 R/W 0x0
0: Assert
1: De-assert
19:18 / / /
USBOHCI1_RST
USBOHCI1 Reset
17 R/W 0x0
0: Assert
1: De-assert
USBOHCI0_RST
USBOHCI0 Reset
16 R/W 0x0
0: Assert
1: De-assert
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Offset: 0x0A8C Register Name: USB_BGR_REG
Bit Read/Write Default/Hex Description
15:9 / / /
USBDRD0_GATING
Gating Clock For USBDRD0
8 R/W 0x0
0: Mask
1: Pass
7:6 / / /
USBEHCI1_GATING
Gating Clock For USBEHCI1
5 R/W 0x0
0: Mask
1: Pass
USBEHCI0_GATING
Gating Clock For USBEHCI0
4 R/W 0x0
0: Mask
1: Pass
3:2 / / /
USBOHCI1_GATING
Gating Clock For USBOHCI1
1 R/W 0x0
0: Mask
1: Pass
USBOHCI0_GATING
Gating Clock For USBOHCI0
0 R/W 0x0
0: Mask
1: Pass
3.3.6.85 0x0ABC DPSS_TOP Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0ABC Register Name: DPSS_TOP_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
DPSS_TOP_RST
DPSS_TOP Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
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Offset: 0x0ABC Register Name: DPSS_TOP_BGR_REG
Bit Read/Write Default/Hex Description
DPSS_TOP_GATING
Gating Clock For DPSS_TOP
0 R/W 0x0
0: Mask
1: Pass
3.3.6.86 0x0B24 DSI Clock Register (Default Value: 0x0000_0000)
Offset: 0x0B24 Register Name: DSI_CLK_REG
Bit Read/Write Default/Hex Description
DSI_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
DSI_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
26:24 R/W 0x0 001: PLL_PERI(1X)
010: PLL_VIDEO0(2X)
011: PLL_VIDEO1(2X)
100: PLL_AUDIO1(DIV2)
23:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.87 0x0B4C DSI Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0B4C Register Name: DSI_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
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Offset: 0x0B4C Register Name: DSI_BGR_REG
Bit Read/Write Default/Hex Description
DSI_RST
DSI Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
DSI_GATING
Gating Clock For DSI
0 R/W 0x0
0: Mask
1: Pass
3.3.6.88 0x0B60 TCONLCD Clock Register (Default Value: 0x0000_0000)
Offset: 0x0B60 Register Name: TCONLCD_CLK_REG
Bit Read/Write Default/Hex Description
TCONLCD_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
TCONLCD_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: PLL_VIDEO0(1X)
001: PLL_VIDEO0(4X)
26:24 R/W 0x0
010: PLL_VIDEO1(1X)
011: PLL_VIDEO1(4X)
100: PLL_PERI(2X)
101: PLL_AUDIO1(DIV2)
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
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Offset: 0x0B60 Register Name: TCONLCD_CLK_REG
Bit Read/Write Default/Hex Description
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1.
FACTOR_M is from 0 to 15.
3.3.6.89 0x0B7C TCONLCD Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0B7C Register Name: TCONLCD_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
TCONLCD_RST
TCON LCD Reset
16 R/W 0x0
0: Assert
1: DE-assert
15:1 / / /
TCONLCD_GATING
Gating Clock For TCON LCD
0 R/W 0x0
0: Mask
1: Pass
3.3.6.90 0x0B80 TCONTV Clock Register (Default Value: 0x0000_0000)
Offset: 0x0B80 Register Name: TCONTV_CLK_REG
Bit Read/Write Default/Hex Description
TCONTV_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
TCONTV_CLK = Clock Source/M/N.
30:27 / / /
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Offset: 0x0B80 Register Name: TCONTV_CLK_REG
Bit Read/Write Default/Hex Description
CLK_SRC_SEL
Clock Source Select
000: PLL_VIDEO0(1X)
001: PLL_VIDEO0(4X)
26:24 R/W 0x0
010: PLL_VIDEO1(1X)
011: PLL_VIDEO1(4X)
100: PLL_PERI(2X)
101: PLL_AUDIO1(DIV2)
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.91 0x0B9C TCONTV Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0B9C Register Name: TCONTV_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
TCONTV_RST
TCONTV Reset
16 R/W 0x0
0: Assert
1: DE-assert
15:1 / / /
TCONTV_GATING.
Gating Clock For TCONTV
0 R/W 0x0
0: Mask
1: Pass
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3.3.6.92 0x0BAC LVDS Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0BAC Register Name: LVDS_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
LVDS0_RST
LVDS0 Reset
16 R/W 0x0
0: Assert
1: De-assert
15:0 / / /
3.3.6.93 0x0BB0 TVE Clock Register (Default Value: 0x0000_0000)
Offset: 0x0BB0 Register Name: TVE_CLK_REG
Bit Read/Write Default/Hex Description
TVE_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
TVE_CLK = Clock Source/M/N.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: PLL_VIDEO0(1X)
001: PLL_VIDEO0(4X)
26:24 R/W 0x0
010: PLL_VIDEO1(1X)
011: PLL_VIDEO1(4X)
100: PLL_PERI(2X)
101: PLL_AUDIO1(DIV2)
23:10 / / /
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Offset: 0x0BB0 Register Name: TVE_CLK_REG
Bit Read/Write Default/Hex Description
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
3.3.6.94 0x0BBC TVE Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0BBC Register Name: TVE_BGR_REG
Bit Read/Write Default/Hex Description
31:18 / / /
TVE_RST
TVE Reset
17 R/W 0x0
0: Assert
1: DE-assert
TVE_TOP_RST
TVE_TOP Reset
16 R/W 0x0
0: Assert
1: DE-assert
15:2 / / /
TVE_GATING
Gating Clock For TVE
1 R/W 0x0
0: Mask
1: Pass
TVE_TOP_GATING
Gating Clock For TVE_TOP
0 R/W 0x0
0: Mask
1: Pass
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3.3.6.95 0x0BC0 TVD Clock Register (Default Value: 0x0000_0000)
Offset: 0x0BC0 Register Name: TVD_CLK_REG
Bit Read/Write Default/Hex Description
TVD_CLK_GATING
Gating Special Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
TVD_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
26:24 R/W 0x0
001: PLL_VIDEO0(1X)
010: PLL_VIDEO1(1X)
011: PLL_PERI(1X)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.96 0x0BDC TVD Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0BDC Register Name: TVD_BGR_REG
Bit Read/Write Default/Hex Description
31:18 / / /
TVD_RST
TVD Reset
17 R/W 0x0
0: Assert
1: De-assert
TVD_TOP_RST
TVD_TOP Reset
16 R/W 0x0
0: Assert
1: De-assert
15:2 / / /
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Offset: 0x0BDC Register Name: TVD_BGR_REG
Bit Read/Write Default/Hex Description
TVD_GATING
Gating Clock For TVD
1 R/W 0x0
0: Mask
1: Pass
TVD_TOP_GATING
Gating Clock For TVD_TOP
0 R/W 0x0
0: Mask
1: Pass
3.3.6.97 0x0BF0 LEDC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0BF0 Register Name: LEDC_CLK_REG
Bit Read/Write Default/Hex Description
LDEC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
LEDC_CLK = Clock Source/M/N.
30:25 / / /
CLK_SRC_SEL
Clock Source Select
24 R/W 0x0
0: HOSC
1: PLL_PERI(1X)
23:10 / / /
FACTOR_N
Factor N
00: 1
9:8 R/W 0x0
01: 2
10: 4
11: 8
7:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
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3.3.6.98 0x0BFC LEDC Bus Gating Reset Register (Default: 0x0000_0000)
Offset: 0x0BFC Register Name: LEDC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
LEDC_RST
LEDC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
LEDC_GATING
Gating Clock For LEDC
0 R/W 0x0
0: Mask
1: Pass
3.3.6.99 0x0C04 CSI Clock Register (Default Value: 0x0000_0000)
Offset: 0x0C04 Register Name: CSI_CLK_REG
Bit Read/Write Default/Hex Description
CSI_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
CSI_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0 000: PLL_PERI(2X)
001: PLL_VIDEO0(2X)
010: PLL_VIDEO1(2X)
23:4 / / /
FACTOR_M
Factor M
3:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 15.
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3.3.6.100 0x0C08 CSI Master Clock Register (Default Value: 0x0000_0000)
Offset: 0x0C08 Register Name: CSI_MASTER_CLK_REG
Bit Read/Write Default/Hex Description
CSI_MASTER_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
CSI_MASTER_CLK = Clock Source/M.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
000: HOSC
001: PLL_PERI(1X)
26:24 R/W 0x0
010: PLL_VIDEO0(1X)
011: PLL_VIDEO1(1X)
100: PLL_AUDIO1(DIV2)
101: PLL_AUDIO1(DIV5)
23:5 / / /
FACTOR_M
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.101 0x0C1C CSI Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0C1C Register Name: CSI_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
CSI_RST
CSI Reset
16 R/W 0x0
0: Assert
1: DE-assert
15:1 / / /
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Offset: 0x0C1C Register Name: CSI_BGR_REG
Bit Read/Write Default/Hex Description
CSI_GATING
Gating Clock For CSI
0 R/W 0x0
0: Mask
1: Pass
3.3.6.102 0x0C50 TPADC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0C50 Register Name: TPADC_CLK_REG
Bit Read/Write Default/Hex Description
TPADC_CLK_GATING
Gating Clock
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
TPADC_CLK = Clock Source.
30:27 / / /
CLK_SRC_SEL
Clock Source Select
26:24 R/W 0x0
000: HOSC
001: PLL_AUDIO0(1X)
23:0 / / /
3.3.6.103 0x0C5C TPADC Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0C5C Register Name: TPADC_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
TPADC_RST
TPADC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
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Offset: 0x0C5C Register Name: TPADC_BGR_REG
Bit Read/Write Default/Hex Description
TPADC_GATING
Gating Clock For TPADC
0 R/W 0x0
0: Mask
1: Pass
3.3.6.104 0x0D00 RISC Clock Register (Default Value: 0x0000_0000)
Offset: 0x0D00 Register Name: RISC_CLK_REG
Bit Read/Write Default/Hex Description
31:27 / / /
RISC_CLK_SEL
Clock Source Select
000: HOSC
001: CLK32K
010: CLK16M_RC
26:24 R/W 0x0 011: PLL_PERI(800M)
100: PLL_PERI(1X)
101: PLL_CPU
110: PLL_AUDIO1(DIV2)
RISC Clock = Clock Source/M.
RISC_AXI Clock = RISC Clock/N.
23:10 / / /
RISC_AXI_DIV_CFG
Factor N
N = FACTOR_N +1
9:8 R/W 0x1
FACTOR_N is from 1 to 3.
Note: The clock division is lack of glitch switching and supports
dynamic configuration.
7:5 / / /
RISC_DIV_CFG
Factor M
4:0 R/W 0x0
M = FACTOR_M +1
FACTOR_M is from 0 to 31.
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3.3.6.105 0x0D04 RISC Gating Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0D04 Register Name: RISC_GATING_REG
Bit Read/Write Default/Hex Description
RISC_GATING
Gating Special Clock
31 R/W 0x1
0: Clock is OFF
1: Clock is ON
30:16 / / /
RISC_GATING_FIELD
15:0 W 0x0
If RISC_gating_field == 16’h16AA, the bit 31 can be configured.
3.3.6.106 0x0D0C RISC_CFG Bus Gating Reset Register (Default Value: 0x0000_0000)
Offset: 0x0D0C Register Name: RISC_CFG_BGR_REG
Bit Read/Write Default/Hex Description
31:17 / / /
RISC_CFG_RST
RISC Reset
16 R/W 0x0
0: Assert
1: De-assert
15:1 / / /
RISC_CFG_GATING
Gating Clock For RISC
0 R/W 0x0
0: Mask
1: Pass
3.3.6.107 0x0F04 PLL Lock Debug Control Register (Default Value: 0x0000_0000)
Offset: 0x0F04 Register Name: PLL_LOCK_DBG_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_LOCK_FLAG_EN
Debug Enable
31 R/W 0x0
0: Disable
1: Enable
30:23 / / /
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Offset: 0x0F04 Register Name: PLL_LOCK_DBG_CTRL_REG
Bit Read/Write Default/Hex Description
PLL_LOCK_FLAG_SEL
Debug Select
000: PLL_CPUX
001: PLL_DDR
010: PLL_PERI(2X)
22:20 R/W 0x0 011: PLL_VIDEO0(4X)
100: PLL_VIDEO1(4X)
101: PLL_VE
110: PLL_AUDIO0
111: PLL_AUDIO1
Others: /
19:0 / / /
3.3.6.108 0x0F08 Frequence Detect Control Register (Default Value: 0x0000_0020)
Offset: 0x0F08 Register Name: FRE_DET_CTRL_REG
Bit Read/Write Default/Hex Description
ERROR_FLAG
Error Flag
31 R/W0C 0x0
0: Write 0 to clear
1: Error
30:9 / / /
DET_TIME
Detect Time
8:4 R/W 0x2
Time=1/32k*(2^RegValue)
RegValue is from 0 to 16.
3:2 / / /
FRE_DET_IRQ_EN
Frequence Detect IRQ Enable
1 R/W 0x0
0: Disable
1: Enable
FRE_DET_FUN_EN
Frequence Detect Function Enable
0 R/W 0x0
0: Disable
1: Enable
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3.3.6.109 0x0F0C Frequence Up Limit Register (Default Value: 0x0000_0000)
Offset: 0x0F0C Register Name: FRE_UP_LIM_REG
Bit Read/Write Default/Hex Description
FRE_UP_LIM
Frequence Up Limit
31:0 R/W 0x0
The value of the register must be an integral multiple of 32. The
unit is kHz.
3.3.6.110 0x0F10 Frequence Down Limit Register (Default Value: 0x0000_0000)
Offset: 0x0F10 Register Name: FRE_DOWN_LIM_REG
Bit Read/Write Default/Hex Description
FRE_DOWN_LIM
Frequence Down Limit
31:0 R/W 0x0
The value of the register must be an integral multiple of 32. The
unit is kHz.
3.3.6.111 0x0F20 RISC LOCK Reset Register (Default Value: 0x0000_0000)
Offset: 0x0F20 Register Name: RISC_RST_REG
Bit Read/Write Default/Hex Description
RISC_KEY_FIELD
31:16 W 0x0 Key field for risc soft reset
If the key field value is 0x16AA, the bit[0] can be modified.
15:1 / / /
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Offset: 0x0F20 Register Name: RISC_RST_REG
Bit Read/Write Default/Hex Description
RISC_SOFT_RSTN
Reset for RISC
0: Assert
1: De-assert
0 R/W UDF When only RISC CPU exists, the RISC reset is de-asserted, and the
ARM reset is asserted, so the RISC_SOFT_RSTN bit is 1 by default.
When RISC coexists with ARM, the ARM reset is de-asserted, and
the RISC reset is asserted, so the RISC_SOFT_RSTN bit is 0 by
default. But whether RISC and ARM are locked is controlled by
the eFuse bit of SID module.
3.3.6.112 0x0F30 CCU FANOUT Clock Gate Register (Default Value: 0x0000_0000)
Offset: 0x0F30 Register Name: CCU_FAN_GATE_REG
Bit Read/Write Default/Hex Description
31:5 / / /
CLK32K_EN
Gating for CLK32K
4 R/W 0x0
0: Clock is OFF
1: Clock is ON
CLK25M_EN
Gating for CLK25M
3 R/W 0x0
0: Clock is OFF
1: Clock is ON
CLK16M_EN
Gating for CLK16M
2 R/W 0x0
0: Clock is OFF
1: Clock is ON
CLK12M_EN
Gating for CLK12M
1 R/W 0x0
0: Clock is OFF
1: Clock is ON
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Offset: 0x0F30 Register Name: CCU_FAN_GATE_REG
Bit Read/Write Default/Hex Description
CLK24M_EN
Gating for CLK24M
0 R/W 0x0
0: Clock is OFF
1: Clock is ON
3.3.6.113 0x0F34 CLK27M FANOUT Register (Default Value: 0x0000_0000)
Offset: 0x0F34 Register Name: CLK27M_FAN_REG
Bit Read/Write Default/Hex Description
CLK27M_EN
Gating for CLK27M
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
SCLK = Clock Source/M/N.
30:26 / / /
CLK27M_SCR_SEL
Clock Source Select
000: PLL_VIDEO0(1X)
25:24 R/W 0x0
001: PLL_VIDEO1(1X)
010: /
011: /
23:10 / / /
CLK27M_DIV1
Factor N
9:8 R/W 0x0
N= FACTOR_N +1.
FACTOR_N is from 0 to 3.
7:5 / / /
CLK27M_DIV0
Factor M
4:0 R/W 0x0
M= FACTOR_M +1.
FACTOR_M is from 0 to 31.
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3.3.6.114 0x0F38 PCLK FANOUT Register (Default Value: 0x0000_0000)
Offset: 0x0F38 Register Name: PCLK_FAN_REG
Bit Read/Write Default/Hex Description
PCLK_DIV_EN
Gating for PCLK
31 R/W 0x0 0: Clock is OFF
1: Clock is ON
PCLK = APB0_CLK/M.
30:5 / / /
PCLK_DIV
Factor M
4:0 R/W 0x0
M= FACTOR_M +1
FACTOR_M is from 0 to 31.
3.3.6.115 0x0F3C CCU FANOUT Register (Default Value: 0x0000_0000)
Offset: 0x0F3C Register Name: CCU_FAN_REG
Bit Read/Write Default/Hex Description
31:27 / / /
26:24 R/W 0x0 Reserved
CLK_FANOUT2_EN
Gating for CLK_FANOUT2
23 R/W 0x0
0: Clock is OFF
1: Clock is ON
CLK_FANOUT1_EN
Gating for CLK_FANOUT1
22 R/W 0x0
0: Clock is OFF
1: Clock is ON
CLK_FANOUT0_EN
Gating for CLK_FANOUT0
21 R/W 0x0
0: Clock is OFF
1: Clock is ON
20:18 / / /
17:9 R/W 0x0 Reserved
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Offset: 0x0F3C Register Name: CCU_FAN_REG
Bit Read/Write Default/Hex Description
CLK_FANOUT2_SEL
000:CLK32K (From PLL_PERI(2X))
001:CLK12M (From DCXO/2)
010:CLK16M (From PLL_PERI(2X))
011:CLK24M (From DCXO)
8:6 R/W 0x0
100:CLK25M (From PLL_PERI(1X))
101:CLK27M
110:PCLK
CLK_FANOUT2 can be selected to output from the above seven
sources.
CLK_FANOUT1_SEL
000:CLK32K (From PLL_PERI(2X))
001:CLK12M (From DCXO/2)
010:CLK16M (From PLL_PERI(2X))
011:CLK24M (From DCXO)
5:3 R/W 0x0
100:CLK25M (From PLL_PERI(1X))
101:CLK27M
110:PCLK
CLK_FANOUT1 can be selected to output from the above seven
sources.
CLK_FANOUT0_SEL
000:CLK32K (From PLL_PERI(2X))
001:CLK12M (From DCXO)
010:CLK16M (From PLL_PERI(2X))
011:CLK24M (From DCXO)
2:0 R/W 0x0
100:CLK25M (From PLL_PERI(1X))
101:CLK27M
110:PCLK
CLK_FANOUT0 can be selected to output from the above seven
sources.
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3.4 BROM System
3.4.1 Overview
The system has several ways to boot. It has an integrated on-chip Boot ROM (BROM) that is considered the
primary program-loader. On the startup process, the F133 starts to fetch the first instruction from address 0x0,
where is the BROM located at.
The BROM system is divided into two parts: the firmware exchange launch (FEL) module and the Medium Boot
module. FEL is responsible for writing the external data to the local NVM, and Medium Boot is responsible for
loading an effective and legitimate BOOT0 from NVM and running.
The BROM system includes the following features:
Supports CPU0 boot process
Supports mandatory upgrade process through USB and SD card
Supports GPIO pin and eFuse to select the boot media type
3.4.2 Functional Description
3.4.2.1 Selecting the Boot Medium
The BROM system supports the following boot media:
SD card
eMMC
SPI NOR FLASH
SPI NAND FLASH
There are two ways to select the boot medium: GPIO Pin Select and eFuse Select. On startup, the BROM will
read the state of BOOT_MODE, and decide whether the GPIO or eFuse to select the type of boot medium based
on the state of BOOT_MODE. The BOOT_MODE is the bit of the SID module (register: 0x03006210).
The following table shows BOOT_MODE Setting.
Table 3-4 BOOT_MODE Setting
BOOT_MODE Boot_Select Type
0 GPIO boot select, indicates that the boot medium is decided by the value of the GPIO pin.
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BOOT_MODE Boot_Select Type
eFuse boot select, indicates that the boot medium is decided by the value of the eFuse
1
type.
GPIO Boot Select
If the state of the BOOT_MODE is 0, the boot medium is decided by the value of the GPIO pin. The following
table shows the boot medium priority. The boot medium priority describes the possibility that each medium
to be selected as the boot medium. The BROM reads the boot0 of the medium with the highest priority first. If
the medium does not exist or has any problems, the BROM will try the next medium. Otherwise, the medium
will be selected as the boot medium.
Table 3-5 GPIO Boot Select Configuration
Pin_Boot_Select[1:0] Boot Medium Priority
00 SPI NOR->SPI NAND
01 SMHC0->SPI NOR->other media
10 SMHC0->SPI NAND->other media
11 SMHC0->EMMC2_BOOT->EMMC2_USR->other media
NOTE
The status of the GPIO boot select pin can be read by the bit[12:11] of the system configuration module
(register: 0x03000024).
eFuse Boot Select
If the state of the BOOT_MODE is 1, the boot medium is decided by the value of eFuse_Boot_Select_Cfg. The
eFuse_Boot_Select_Cfg is divided into 4 groups and each group is 3-bit. The following table shows the groups
of eFUSE_Boot_Select.
NOTE
The status of the efuse boot select pin can be read by the bit[27:16] of the SID module (register:
0x03006210).
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Table 3-6 Groups of eFuse_Boot_Select
eFuse_Boot_Select_Cfg[11:0] Group
eFuse_Boot_Select_Cfg[2:0] eFuse_Boot_Select_1
eFuse_Boot_Select_Cfg[5:3] eFuse_Boot_Select_2
eFuse_Boot_Select_Cfg[8:6] eFuse_Boot_Select_3
eFuse_Boot_Select_Cfg[11:9] eFuse_Boot_Select_4
The four groups take effect with the following priority:
eFuse_Boot_Select_1 -> eFuse_Boot_Select_2 -> eFuse_Boot_Select_3 -> eFuse_Boot_Select_4
For example, eFuse_Boot_Select_2 will not take effect unless eFuse_Boot_Select_1 is set as 0x111,
eFuse_Boot_Select_3 will not take effect unless eFuse_Boot_Select_2 is set as 0x111, and so on.
The following table shows the boot medium priority for the different values of eFuse_Boot_Select_n, where n
= [4:1]. The eFuse_Boot_Select_1 to eFuse_Boot_Select_3 are the same setting. But for eFuse_Boot_Select_4,
if its value is 0x111, the BROM will select the boot medium in the Try mode. The BROM in the Try mode follows
the order below to select the boot medium:
SMHC0 -> SPI NOR -> SPI NAND -> SMHC2
Table 3-7 eFuse Boot Select Setting
eFuse_Boot_Select_n Boot Medium Priority
000 Select the boot medium in Try mode.
001 Reserved
010 SHMC2
011 SPI NOR
100 SPI NAND
101 Reserved
110 Reserved
When n is 1 to 3:
The boot medium is decided by the value of eFuse_Boot_Select_(n + 1).
111
When n is 4:
Select the boot medium in Try mode.
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3.4.2.2 BROM Process
The following figure shows the BROM process.
Figure 3-6 BROM Process
RISC CPU Boot
Hotplug Flag
Read Hotplug
Hotplug Process
Flag
others
Selected Unselected
FEL_SEL
Fail
Mandatory Upgrade Try Media Boot
Process Process
Pass
Mandatory Upgrade
Finishes Run Boot0
Hotplug Process
The Hotplug Flag determines whether the system will do Hotplug boot, if the CPU Hotplug Flag value is equal
to 0xFA50392F, then read the Soft Entry Register and the system will jump to the Soft Entry Address. The
following figure shows the CPU0 Hotplug Process.
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Figure 3-7 CPU0 Hotplug Process Diagram
NOTE
The Hotplug Flag Register is 0x070005DC.
The Soft Entry Address Register is 0x070005E0.
Mandatory Upgrade Process
If the FEL pin is detected to pull low, the system will jump to the mandatory upgrade process. The following
figure shows the mandatory upgrade process.
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Figure 3-8 Mandatory Upgrade Process
Mandatory Upgrade
Start
Jump to the FEL
address
End
NOTE
The status of the FEL pin is the bit[8] of the system configuration module (register: 0x03000024).
FEL Process
When the system chooses to enter the Mandatory Upgrade Process, the system will jump to the FEL process.
The following figure shows the FEL upgrade process.
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Figure 3-9 USB FEL Process
FEL Start
Clock_init
USB_init
Wait for USB
connection Not-Connected
Connected
USB enums
Wait for Not received
commands
Received
Return success Return failure
Execute commands
command command
Yes Executed No
successfully
3.4.2.3 Fast Boot Process
If the value of the Fast Boot register (0x07090120) in RTC module is not zero, the system will enter the Fast
Boot Process. The following table shows the boot medium priority for different values of the Fast Boot register.
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Table 3-8 Fast Boot Select Setting
Reg_bit[31:28] Boot Medium Priority
1 Try process
2 SMHC0->EMMC2_USER->EMMC2_BOOT->Other media
3 SMHC0->SPI NOR->Other media
4 SMHC0->SPI NAND->Other media
5 EMMC2_BOOT->EMMC2_USER->Other media
6 SMHC0->Try process
7 SMHC0->Try process
NOTE
The bit[28:0] of Fast Boot register is used to record the media information.
The try process is SMHC0->SPI NOR->SPI NAND->EMMC2_USER->EMMC2_BOOT.
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3.5 System Configuration
3.5.1 Overview
The system configuration module is used to configure parameters for system domain, such as SRAM, CPU, PLL,
BROM, and so on.
3.5.2 Register List
Module Name Base Address
SYS_CFG 0x03000000
Register Name Offset Description
VER_REG 0x0024 Version Register
EMAC_EPHY_CLK_REG0 0x0030 EMAC-EPHY Clock Register 0
SYS_LDO_CTRL_REG 0x0150 System LDO Control Register
RESCAL_CTRL_REG 0x0160 Resistor Calibration Control Register
RES240_CTRL_REG 0x0168 240ohms Resistor Manual Control Register
RESCAL_STATUS_REG 0x016C Resistor Calibration Status Register
3.5.3 Register Description
3.5.3.1 0x0024 Version Register (Default Value: UDF)
Offset: 0x0024 Register Name: VER_REG
Bit Read/Write Default/Hex Description
31:13 / / /
BOOT_SEL_PAD_STA
12:11 R UDF The value of this bit decides the priority order for each medium
type to be selected as the boot media.
10:9 / / /
FEL_SEL_PAD_STA
Fel_Select_Pin_Status
8 R UDF
0: Run_FEL
1: Try Media Boot
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Offset: 0x0024 Register Name: VER_REG
Bit Read/Write Default/Hex Description
7:0 / / /
3.5.3.2 0x0030 EMAC-EPHY Clock Register 0 (Default Value: 0x0005_8000)
Offset: 0x0030 Register Name: EMAC_EPHY_CLK_REG0
Bit Read/Write Default/Hex Description
31:28 R/W 0x0 BPS_EFUSE
XMII_SEL
27 R/W 0x0 0: Internal SMI and MII
1: External SMI and MII
EPHY_MODE
Operation Mode Selection
00: Normal Mode
26:25 R/W 0x0
01: Simulation Mode
10: AFE Test Mode
11: Reserved
PHY_ADDR
24:20 R/W 0x0
PHY Address
19 R/W 0x0 Reserved
CLK_SEL
18 R/W 0x1 0: 25 MHz
1: 24 MHz
LED_POL
17 R/W 0x0 0: High active
1: Low active
SHUTDOWN
16 R/W 0x1 0: Power up
1: Shut down
PHY_SELECT
15 R/W 0x1 0: External PHY
1: Internal PHY
14 / / /
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Offset: 0x0030 Register Name: EMAC_EPHY_CLK_REG0
Bit Read/Write Default/Hex Description
RMII_EN
0: Disable RMII Module
13 R/W 0x0 1: Enable RMII Module
This bit is prior to bit[2]. When this bit is asserted, the MII and
RGMII interfaces will be both disabled.
ETXDC
12:10 R/W 0x0
Configure EMAC Transmit Clock Delay Chain
ERXDC
9:5 R/W 0x0
Configure EMAC Receive Clock Delay Chain
ERXIE
Enable EMAC Receive Clock Invertor
4 R/W 0x0
0: Disabled
1: Enabled
ETXIE
Enable EMAC Transmit Clock Invertor
3 R/W 0x0
0: Disabled
1: Enabled
EPIT
EMAC PHY Interface Type
2 R/W 0x0
0: MII
1: RGMII
ETCS
EMAC Transmit Clock Source
00: Transmit clock source for MII
1:0 R/W 0x0
01: External transmit clock source for GMII and RGMII
10: Internal transmit clock source for GMII and RGMII
11: Reserved
3.5.3.3 0x0150 System LDO Control Register (Default Value: 0x0000_0E0F)
Offset: 0x0150 Register Name: SYS_LDO_CTRL_REG
Bit Read/Write Default/Hex Description
SPARE
31:24 R/W 0x0
Reserved spare register
23:22 / / /
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Offset: 0x0150 Register Name: SYS_LDO_CTRL_REG
Bit Read/Write Default/Hex Description
21 R/W 0x0 reserved
20 R/W 0x0 reserved
19:18 / / /
17 R/W 0x0 reserved
16 R/W 0x0 reserved
LDOB_TRIM
LDOB Trimming.
Adjust LDOB output, only the low 6-bit is used.
000000:1.167
000001:1.18
000010:1.193
000011:1.207
000100:1.22
000101:1.233
000110:1.247
000111:1.260
001000:1.273
001001:1.287
001010:1.3
001011:1.313
15:8 R/W 0xE 001100:1.327
001101:1.340
001110:1.353 (default)
001111:1.367
010000:1.38
010001:1.393
010010:1.407
010011:1.42
010100:1.433
010101:1.447
010110:1.46
010111:1.473
011000:1.487
011001:1.5
011010:1.513
011011:1.527
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Offset: 0x0150 Register Name: SYS_LDO_CTRL_REG
Bit Read/Write Default/Hex Description
011100:1.54
011101:1.553
011110:1.567
011111:1.58
100000:1.593
100001:1.607
100010:1.627
100011:1.64
100100:1.653
100101:1.667
100110:1.680
100111:1.693
101000:1.707
101001:1.720
101010:1.733
101011:1.747
101100:1.76
101101:1.773
101110:1.787
101111:1.8
110000:1.813
110001:1.827
110010:1.84
110011:1.853
110100:1.867
110101:1.88
110110:1.893
110111:1.907
111000:1.92
111001:1.933
111010:1.947
111011:1.96
111100:1.973
111101:1.987
111110:2
111111:2.013
7:0 R/W 0xF LDOA_TIM.
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Offset: 0x0150 Register Name: SYS_LDO_CTRL_REG
Bit Read/Write Default/Hex Description
LDOA Trimming
Adjust LDOA output, only the low 5-bit is used.
00000:1.593
00001:1.607
00010:1.627
00011:1.64
00100:1.653
00101:1.667
00110:1.680
00111:1.693
01000:1.707
01001:1.720
01010:1.733
01011:1.747
01100:1.76
01101:1.773
01110:1.787
01111:1.8 (default)
10000:1.813
10001:1.827
10010:1.84
10011:1.853
10100:1.867
10101:1.88
10110:1.893
10111:1.907
11000:1.92
11001:1.933
11010:1.947
11011:1.96
11100:1.973
11101:1.987
11110:2
11111:2.013
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3.5.3.4 0x0160 Resistor Calibration Control Register (Default Value: 0x0033_0003)
Offset: 0x0160 Register Name: RESCAL_CTRL_REG
Bit Read/Write Default/Hex Description
31:25 / / /
24 R/W 0x0 Reserved
23:22 / / /
21:16 R/W 0x33 Reserved
15:9 / / /
DDR_RES240_Trimming_SEL
240ohms Resistor Trimming Source Select
8 R/W 0x0
0: Trimming value from RESCAL
1: Trimming value from RES240_TRIM
7:3 / / /
RESCAL_MODE
RESCAL Calibration Mode Select
2 R/W 0x0
0: Auto Calibration
1: Reserved
CAL_ANA_EN.
Calibration Circuits Analog Enable
1 R/W 0x1
0: Disable
1: Enable
CAL_EN
Auto Calibration Enable
0 R/W 0x1
0: Disable
1: Enable
3.5.3.5 0x0168 240ohms Resistor Manual Control Register (Default Value: 0x0000_0033)
Offset: 0x0168 Register Name: RES240_CTRL_REG
Bit Read/Write Default/Hex Description
31:6 / / /
DDR_RES240_TRIM
5:0 R/W 0x33
240ohms Resistor trimming bit
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3.5.3.6 0x016C Resistor Calibration Status Register (Default Value: 0x0000_0000)
Offset: 0x016C Register Name: RESCAL_STATUS_REG
Bit Read/Write Default/Hex Description
31:9 / / /
COUT
8 RO 0x0
Calibration Circuits Analog Compare Output
7:6 / / /
RES_CAL_DO
5:0 RO 0x0
RESCAL Calibration Results Output
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3.6 Timer
3.6.1 Overview
The timer module implements the timing and counting functions. The timer module includes timer0, timer1,
watchdog and audio video synchronization (AVS).
The timer0 and timer1 are completely consistent. The main features for timer0 and timer1 are as follows:
Alternative count clock: LOSC or OSC24M. The LOSC can be either the internal or external low-frequency
clock, and the external one has more accuracy.
Supports 8 prescale factors
Programmable 32-bit down timer
Supports two timing modes: periodic mode and single counting mode
Generates an interrupt when the count is decreased to 0
The watchdog is used to transmit a reset signal to reset the entire system when an exception occurs in the
system. The main features for the watchdog are as follows:
Single clock source: OSC24M/750
Supports 12 initial values
Supports the generation of timeout interrupts
Supports the generation of reset signals
Supports Watchdog Restart
The AVS is used to synchronize the audio and video. The AVS module includes AVS0 and AVS1, which are
completely consistent. The main features for the AVS are as follows:
Single clock source: OSC24M
Programmable 33-bit up timer
Supports updating the initial value anytime
12-bit frequency divider factor
Supports Pause/Start function
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3.6.2 Block Diagram
The following figure shows the functional block diagram of the timer module.
Figure 3-10 Timer Block Diagram
APB0
reset
Watchdog Timer AVS
irq irq
The watchdog, timer (including timer0 and timer1), and AVS are all mounted at the APB0 bus. The system
configures the parameters of these configure registers via APB0 bus.
The timer and watchdog are both down counters and support generating interrupts after the counting value
reaches 0.
For watchdog, the system is responsible for configuring the interval value. If the system fails to restart the
watchdog regularly because of some exceptional situations, such as the bus hang, the watchdog will send out
a Watchdog Reset External signal to reset the system. And the signal will be transmitted to the Reset pad to
reset the PMIC.
3.6.3 Functional Description
3.6.3.1 Timer
The timer (including timer0 and timer1) is a 32-bit down counter. The counter value is decremented by 1 on
each rising edge of the timer clock.
The following figure shows the block diagram for the timer.
Figure 3-11 Block Diagram for the Timer
/1
/2
IRQ EN
/4
Single Counting
/8 Timer 0
OSC24M Mode
Yes
/16 Interval Value Enable IV = 0? Pending IRQ
LOSC /32
Timer 1 Periodic Mode
/64
/128
The clock source for the timer can be either OSC24M or LOSC. For LOSC, it can be either the internal or external
low-frequency clock. The external one has more accuracy.
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Each timer has a prescale that divides the working clock frequency by 1, 2, 4, 8, 16, 32, 64, or 128. And each
timer can generate independent interrupts.
Timing Modes
The timer has two timing modes: the single counting mode and periodic mode. You can configure the timing
mode via the bit[7] of TMRn_CTRL_REG (n = 0 or 1). The value 0 is for the period mode and value 1 is for the
single counting mode.
Single Counting Mode
In the single counting mode, the timer starts counting from the interval value and generates an interrupt
after the counter decreases to 0, and then stops counting. It starts to count again only when a new interval
value is loaded.
Periodic Mode
In the periodic mode, the timer restarts another round of counting after generating the interrupt. It
reloads data from the TMRn_INTV_VALUE_REG and then continues to count.
Formula for Calculating the Timer Time
The following formula decribes the relationship among timer parameters.
TMRn_INTV_VALUE_REG TMRn_CUR_VALUE_REG
Ttimer TMRn_CLK_PRES
TMRn_CLK_SRC
Where,
The parameter n is either 0 or 1;
Ttimer is the remaining time of the timer;
TMRn_INTV_VALUE_REG is the interval value of the timer;
TMRn_CUR_VALUE_REG is the current value of the timer;
TMRn_CLK_SRC is the frequency of the timer clock source;
TMRn_CLK_PRES is the prescale ratio of the timer clock.
Initializing the Timer
Follow the steps below to initialize the timer:
1. Configure the timer parameters clock source, prescale factor, and timing mode by writing
TMRn_CTRL_REG. There is no sequence requirement of configuring the parameters.
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2. Write the interval value.
a) Write TMRn_INTV_VALUE_REG to configure the interval value for the timer.
b) Write bit[1] of TMRn_CTRL_REG to load the interval value to the timer. The value of the bit will be
cleared automatically after loading the interval value.
3. Write bit[0] of TMRn_CTRL_REG to start the timer. To get the current value of the timer, read
TMRn_CUR_VALUE_REG.
Processing the Interrupt
Follow the steps below to process the interrupt:
1. Enable interrupts for the timer: write the enable bit of the corresponding interrupt in TMR_IRQ_EN_REG
for the timer. The timer will generate an interrupt everytime the count value reaches 0.
2. After entering the interrupt process, write the pending bit of the corresponding interrupt in
TMR_IRQ_STA_REG to clear the interrupt pending, and execute the process of waiting for the interrupt.
3. Resume the interrupt and continue to execute the interrupted process.
3.6.3.2 Watchdog
The watchdog is a 32-bit down counter. The counter value is decremented by 1 on each rising edge of the count
clock.
The following figure shows the block diagram for the watchdog.
Figure 3-12 Block Diagram for the Watchdog
16k Cycles
32k Cycles Time Yes
Reset Mode Whole System Enable Pending Reset
64k Cycles Out?
No
96k Cycles
32 KHz 128k Cycles Watchdog Restart
160k Cycles
192k Cycles
Time Yes
Others Cycles Interrupt Mode Enable Pending IRQ
out?
No
Restart
The clock source of the watchdog is OSC24M/750. There are 12 configurable initial count values.
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Operating Modes
The watchdog has two operating modes: the interrupt mode and reset mode.
In the interrupt mode, when the counter value reaches 0 and WDOG_IRQ_EN_REG is enabled, the
watchdog generates an interrupt.
In the reset mode, when the counter value reaches 0, the watchdog generates a reset signal to reset the
entire system.
You can configure the operating mode for the watchdog via the bit[1:0] of the WDOG_CFG_REG. The value 0x2
is for the interrupt mode and the value 0x1 is for the reset mode.
Both the interrupt mode and reset mode support Watchdog Restart. You can make the watchdog to count
from the initial value at any time by configuring the WDOG_CTRL_REG: write 0xA57 to bit[12:1], then write 1
to bit[0].
Initializing the Watchdog
Follow the steps below to initialize the watchdog:
1. Write the bit[1:0] of WDOG_CFG_REG to configure the watchdog operating mode so that the watchdog
can generate interrupts or output reset signals.
2. Write the bit[7:4] of WDOG_MODE_REG to configure the initial count value.
3. Write the bit[0] of WDOG_MODE_REG to enable the watchdog.
Processing the Interrupt
In the interrupt mode, the watchdog is used as a counter. It generates an interrupt everytime the count value
reaches 0.
Follow the steps below to process the interrupt:
1. Write the enable bit of WDOG_IRQ_EN_REG to enable the interrupt.
2. After entering the interrupt process, write the pending bit of WDOG_IRQ_STA_REG to clear the interrupt
pending and execute the process of waiting for the interrupt.
3. Resume the interrupt and continue to execute the interrupted process.
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3.6.3.3 AVS
The AVS is a 33-bit up counter. The counter value is increased by 1 on each rising edge of the count clock. There
is a clock gate in CCU module to control the output of the AVS counter. To operate the AVS, open the clock
gate first.
The following figure shows the block diagram for the AVS.
Figure 3-13 Block Diagram for the AVS
AVS0
Cycle Output
OSC24M Enable Pause
AVS1
The clock source of the AVS is OSC24M. There is a 12-bit division factor for each AVS, N0 for AVS0 and N1 for
AVS1. When the timer increases from 0 to N1 or N2, the AVS counter adds 1. When the counter reaches 33-bit
upper limit, the AVS will start to count from the initial value again.
The AVS supports changing the initial value and division factor at anytime. And the AVS supports restarting
from the initial value or pausing at anytime.
Starting or Pausing the AVS
Follow the steps below:
1. Write AVS_CNT_DIV_REG to configure the division factor.
2. Write AVS_CNTn_REG (n = 0 or 1) to configure the initial value.
3. Write AVS_CNT_CTL_REG to enable the AVS. You can pause the AVS at any time.
3.6.4 Programming Guidelines
3.6.4.1 Configuring the Timer
The following example shows how to make a one-millisecond delay with the clock source selected as OSC24M,
the operating mode sets as single counting mode, and the pre-scale sets as 2.
writel(0x2EE0, TMR_0_INTV); //Set the interval value
writel(0x94, TMR_0_CTRL); //Select Single mode, 24 MHz clock source, 2 pre-scale
writel(readl(TMR_0_CTRL)|(1<<1), TMR_0_CTRL); //Set the Reload bit
while((readl(TMR_0_CTRL)>>1)&1); //Waiting the Reload bit turns to 0
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writel(readl(TMR_0_CTRL)|(1<<0), TMR_0_CTRL); //Enable Timer0
3.6.4.2 Resetting the Watchdog
The following example shows how to make the watchdog to generate a reset signal to the whole system after
1 second. The clock source for the watchdog is OSC24M/750.
writel(0x1, WDOG_CONFIG); //Set the operating mode as the reset mode.
writel(0x10, WDOG_MODE); //Set the interval value as 1 s.
writel(readl(WDOG_MODE)|(1<<0), WDOG_MODE); //Enable the Watchdog.
3.6.4.3 Restarting the Watchdog
The following example shows how to restart the watchdog. In this example, the clock source is OSC24M/750,
the interval value is 1 second, and the watchdog operating mode is the reset mode.
If the execution time of “other codes” is shorter than 1 second, the watchdog will restart from the interval
value before it count to zero and generates the reset signal. Otherwise, the watchdog will reset the whole
system before the code “writel(readl(WDOG_CTRL)|(0xA57<<1)|(1<<0), WDOG_CTRL)” is executed.
writel(0x1, WDOG_CONFIG); //To whole system
writel(0x10, WDOG_MODE); //Interval Value set 1s
writel(readl(WDOG_MODE)|(1<<0), WDOG_MODE); //Enable Watchdog
----other codes---
writel(readl(WDOG_CTRL)|(0xA57<<1)|(1<<0), WDOG_CTRL); //Write 0xA57 at Key Field and Restart
Watchdog
3.6.5 Register List
Module Name Base Address
Timer 0x02050000
Register Name Offset Description
TMR_IRQ_EN_REG 0x0000 Timer IRQ Enable Register
TMR_IRQ_STA_REG 0x0004 Timer Status Register
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Register Name Offset Description
TMR0_CTRL_REG 0x0010 Timer0 Control Register
TMR0_INTV_VALUE_REG 0x0014 Timer0 Interval Value Register
TMR0_CUR_VALUE_REG 0x0018 Timer0 Current Value Register
TMR1_CTRL_REG 0x0020 Timer1 Control Register
TMR1_INTV_VALUE_REG 0x0024 Timer1 Interval Value Register
TMR1_CUR_VALUE_REG 0x0028 Timer1 Current Value Register
WDOG_IRQ_EN_REG 0x00A0 Watchdog IRQ Enable Register
WDOG_IRQ_STA_REG 0x00A4 Watchdog Status Register
WDOG_SOFT_RST_REG 0x00A8 Watchdog Software Reset Register
WDOG_CTRL_REG 0x00B0 Watchdog Control Register
WDOG_CFG_REG 0x00B4 Watchdog Configuration Register
WDOG_MODE_REG 0x00B8 Watchdog Mode Register
WDOG_OUTPUT_CFG_REG 0x00BC Watchdog Output Configuration Register
AVS_CNT_CTL_REG 0x00C0 AVS Control Register
AVS_CNT0_REG 0x00C4 AVS Counter 0 Register
AVS_CNT1_REG 0x00C8 AVS Counter 1 Register
AVS_CNT_DIV_REG 0x00CC AVS Divisor Register
3.6.6 Register Description
3.6.6.1 0x0000 Timer IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TMR_IRQ_EN_REG
Bit Read/Write Default/Hex Description
31:2 / / /
TMR1_IRQ_EN
Timer1 Interrupt Enable
1 R/W 0x0
0: Disabled
1: Enabled
TMR0_IRQ_EN
Timer0 Interrupt Enable
0 R/W 0x0
0: Disabled
1: Enabled
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3.6.6.2 0x0004 Timer IRQ Status Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: TMR_IRQ_STA_REG
Bit Read/Write Default/Hex Description
31:2 / / /
TMR1_IRQ_PEND
The IRQ pending bit for Timer1
0: No effect
1 R/W1C 0x0
1: Pending, indicates that the interval value of the timer 1 is
reached.
Write 1 to clear the pending status.
TMR0_IRQ_PEND
The IRQ pending bit for Timer0
0: No effect
0 R/W1C 0x0
1: Pending, indicates that the interval value of the timer 0 is
reached.
Write 1 to clear the pending status.
3.6.6.3 0x0010 Timer0 Control Register (Default Value: 0x0000_0004)
Offset: 0x0010 Register Name: TMR0_CTRL_REG
Bit Read/Write Default/Hex Description
31:8 / / /
TMR0_MODE
Select the timing mode for timer0
0: Periodic mode. When the interval value of the timer 0 is reached,
7 R/W 0x0
the timer will restart another round of counting automatically.
1: Single counting mode. When the interval value of the timer 0 is
reached, the timer will stop counting.
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Offset: 0x0010 Register Name: TMR0_CTRL_REG
Bit Read/Write Default/Hex Description
TMR0_CLK_PRES
Select the pre-scale of timer0 clock source
000: /1
001: /2
010: /4
6:4 R/W 0x0
011: /8
100: /16
101: /32
110: /64
111: /128
TMR0_CLK_SRC
Select the clock source for timer0
00: LOSC
3:2 R/W 0x1
01: OSC24M
10: /
11: /
TMR0_RELOAD
Timer0 Reload
0: No effect
1 R/W 0x0
1: Reload the Interval value for timer0
After the bit is set, it can not be written again before it is cleared
automatically.
TMR0_EN
Timer0 Enable
0: Stop/Pause
1: Start
By setting the bit to 1, the timer will be started. It reloads the
interval value register and then counts from the interval value to 0.
By setting the bit to 0 before the timer counts to 0, the timer will be
0 R/W 0x0 paused. The bit will be locked to 0 for at least 2 cycles. Within the 2
cycles, you cannot set the bit to 1 to restart the timer.
The timer supports updating the interval value in the pause state.
To start to down-count from the updated interval value, set both
the reload bit and enable bit to 1.
Additionally, in the single counting mode, after the count value
reaches 0, the system will automatically change the bit to 0 to stop
the timer.
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3.6.6.4 0x0014 Timer0 Interval Value Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: TMR0_INTV_VALUE_REG
Bit Read/Write Default/Hex Description
TMR0_INTV_VALUE
31:0 R/W 0x0
Timer0 Interval Value
NOTE
Take the system clock and timer clock source into consideration when setting the interval value.
3.6.6.5 0x0018 Timer0 Current Value Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: TMR0_CUR_VALUE_REG
Bit Read/Write Default/Hex Description
TMR0_CUR_VALUE
Timer0 Current Value
31:0 R/W 0x0
Timer0 current value is a 32-bit down-counter (from interval value
to 0).
3.6.6.6 0x0020 Timer1 Control Register (Default Value: 0x0000_0004)
Offset: 0x0020 Register Name: TMR1_CTRL_REG
Bit Read/Write Default/Hex Description
31:8 / / /
TMR1_MODE
Select the timing mode for timer1
0: Periodic mode. When the interval value of the timer 1 is reached,
7 R/W 0x0
the timer will restart another round of counting automatically.
1: Single counting mode. When the interval value of the timer 1 is
reached, the timer will stop counting.
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Offset: 0x0020 Register Name: TMR1_CTRL_REG
Bit Read/Write Default/Hex Description
TMR1_CLK_PRES
Select the pre-scale of timer1 clock source
000: /1
001: /2
010: /4
6:4 R/W 0x0
011: /8
100: /16
101: /32
110: /64
111: /128
TMR1_CLK_SRC
Select the pre-scale of timer1 clock source
00: LOSC
3:2 R/W 0x1
01: OSC24M
10: /
11: /
TMR1_RELOAD
Timer1 Reload
0: No effect
1 R/W 0x0
1: Reload the interval value for timer1
After the bit is set, it can not be written again before it is cleared
automatically.
TMR1_EN
Timer1 Enable
0: Stop/Pause
1: Start
By setting the bit to 1, the timer will be started. It reloads the
interval value register and then counts from the interval value to 0.
By setting the bit to 0 before the timer counts to 0, the timer will be
0 R/W 0x0 paused. The bit will be locked to 0 for at least 2 cycles. Within the 2
cycles, you cannot set the bit to 1 to restart the timer.
The timer supports updating the interval value in the pause state.
To start to down-count from the updated interval value, set both
the reload bit and enable bit to 1.
Additionally, in the single counting mode, after the count value
reaches 0, the system will automatically change the bit to 0 to stop
the timer.
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3.6.6.7 0x0024 Timer1 Interval Value Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: TMR1_INTV_VALUE_REG
Bit Read/Write Default/Hex Description
TMR1_INTV_VALUE
31:0 R/W 0x0
Timer1 Interval Value
NOTE
Take the system clock and timer clock source into consideration when setting the interval value.
3.6.6.8 0x0028 Timer1 Current Value Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: TMR1_CUR_VALUE_REG
Bit Read/Write Default/Hex Description
TMR1_CUR_VALUE
Timer1 Current Value
31:0 R/W 0x0
Timer1 current value is a 32-bit down-counter (from interval value
to 0).
3.6.6.9 0x00A0 Watchdog IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x00A0 Register Name: WDOG_IRQ_EN_REG
Bit Read/Write Default/Hex Description
31:1 / / /
WDOG_IRQ_EN
Watchdog Interrupt Enable
0 R/W 0x0
0: Disabled
1: Enabled
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3.6.6.10 0x00A4 Watchdog Status Register (Default Value: 0x0000_0000)
Offset: 0x00A4 Register Name: WDOG_IRQ_STA_REG
Bit Read/Write Default/Hex Description
31:1 / / /
WDOG_IRQ_PEND
The IRQ pending bit for the watchdog
Write 1 to clear the pending status.
0 R/W1C 0x0
0: No effect
1: Pending, indicates that the interval value of the watchdog is
reached.
3.6.6.11 0x00A8 Watchdog Software Reset Register (Default Value: 0x0000_0000)
Offset: 0x00A8 Register Name: WDOG_SOFT_RST_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 W 0x0
To change the value of bit[0], this field should be filled with
0x16AA.
15:1 / / /
Soft Reset Enable
0: De-assert
0 R/W1C 0x0 1: Reset the system
Note: To use the bit to reset the system, the watchdog first needs
to be disabled.
3.6.6.12 0x00B0 Watchdog Control Register (Default Value: 0x0000_0000)
Offset: 0x00B0 Register Name: WDOG_CTRL_REG
Bit Read/Write Default/Hex Description
31:13 / / /
WDOG_KEY_FIELD
Watchdog Key Field
12:1 W 0x0
It should be written to 0xA57. Writing any other value in this field
aborts the write operation.
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Offset: 0x00B0 Register Name: WDOG_CTRL_REG
Bit Read/Write Default/Hex Description
WDOG_RESTART
Watchdog Restart
0 R/W1S 0x0
0: No effect
1: Restart the watchdog
3.6.6.13 0x00B4 Watchdog Configuration Register (Default Value: 0x0000_0001)
Offset: 0x00B4 Register Name: WDOG_CFG_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 W 0x0
To change the value of bit[15:0], this field should be filled with
0x16AA.
15:9 / / /
WDOG_CLK_SRC
Select the clock source for the watchdog.
8 R/W 0x0 0: HOSC_32K, that is, OSC24M/750. It is a 32 KHz clock divided
from the OSC24M.
1: LOSC_32K. A clock provided by the LOSC.
7:2 / / /
WDOG_MODE
Configure the operating mode for the watchdog
00: /
1:0 R/W 0x1
01: To whole system
10: Only interrupt mode
11: /
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3.6.6.14 0x00B8 Watchdog Mode Register (Default Value: 0x0000_0000)
Offset: 0x00B8 Register Name: WDOG_MODE_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 W 0x0
To change the value of bit[15:0], this field should be filled with
0x16AA.
15:8 / / /
WDOG_INTV_VALUE
Watchdog Interval Value
0000: 16000 cycles (0.5 s)
0001: 32000 cycles (1 s)
0010: 64000 cycles (2 s)
0011: 96000 cycles (3 s)
0100: 128000 cycles (4 s)
0101: 160000 cycles (5 s)
0110: 192000 cycles (6 s)
0111: 256000 cycles (8 s)
7:4 R/W 0x0 1000: 320000 cycles (10 s)
1001: 384000 cycles (12 s)
1010: 448000 cycles (14 s)
1011: 512000 cycles (16 s)
Others: Reserved
Note: The corresponding clock cycles for the interval value (IV)
depends on the frequency of the clock: Cycles = FCLK * IV.
For example, to get a interval value of 0.5 second, if the clock
source is HOSC_32K (whose frequency is 32 KHz), the cycle
number is 16,000; if the clock source is LOSC_32K (whose
frequency is 32.768 kHz), the cycle number is 16,384.
3:1 / / /
WDOG_EN
Watchdog Enable
0 R/W 0x0
0: No effect
1: Enable the Watchdog
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3.6.6.15 0x00BC Watchdog Output Configuration Register (Default Value: 0x0000_001F)
Offset: 0x00BC Register Name: WDOG_OUTPUT_CFG_REG
Bit Read/Write Default/Hex Description
31:12 / / /
WDOG OUTPUT CONFIG
Configure the valid time for the watchdog reset signal.
11:0 R/W 0x1F
T = 1/32ms*(N + 1)
The default value is 1 ms.
3.6.6.16 0x00C0 AVS Counter Control Register (Default Value: 0x0000_0000)
Offset: 0x00C0 Register Name: AVS_CNT_CTL_REG
Bit Read/Write Default/Hex Description
31:10 / / /
AVS_CNT1_PS
Audio/Video Sync Counter 1 Pause Control
9 R/W 0x0
0: Do not pause.
1: Pause the AVS counter1.
AVS_CNT0_PS
Audio/Video Sync Counter 0 Pause Control
8 R/W 0x0
0: Do not pause.
1: Pause the AVS counter0.
7:2 / / /
AVS_CNT1_EN
Audio/Video Sync Counter 1 Enable/Disable
1 R/W 0x0 The clock source is OSC24M.
0: Disabled
1: Enabled
AVS_CNT0_EN
Audio/Video Sync Counter 0 Enable/Disable
0 R/W 0x0 The clock source is OSC24M.
0: Disabled
1: Enabled
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3.6.6.17 0x00C4 AVS Counter 0 Register (Default Value: 0x0000_0000)
Offset: 0x00C4 Register Name: AVS_CNT0_REG
Bit Read/Write Default/Hex Description
AVS_CNT0
The higher 32 bits of AVS counter0.
AVS counter0 is a 33-bit up counter. The initial value consists of two
parts: this register forms the bit[32:1] of AVS counter0 and the bit[0] is
31:0 R/W 0x0 zero.
You can set the initial value of the AVS counter0 by software. The initial
value can be updated at anytime. You can also pasuse the counter by
setting AVS_CNT0_PS to ”1”. The counter value will not increase when
it is paused.
3.6.6.18 0x00C8 AVS Counter 1 Register (Default Value: 0x0000_0000)
Offset: 0x00C8 Register Name: AVS_CNT1_REG
Bit Read/Write Default/Hex Description
AVS_CNT1
The higher 32 bits of AVS counter1.
AVS counter1 is a 33-bit up counter. The initial value consists of two
parts: this register forms the bit[32:1] of AVS counter0 and the bit[0] is
31:0 R/W 0x0 zero.
You can set the initial value of the AVS counter1 by software. The initial
value can be updated at anytime. You can also pasuse the counter by
setting AVS_CNT1_PS to ”1”. The counter value will not increase when
it is paused.
3.6.6.19 0x00CC AVS Counter Divisor Register (Default Value: 0x05DB_05DB)
Offset: 0x00CC Register Name: AVS_CNT_DIV_REG
Bit Read/Write Default/Hex Description
31:28 / / /
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Offset: 0x00CC Register Name: AVS_CNT_DIV_REG
Bit Read/Write Default/Hex Description
AVS_CNT1_D
N1, the divisor factor for AVS1.
The clock for AVS1 is 24 MHz/N1.
N1 = Bit[27:16] + 1.
The valid value for N1 is from 1 to 0x7ff.
27:16 R/W 0x5DB There is an internal 12-bit counter maintained by the engine of the 33-
bit AVS1. The 12-bit counter is used for counting the cycle number of
the clock OSC24M. When the value of the 12-bit counter reaches N1,
the internal 33-bit counter register will increase 1 and the 12-bit
counter will reset to zero and restart again.
You can change the value of N1 via the software at any time.
15:12 / / /
AVS_CNT0_D
N0, the divisor factor for AVS0.
The clock for AVS0 is 24MHz/N0.
N0 = Bit[11:0] + 1.
The valid value for N0 is from 1 to 0x7ff.
11:0 R/W 0x5DB There is an internal 12-bit counter maintained by the engine of the 33-
bit AVS0. The 12-bit counter is used for counting the cycle number of
the clock OSC24M. When the value of the 12-bit counter reaches N0,
the internal 33-bit counter register will increase 1 and the 12-bit
counter will reset to zero and restart again.
You can change the value of N0 via the software at any time.
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3.7 High Speed Timer
3.7.1 Overview
The high speed timer (HSTimer) module consists of HSTimer0 and HSTimer1. HSTimer0 and HSTimer1 are down
counters that implement timing and counting functions. They are completely consistent. Compared with the
timer module, the HSTimer module provides more precise timing and counting.
The HSTimer has the following features:
Single clock source: AHB0
Supports 5 prescale factors
Configurable 56-bit down timer
Supports 2 timing modes: periodic mode and one-shot mode
Supports the test mode
Generates an interrupt when the count is decreased to 0
3.7.2 Block Diagram
The following figure shows the block diagram of the HSTimer.
Figure 3-14 HSTimer Block Diagram
Single Counting
N_Mode
Mode
IRQ EN
Yes
Interval Value
AHBCLK HSTimer Enable IV=0 ? Pending IRQ
(IV)
Test Mode Periodic Mode
3.7.3 Functional Description
The HSTimers are 56-bit down counters. The counter value is decremented by 1 on each rising edge of the
count clock. Each HSTimer has a prescaler that divides the working clock frequency of each working timer by 1,
2, 4, 8, or 16.
3.7.3.1 Typical Application
The following figure shows a typical application of HSTimer module.
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Figure 3-15 Typical Application for HSTimer
AHB0
AHB0_CLK
High Speed Timer irq
The HSTimer module is mounted at AHB0, and can control the registers via AHB0. AHB0 is the clock source of
the HSTimer. When the count value reaches zero, the HSTimer generates an interrupt.
3.7.3.2 Count Modes
The HSTimer has two count modes: one-shot mode and periodic mode. You can configure the timing mode via
the bit[7] of HS_TMRn_CTRL_REG (n = 0 or 1). The value 0 is for the period mode and value 1 is for the one-
shot mode.
One-shot Mode
When the count value of the HSTimer reaches 0, the HSTimer stops counting. The HSTimer starts to count
again only when a new value is loaded.
Periodic Mode
The HSTimer counts continuously. When the count value of the HSTimer reaches 0, the HSTimer reloads
an initial value from HS_TMRn_INTV_LO_REG and HS_TMRn_INTV_HI_REG and then continues to count.
3.7.3.3 Operating Modes
The HSTimer has two operating modes: the normal mode and test mode. You can configure the operating
mode via the bit[31] of HS_TMRn_CTRL_REG. The value 0 is for the normal mode and value 1 is for the test
mode.
Normal Mode
In the normal mode, the HSTimer is used as a 56-bit down counter, which can finish one-shot counting
and periodic counting. The interval value for the HSTimer consists of two parts: HS_TMRn_INTV_LO_REG
forms the bit[31:0] and HS_TMRn_INTV_HI_REG forms the bit[55:32]. To read or write the interval value,
HS_TMRn_INTV_LO_REG should be done before HS_TMRn_INTV_HI_REG.
Test Mode
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In the test mode, the HSTimer is used as a 24-bit down counter. HS_TMRn_INTV_LO_REG must be set to
0x1, and HS_TMRn_INTV_HI_REG acts as the initial value for the HSTimer.
3.7.3.4 HSTimer Formula
The following formula describes the relationship among HSTimer parameters in the normal mode.
(HS_TMRn_INTV_HI_REG<<32 + HS_TMRn_INTV_LO_REG) – (HS_TMRn_CURNT_HI_REG<<32 + HS_TMRn_CURNT_LO_REG)
THSTimer = × HS_TMRn_CLK
AHB0CLK
Where,
The parameter n is either 0 or 1;
THSTimer is the remaining time of the timer;
HS_TMRn_INTV_HI_REG is bit[55:32] of the HSTimer interval value;
HS_TMRn_INTV_LO_REG is bit[31:0] of the HSTimer interval value;
HS_TMRn_CURNT_HI_REG is bit[55:32] of the HSTimer current value;
HS_TMRn_CURNT_LO_REG is bit[31:0] of the HSTimer current value;
AHB0CLK is the frequency of AHB0 Clock (the HSTimer clock source);
HS_TMRn_CLK is the prescale ratio of the HSTimer clock.
3.7.3.5 Initializing the HSTimer
The following figure shows the process of HSTimer initialization.
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Figure 3-16 HSTimer Initialization Process
AHB0 Clock Management
Set HSTimer Parameters
Set Interval Value
Enable HSTimer
1. AHB0 clock management: Open the clock gate of AHB0 and de-assert the soft reset of AHB0 in CCU.
2. Configure the corresponding parameters of the HSTimer: clock source, prescaler factor, operating mode,
and timing mode. There is no sequence requirement when writing the above parameters to
HS_TMRn_CTRL_REG.
3. Write the initial value: Write the lower 32 bits of the initial value to HS_TMRn_INTV_LO_REG first, and
then the higher 24 bits to HS_TMRn_INTV_HI_REG. Normally, write the bit[1] of HS_TMRn_CTRL_REG to
load the initial value. If the HSTimer is in the timing stop stage, write 1 to the bit[1] and bit[0] of
HS_TMRn_CTRL_REG at the same time to reload the initial value.
4. Enable HSTimer: Write the bit[0] of HS_TMRn_CTRL_REG to enable HSTimer to count.
5. Reading HS_TMRn_CURNT_LO_REG and HS_TMRn_CURNT_HI_REG can get current counting value.
3.7.3.6 Processing the HSTimer Interrupt
Follow the steps below to process the HSTimer interrupt:
1. Enable interrupt: Write the corresponding interrupt enable bit of HS_TMR_IRQ_EN_REG, when the
counting time of HSTimer reaches, the corresponding interrupt generates.
2. After entering the interrupt process, write HS_TMR_IRQ_STAS_REG to clear the interrupt pending.
3. Resume the interrupt and continue to execute the interrupted process.
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3.7.4 Programming Guidelines
The following example shows how to make a 1 us delay with HSTimer0. The frequency of the AHB0 clock is 100
MHz, the operating mode is the normal mode, the timing mode is single counting mode, and the pre-scale is 2.
writel(0x32, HS_TMR0_INTV_LO); //Set bit[31:0] of the interval value as 0x32.
writel(0x0, HS_TMR0_INTV_HI); //Set bit[55:32] of the interval value as 0x0.
writel(0x90, HS_TMR0_CTRL);
//Set the operating mode as Normal Mode, the pre-scale as 2, and the timing mode as Single Counting Mode.
writel(readl(HS_TMR0_CTRL)|(1<<1), HS_TMR0_CTRL); //Set the reload bit.
writel(readl(HS_TMR0_CTRL)|(1<<0), HS_TMR0_CTRL); //Enable HSTimer0.
while(!(readl(HS_TMR_IRQ_STAS)&1)); //Wait for HSTimer0 to generate pending.
writel(1, HS_TMR_IRQ_STAS); //Clear HSTimer0 pending.
3.7.5 Register List
Module Name Base Address
HSTimer 0x03008000
Register Name Offset Description
HS_TMR_IRQ_EN_REG 0x0000 HS Timer IRQ Enable Register
HS_TMR_IRQ_STAS_REG 0x0004 HS Timer Status Register
HS_TMR0_CTRL_REG 0x0020 HS Timer0 Control Register
HS_TMR0_INTV_LO_REG 0x0024 HS Timer0 Interval Value Low Register
HS_TMR0_INTV_HI_REG 0x0028 HS Timer0 Interval Value High Register
HS_TMR0_CURNT_LO_REG 0x002C HS Timer0 Current Value Low Register
HS_TMR0_CURNT_HI_REG 0x0030 HS Timer0 Current Value High Register
HS_TMR1_CTRL_REG 0x0040 HS Timer1 Control Register
HS_TMR1_INTV_LO_REG 0x0044 HS Timer1 Interval Value Low Register
HS_TMR1_INTV_HI_REG 0x0048 HS Timer1 Interval Value High Register
HS_TMR1_CURNT_LO_REG 0x004C HS Timer1 Current Value Low Register
HS_TMR1_CURNT_HI_REG 0x0050 HS Timer1 Current Value High Register
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3.7.6 Register Description
3.7.6.1 0x0000 HS Timer IRQ Enable Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: HS_TMR_IRQ_EN_REG
Bit Read/Write Default/Hex Description
31:2 / / /
HS_TMR1_INT_EN
HSTimer1 Interrupt Enable
1 R/W 0x0
0: Disabled
1: Enabled
HS_TMR0_INT_EN
HSTimer0 Interrupt Enable
0 R/W 0x0
0: Disabled
1: Enabled
3.7.6.2 0x0004 HS Timer IRQ Status Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: HS_TMR_IRQ_STAS_REG
Bit Read/Write Default/Hex Description
31:2 / / /
HS_TMR1_IRQ_PEND
HSTimer1 IRQ Pending
The IRQ pending bit for HSTimer1. Write 1 to clear the pending
1 R/W1C 0x0 status.
0: No effect
1: Pending, indicates that the initial value of the HSTimer is
reached.
HS_TMR0_IRQ_PEND
HSTimer0 IRQ Pending
The IRQ pending bit for HSTimer0. Write 1 to clear the pending
0 R/W1C 0x0 status.
0: No effect
1: Pending, indicates that the initial value of the HSTimer is
reached.
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3.7.6.3 0x0020 HS Timer0 Control Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: HS_TMR0_CTRL_REG
Bit Read/Write Default/Hex Description
HS_TMR0_TEST
Select the operating mode for HSTimer0
0: Normal mode
31 R/W 0x0
1: Test mode
In the test mode, the HS_TMR0_INTV_LO_REG must be set to 0x1,
and HS_TMR0_INTV_HI_REG acts as the initial value for HSTimer0.
30:8 / / /
HS_TMR0_MODE
Select the timing mode for HSTimer0
0: Periodic mode. When the count value is decreased to 0, the timer
7 R/W 0x0
will restart another round of counting automatically.
1: One-shot mode. When the count value is decreased to 0, the timer
will stop counting.
HS_TMR0_CLK
Select the pre-scale for the HSTimer0 clock sources
000: /1
001: /2
010: /4
6:4 R/W 0x0
011: /8
100: /16
101: /
110: /
111: /
3:2 / / /
HS_TMR0_RELOAD
HSTimer0 Reload
1 R/W1S 0x0
0: No effect
1: Reload the interval value of the HSTimer0
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Offset: 0x0020 Register Name: HS_TMR0_CTRL_REG
Bit Read/Write Default/Hex Description
HS_TMR0_EN
HSTimer0 Enable
0: Stop/Pause
1: Start
By setting the bit to 1, the timer will be started. It reloads the interval
value register and then counts from the interval value to 0.
0 R/W 0x0 By setting the bit to 0 before the timer counts to 0, the timer will be
paused. The bit will be locked to 0 for at least 2 cycles. Within the 2
cycles, you cannot set the bit to 1 to restart the timer.
The timer supports updating the interval value in the pause state. To
start from the updated interval value, set both the reload bit and
enable bit to 1.
Additionally, in the one-shot mode, after the count value reaches 0,
the system will automatically change the bit to 0 to stop the timer.
3.7.6.4 0x0024 HS Timer0 Interval Value Lo Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: HS_TMR0_INTV_LO_REG
Bit Read/Write Default/Hex Description
HS_TMR0_INTV_VALUE_LO
31:0 R/W 0x0
Bit[31:0] of the HSTimer0 interval value.
3.7.6.5 0x0028 HS Timer0 Interval Value Hi Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: HS_TMR0_INTV_HI_REG
Bit Read/Write Default/Hex Description
31:24 / / /
HS_TMR0_INTV_VALUE_HI
23:0 R/W 0x0
Bit[55:32] of the HSTimer0 interval value.
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NOTE
HSTimer0 is a 56-bit counter. The interval value consists of two parts: HS_TMR0_INTV_VALUE_LO acts as
the bit[31:0] and HS_TMR0_INTV_VALUE_HI acts as the bit[55:32]. To read or write the interval value,
HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.
3.7.6.6 0x002C HS Timer0 Current Value Lo Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: HS_TMR0_CURNT_LO_REG
Bit Read/Write Default/Hex Description
HS_TMR0_CUR_VALUE_LO
31:0 R/W 0x0
Bit[31:0] of the HSTimer0 current value.
3.7.6.7 0x0030 HS Timer0 Current Value Hi Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: HS_TMR0_CURNT_HI_REG
Bit Read/Write Default/Hex Description
31:24 / / /
HS_TMR0_CUR_VALUE_HI
23:0 R/W 0x0
Bit[55:32] of the HSTimer0 current value.
NOTE
HSTimer0 is a 56-bit counter. The current value consists of two parts: HS_TMR0_CUR_VALUE_LO acts as the
bit[31:0] and HS_TMR0_CUR_VALUE_HI acts as the bit[55:32]. To read or write the current value,
HS_TMR0_CUR_VALUE_LO should be done before HS_TMR0_CUR_VALUE_HI.
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3.7.6.8 0x0040 HS Timer1 Control Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: HS_TMR1_CTRL_REG
Bit Read/Write Default/Hex Description
HS_TMR1_TEST
Select the operating mode for HSTimer1.
0: Normal mode
31 R/W 0x0 1: Test mode
In the test mode, the HS_TMR1_INTV_LO_REG must be set to 0x1,
and HS_TMR1_INTV_HI_REG acts as the interval value for
HSTimer1.
30:8 / / /
HS_TMR1_MODE
Select the timing mode for HSTimer1.
0: Periodic mode. When the count value is decreased to 0, the timer
7 R/W 0x0
will restart another round of counting automatically.
1: One-shot mode. When the count value is decreased to 0, the
timer will stop counting.
HS_TMR1_CLK
Select the pre-scale of the HSTimer1 clock sources.
000: /1
001: /2
010: /4
6:4 R/W 0x0
011: /8
100: /16
101: /
110: /
111: /
3:2 / / /
HS_TMR1_RELOAD
HSTimer1 Reload
1 R/W1S 0x0
0: No effect
1: Reload the HSTimer1 interval value.
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Offset: 0x0040 Register Name: HS_TMR1_CTRL_REG
Bit Read/Write Default/Hex Description
HS_TMR1_EN
HSTimer1 Enable
0: Stop/Pause
1: Start
By setting the bit to 1, the timer will be started. It reloads the
interval value register and then counts from the interval value to 0.
0 R/W 0x0 By setting the bit to 0 before the timer counts to 0, the timer will be
paused. The bit will be locked to 0 for at least 2 cycles. Within the 2
cycles, you cannot set the bit to 1 to restart the timer.
The timer supports updating the interval value in the pause state.
To start from the updated interval value, set both the reload bit and
enable bit to 1.
Additionally, in the one-shot mode, after the count value reaches 0,
the system will automatically change the bit to 0 to stop the timer.
3.7.6.9 0x0044 HS Timer1 Interval Value Lo Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: HS_TMR1_INTV_LO_REG
Bit Read/Write Default/Hex Description
HS_TMR1_INTV_VALUE_LO
31:0 R/W 0x0
Bit[31:0] of the HSTimer1 interval value
3.7.6.10 0x0048 HS Timer1 Interval Value Hi Register (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: HS_TMR1_INTV_HI_REG
Bit Read/Write Default/Hex Description
31:24 / / /
HS_TMR1_INTV_VALUE_HI
23:0 R/W 0x0
Bit[55:32] of the HSTimer1 interval value
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NOTE
HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as
the bit[31:0] and HS_TMR1_INTV_VALUE_HI acts as the bit[55:32]. To read or write the interval value,
HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.
3.7.6.11 0x004C HS Timer1 Current Value Lo Register (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: HS_TMR1_CURNT_LO_REG
Bit Read/Write Default/Hex Description
HS_TMR1_CUR_VALUE_LO
31:0 R/W 0x0
Bit[31:0] of the HSTimer1 current value
3.7.6.12 0x0050 HS Timer1 Current Value Hi Register (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: HS_TMR1_CURNT_HI_REG
Bit Read/Write Default/Hex Description
31:24 / / /
HS_TMR1_CUR_VALUE_HI
23:0 R/W 0x0
Bit[55:32] of the HSTimer1 current value
NOTE
HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the
bit[31:0] and HS_TMR1_CUR_VALUE_HI acts as the bit[55:32]. To read or write the current value,
HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.
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3.8 Platform-Level Interrupt Controller (PLIC)
3.8.1 Overview
The PLIC is only used for sampling, priority arbitration and distribution for external interrupt sources.
Sampling, priority arbitration and distribution for external interrupt sources
The interrupt can be configured as machine mode and super user mode
Up to 256 interrupt source sampling, supporting level interrupt and pulse interrupt
32 levels of interrupt priority
Maintains independently the interrupt enable for each interrupt mode (machine/super user)
Maintains independently the interrupt threshold for each interrupt mode (machine/super user)
Configurable access permission for PLIC registers
3.8.2 Functional Description
The following table describes the details of interrupt sources.
Table 3-9 Interrupt Sources
Interrupt Number Interrupt Source Interrupt Vector Description
0–15 Reserved 0x0000–0x003C Not used
16 0x0040
17 0x0044
18 UART0 0x0048
19 UART1 0x004C
20 UART2 0x0050
21 UART3 0x0054
22 UART4 0x0058
23 UART5 0x005C
24 0x0060
25 TWI0 0x0064
26 TWI1 0x0068
27 TWI2 0x006C
28 TWI3 0x0070
29 0x0074
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Interrupt Number Interrupt Source Interrupt Vector Description
30 0x0078
31 SPI0 0x007C
32 SPI1 0x0080
33 0x0084
34 PWM 0x0088
35 CIR_TX 0x008C
36 LEDC 0x0090
37 0x0094
38 0x0098
39 OWA 0x009C
40 DMIC 0x00A0
41 AUDIO_CODEC 0x00A4
42 0x00A8
43 I2S/PCM1 0x00AC
44 I2S/PCM2 0x00B0
45 USB0_DEVICE 0x00B4
46 USB0_EHCI 0x00B8
47 USB0_OHCI 0x00BC
48 0x00C0
49 USB1_EHCI 0x00C4
50 USB1_OHCI 0x00C8
51 0x00CC
52 0x00D0
53 0x00D4
54 0x00D8
55 0x00DC
56 SMHC0 0x00E0
57 SMHC1 0x00E4
58 SMHC2 0x00E8
59 MSI 0x00EC
60 0x00F0
61 0x00F4
62 EMAC 0x00F8
63 0x00FC
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Interrupt Number Interrupt Source Interrupt Vector Description
64 CCU_FERR 0x0100
SYS_CTRL ahb_hready time
65 AHB_HREADY_TIME_OUT 0x0104
out
66 DMAC_NS 0x0108
67 0x010C
68 CE_NS 0x0110
69 0x0114
70 0x0118
71 HSTIMER0 0x011C
72 HSTIMER1 0x0120
73 GPADC 0x0124
74 THS 0x0128 Thermal Sensor IRQ
75 TIMER0 0x012C
76 TIMER1 0x0130
77 LRADC 0x0134
78 TPADC 0x0138
79 WATCHDOG 0x013C
80 IOMMU 0x0140
81 0x0144
82 VE 0x0148
83 0x014C
84 0x0150
85 GPIOB_NS 0x0154
86 0x0158
87 GPIOC_NS 0x015C
88 0x0160
89 GPIOD_NS 0x0164
90 0x0168
91 GPIOE_NS 0x016C
92 0x0170
93 GPIOF_NS 0x0174
94 0x0178
95 GPIOG_NS 0x017C
96 0x0180
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Interrupt Number Interrupt Source Interrupt Vector Description
97 0x0184
98 0x0188
99 0x018C
100 0x0190
101 0x0194
102 0x0198
103 DE 0x019C
104 DI 0x01A0
105 G2D 0x01A4
106 LCD 0x01A8
107 TV 0x01AC
108 DSI 0x01B0
109 0x01B4
110 TVE 0x01B8 CVBS OUT interrupt
111 CSI_DMA0 0x01BC
112 CSI_DMA1 0x01C0
113 0x01C4
114 0x01C8
115 0x01CC
116 CSI_PARSER0 0x01D0
117 0x01D4
118 0x01D8
119 0x01DC
120 0x01E0
121 0x01E4
122 CSI_TOP_PKT 0x01E8
123 TVD 0x01EC CVBS IN interrupt
124 0x01F0
125 0x01F4
126 0x01F8
127 0x01FC
128 0x0200
129 0x0204
130 0x0208
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Interrupt Number Interrupt Source Interrupt Vector Description
131 0x020C
132 0x0210
133 0x0214
134 0x0218
135 0x021C
136 0x0220
137 0x0224
138 0x0228
139 0x022C
140 0x0230
141 0x0234
142 0x0238
143 0x023C
144 0x0240
145 0x0244
146 0x0248
147 RISC_WDG 0x024C
148 0x0250
149 0x0254
150 0x0258
151 0x025C
152 0x260
153 0x264
154 0x268
155 0x26C
156 0x270
157 0x274
158 0x278
159 0x27C
160 0x280
161 0x284
162 0x288
163 0x28C
164 0x290
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Interrupt Number Interrupt Source Interrupt Vector Description
165 0x294
166 0x298
167 IRRX 0x29C
168 0x2A0
169 0x2A4
170 0x2A8
171 0x2AC
172 0x2B0
173 0x2B4
174 0x2B8
175 0x2BC
CPUX Related
176 C0_CTI0 0x2C0 C0_CTI0 interrupt
177 C0_CTI1 0x2C4 C0_CTI1 interrupt
178 0x2C8
179 0x2CC
180 C0_COMMTX0 0x2D0 C0_COMMTX0 interrupt
181 C0_COMMTX1 0x2D4 C0_COMMTX1 interrupt
182 0x2D8
183 0x2DC
184 C0_COMMRX0 0x2E0 C0_COMMRX0 interrupt
185 C0_COMMRX1 0x2E4 C0_COMMRX1 interrupt
186 0x2EC
187 0x2F0
188 C0_PMU0 0x2F4 C0_PMU0 interrupt
189 C0_PMU1 0x2F8 C0_PMU1 interrupt
190 0x2FC
191 0x300
192 C0_AXI_ERROR 0x304 C0_AXI_ERROR interrupt
193 0x308
194 AXI_WR_IRQ 0x30C
195 AXI_RD_IRQ 0x310
196 DBGPWRUPREQ_out[0] 0x314
197 DBGPWRUPREQ_out[1] 0x318
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Interrupt Number Interrupt Source Interrupt Vector Description
198 0x31C
199 0x320
200 0x324
201 0x328
202 0x32C
203 0x330
204 0x334
205 0x338
206 0x33C
207 0x340
208 0x344
209 0x348
210 0x34C
211 0x350
212 0x354
213 0x358
214 0x35C
215 0x360
216 0x364
217 0x368
218 0x36C
219 0x370
220 0x374
221 0x378
222 0x37C
223 0x380
3.8.3 Register List
Module Name Base Address
RISC PLIC 0x10000000
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Register Name Offset Description
PLIC_PRIO_REGn 0x0000+n*0x0004 (0<n<256) PLIC Priority Register n
PLIC_IP_ REGn 0x1000+n*0x0004 (0≤n<9) PLIC Interrupt Pending Register n
PLIC_MIE_ REGn 0x2000+n*0x0004 (0≤n<9) PLIC Machine Mode Interrupt Enable Register n
PLIC_SIE_ REGn 0x2080+n*0x0004 (0≤n<9) PLIC Superuser Mode Interrupt Enable Register n
PLIC_CTRL_REG 0x1FFFFC PLIC Control Register
PLIC_MTH_REG 0x200000 PLIC Machine Threshold Register
PLIC_MCLAIM_REG 0x200004 PLIC Machine Claim Register
PLIC_STH_REG 0x201000 PLIC Superuser Threshold Register
PLIC_SCLAIM_REG 0x201004 PLIC Superuser Claim Register
3.8.4 Register Description
3.8.4.1 0x0000+n*0x0004 (0<n<256) PLIC Priority Register n (Default Value: 0x0000_0000)
Offset: 0x0000+n*0x0004
Register Name: PLIC_PRIO_REGn
(0<n<256)
Bit Read/Write Default/Hex Description
31:1 / / /
PLIC_PRIO
PLIC Priority
Support for 32 different levels of priority.
Where, a priority sets to 0 indicates that the interrupt is invalid.
0 R/W 0x0 Machine mode interrupts have unconditionally higher priority
than super-user mode interrupts. When the interrupt target mode
is the same, priority 1 is the lowest priority, priority 31 is the
highest priority. When multiple interrupts of the same priority are
waiting arbitration, the interrupt source ID is compared. The
smaller ID has the higher priority.
3.8.4.2 0x1000+n*0x0004 (0≤n<9) PLIC Interrupt Pending Register n (Default Value: 0x0000_0000)
Offset: 0x1000+n*0x0004 (0≤n<9) Register Name: PLIC_IP_REGn
Bit Read/Write Default/Hex Description
PLIC_IP
31:0 R/W 0x0
PLIC Interrupt Pending.
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3.8.4.3 0x2000+n*0x0004 (0≤n<9) PLIC Machine Mode Interrupt Enable Register n (Default Value: 0x0000_0000)
Offset: 0x2000+n*0x0004 (0≤n<9) Register Name: PLIC_MIE_REGn
Bit Read/Write Default/Hex Description
PLIC_MIE
31:0 R/W 0x0
PLIC Machine Mode Interrupt Enable.
3.8.4.4 0x2080+n*0x0004 PLIC Superuser Mode Interrupt Enable Register n (0≤n<9) (Default Value: 0x0000_0000)
Offset: 0x2080+n*0x0004 (0≤n<9) Register Name: PLIC_SIE_REGn
Bit Read/Write Default/Hex Description
PLIC_SIE
31:0 R/W 0x0
PLIC Superuser Mode Interrupt Enable.
3.8.4.5 0x1FFFFC PLIC Control Register (Default Value: 0x0000_0000)
Offset: 0x1FFFFC Register Name: PLIC_CTRL_REG
Bit Read/Write Default/Hex Description
31:1 / / /
PLIC_CTRL
PLIC Control
0: Only the machine mode can access to all registers in PLIC. The
super-user mode can not access PLIC_CTRL, PLIC_PRIO, PLIC_IP,
and PLIC_IE registers, only access the interrupt threshold register
0 R/W 0x0
and the interrupt response/completion register. The normal-user
mode can not access any registers in PLIC.
1: The machine mode can access to all registers in PLIC. The super-
user mode can access all registers except PLL_CTRL in PLIC. The
normal-user mode can not access any registers in PLIC.
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3.8.4.6 0x200000 PLIC Machine Threshold Register (Default Value: 0x0000_0000)
Offset: 0x200000 Register Name: PLIC_MTH_REG
Bit Read/Write Default/Hex Description
31:5 / / /
PLIC_MTH
PLIC Machine Threshold
4:0 R/W 0x0 Indicate the interrupt threshold of the current interrupt mode.
If the threshold is configured to 0, it indicates that all interrupts
are permitted.
3.8.4.7 0x200004 PLIC Machine Claim Register (Default Value: 0x0000_0000)
Offset: 0x200004 Register Name: PLIC_MCLAIM_REG
Bit Read/Write Default/Hex Description
31:10 / / /
PLIC_MCLAIM
PLIC Machine Claim
Read register: Return the current stored ID value of the register.
The read operation indicates that the interrupt of the
corresponding ID starts to perform. The PLIC starts to process the
9:0 R/W 0x0
interrupt response.
Write register: Indicate that the interrupt of the corresponding ID
is complete. The writing operation can not update the
response/completion register. The PLIC starts to process the
interrupt completion.
3.8.4.8 0x201000 PLIC Superuser Threshold Register (Default Value: 0x0000_0000)
Offset: 0x201000 Register Name: PLIC_STH_REG
Bit Read/Write Default/Hex Description
31:5 / / /
PLIC_STH.
PLIC Superuser Threshold.
4:0 R/W 0x0 Indicate the interrupt threshold of the current interrupt mode.
If the threshold is configured to 0, it indicates that all interrupts
are permitted.
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3.8.4.9 0x201004 PLIC Superuser Claim Register (Default Value: 0x0000_0000)
Offset: 0x201004 Register Name: PLIC_SCLAIM_REG
Bit Read/Write Default/Hex Description
31:10 / / /
PLIC_SCLAIM.
PLIC Superuser Claim.
Read register: Return the current stored ID value of the register.
The read operation indicates that the interrupt of the
corresponding ID starts to perform. The PLIC starts to process the
9:0 R/W 0x0
interrupt response.
Write register: Indicate that the interrupt of the corresponding ID
is complete. The writing operation can not update the
response/completion register. The PLIC starts to process the
interrupt completion.
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3.9 Direct Memory Access Controller (DMAC)
3.9.1 Overview
The direct memory access (DMA) is a method of transferring data between peripherals and memories
(including the SRAM and DRAM) without using the CPU. It is an efficient way to offload data transfer duties
from the CPU. Without DMA, the CPU has to control all the data transfers. While with DMA, the DMAC directly
transfers data between a peripheral and a memory, between peripherals, or between memories.
The DMAC has the following features:
Up to 16 DMA channels
Provides 32 peripheral DMA requests for data reading and 32 peripheral DMA requests for data writing
Supports transferring data with a linked list
Supports programmable 8-bit, 16-bit, 32-bit, and 64-bit data width
Supports programmable DMA burst length
DRQ response includes the waiting mode and handshake mode
DMA channel supports pause function
Memory devices support non-aligned transform
3.9.2 Block Diagram
The following figure shows a block diagram of DMAC.
Figure 3-17 DMAC Block Diagram
AHB slave I/F
DMA_REG I/F DMA_CLK GATE
Memory Bus
DMA_CHANNEL0 DMA_MPORT
DMA_CHANNEL1
DMA_FIFO CTRL
DRQs
DMA_ARBITER
DMA_CHANNEL 14
DMA_CHANNEL 15
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DMAC contains the following sub-blocks:
Table 3-10 DMAC Sub-blocks
Sub-block Description
Arbitrates the DMA read/write requests from all channels, and converts
DMA_ARBITER
the requests to the read/write requests of ports.
DMA transfer engine. Each channel is independent. When the DMA
requests from multiple peripherals are valid simultaneously, the channel
with the highest priority starts data transfer first. The system uses the
polling mechanism to decide the priorities of DMA channels. When
DMA_CHANNELs
DMA_ARBITER is idle, channel 0 has the highest priority, whereas channel
15 has the lowest priority. When DMA_ARBITER is busy processing the
request from channel n, channel (n+1) has the highest priority. For n = 15,
the channel (n + 1) should be channel 0.
DMA requests. Peripherals use the DMA request signals to request a data
DRQs
transfer.
Receives the read/write requests from DMA_ARBITER, and converts the
DMA_MPORT requests to the corresponding MBUS access requests. It is mainly used for
accessing the DRAM.
The port for accessing the AHB Master. It is mainly used for accessing the
DMA_HPORT
SRAM and IO devices.
DMA_FIFO CTRL Internal FIFO cell control module.
DMA_REG is the common register module that is mainly used to resolve
DMA_REG Interface
AHB demands.
DMA_CLKGATE The control module for hardware auto clock gating.
The DMAC integrates 16 independent DMA channels and each channel has an independent FIFO controller.
When the DMA channel starts, the DMAC gets a DMA descriptor from the DMA_DESC_ADDR_REG and uses it
as the configuration information for the data transfer of the current DMA package. Then the DMAC can transfer
data between the specified devices. After transferring a DMA package, the DMAC judges if the current channel
transfer is finished via the linked address in the descriptor. If the linked address shows all the packages are
transferred, the DMAC will end the chain transmission and close the channel.
3.9.3 Functional Description
3.9.3.1 Clock
The DMAC is on MBUS. The clock of MBUS influences the transfer efficiency of the DMAC.
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3.9.3.2 Typical Application
The following figure shows a typical application of the DMAC.
Figure 3-18 DMAC Typical Application Diagram
Device 0
Device 1
Device 2
Device 3
BUS
AHB Slave Interface DMA
Interface
Device 4
Device 5
Device 14
Device 15
3.9.3.3 DRQ Port of Peripherals
The following table shows the source DRQ types and destination DRQ types of different ports.
Table 3-11 DMA DRQ Type
Source DRQ Type Destination DRQ Type
port0 SRAM port0 SRAM
port1 DRAM port1 DRAM
port2 OWA-RX port2 OWA-TX
port3 port3
port4 I2S/PCM1-RX port4 I2S/PCM1-TX
port5 I2S/PCM2-RX port5 I2S/PCM2-TX
port6 port6
port7 Audio_Codec port7 Audio_Codec
port8 DMIC port8
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Source DRQ Type Destination DRQ Type
port9 port9
port10 port10
port11 port11
port12 GPADC port12
port13 TPADC port13 IR-TX
port14 UART0-RX port14 UART0-TX
port15 UART1-RX port15 UART1-TX
port16 UART2-RX port16 UART2-TX
port17 UART3-RX port17 UART3-TX
port18 UART4-RX port18 UART4-TX
port19 UART5-RX port19 UART5-TX
port20 port20
port21 port21
port22 SPI0-RX port22 SPI0-TX
port23 SPI1-RX port23 SPI1-TX
port24 port24
port25 port25
port26 port26
port27 port27
port28 port28
port29 port29
Port30 USB0_EP1 Port30 USB0_EP1
Port31 USB0_EP2 Port31 USB0_EP2
Port32 USB0_EP3 Port32 USB0_EP3
Port33 USB0_EP4 Port33 USB0_EP4
Port34 USB0_EP5 Port34 USB0_EP5
Port35 Port35
Port36 Port36
Port37 Port37
Port38 Port38
Port39 Port39
Port40 Port40
Port41 Port41
Port42 Port42 LEDC
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Source DRQ Type Destination DRQ Type
Port43 TWI0 Port43 TWI0
Port44 TWI1 Port44 TWI1
Port45 TWI2 Port45 TWI2
Port46 TWI3 Port46 TWI3
Port47 Port47
Port48 Port48
Port49 Port49
Port50 Port50
Port51 Port51
Port52 Port52
Port53 Port53
3.9.3.4 DMA Descriptor
The DMAC descriptor is the configuration information of DMA transfer that decides the DMA working mode.
Each descriptor includes 6 words: Configuration, Source Address, Destination Address, Byte Counter,
Parameter, and Link. The following figure shows the structure of the DMA descriptor.
Figure 3-19 DMA Descriptor
Configuration
Source
Address
Destination
Address
Byte Counter
Parameter
Link
Configuration: Configure the following information by DMA_CFG_REG.
- DRQ type: DRQ type of the source and destination devices.
- Address counting mode: For both the source and destination devices, there are two address counting
modes: the IO mode and linear mode. The IO mode is for IO devices whose address is fixed during
the data transfer and the linear mode is for the memory whose address is increasing during the data
transfer.
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- Transferred block length: The amount of data that non-memory peripherals can transfer in a valid
DRQ. The block length supports 1 bit, 4 bits, 8 bits, and 16 bits.
- Transferred data width: The data width of operating the non-memory peripherals. The data width
supports 8 bits, 16 bits, 32 bits, and 64 bits.
NOTE
The configuration supports BMODE mode. The BMODE is used in the following scenario: the source is
an IO device, and the destination is a memory device. Setting the BMODE mode can limit the amount
of block data transferred in DMA block transmission to the amount of data transferred when the DRQ
threshold of the source IO device is 1. For example,
Source Address: Configure the address of the source device.
Destination Address: Configure the address of the destination device.
DMA reads data from the source address and then writes data to the destination address.
Both the DMA source and destination addresses have 34 bits. In the descriptor, because there are only 32
bits in the Source/Destination Address field, another 2 bits are stored in the Parameter field.
The following table shows the details of the related fields in the descriptor.
Table 3-12 Source/Destination Address Distribution
Descriptor Group Bit Description
Source Address 31:0 DMA transfers the lower 32 bits of the 34-bit source address
Destination Address 31:0 DMA transfers the lower 32 bits of the 34-bit destination address
31:20 Reserved
19:18 DMA transfers the higher 2 bits of the 34-bit destination address
17:16 DMA transfers the high 2 bits of the 34-bit source address
Parameter
15:8 Reserved
Wait Clock Cycles
7:0
Set the waiting time in DRQ mode
The address of the next group descriptor, the lower 30 bits of the
31:2
word address
Link
The address of the next group descriptor, the higher 2 bits of the
1:0
word address
From the above table, you can get:
Real DMA source address (in byte mode) = {Parameter [17:16], Source Address [31:0]};
Real DMA destination address (in byte mode) = {Parameter [19:18], Destination Address [31:0]};
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Real link address (in byte mode) = {Link[1:0], Link[31:2], 2’b00}.
Byte counter: Configure the data amount of a package. The maximum value is (2^25-1) bytes. If the data
amount of the package reaches the maximum value, even if DRQ is valid, the DMA will stop the current
transfer.
Parameter: Configure the interval between the data block. The parameter is valid for non-memory
peripherals. When DMA detects that the DRQ is high, the DMA transfers the data block and ignores the
status changes of the DRQ until the data transfer finishes. After that, the DMA waits for certain clock
cycles (WAIT_CYC) and executes the next DRQ detection.
Link: If the value of the link is 0xFFFFF800, the current package is at the end of the linked list. The DMAC
will stop the data transfer after transferring the package; otherwise, the value of the link is considered
as the descriptor address of the next package.
Figure 3-20 DMA Chain Transfer
3.9.3.5 Interrupts
There are three kinds of DMA interrupts: the half package interrupt, package end interrupt, and queue end
interrupt.
Half package interrupt: When enabled, the DMAC sends out a half package interrupt after transferring half of
a package.
Package end interrupt: When enabled, the DMAC sends out a package end interrupt after transferring a
complete package.
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Queue end interrupt: When enabled, the DMAC sends out a queue end interrupt after transferring a complete
queue.
Notice that when CPU does not respond to the interrupts timely, or two DMA interrupts are generated very
closely, the later interrupt may override the former one. That is, from the perspective of the CPU, the DMAC
has only a system interrupt source.
NOTE
The DMAC has 16 channels and 2 groups of interrupts. The channel [7:0] corresponds to one group of interrupt,
the channel [15:8] corresponds to anther group of interrupt.
3.9.3.6 Clock Gating
The DMA_CLK_GATE module is a hardware module for controlling the clock gating automatically. It provides
clock sources for sub-modules in DMAC and the module local circuits.
The DMA_CLK_GATE module consists of two parts: the channel clock gate and the common clock gate.
Channel clock gate: Controls the DMA clock of the DMA channels. When the system accesses the register of
the current DMA channel and the DMA channel is enabled, the channel clock gate automatically opens the
DMA clock. With a 16-HCLK-cycle delay after the system finishes accessing the register or the DMA data transfer
is completed, the channel clock gate automatically closes the DMA clock. Also, the clock for the related circuits,
such as for the channel control and FIFO control modules, will be closed.
Common clock gate: Controls the clocks of the DMA common circuits. The common circuits include the
common circuit of the FIFO control module, MPORT module, and MBUS. When all the DMA channels are
enabled, the common clock gate automatically closes the clocks for the above circuits.
The DMA clock gating can support all the functions stated above or not by software.
3.9.3.7 Transfer Mode
The peripherals initiate data transfer by transmitting DMA request signals to the DMAC. After receiving the
request signal, the DMAC converts it to the internal DRQ signal and controls the DMA data transfer.
The DMAC supports two data transfer modes: the waiting mode and handshake mode.
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The principle of waiting mode
When the DMAC detects a valid external request signal, the DMAC starts to operate the peripheral device.
The internal DRQ always holds high before the transferred data amount reaches the transferred block
length.
When the transferred data amount reaches the transferred block length, the internal DRQ pulls low
automatically.
The internal DRQ holds low for certain clock cycles (WAIT_CYC), and then the DMAC restarts to detect the
external requests. If the external request signal is valid, then the next transfer starts.
The principle of handshake mode
When the DMAC detects a valid external request signal, the DMAC starts to operate the peripheral device.
The internal DRQ always holds high before the transferred data amount reaches the transferred block
length.
When the transferred data amount reaches the transferred block length, the internal DRQ will be pulled
down automatically. For the last data transfer of the block, the DMAC sends a DMA Last signal with the
DMA commands to the peripheral device. The DMA Last signal will be packed as part of the DMA
commands and transmitted on the bus. It is used to inform the peripheral device that it is the end of the
data transfer for the current DRQ.
When the peripheral device receives the DMA Last signal, it can judge that the data transfer for the current
DRQ is finished. To continue the data transfer, it sends a DMA Active signal to the DMAC.
NOTE
One DMA Active signal will be converted to one DRQ signal in the DMA module. To generate multiple
DRQs, the peripheral device needs to send out multiple DMA Active signals via the bus protocol.
When the DMAC received the DMA Active signal, it sends back a DMA ACK signal to the peripheral device.
When the peripheral device receives the DMA ACK signal, it waits for all the operations on the local device
completed, and both the FIFO and DRQ status refreshed. Then it invalidates the DMA Active signal.
When the DMAC detects the falling edge of the DMA Active signal, it invalidates the corresponding DMA
ACK signal, and restarts to detect the external request signals. If a valid request signal is detected, the next
data transfer starts.
The following figure shows the workflow of the handshake mode.
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Figure 3-21 Workflow of the DMAC Handshake Mode
DMAC DEVICE
3.9.3.8 Address Auto-Alignment
For the non-IO devices whose start address is not 32-byte-aligned, the DMAC will adjust the address to 32-
byte-aligned through the burst transfer within 32 bytes. Adjusting address to 32-byte-aligned improves the
DRAM access efficiency.
The following example shows how the DMAC adjusts the address: when the peripheral device of a DMA channel
is a non-IO device whose start address is 0x86 (not 32-byte-aligned), the DMAC firstly uses a 26-byte burst
transfer to align the address to 0xA0 (32-byte-aligned), and then transfers data by 64-byte burst (the maximum
transfer amount that MBUS allows).
The IO devices do not support address alignment, so the bit width of IO devices must match the address offset;
otherwise, the DMAC will ignore the inconsistency and directly transmit data of the corresponding bit width to
the address.
The address of the DMA descriptor does not support the address auto-alignment. Make sure the address is
word-aligned; otherwise the DMAC cannot identify the descriptor.
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3.9.3.9 DMAC Clock Control
The DMAC clock is synchronous with the AHB0 clock. Make sure that the DMAC gating bit of AHB0 clock
is enabled before accessing the DMAC register.
The reset input signal of the DMAC is asynchronous with AHB0 and is low valid by default. Make sure that
the reset signal of the DMAC is de-asserted before accessing the DMA register.
To avoid the indefinite state within registers, de-assert the reset signal first, and then open the gating bit
of AHB0.
The DMAC supports Clock Auto Gating function to reduce power consumption, the system will
automatically disable the DMAC clock in the DMAC idle state. Clock Auto Gating is enabled by default.
3.9.4 Programming Guidelines
3.9.4.1 Using DMAC Transfer Process
The DMAC transfer process is as follows.
Step 1 Request DMA channel, and check if the DMA channel is idle by checking if it is enabled. A disabled
channel indicates it is idle, while an enabled channel indicates it is busy.
Step 2 Write the descriptor with 6 words into the memory. The descriptor must be word-aligned. For more
details, refer to section 3.9.3.4 “DMA Descriptor”.
Step 3 Write the start address of the descriptor to DMA_DESC_ADDR_REGN.
Step 4 Enable the DMA channel, and write the corresponding channel to DMAC_EN_REGN.
Step 5 The DMA obtains the descriptor information.
Step 6 Start to transmit a package. When half of the package is completed, the DMA sends a Half Package
Transfer Interrupt; when a total package is completed, the DMA sends a Package End Transfer
Interrupt. These interrupt status can be read by DMAC_IRQ_PEND_REG0.
Step 7 Set DMAC_PAU_REGN to pause or resume the data transfer.
Step 8 After completing a total package transfer, the DMA decides to start the next package transfer or end
the transfer by the link of the descriptor. If the link is 0xFFFFF800, the transfer ends; otherwise, the
next package starts to transmit. When the transfer ends, the DMA sends a Queue End Transfer
Interrupt.
Step 9 Disable the DMA channel.
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Figure 3-22 DMAC Transfer Process
Request DMA channel
No
Any Idle?
Yes
Write DMA transfer configuration
information to the memory
Write starting address of
configuration information to
DMA_DESC_ADDR_REG
Enable DMA channel
DMA Obtain descriptor information
Half-Pending Yes
DMA transmit package data
Pkg-Pending
Resume?
Yes
Pause?
No
No
Link = 0xFFFFF800?
Yes
End-Pending
DMA transfer end
3.9.4.2 Processing DMAC Interrupt
Follow the steps below to process the DMAC interrupt:
Step 1 Enable interrupt: write the corresponding interrupt enable bit of DMAC_IRQ_EN_REG0. The system
generates an interrupt when the corresponding condition is satisfied.
Step 2 After entering the interrupt process, write to clear the interrupt pending and execute the process of
waiting for the interrupt.
Step 3 Resume the interrupt and continue to execute the interrupted process.
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3.9.4.3 Configuring DMAC
To configure the DMAC, follow the guidelines below:
Make sure the transfer bit width of IO devices is consistent with the offset of the start address.
The MBUS protocol does not support the read operation of non-integer words. For the devices whose bit
width is not word-aligned, after receiving the read command, they should resolve the read command
according to their FIFO bit width instead of the command bit width, and ignore the redundant data caused
by the inconsistency of the bit width.
When the DMA transfer is paused, this is equivalent to invalid DRQ. Because there is a certain time delay
between DMA transfer commands, the DMAC will not stop data transfer until the DMAC finishes
processing the current command and the commands in Arbiter (at most 32 bytes data).
DMAC application example:
writel(0x00000000, mem_address + 0x00); //Set configurations. The mem_address must be word-aligned.
writel(0x00001000, mem_address + 0x04); // Set the start address for the source device.
writel(0x20000000, mem_address + 0x08); //Set the start address for the destination device.
writel(0x00000020, mem_address + 0x0C); // Set the data package size.
writel(0x00000000, mem_address + 0x10); //Set the parameters.
writel(0xFFFFF800, mem_address + 0x14); //Set the start address for the next descriptor.
writel(mem_address, 0x01C02000+ 0x100 + 0x08); //Set the start address for the DMA channel0 descriptor.
do{
If(mem_address == readl(0x01C02000 + 0x100 + 0x08));
break;
}while(1); //Make sure that the writing operation is valid.
writel(0x000000001, 0x01C02000 + 0x100 + 0x00); // Enable DMA channel0 transfer.
The DMAC supports increasing data package in transfer, pay attention to the following points:
The 0xFFFFF800 value of DMAC_FDESC_ADDR_REGN indicates that the DMA channel has got back the
descriptor of the last package. The DMA channel will automatically stop the data transfer after transferring
the current package.
To add a package during the data transfer, check if the DMA channel has got back the descriptor of the
last package. If yes, you cannot add any package in the current queue. Request another DMA channel with
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a new DRQ to transfer the package. Otherwise, you can add the package by modifying the
DMAC_FDESC_ADDR_REGN of the last package from 0xFFFFF800 to the start address of the to-be-added
package.
To ensure that the modification is valid, read the value of DMAC_FDESC_ADDR_REGN after the
modification. The value 0xFFFFF800 indicates the modification fails and the other values indicate you have
successfully added packages to the queue.
Another problem is, the system needs some time to process the modification, during which the DMA
channel may get back the descriptor of the last package. You can read DMAC_CUR_SRC_REGN and
DMAC_CUR_DEST_REGN and check if the increasing memory address accords with the information of the
added package. If yes, the package is added successfully; otherwise, the modification failed.
To ensure a higher rate of success, it is suggested that you add the package before the half package
interrupt of the penultimate package.
3.9.5 Register List
Module Name Base Address
DMAC 0x03002000
Register Name Offset Description
DMAC_IRQ_EN_REG0 0x0000 DMAC IRQ Enable Register 0
DMAC_IRQ_EN_REG1 0x0004 DMAC IRQ Enable Register 1
DMAC_IRQ_PEND_REG0 0x0010 DMAC IRQ Pending Register 0
DMAC_IRQ_PEND_REG1 0x0014 DMAC IRQ Pending Register 1
DMAC_AUTO_GATE_REG 0x0028 DMAC Auto Gating Register
DMAC_STA_REG 0x0030 DMAC Status Register
DMAC_EN_REGN 0x0100 + N*0x0040 DMAC Channel Enable Register N (N = 0 to 15)
DMAC_PAU_REGN 0x0104 + N*0x0040 DMAC Channel Pause Register N (N = 0 to 15)
DMAC_DESC_ADDR_REGN 0x0108 + N*0x0040 DMAC Channel Start Address Register N (N = 0 to 15)
DMAC_CFG_REGN 0x010C + N*0x0040 DMAC Channel Configuration Register N (N = 0 to 15)
DMAC_CUR_SRC_REGN 0x0110 + N*0x0040 DMAC Channel Current Source Register N (N = 0 to 15)
DMAC Channel Current Destination Register N (N = 0
DMAC_CUR_DEST_REGN 0x0114 + N*0x0040
to 15)
DMAC Channel Byte Counter Left Register N (N = 0 to
DMAC_BCNT_LEFT_REGN 0x0118 + N*0x0040
15)
DMAC_PARA_REGN 0x011C + N*0x0040 DMAC Channel Parameter Register N (N = 0 to 15)
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Register Name Offset Description
DMAC_MODE_REGN 0x0128 + N*0x0040 DMAC Mode Register N (N = 0 to 15)
DMAC Former Descriptor Address Register N (N = 0 to
DMAC_FDESC_ADDR_REGN 0x012C + N*0x0040
15)
DMAC_PKG_NUM_REGN 0x0130 + N*0x0040 DMAC Package Number Register N (N = 0 to 15)
3.9.6 Register Description
3.9.6.1 0x0000 DMAC IRQ Enable Register0 (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: DMAC_IRQ_EN_REG0
Bit Read/Write Default/Hex Description
31 / / /
DMA7_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 7
30 R/W 0x0
0: Disabled
1: Enabled
DMA7_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 7
29 R/W 0x0
0: Disabled
1: Enabled
DMA7_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 7
28 R/W 0x0
0: Disabled
1: Enabled
27 / / /
DMA6_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 6
26 R/W 0x0
0: Disabled
1: Enabled
DMA6_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 6
25 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0000 Register Name: DMAC_IRQ_EN_REG0
Bit Read/Write Default/Hex Description
DMA6_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 6
24 R/W 0x0
0: Disabled
1: Enabled
23 / / /
DMA5_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 5
22 R/W 0x0
0: Disabled
1: Enabled
DMA5_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 5
21 R/W 0x0
0: Disabled
1: Enabled
DMA5_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 5
20 R/W 0x0
0: Disabled
1: Enabled
19 / / /
DMA4_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 4
18 R/W 0x0
0: Disabled
1: Enabled
DMA4_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 4
17 R/W 0x0
0: Disabled
1: Enabled
DMA4_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 4
16 R/W 0x0
0: Disabled
1: Enabled
15 / / /
DMA3_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 3
14 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0000 Register Name: DMAC_IRQ_EN_REG0
Bit Read/Write Default/Hex Description
DMA3_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 3
13 R/W 0x0
0: Disabled
1: Enabled
DMA3_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 3
12 R/W 0x0
0: Disabled
1: Enabled
11 / / /
DMA2_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 2
10 R/W 0x0
0: Disabled
1: Enabled
DMA2_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 2
9 R/W 0x0
0: Disabled
1: Enabled
DMA2_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 2
8 R/W 0x0
0: Disabled
1: Enabled
7 / / /
DMA1_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 1
6 R/W 0x0
0: Disabled
1: Enabled
DMA1_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 1
5 R/W 0x0
0: Disabled
1: Enabled
DMA1_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 1
4 R/W 0x0
0: Disabled
1: Enabled
3 / / /
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Offset: 0x0000 Register Name: DMAC_IRQ_EN_REG0
Bit Read/Write Default/Hex Description
DMA0_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 0
2 R/W 0x0
0: Disabled
1: Enabled
DMA0_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 0
1 R/W 0x0
0: Disabled
1: Enabled
DMA0_HLAF_IRQ_EN
Enable the half package interrupt of DMA channel 0
0 R/W 0x0
0: Disabled
1: Enabled
3.9.6.2 0x0004 DMAC IRQ Enable Register1 (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: DMAC_IRQ_EN_REG1
Bit Read/Write Default/Hex Description
31 / / /
DMA15_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 15
30 R/W 0x0
0: Disabled
1: Enabled
DMA15_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 15
29 R/W 0x0
0: Disabled
1: Enabled
DMA15_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 15
28 R/W 0x0
0: Disabled
1: Enabled
27 / / /
DMA14_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 14
26 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0004 Register Name: DMAC_IRQ_EN_REG1
Bit Read/Write Default/Hex Description
DMA14_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 14
25 R/W 0x0
0: Disabled
1: Enabled
DMA14_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 14
24 R/W 0x0
0: Disabled
1: Enabled
23 / / /
DMA13_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 13
22 R/W 0x0
0: Disabled
1: Enabled
DMA13_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 13
21 R/W 0x0
0: Disabled
1: Enabled
DMA13_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 13
20 R/W 0x0
0: Disabled
1: Enabled
19 / / /
DMA12_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 12
18 R/W 0x0
0: Disabled
1: Enabled
DMA12_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 12
17 R/W 0x0
0: Disabled
1: Enabled
DMA12_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 12
16 R/W 0x0
0: Disabled
1: Enabled
15 / / /
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Offset: 0x0004 Register Name: DMAC_IRQ_EN_REG1
Bit Read/Write Default/Hex Description
DMA11_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 11
14 R/W 0x0
0: Disabled
1: Enabled
DMA11_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 11
13 R/W 0x0
0: Disabled
1: Enabled
DMA11_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 11
12 R/W 0x0
0: Disabled
1: Enabled
11 / / /
DMA10_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 10
10 R/W 0x0
0: Disabled
1: Enabled
DMA10_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 10
9 R/W 0x0
0: Disabled
1: Enabled
DMA10_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 10
8 R/W 0x0
0: Disabled
1: Enabled
7 / / /
DMA9_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 9
6 R/W 0x0
0: Disabled
1: Enabled
DMA9_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 9
5 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0004 Register Name: DMAC_IRQ_EN_REG1
Bit Read/Write Default/Hex Description
DMA9_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 9
4 R/W 0x0
0: Disabled
1: Enabled
3 / / /
DMA8_QUEUE_IRQ_EN
Enable the queue end interrupt of DMA channel 8
2 R/W 0x0
0: Disabled
1: Enabled
DMA8_PKG_IRQ_EN
Enable the package end interrupt of DMA channel 8
1 R/W 0x0
0: Disabled
1: Enabled
DMA8_HALF_IRQ_EN
Enable the half package interrupt of DMA channel 8
0 R/W 0x0
0: Disabled
1: Enabled
3.9.6.3 0x0010 DMAC IRQ Pending Status Register 0 (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
31 / / /
DMA7_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
30 R/W1C 0x0 channel 7. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA7_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
29 R/W1C 0x0 channel 7. Write 1 to clear the pending status.
0: No effect
1: Pending
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA7_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
28 R/W1C 0x0 channel 7. Write 1 to clear the pending status.
0: No effect
1: Pending
27 / / /
DMA6_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
26 R/W1C 0x0 channel 6. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA6_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
25 R/W1C 0x0 channel 6. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA6_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
24 R/W1C 0x0 channel 6. Write 1 to clear the pending status.
0: No effect
1: Pending
23 / / /
DMA5_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
22 R/W1C 0x0 channel 5. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA5_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
21 R/W1C 0x0 channel 5. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA5_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
20 R/W1C 0x0 channel 5. Write 1 to clear the pending status.
0: No effect
1: Pending
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
19 / / /
DMA4_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
18 R/W1C 0x0 channel 4. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA4_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
17 R/W1C 0x0 channel 4. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA4_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
16 R/W1C 0x0 channel 4. Write 1 to clear the pending status.
0: No effect
1: Pending
15 / / /
DMA3_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
14 R/W1C 0x0 channel 3. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA3_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
13 R/W1C 0x0 channel 3. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA3_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
12 R/W1C 0x0 channel 3. Write 1 to clear the pending status.
0: No effect
1: Pending
11 / / /
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA2_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
10 R/W1C 0x0 channel 2. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA2_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
9 R/W1C 0x0 channel 2. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA2_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
8 R/W1C 0x0 channel 2. Write 1 to clear the pending status.
0: No effect
1: Pending
7 / / /
DMA1_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
6 R/W1C 0x0 channel 1. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA1_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
5 R/W1C 0x0 channel 1. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA1_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
4 R/W1C 0x0 channel 1. Write 1 to clear the pending status.
0: No effect
1: Pending
3 / / /
DMA0_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
2 R/W1C 0x0 channel 0. Write 1 to clear the pending status.
0: No effect
1: Pending
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA0_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
1 R/W1C 0x0 channel 0. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA0_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
0 R/W1C 0x0 channel 0. Write 1 to clear the pending status.
0: No effect
1: Pending
3.9.6.4 0x0014 DMAC IRQ Pending Status Register 1 (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
31 / / /
DMA15_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
30 R/W1C 0x0 channel 15. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA15_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
29 R/W1C 0x0 channel 15. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA15_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
28 R/W1C 0x0 channel 15. Write 1 to clear the pending status.
0: No effect
1: Pending
27 / / /
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA14_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
26 R/W1C 0x0 channel 14. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA14_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
25 R/W1C 0x0 channel 14. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA14_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
24 R/W1C 0x0 channel 14. Write 1 to clear the pending status.
0: No effect
1: Pending
23 / / /
DMA13_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
22 R/W1C 0x0 channel 13. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA13_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
21 R/W1C 0x0 channel 13. Write 1 to clear the pending status.
0: No effect
1: Pending.
DMA13_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
20 R/W1C 0x0 channel 13. Write 1 to clear the pending status.
0: No effect
1: Pending
19 / / /
DMA12_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
18 R/W1C 0x0 channel 12. Write 1 to clear the pending status.
0: No effect
1: Pending
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA12_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
17 R/W1C 0x0 channel 12. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA12_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
16 R/W1C 0x0 channel 12. Write 1 to clear the pending status.
0: No effect
1: Pending
15 / / /
DMA11_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
14 R/W1C 0x0 channel 11. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA11_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
13 R/W1C 0x0 channel 11. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA11_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
12 R/W1C 0x0 channel 11. Write 1 to clear the pending status.
0: No effect
1: Pending
11 / / /
DMA10_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
10 R/W1C 0x0 channel 10. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA10_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
9 R/W1C 0x0 channel 10. Write 1 to clear the pending status.
0: No effect
1: Pending
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Offset: 0x0010 Register Name: DMAC_IRQ_PEND_REG0
Bit Read/Write Default/Hex Description
DMA10_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
8 R/W1C 0x0 channel 10. Write 1 to clear the pending status.
0: No effect
1: Pending
7 / / /
DMA9_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
6 R/W1C 0x0 channel 9. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA9_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
5 R/W1C 0x0 channel 9. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA9_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
4 R/W1C 0x0 channel 9. Write 1 to clear the pending status.
0: No effect
1: Pending
3 / / /
DMA8_QUEUE_IRQ_PEND
The IRQ pending bit for the queue end interrupt of the DMA
2 R/W1C 0x0 channel 8. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA8_PKG_IRQ_PEND
The IRQ pending bit for the package end interrupt of the DMA
1 R/W1C 0x0 channel 8. Write 1 to clear the pending status.
0: No effect
1: Pending
DMA8_HALF_IRQ_PEND
The IRQ pending bit for the half package interrupt of the DMA
0 R/W1C 0x0 channel 8. Write 1 to clear the pending status.
0: No effect
1: Pending
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3.9.6.5 0x0028 DMAC Auto Gating Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: DMAC_AUTO_GATE_REG
Bit Read/Write Default/Hex Description
31:3 / / /
DMA_MCLK_CIRCUIT
Auto gating bit of DMA MCLK interface circuit
2 R/W 0x0
0: Auto gating enabled
1: Auto gating disabled
DMA_COMMON_CIRCUIT
Auto gating bit of DMA common circuit
1 R/W 0x0
0: Auto gating enabled
1: Auto gating disabled
DMA_CHAN_CIRCUIT
Auto gating bit of DMA channel circuit
0 R/W 0x0
0: Auto gating enabled
1: Auto gating disabled
NOTE
When initializing the DMA Controller, the bit[2] should be set up.
3.9.6.6 0x0030 DMAC Status Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: DMAC_STA_REG
Bit Read/Write Default/Hex Description
MBUS FIFO Status
31 R 0x0 0: Empty
1: Not Empty
30:16 / / /
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Offset: 0x0030 Register Name: DMAC_STA_REG
Bit Read/Write Default/Hex Description
DMA_STATUS
DMA Channel[15:0] Status
15:0 R 0x0 The meaning of each bit:
0: Idle
1: Busy
3.9.6.7 0x0100 + N*0x0040 DMAC Channel Enable Register N (Default Value: 0x0000_0000)
Offset: 0x0100 + N*0x0040
Register Name: DMAC_EN_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31:1 / / /
DMA_EN
DMA Channel Enable
0 R/W 0x0
0: Disabled
1: Enabled
3.9.6.8 0x0104 + N*0x0040 DMAC Channel Pause Register N (Default Value: 0x0000_0000)
Offset: 0x0104 + N*0x0040
Register Name: DMAC_PAU_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31:1 / / /
DMA_PAUSE
Pause the DMA Channel Transfer Data
0 R/W 0x0
0: Resume Transferring
1: Pause Transferring
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3.9.6.9 0x0108 + N*0x0040 DMAC Channel Descriptor Address Register N (Default Value: 0x0000_0000)
Offset: 0x0108 + N*0x0040
Register Name: DMAC_DESC_ADDR_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_DESC_ADDR
31:2 R/W 0x0 Lower 30 bits of DMA channel descriptor address
The descriptor address must be word-aligned.
DMA_DESC_HIGH_ADDR
Higher 2 bits of DMA channel descriptor high address
1:0 R/W 0x0
The real address is as follows.
DMA Channel Descriptor Address = {bit[1:0], bit[31:2], 2’b00}
3.9.6.10 0x010C + N*0x0040 DMAC Channel Configuration Register N (Default Value: 0x0000_0000)
Offset: 0x010C + N*0x0040
Register Name: DMAC_CFG_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31 / / /
BMODE_SEL
30 R 0x0 0: Normal Mode
1: BMODE
29:27 / / /
DMA_DEST_DATA_WIDTH
DMA Destination Data Width
00: 8-bit
26:25 R 0x0
01: 16-bit
10: 32-bit
11: 64-bit
DMA_ADDR_MODE
DMA Destination Address Mode
24 R 0x0
0: Linear Mode
1: IO Mode
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Offset: 0x010C + N*0x0040
Register Name: DMAC_CFG_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_DEST_BLOCK_SIZE
DMA Destination Block Size
00: 1
23:22 R 0x0
01: 4
10: 8
11: 16
DMA_DEST_DRQ_TYPE
21:16 R 0x0 DMA Destination DRQ Type
The details in DRQ Type and Port Corresponding Relation.
15:11 / / /
DMA_SRC_DATA_WIDTH
DMA Source Data Width
00: 8-bit
10:9 R 0x0
01: 16-bit
10: 32-bit
11: 64-bit
DMA_SRC_ADDR_MODE
DMA Source Address Mode
8 R 0x0
0: Linear Mode
1: IO Mode
DMA_SRC_BLOCK_SIZE
DMA Source Block Size
00: 1
7:6 R 0x0
01: 4
10: 8
11: 16
DMA_SRC_DRQ_TYPE
5:0 R 0x0 DMA Source DRQ Type
The details in DRQ Type and Port Corresponding Relation.
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3.9.6.11 0x0110 + N*0x0040 DMAC Channel Current Source Address Register N (Default Value: 0x0000_0000)
Offset: 0x0110 + N*0x0040
Register Name: DMAC_CUR_SRC_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_CUR_SRC
31:0 R 0x0
DMA Channel Current Source Address.
3.9.6.12 0x0114 + N*0x0040 DMAC Channel Current Destination Address Register N (Default Value: 0x0000_0000)
Offset: 0x0114 + N*0x0040
Register Name: DMAC_CUR_DEST_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_CUR_DEST
31:0 R 0x0
DMA Channel Current Destination Address.
3.9.6.13 0x0118 + N*0x0040 DMAC Channel Byte Counter Left Register N (Default Value: 0x0000_0000)
Offset: 0x0118 + N*0x0040
Register Name: DMAC_BCNT_LEFT_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31:25 / / /
DMA_BCNT_LEFT
24:0 R 0x0
DMA Channel Byte Counter Left.
3.9.6.14 0x011C + N*0x0040 DMAC Channel Parameter Register N (Default Value: 0x0000_0000)
Offset: 0x011C + N*0x0040
Register Name: DMAC_PARA_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31:8 / / /
WAIT_CYC
7:0 R 0x0
Wait Clock Cycles
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3.9.6.15 0x0128 + N*0x0040 DMAC Mode Register N (Default Value: 0x0000_0000)
Offset: 0x0128 + N*0x0040
Register Name: DMAC_MODE_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
31:4 / / /
DMA_DST_MODE
Destination Communication Mode Select
3 R/W 0x0
0: Waiting mode
1: Handshake mode
DMA_SRC_MODE
Source Communication Mode Select
2 R/W 0x0
0: Waiting mode
1: Handshake mode
1:0 / / /
3.9.6.16 0x012C + N*0x0040 DMAC Former Descriptor Address Register N (Default Value: 0x0000_0000)
Offset: 0x012C + N*0x0040
Register Name: DMAC_FDESC_ADDR_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_FDESC_ADDR
31:0 R 0x0 This register is used to store the former value of DMA Channel
Descriptor Address Register.
3.9.6.17 0x0130 + N*0x0040 DMAC Package Number Register N (Default Value: 0x0000_0000)
Offset: 0x0130 + N*0x0040
Register Name: DMAC_PKG_NUM_REGN
(N = 0 to 15)
Bit Read/Write Default/Hex Description
DMA_PKG_NUM
31:0 R 0x0 This register records the number of packages which has been
completed in one transmission.
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3.10 Thermal Sensor Controller (THS)
3.10.1 Overview
The thermal sensors are common elements in wide range of modern system on chips (SoCs) platform. The
thermal sensors are used to constantly monitor the temperature on the chip.
The thermal sensor controller (THS) embeds one thermal sensor located in the CPU. When the temperature
reaches a certain thermal threshold, the thermal sensor can generate interrupts to the software to lower the
temperature via the dynamic voltage and frequency scaling (DVFS) technology.
The THS has the following features:
Temperature accuracy: ±3°C from 0°C to +100°C, ±5°C from -25°C to +125°C
Averaging filter for thermal sensor reading
Supports over-temperature protection interrupt and over-temperature alarm interrupt
3.10.2 Block Diagram
The following figure shows a block diagram of the THS.
Figure 3-23 THS Block Diagram
CLK_IN
Clock Div
24 MHz
THS0 Digital
M APB
THS U ADC Logic Reg
THS2 X Process BUS
GN
D Vref
AVCC IRQ RESET
3.10.3 Functional Description
3.10.3.1 Clock Source
The THS gets one clock source: OSC24M. For details about clock configurations, refer to section 3.3 “CCU”.
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3.10.3.2 Timing Requirements
The following figure shows the timing requirements for the THS.
Figure 3-24 Thermal Sensor Timing Requirement
TACQ CONV_TIME
ADC_Sample_Frequency
THERMAL_PER
CLK_IN = 24 MHz
CONV_TIME (Conversion Time) = 1/24 MHz x 14 Cycles = 0.583 us
TACQ > 1/24 MHz x 24 Cycles
THERMAL_PER > ADC_Sample_Frequency > TACQ + CONV_TIME
3.10.3.3 Interrupts
The THS has four interrupt sources: DATA_IRQ, SHUTDOWN_IRQ, ALARM_IRQ, and ALARM_OFF_IRQ. The
following figure shows thermal sensor interrupt sources.
Figure 3-25 Thermal Sensor Controller Interrupt Source
DATA_IRQ_EN
DATA_IRQ
SHUTDOWN_IRQ_EN THS_IRQ
SHUTDOWN_IRQ
ALARM_IRQ_EN
ALARM_IRQ
ALARM_OFF_IRQ
DATA_IRQ: The interrupt is generated when the measured sensor_data is updated.
SHUTDOWN_IRQ: The interrupt is generated when the temperature is higher than the shutdown threshold.
ALARM_IRQ: The interrupt is generated when the temperature is higher than the Alarm_Threshold.
ALARM_OFF_IRQ: The interrupt is generated when the temperature drops to lower than the
Alarm_Off_Thershold. It is triggered at the fall edge.
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3.10.3.4 THS Temperature Conversion Formula
T = (sensor_data - 2800)/(-14.85)
Unit of T: Celsius degree (°C).
The sensor_data is read from the sensor data register.
3.10.4 Programming Guidelines
The initial process of the THS is as follows.
Figure 3-26 THS Initial Process
Start
Set THS_GATING, RESET (in CCU)
Set THS_ACQ, THERMAL_PER, median filter, alarm
threshold, shutdown threshold, and THS_CDATA,
and enable interrupts
Enable THS
In the final test (FT) stage, the THS is calibrated through the ambient temperature, and the calibration value is
written in the SID module. The following table shows the THS information in the SID.
Table 3-13 THS Information in the SID
Base Address: 0x14 Register Name: THS
Bit Description
27:16 The calibration value of the T-sensor.
Before enabling THS, read eFuse value and write the value to THS_CDATA.
Query Mode
Step 1 Write 0x1 to the bit[16] of THS_BGR_REG to dessert the reset.
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Step 2 Write 0x1 to the bit[0] of THS_BGR_REG to open the THS clock.
Step 3 Write 0x2F to the bit[15:0] of THS_CTRL to set the ADC acquire time.
Step 4 Write 0x1DF to the bit[31:16] of THS_CTRL to set the ADC sample frequency divider.
Step 5 Write 0x3A to the bit[31:12] of THS_PER to set the THS work period.
Step 6 Write 0x1 to the bit[2] of THS_FILTER to enable the temperature convert filter.
Step 7 Write 0x1 to the bit[1:0] of THS_FILTER to select the filter type.
Step 8 Read THS eFuse value from SID, then write the eFuse value to THS_CDATA to calibrate THS.
Step 9 Write 0x1 to the bit[0] of THS0_EN to enable THS.
Step 10 Read the bit[0] of THS_DATA_INTS. If it is 1, the temperature conversion is complete.
Step 11 Read the bit[11:0] of THS_DATA, and calculate the THS temperature based on section 3.10.3.4 “THS
Temperature Conversion Formula”.
Interrupt Mode
Step 1 Write 0x1 to the bit16 of THS_BGR_REG to dessert the reset.
Step 2 Write 0x1 to the bit0 of THS_BGR_REG to open the THS clock.
Step 3 Write 0x2F to the bit[15:0] of THS_CTRL to set the ADC acquire time.
Step 4 Write 0x1DF to the bit[31:16] of THS_CTRL to set the ADC sample frequency divider.
Step 5 Write 0x3A to the bit[31:12] of THS_PER to set the THS work period.
Step 6 Write 0x1 to the bit2 of THS_FILTER to enable the temperature convert filter.
Step 7 Write 0x1 to the bit[1:0] of THS_FILTER to select the filter type.
Step 8 Read THS eFuse value from SID, and then write the eFuse value to THS_CDATA to calibrate THS.
Step 9 Write 0x1 to the bit[0] of THS_DATA_INTC to enable the interrupt of THS.
Step 10 Set interrupt based on PLIC module.
Step 11 Put the interrupt handler address into the interrupt vector table.
Step 12 Write 0x1 to the bit[0] of THS0_EN to enable THS.
Step 13 Read the bit[0] of THS_DATA_INTS. If it is 1, the temperature conversion is complete.
Step 14 Read the bit[11:0] of THS_DATA, and calculate the THS temperature based on section 3.10.3.4 “THS
Temperature Conversion Formula”.
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3.10.5 Register List
Module Name Base Address
THS 0x02009400
Register Name Offset Description
THS_CTRL 0x0000 THS Control Register
THS_EN 0x0004 THS Enable Register
THS_PER 0x0008 THS Period Control Register
THS_DATA_INTC 0x0010 THS Data Interrupt Control Register
THS_SHUT_INTC 0x0014 THS Shut Interrupt Control Register
THS_ALARM_INTC 0x0018 THS Alarm Interrupt Control Register
THS_DATA_INTS 0x0020 THS Data Interrupt Status Register
THS_SHUT_INTS 0x0024 THS Shut Interrupt Status Register
THS_ALARMO_INTS 0x0028 THS Alarm off Interrupt Status Register
THS_ALARM_INTS 0x002C THS Alarm Interrupt Status Register
THS_FILTER 0x0030 THS Median Filter Control Register
THS_ALARM_CTRL 0x0040 THS Alarm Threshold Control Register
THS_SHUTDOWN_CTRL 0x0080 THS Shutdown Threshold Control Register
THS_CDATA 0x00A0 THS Calibration Data
THS_DATA 0x00C0 THS Data Register
3.10.6 Register Description
3.10.6.1 0x0000 THS Control Register (Default Value: 0x01DF_002F)
Offset: 0x0000 Register Name: THS_CTRL
Bit Read/Write Default/Hex Description
TACQ
ADC acquire time
31:16 R/W 0x1DF
CLK_IN/(n + 1)
The default value is 2 us.
15:0 R/W 0x2F Reserved
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3.10.6.2 0x0004 THS Enable Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: THS_EN
Bit Read/Write Default/Hex Description
31:1 / / /
THS_EN
Enable temperature measurement sensor
0 R/W 0x0
0: Disable
1: Enable
3.10.6.3 0x0008 THS Period Control Register (Default Value: 0x0003_A000)
Offset: 0x0008 Register Name: THS_PER
Bit Read/Write Default/Hex Description
THERMAL_PER
Temperature measurement period
31:12 R/W 0x3A
4096*(n + 1)/CLK_IN
The default value is 10 ms.
11:0 / / /
3.10.6.4 0x0010 THS Data Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: THS_DATA_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
THS_DATA_IRQ_EN
Enable the interrupt of sensor_data update
If enabled, when the measured sensor_data is updated, it will
0 R/W 0x0
generate an interrupt.
0: Disabled
1: Enabled
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3.10.6.5 0x0014 THS Shut Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: THS_SHUT_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
SHUT_INT_EN
Enable the shutdown interrupt for the sensor
0 R/W 0x0
0: Disabled
1: Enabled
3.10.6.6 0x0018 THS Alarm Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: THS_ALARM_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM_INT_EN
Enable the alarm interrupt for the sensor
0 R/W 0x0
0: Disabled
1: Enabled
3.10.6.7 0x0020 THS Data Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: THS_DATA_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
THS_DATA_IRQ_STS
Indicates the pending status of the sensor’s data interrupt. Write
0 R/W1C 0x0 1 to clear the pending status.
0: No effect
1: Pending
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3.10.6.8 0x0024 THS Shut Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: THS_SHUT_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
SHUT_INT_STS
Indicates the pending status of the sensor’s shutdown interrupt.
0 R/W1C 0x0 Write 1 to clear the pending status.
0: No effect
1: Pending
3.10.6.9 0x0028 THS Alarm Off Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: THS_ALARM_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM_OFF_STS
Alarm interrupt off pending for sensor
0 R/W1C 0x0 Write 1 to clear the pending status.
0: No effect
1: Pending
3.10.6.10 0x002C THS Alarm Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: THS_ALARM_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM_INT_STS
Alarm interrupt pending for sensor
0 R/W1C 0x0 Write 1 to clear the pending status.
0: No effect
1: Pending
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3.10.6.11 0x0030 Median Filter Control Register (Default Value: 0x0000_0001)
Offset: 0x0030 Register Name: THS_FILTER
Bit Read/Write Default/Hex Description
31:3 / / /
FILTER_EN
Filter enable
2 R/W 0x0
0: Disabled
1: Enabled
FILTER_TYPE
Averaging filter type
00: 2
1:0 R/W 0x1
01: 4
10: 8
11: 16
3.10.6.12 0x0040 THS Alarm Threshold Control Register (Default Value: 0x05A0_0684)
Offset: 0x0040 Register Name: THS_ALARM_CTRL
Bit Read/Write Default/Hex Description
31:28 / / /
ALARM_T_HOT
27:16 R/W 0x5A0
Thermal sensor alarm threshold for hot temperature
15:12 / / /
ALARM_T_HYST
11:0 R/W 0x684
Thermal sensor alarm threshold for hysteresis temperature
3.10.6.13 0x0080 THS Shutdown Threshold Control Register (Default Value: 0x0000_04E9)
Offset: 0x0080 Register Name: THS_SHUTDOWN_CTRL
Bit Read/Write Default/Hex Description
31:28 / / /
SHUT_T_HOT
11:0 R/W 0x4E9
Thermal sensor shutdown threshold for hot temperature
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3.10.6.14 0x00A0 THS Calibration Data Register (Default Value: 0x0000_0800)
Offset: 0x00A0 Register Name: THS_CDATA
Bit Read/Write Default/Hex Description
31:12 / / /
THS_CDATA
11:0 R/W 0x800
Thermal sensor calibration data
3.10.6.15 0x00C0 THS Data Register (Default Value: 0x0000_0000)
Offset: 0x00C0 Register Name: THS_DATA
Bit Read/Write Default/Hex Description
31:12 / / /
THS_DATA
11:0 R 0x0
Temperature measurement data of sensor
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3.11 IOMMU
3.11.1 Overview
The I/O Memory management unit (IOMMU) is designed for the specific memory requirements of products. It
maps the virtual address (sent by peripheral access memory) to the physical address. The IOMMU allows
multiple ways to manage the location of physical address, and it can use physical address which has potentially
conflict mapping for different processes to allocate memory space, and also allow application of non-
continuous address mapping to continuous virtual address space.
Features:
Supports virtual address to physical address mapping by hardware implementation
Supports VE, CSI, DE, G2D, DI parallel address mapping
Supports VE, CSI, DE, G2D, DI bypass function independently
Supports VE, CSI, DE, G2D, DI pre-fetch independently
Supports VE, CSI, DE, G2D, DI interrupt handing mechanism independently
Supports 2 levels TLB (level1 TLB for special using, and level2 TLB for sharing)
Supports TLB Fully cleared and Partially disabled
Supports trigger PTW behavior when TLB miss
Supports checking the permission
3.11.2 Block Diagram
The internal module of IOMMU mainly has the following parts.
Micro TLB: level1 TLB, 64 words. Each peripheral corresponds to a TLB, which caching the level2 page table for
the peripheral.
Macro TLB: level2 TLB, 4K words. Each peripheral shares a level2 TLB for caching the level2 page table.
Prefetch Logic: Each Micro TLB corresponds to a Prefetch Logic. By monitoring each master device to predict
the bus access, the secondary page table corresponding to the address to be accessed can be read from
memory and stored in the secondary TLB to improve hit ratio.
PTW Logic: Page Table Walk, mainly contains PTW Cache and PTW. The PTW Cache is used to store the level1
page table; when the virtual address VA missed in the level1 and level2 TLB, it will trigger the PTW. PTW Cache
can store 512 level1 page tables, that is, 512 words.
PMU: Performance Monitoring Unit, which is used to count hit efficiency and latency.
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APB Interface: IOMMU register instantiation module. CPU reads and writes the IOMMU register by APB bus.
The following figure shows the internal block diagram of IOMMU.
Figure 3-27 IOMMU Block Diagram
IOMMU
VE MBUS64 VA->PA Translation
CSI VA->PA Translation
DE MBUS128 VA->PA Translation
G2D MBUS64 VA->PA Translation
DI VA->PA Translation
Micro Micro Micro Micro Micro
TLB4 TLB3 TLB2 TLB1 TLB0 DRAM
Shared Macro TLB
APB
CPU Interface
Prefetch
Logic4
Prefetch
Logic3
Prefetch
Logic2
Prefetch
Logic1
Prefetch
Logic0
PTW Logic
PTW Cache Page Table Walk
Performance Monitor Unit
Table 3-14 Correspondence Relation between Master and Module
Master Number Module
Master0 VE
Master1 CSI
Master2 DE
Master3 G2D
Master4 DI
3.11.3 Functional Description
3.11.3.1 Initialization
Release the IOMMU reset signal by writing 1 to IOMMU_RESET_REG[31];
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Write the base address of the first TLB to IOMMU_TTB_REG;
Set IOMMU_INT_ENABLE_REG;
Enable the IOMMU by configuring IOMMU_ENABLE_REG in the final.
3.11.3.2 Address Changing
In the process of address mapping, The peripheral virtual address VA[31:12] are retrieved in the Level1 TLB,
when TLB hits, the mapping finished, or they are retrieved in the Level2 TLB in the same way. If TLB hits, it will
write the hit mapping to the Level1 TLB, and hits in Level1 TLB. If Level1 and Level2 TLB are retrieved fail, it will
trigger the PTW. After opening peripheral bypass function by setting IOMMU Bypass Register, IOMMU will not
map the address for peripheral typed the address, and it will output the virtual address as physical address.
The typical scenarios are as follows.
Micro TLB hit
Step 1 The master device sends a transfer command to send the address to the corresponding Micro TLB,
and searches the Level2 page table corresponding to virtual address;
Step 2 If Micro TLB hits, it will return a corresponding physical addresses and the Level2 page table of
permission Index;
Step 3 Address transform module converts the virtual address into physical address, and checks the
permissions at the same time. If pass, the transfer is completed.
Micro TLB miss, Macro TLB hit
Step 1 The master device sends a transfer command to send the address to the corresponding Micro TLB,
and searches the Level2 page table corresponding to virtual address;
Step 2 If Micro TLB misses, then continue to search Macro TLB;
Step 3 If Macro TLB hits, it will return the Level2 page table to Micro TLB;
Step 4 Micro TLB receives the page table and puts it to Micro TLB (if this Micro TLB is full, there will happen
the replace activity), at the same time, the page table entry is sent to address translation module;
Step 5 Address transform module converts the virtual address into physical address, and checks the
permissions at the same time. If pass, the transfer is completed.
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Micro TLB miss, Macro TLB miss, PTW Cache hit
Step 1 The master device sends a transfer command to send the address to the corresponding Micro TLB,
and searches the Level2 page table corresponding to virtual address;
Step 2 If Micro TLB misses, then continue to search Macro TLB;
Step 3 If Macro TLB misses, then it will send the request to the PTW to return the corresponding page table;
Step 4 PTW first accesses PTW Cache, confirms that the required Level1 page table exists in the PTW Cache,
sends the page table to PTW logic;
Step 5 PTW logic returns the corresponding Level2 page table from memory page table according to Level1
page table, checks the effectiveness, and sends to Macro TLB;
Step 6 Macro TLB stores the Level2 page table (there may happen the replace activity), and will return the
Level2 page table to Micro TLB;
Step 7 Micro TLB receives the page table entries and puts it to the Micro TLB (if this Micro TLB is full, there
will happen the replace activity), and sends page table entries to address translation module;
Step 8 Address transform module converts the virtual address into physical address, and checks the
permissions at the same time. If pass, the transfer is completed.
Micro TLB miss, Macro TLB miss, PTW Cache miss
Step 1 The master device sends a transfer command to send the address to the corresponding Micro TLB,
and searches the Level2 page table corresponding to virtual address;
Step 2 If Micro TLB misses, then continue to search Macro TLB;
Step 3 If Macro TLB misses, there will send the request to the PTW to return the corresponding page table;
Step 4 PTW accesses PTW Cache, the Level1 page table is unnecessary;
Step 5 PTW accesses memory to get the corresponding Level1 page table and stores it to the PTW Cache
(there may happen the replace activity);
Step 6 PTW logic returns the corresponding Level2 page table from memory page table according to Level1
page table, checks the effectiveness, and sends to Macro TLB;
Step 7 Macro TLB stores the Level2 page table (there may happen the replace activity), and returns the Level
2 page table to Micro TLB;
Step 8 Micro TLB receives the page table entries and puts it to the Micro TLB (if this Micro TLB is full, there
will happen the replace activity), and sends page table entries to address translation module;
Step 9 Address transform module converts the virtual address into physical address, and checks the
permissions at the same time. If pass, the transfer is completed.
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Permission error
Step 1 Permission checking always performs in the address conversion;
Step 2 Once the permission checking makes mistake, the new access of the master suspends, but continues
before this access;
Step 3 Set the error status register;
Step 4 Trigger interrupt.
Invalid Level1 page table
Step 1 Invalid Level1 page table is checked when PTW logic reads the new level page table from memory;
Step 2 The PTW reads sequentially two page table entries from the memory (64-bit data, a complete cache
line), and stores in the PTW cache;
Step 3 If the current page table is detected invalid, then the error flag is set, and the interrupt is triggered,
the cache line need to be invalidated.
NOTE
Invalid page table has two situations: the reading target page table from the memory is invalid; and the
page table stored in PTW Cache with target page table is found to be invalid after using;
If a page table is invalid, then the total cache line (that is two page tables) need to be invalidated.
Invalid Level2 page table
Step 1 Invalid Level2 page table checks when Macro TLB reads the new level page table from memory;
Step 2 The Macro TLB reads sequentially two page table entries from the memory (64-bit data, a complete
cache line), and stores in the Macro TLB;
Step 3 If the current page table is detected invalid, then the error flag is set, and the interrupt is triggered,
the cache line need to be invalidated.
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NOTE
Invalid page table has two situations: the reading target page table from the memory is invalid; and the
page table stored in Macro TLB with target page table is found to be invalid after using.
If a page table is invalid, then the total cache line (that is two page tables) need to be invalidated.
The following figure shows the internal address switch process.
Figure 3-28 Internal Switch Process
Start
Search Micro TLB
Yes
Micro TLB hit
No
Search Macro TLB
Yes Return L2 page table to
Macro TLB hit Micro TLB and update
Micro TLB
No
Trigger PTW
PTW accesses L1 page No L1 page table in
table from memory Cache
Yes
Yes PTW obtains L2 page
Valid L1 page table Update PTW Cache
table
No
No
Valid L2 page table
Yes
Return L2 page table to Yes
Macro TLB and update Permission check
Macro TLB
No
Page table invalid Permission invalid
Address switch
interrupt interrupt
End
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3.11.3.3 VA-PA Mapping
IOMMU page table is defined as Level2 mapping, the first level is 1M address space mapping, the second level
is 4K address space. This version does not support 1K, 16K and other page table size. IOMMU supports a page
table only, its meaning is:
All peripherals connected to IOMMU use the same virtual address space;
The virtual address space of the peripherals can overlap;
Different virtual addresses can map to the same physical address space;
Base address of the page table is defined by software, and it needs 16 KB address alignment; Page table of the
Level2 table item needs 1 KB address alignment. The following figure shows a complete VA-PA address
translation process.
Figure 3-29 VA-PA Switch Process
31 14 0
IOMMU_TTB_REG Start address of Level1 page table
31 2019 1211 0
Virtual address(VA) Index of Level1 page table Index of Level2 page tableOffset within page
31 1413 2 1 0
Address of Level1
Start address of Level1 page table Index of Level1 page table 00
page table
Read data from the address
31 10 2 1 0
Level1 page table
Start address of Level2 page table Reserved 01
entry
31 10 9 2 1 0
Address of Level2
Start address of Level2 page table Index of Level2 page table 00
page table
Read data from the address
31 12 7 4 1 0
Level2 page table
Physical base address ACI 1
entry
31 1211 0
Physical address(PA) Physical base address Offset within page
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3.11.3.4 Clear and Invalidate TLB
When the content of multi page tables refreshes or the address of page table changes, all VA-PA mapping which
has been cached in TLB will no longer be valid, then you need configure IOMMU TLB Flush Enable Register to
clear the TLB or PTW Cache. First suspend the access to TLB or Cache, then configure the corresponding Flush
bit of IOMMU TLB Flush Enable Register, after the operation takes effect, the related peripherals can continue
to send new access memory operations.
When some page table is invalid or incorrect mapping, you can set the TLB Invalidation relevant register to
invalidate some TLB VA-PA mapping pairs. There are two modes to invalidate the TLB operation.
(1) Mode0 (Old mode)
Step 1 Set IOMMU TLB Invalidation Mode Select Register to 0 to select mode0;
Step 2 Write target address to IOMMU TLB Invalidation Address Register;
Step 3 Set configuration values to IOMMU TLB Invalidation Address Mask Register, the requirements are
as follows:
The value of IOMMU TLB Invalidation Address Mask Register cannot be less than the IOMMU TLB
Invalidation Address Register.
The higher bit of IOMMU TLB Invalidation Address Mask Register must be continuous 1, the lower
bit must be continuous 0. For example, 0xfffff000, 0xffffe000, 0xffffc000, 0xffff8000, 0xffff0000
belongs to the legal value; and 0xffffd000, 0xffffb000, 0xffffa000, 0xffff9000, 0xffff7000 belongs to
the illegal values.
Step 4 Configure IOMMU TLB Invalidation Enable Register to enable the invalid operation. Among the way
to determine the invalid address is to get maximum valid bit and determine target address range by
target address AND mask address. The following figure shows the process.
Figure 3-30 Invalid TLB Address Range
IOMMU_TLB_IVLD_ADDR_REG，REG0 IOMMU_TLB_IVLD_ADDR_MASK_REG，REG1
31 11 0 31 Y 11 0
XXXXXXXXXXXXXXXXXXXX00 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 0 0 0 0 0 0 0 0 0 00 0 0 0
The result of AND 11≤Y≤31
bit[31]~bit[Y+1]=1
31 Z 11 0
bit[Y]~bit[11]=0
Min range of target address，
XXXXXXXXXXXXXXXXX0 0 0 0 0 0 0 0 0 0 0 0 0 00
L_ADDR
11≤Z≤31, Z≥Y
bit[Z+1]=1
bit[Z]~bit[11]=0
31 Z 11 0
Max range of target address，
X X X X X X X X X X X X X X X X X ？？？0 0 0 0 0 0 0 0 0 0 0 0
H_ADDR
H_ADDR[Z:11] && REG1[Z:11] = L_ADDR[Z:11]，that is 0；
Fetch max value of H_ADDR[Z:11]，that is maximum address
For example:
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a) When the value of IOMMU TLB Invalidation Address Mask Register is 0xFFFFF000 by default, the result
of AND is target address, that is, only target address is invalid.
b) When the value of IOMMU TLB Invalidation Address Mask Register is 0xFFFF0000, the value of IOMMU
TLB Invalidation Address Register is 0xEEEE1000, then the range of target address is from 0xEEEE0000 to
0xEEEEF000.
c) When the value of IOMMU TLB Invalidation Address Mask Register is 0xFFFFC000, the value of IOMMU
TLB Invalidation Address Register is 0xEEEE8000, then the range of target address is from 0xEEEE8000 to
0xEEEEB000.
d) When the value of IOMMU TLB Invalidation Address Mask Register is 0xFFFF8000, the value of IOMMU
TLB Invalidation Address Register is 0xEEEEC000, then the range of target address is from 0xEEEE8000 to
0xEEEEF000.
e) When the value of IOMMU TLB Invalidation Address Mask Register is 0xFFFFC000, the value of IOMMU
TLB Invalidation Address Register is 0xEEEE0000, then the range of target address is from 0xEEEE0000 to
0xEEEE3000.
(2) Mode1 (New mode)
Step 1 Set IOMMU TLB Invalidation Mode Select Register to 1 to select mode1;
Step 2 Set the starting address of invalid TLB by IOMMU TLB Invalidation Start Address Register, and set
the ending address of invalid TLB by IOMMU TLB Invalidation Start Address Register;
Step 3 Configure IOMMU TLB Invalidation Enable Register to enable invalid operation, then the related TLB
operation is invalidated.
3.11.3.5 Clear and Invalidate PTW Cache
There are two modes to invalidate the PTW cache operation.
(1) Mode0 (Old mode)
Step 1 Set IOMMU PC Invalidation Mode Select Register to 0 to select mode0;
Step 2 Set the address register that needs to be invalidated to IOMMU PC Invalidation Address Register
(the addresses need to be aligned with 1 MB);
Step 3 Configure IOMMU PC Invalidation Enable Register to enable the invalid operation. That is, the PTW
cache operation of a cacheline is invalidated.
(2) Mode1 (New mode)
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Step 1 Set IOMMU PC Invalidation Mode Select Register to 1 to select mode1;
Step 2 Set the starting address of invalid TLB by IOMMU PTW Invalidation Start Address Register, and set
the ending address of invalid TLB by IOMMU PC Invalidation Start Address Register;
Step 3 Configure IOMMU PC Invalidation Enable Register to enable invalid operation, then to invalid the
related PWM cache operation is completed.
3.11.3.6 Page Table Format
Level1 Page Table
The format of Level1 page table is as follows.
Figure 3-31 Level1 Page Table Format
31 10 9 2 1 0
Start address of Level2 page table Reserved 01
Bit[31:10]: Base address of Level2 page table;
Bit[9:2]: Reserved;
Bit[1:0]: 01 is valid page table; others are fault;
Level2 Page Table
The format of Level2 page table is as follows.
Figure 3-32 Level1 Page Table Format
31 12 7 4 1 0
Physical base address ACI 1
Bit[31:12]: Physical address of 4K address;
Bit[11:8]: Reserved;
Bit[7:4]: ACI, permission control index; correspond to permission control bit of IOMMU Domain Authority
Control Register;
Bit[3:2]: Reserved;
Bit[1]: 1 is valid page table; 0 is fault;
Bit[0]: Reserved
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Permission Index
The read/write access control of series register such as IOMMU Domain Authority Control Register is as
follows.
Figure 3-33 Read/Write Permission Control
Bit[1:0]/Bit[17:16]: Master0 read/write permission control;
Bit[3:2]/Bit[19:18]: Master1 read/write permission control;
Bit[5:4]/Bit[21:20]: Master2 read/write permission control;
Bit[7:6]/Bit[23:22]: Master3 read/write permission control;
Bit[9:8]/Bit[25:24]: Master4 read/write permission control;
Bit[11:10]/Bit[27:26]: Master5 read/write permission control;
Bit[13:12]/Bit[29:28]: Master6 read/write permissiom control.
The value of IOMMU Domain Authority Control Register is read-only by default. Other registers can configure
through system requirement. In address switch process, the corresponding relation between ACI and Domain
is as follows.
Table 3-15 Relation between ACI and Domain
ACI Domain Register
0 Domain 0 IOMMU Domain Authority Control Register 0
1 Domain 1 IOMMU Domain Authority Control Register 0
2 Domain 2 IOMMU Domain Authority Control Register 1
3 Domain 3 IOMMU Domain Authority Control Register 1
4 Domain 4 IOMMU Domain Authority Control Register 2
5 Domain 5 IOMMU Domain Authority Control Register 2
6 Domain 6 IOMMU Domain Authority Control Register 3
7 Domain 7 IOMMU Domain Authority Control Register 3
8 Domain 8 IOMMU Domain Authority Control Register 4
9 Domain 9 IOMMU Domain Authority Control Register 4
10 Domain 10 IOMMU Domain Authority Control Register 5
11 Domain 11 IOMMU Domain Authority Control Register 5
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ACI Domain Register
12 Domain 12 IOMMU Domain Authority Control Register 6
13 Domain 13 IOMMU Domain Authority Control Register 6
14 Domain 14 IOMMU Domain Authority Control Register 7
15 Domain 15 IOMMU Domain Authority Control Register 7
After enabled IOMMU Domain Authority Overwrite Register, the read/write control permission can override
all IOMMU Domain Authority Control Register.
3.11.4 Programming Guidelines
3.11.4.1 Resetting IOMMU
Before the IOMMU module software reset operation, make sure IOMMU is never opened, or all bus operations
are completed, or DRAM and peripherals already open the corresponding switch, to shield the influence of
IOMMU reset.
3.11.4.2 Enabling IOMMU
Before opening the IOMMU address mapping function, the Translation Table Base Register should be correctly
configured, or all the masters are in the bypass state, or all the masters do not send the bus command.
3.11.4.3 Configuring TTB
Operating the register must close the address mapping function of IOMMU, that is, the
IOMMU_ENABLE_REG[0] is 0; or the bypass function of all masters is set to 1; or the state of the TX bus
command is none.
3.11.4.4 Clearing TTB
In the Flush operation, all TLB/Cache access will be suspended; but the operation entered the TLB will continue
to complete before the Flush starts.
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3.11.4.5 Reading/Writing VA Data
For target virtual address, read and write the corresponding physical address data to make sure whether
IOMMU module address mapping function is normal. First, make sure to read or write, and then configure the
target virtual address or write data, then start to read or write function, check whether the results are as
expected after the operation is finished.
3.11.4.6 Using PMU Statistics Function
When PMU function is used for the first time, set IOMMU PMU Enable Register to enable statistics function;
when reading the relevant Register, clear the enable bit of IOMMU PMU Enable Register; when PMU function
is used next time, first IOMMU PMU Clear Register is set, after counter is cleared, set the enable bit of IOMMU
PMU Enable Register.
Given a Level2 page table administers continuous 4 KB address, if Micro TLB misses in continuous virtual
address, there may need to return a Level2 page table to hit from Macro TLB; but the hit number is not recorded
in the Macro TLB hit and Micro TLB hit related register. So the true hit rate calculation is as follows:
Hit Rate = N1/M1 + (1-N1/M1)*N2/M2
N1: Micro TLB hit number
M1: Micro TLB access number
N2: Macro TLB hit number
M2: Macro TLB access number
3.11.5 Register List
Module Name Base Address
IOMMU 0x02010000
Register Name Offset Description
IOMMU_RESET_REG 0x0010 IOMMU Reset Register
IOMMU_ENABLE_REG 0x0020 IOMMU Enable Register
IOMMU_BYPASS_REG 0x0030 IOMMU Bypass Register
IOMMU_AUTO_GATING_REG 0x0040 IOMMU Auto Gating Register
IOMMU_WBUF_CTRL_REG 0x0044 IOMMU Write Buffer Control Register
IOMMU_OOO_CTRL_REG 0x0048 IOMMU Out of Order Control Register
IOMMU_4KB_BDY_PRT_CTRL_REG 0x004C IOMMU 4KB Boundary Protect Control Register
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Register Name Offset Description
IOMMU_TTB_REG 0x0050 IOMMU Translation Table Base Register
IOMMU_TLB_ENABLE_REG 0x0060 IOMMU TLB Enable Register
IOMMU_TLB_PREFETCH_REG 0x0070 IOMMU TLB Prefetch Register
IOMMU_TLB_FLUSH_ENABLE_REG 0x0080 IOMMU TLB Flush Enable Register
IOMMU_TLB_IVLD_MODE_SEL_REG 0x0084 IOMMU TLB Invalidation Mode Select Register
IOMMU_TLB_IVLD_STA_ADDR_REG 0x0088 IOMMU TLB Invalidation Start Address Register
IOMMU_TLB_IVLD_END_ADDR_REG 0x008C IOMMU TLB Invalidation End Address Register
IOMMU_TLB_IVLD_ADDR_REG 0x0090 IOMMU TLB Invalidation Address Register
IOMMU_TLB_IVLD_ADDR_MASK_REG 0x0094 IOMMU TLB Invalidation Address Mask Register
IOMMU_TLB_IVLD_ENABLE_REG 0x0098 IOMMU TLB Invalidation Enable Register
IOMMU_PC_IVLD_MODE_SEL_REG 0x009C IOMMU PC Invalidation Mode Select Register
IOMMU_PC_IVLD_ADDR_REG 0x00A0 IOMMU PC Invalidation Address Register
IOMMU_PC_IVLD_STA_ADDR_REG 0x00A4 IOMMU PC Invalidation Start Address Register
IOMMU_PC_IVLD_ENABLE_REG 0x00A8 IOMMU PC Invalidation Enable Register
IOMMU_PC_IVLD_END_ADDR_REG 0x00AC IOMMU PC Invalidation End Address Register
IOMMU_DM_AUT_CTRL0_REG 0x00B0 IOMMU Domain Authority Control 0 Register
IOMMU_DM_AUT_CTRL1_REG 0x00B4 IOMMU Domain Authority Control 1 Register
IOMMU_DM_AUT_CTRL2_REG 0x00B8 IOMMU Domain Authority Control 2 Register
IOMMU_DM_AUT_CTRL3_REG 0x00BC IOMMU Domain Authority Control 3 Register
IOMMU_DM_AUT_CTRL4_REG 0x00C0 IOMMU Domain Authority Control 4 Register
IOMMU_DM_AUT_CTRL5_REG 0x00C4 IOMMU Domain Authority Control 5 Register
IOMMU_DM_AUT_CTRL6_REG 0x00C8 IOMMU Domain Authority Control 6 Register
IOMMU_DM_AUT_CTRL7_REG 0x00CC IOMMU Domain Authority Control 7 Register
IOMMU_DM_AUT_OVWT_REG 0x00D0 IOMMU Domain Authority Overwrite Register
IOMMU_INT_ENABLE_REG 0x0100 IOMMU Interrupt Enable Register
IOMMU_INT_CLR_REG 0x0104 IOMMU Interrupt Clear Register
IOMMU_INT_STA_REG 0x0108 IOMMU Interrupt Status Register
IOMMU_INT_ERR_ADDR0_REG 0x0110 IOMMU Interrupt Error Address 0 Register
IOMMU_INT_ERR_ADDR1_REG 0x0114 IOMMU Interrupt Error Address 1 Register
IOMMU_INT_ERR_ADDR2_REG 0x0118 IOMMU Interrupt Error Address 2 Register
IOMMU_INT_ERR_ADDR3_REG 0x011C IOMMU Interrupt Error Address 3 Register
IOMMU_INT_ERR_ADDR4_REG 0x0120 IOMMU Interrupt Error Address 4 Register
IOMMU_INT_ERR_ADDR5_REG 0x0124 IOMMU Interrupt Error Address 5 Register
IOMMU_INT_ERR_ADDR6_REG 0x0128 IOMMU Interrupt Error Address 6 Register
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Register Name Offset Description
IOMMU_INT_ERR_ADDR7_REG 0x0130 IOMMU Interrupt Error Address 7 Register
IOMMU_INT_ERR_ADDR8_REG 0x0134 IOMMU Interrupt Error Address 8 Register
IOMMU_INT_ERR_DATA0_REG 0x0150 IOMMU Interrupt Error Data 0 Register
IOMMU_INT_ERR_DATA1_REG 0x0154 IOMMU Interrupt Error Data 1 Register
IOMMU_INT_ERR_DATA2_REG 0x0158 IOMMU Interrupt Error Data 2 Register
IOMMU_INT_ERR_DATA3_REG 0x015C IOMMU Interrupt Error Data 3 Register
IOMMU_INT_ERR_DATA4_REG 0x0160 IOMMU Interrupt Error Data 4 Register
IOMMU_INT_ERR_DATA5_REG 0x0164 IOMMU Interrupt Error Data 5 Register
IOMMU_INT_ERR_DATA6_REG 0x0168 IOMMU Interrupt Error Data 6 Register
IOMMU_INT_ERR_DATA7_REG 0x0170 IOMMU Interrupt Error Data 7 Register
IOMMU_INT_ERR_DATA8_REG 0x0174 IOMMU Interrupt Error Data 8 Register
IOMMU_L1PG_INT_REG 0x0180 IOMMU L1 Page Table Interrupt Register
IOMMU_L2PG_INT_REG 0x0184 IOMMU L2 Page Table Interrupt Register
IOMMU_VA_REG 0x0190 IOMMU Virtual Address Register
IOMMU_VA_DATA_REG 0x0194 IOMMU Virtual Address Data Register
IOMMU_VA_CONFIG_REG 0x0198 IOMMU Virtual Address Configuration Register
IOMMU_PMU_ENABLE_REG 0x0200 IOMMU PMU Enable Register
IOMMU_PMU_CLR_REG 0x0210 IOMMU PMU Clear Register
IOMMU_PMU_ACCESS_LOW0_REG 0x0230 IOMMU PMU Access Low 0 Register
IOMMU_PMU_ACCESS_HIGH0_REG 0x0234 IOMMU PMU Access High 0 Register
IOMMU_PMU_HIT_LOW0_REG 0x0238 IOMMU PMU Hit Low 0 Register
IOMMU_PMU_HIT_HIGH0_REG 0x023C IOMMU PMU Hit High 0 Register
IOMMU_PMU_ACCESS_LOW1_REG 0x0240 IOMMU PMU Access Low 1 Register
IOMMU_PMU_ACCESS_HIGH1_REG 0x0244 IOMMU PMU Access High 1 Register
IOMMU_PMU_HIT_LOW1_REG 0x0248 IOMMU PMU Hit Low 1 Register
IOMMU_PMU_HIT_HIGH1_REG 0x024C IOMMU PMU Hit High 1 Register
IOMMU_PMU_ACCESS_LOW2_REG 0x0250 IOMMU PMU Access Low 2 Register
IOMMU_PMU_ACCESS_HIGH2_REG 0x0254 IOMMU PMU Access High 2 Register
IOMMU_PMU_HIT_LOW2_REG 0x0258 IOMMU PMU Hit Low 2 Register
IOMMU_PMU_HIT_HIGH2_REG 0x025C IOMMU PMU Hit High 2 Register
IOMMU_PMU_ACCESS_LOW3_REG 0x0260 IOMMU PMU Access Low 3 Register
IOMMU_PMU_ACCESS_HIGH3_REG 0x0264 IOMMU PMU Access High 3 Register
IOMMU_PMU_HIT_LOW3_REG 0x0268 IOMMU PMU Hit Low 3 Register
IOMMU_PMU_HIT_HIGH3_REG 0x026C IOMMU PMU Hit High 3 Register
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Register Name Offset Description
IOMMU_PMU_ACCESS_LOW4_REG 0x0270 IOMMU PMU Access Low 4 Register
IOMMU_PMU_ACCESS_HIGH4_REG 0x0274 IOMMU PMU Access High 4 Register
IOMMU_PMU_HIT_LOW4_REG 0x0278 IOMMU PMU Hit Low 4 Register
IOMMU_PMU_HIT_HIGH4_REG 0x027C IOMMU PMU Hit High 4 Register
IOMMU_PMU_ACCESS_LOW5_REG 0x0280 IOMMU PMU Access Low 5 Register
IOMMU_PMU_ACCESS_HIGH5_REG 0x0284 IOMMU PMU Access High 5 Register
IOMMU_PMU_HIT_LOW5_REG 0x0288 IOMMU PMU Hit Low 5 Register
IOMMU_PMU_HIT_HIGH5_REG 0x028C IOMMU PMU Hit High 5 Register
IOMMU_PMU_ACCESS_LOW6_REG 0x0290 IOMMU PMU Access Low 6 Register
IOMMU_PMU_ACCESS_HIGH6_REG 0x0294 IOMMU PMU Access High 6 Register
IOMMU_PMU_HIT_LOW6_REG 0x0298 IOMMU PMU Hit Low 6 Register
IOMMU_PMU_HIT_HIGH6_REG 0x029C IOMMU PMU Hit High 6 Register
IOMMU_PMU_ACCESS_LOW7_REG 0x02D0 IOMMU PMU Access Low 7 Register
IOMMU_PMU_ACCESS_HIGH7_REG 0x02D4 IOMMU PMU Access High 7 Register
IOMMU_PMU_HIT_LOW7_REG 0x02D8 IOMMU PMU Hit Low 7 Register
IOMMU_PMU_HIT_HIGH7_REG 0x02DC IOMMU PMU Hit High 7 Register
IOMMU_PMU_ACCESS_LOW8_REG 0x02E0 IOMMU PMU Access Low 8 Register
IOMMU_PMU_ACCESS_HIGH8_REG 0x02E4 IOMMU PMU Access High 8 Register
IOMMU_PMU_HIT_LOW8_REG 0x02E8 IOMMU PMU Hit Low 8 Register
IOMMU_PMU_HIT_HIGH8_REG 0x02EC IOMMU PMU Hit High 8 Register
IOMMU_PMU_TL_LOW0_REG 0x0300 IOMMU Total Latency Low 0 Register
IOMMU_PMU_TL_HIGH0_REG 0x0304 IOMMU Total Latency High 0 Register
IOMMU_PMU_ML0_REG 0x0308 IOMMU Max Latency 0 Register
IOMMU_PMU_TL_LOW1_REG 0x0310 IOMMU Total Latency Low 1 Register
IOMMU_PMU_TL_HIGH1_REG 0x0314 IOMMU Total Latency High 1 Register
IOMMU_PMU_ML1_REG 0x0318 IOMMU Max Latency 1 Register
IOMMU_PMU_TL_LOW2_REG 0x0320 IOMMU Total Latency Low 2 Register
IOMMU_PMU_TL_HIGH2_REG 0x0324 IOMMU Total Latency High 2 Register
IOMMU_PMU_ML2_REG 0x0328 IOMMU Max Latency 2 Register
IOMMU_PMU_TL_LOW3_REG 0x0330 IOMMU Total Latency Low 3 Register
IOMMU_PMU_TL_HIGH3_REG 0x0334 IOMMU Total Latency High 3 Register
IOMMU_PMU_ML3_REG 0x0338 IOMMU Max Latency 3 Register
IOMMU_PMU_TL_LOW4_REG 0x0340 IOMMU Total Latency Low 4 Register
IOMMU_PMU_TL_HIGH4_REG 0x0344 IOMMU Total Latency High 4 Register
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Register Name Offset Description
IOMMU_PMU_ML4_REG 0x0348 IOMMU Max Latency 4 Register
IOMMU_PMU_TL_LOW5_REG 0x0350 IOMMU Total Latency Low 5 Register
IOMMU_PMU_TL_HIGH5_REG 0x0354 IOMMU Total Latency High 5 Register
IOMMU_PMU_ML5_REG 0x0358 IOMMU Max Latency 5 Register
IOMMU_PMU_TL_LOW6_REG 0x0360 IOMMU Total Latency Low 6 Register
IOMMU_PMU_TL_HIGH6_REG 0x0364 IOMMU Total Latency High 6 Register
IOMMU_PMU_ML6_REG 0x0368 IOMMU Max Latency 6 Register
3.11.6 Register Description
3.11.6.1 0x0010 IOMMU Reset Register (Default Value: 0x8003_007F)
Offset: 0x0010 Register Name: IOMMU_RESET_REG
Bit Read/Write Default/Hex Description
IOMMU_RESET
IOMMU Software Reset Switch
0: Set reset signal
1: Release reset signal
31 R/W 0x1
Before IOMMU software reset operation, ensure IOMMU never
be opened; or all bus operations are completed; or DRAM and
the peripherals have opened the corresponding switch, for
shielding the effects of IOMMU reset.
30:18 / / /
PC_RST
PTW Cache Reset
PTW Cache address convert lane software reset switch.
17 R/W 0x1 0: Set reset signal
1: Release reset signal
When PTW Cache occurs abnormal, the bit is used to reset PTW
Cache individually.
MTLB_RST
Macrotlb Reset
Macro TLB address convert lane software reset switch.
16 R/W 0x1 0: Set reset signal
1: Release reset signal
When PTW Cache occurs abnormal, the bit is used to reset PTW
Cache individually.
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Offset: 0x0010 Register Name: IOMMU_RESET_REG
Bit Read/Write Default/Hex Description
15:7 / / /
M6_RST
Master6 Reset
Master6 address convert lane software reset switch.
0: Set reset signal
6 R/W 0x1
1: Release reset signal
When Master6 occurs abnormal, the bit is used to reset PTW
Cache individually.
Note: This bit is not used.
M5_RST
Master5 Reset
Master5 address convert lane software reset switch.
5 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master5 occurs abnormal, the bit is used to reset PTW
Cache individually.
M4_RST
Master4 Reset
Master4 address convert lane software reset switch.
4 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master4 occurs abnormal, the bit is used to reset PTW
Cache individually.
M3_RST
Master3 Reset
Master3 address convert lane software reset switch.
3 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master3 occurs abnormal, the bit is used to reset PTW
Cache individually.
M2_RST
Master2 Reset
Master2 address convert lane software reset switch.
2 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master2 occurs abnormal, the bit is used to reset PTW
Cache individually.
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Offset: 0x0010 Register Name: IOMMU_RESET_REG
Bit Read/Write Default/Hex Description
M1_RST
Master1 Reset
Master1 address convert lane software reset switch.
1 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master1 occurs abnormal, the bit is used to reset PTW
Cache individually.
M0_RST
Master0 Reset
Master0 address convert lane software reset switch.
0 R/W 0x1 0: Set reset signal
1: Release reset signal
When Master0 occurs abnormal, the bit is used to reset PTW
Cache individually.
3.11.6.2 0x0020 IOMMU Enable Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: IOMMU_ENABLE_REG
Bit Read/Write Default/Hex Description
31:1 / / /
ENABLE
IOMMU module enable switch
0: Disable IOMMU
1: Enable IOMMU
0 R/W 0x0
Before IOMMU address mapping function opens, configure the
Translation Table Base register; or ensure all masters are in
bypass status or no the status of sending bus demand(such as
reset)
3.11.6.3 0x0030 IOMMU Bypass Register (Default Value: 0x0000_007F)
Offset: 0x0030 Register Name: IOMMU_BYPASS_REG
Bit Read/Write Default/Hex Description
31:7 / / /
M6_BP
6 R/W 0x1
Master6 bypass switch
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Offset: 0x0030 Register Name: IOMMU_BYPASS_REG
Bit Read/Write Default/Hex Description
After bypass function is opened, IOMMU can not map the
address of Master6 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
Note: The bit is not used.
M5_BP
Master5 bypass switch
After bypass function is opened, IOMMU can not map the
5 R/W 0x1 address of Master5 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
M4_BP
Master4 bypass switch
After bypass function is opened, IOMMU can not map the
4 R/W 0x1 address of Master4 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
M3_BP
Master3 bypass switch
After bypass function is opened, IOMMU can not map the
3 R/W 0x1 address of Master3 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
M2_BP
Master2 bypass switch
After bypass function is opened, IOMMU can not map the
2 R/W 0x1 address of Master2 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
M1_BP
1 R/W 0x1
Master1 bypass switch
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Offset: 0x0030 Register Name: IOMMU_BYPASS_REG
Bit Read/Write Default/Hex Description
After bypass function is opened, IOMMU can not map the
address of Master1 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
M0_BP
Master0 bypass switch
After bypass function is opened, IOMMU can not map the
0 R/W 0x1 address of Master0 sending, and directly output the virtual
address to MBUS as physical address.
0: Disable bypass function
1: Enable bypass function
NOTE
Operating the register belongs to non-accurate timing sequence control function. That is, before the
function is valid, master operation will complete address mapping function, and any subsequent operation
will not perform address mapping.
It is suggested that master is in reset state or in no any bus operation before operating the register.
3.11.6.4 0x0040 IOMMU Auto Gating Register (Default Value: 0x0000_0001)
Offset: 0x0040 Register Name: IOMMU_AUTO_GATING_REG
Bit Read/Write Default/Hex Description
31:1 / / /
IOMMU_AUTO_GATING
IOMMU circuit auto gating control
0 R/W 0x1 The purpose is to decrease power consumption of the module.
0: Disable auto gating function
1: Enable auto gating function
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3.11.6.5 0x0044 IOMMU Write Buffer Control Register (Default Value: 0x0000_007F)
Offset: 0x0044 Register Name: IOMMU_WBUF_CTRL_REG
Bit Read/Write Default/Hex Description
31:7 / / /
6 R/W 0x1 Reserved
5 R/W 0x1 Reserved
4 R/W 0x1 Reserved
3 R/W 0x1 Reserved
2 R/W 0x1 Reserved
1 R/W 0x1 Reserved
0 R/W 0x1 Reserved
3.11.6.6 0x0048 IOMMU Out Of Order Control Register (Default Value: 0x0000_007F)
Offset: 0x0048 Register Name: IOMMU_OOO_CTRL_REG
Bit Read/Write Default/Hex Description
31:7 / / /
M6_OOO_CTRL
Master6 out-of-order control bit
6 R/W 0x1 0: Disable out-of-order
1: Enable out-of-order
Note: This bit is not used.
M5_OOO_CTRL
Master5 out-of-order control bit
5 R/W 0x1
0: Disable out-of-order
1: Enable out-of-order
M4_OOO_CTRL
Master4 out-of-order control bit
4 R/W 0x1
0: Disable out-of-order
1: Enable out-of-order
M3_OOO_CTRL
Master3 out-of-order control bit
3 R/W 0x1
0: Disable out-of-order
1: Enable out-of-order
M2_OOO_CTRL
2 R/W 0x1
Master2 out-of-order control bit
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Offset: 0x0048 Register Name: IOMMU_OOO_CTRL_REG
Bit Read/Write Default/Hex Description
0: Disable out-of-order
1: Enable out-of-order
M1_OOO_CTRL
Master1 out-of-order control bit
1 R/W 0x1
0: Disable out-of-order
1: Enable out-of-order
M0_OOO_CTRL
Master0 out-of-order control bit
0 R/W 0x1
0: Disable out-of-order
1: Enable out-of-order
3.11.6.7 0x004C IOMMU 4KB Boundary Protect Control Register (Default Value: 0x0000_007F)
NOTE
When the virtual address sent by master is over the 4 KB boundary, 4 KB protection unit will split it into two
serial access.
Offset: 0x004C Register Name: IOMMU_4KB_BDY_PRT_CTRL_REG
Bit Read/Write Default/Hex Description
31:7 / / /
M6_4KB_BDY_PRT_CTRL
Master6 4 KB boundary protect control bit
6 R/W 0x1 0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
Note: This bit is not used.
M5_4KB_BDY_PRT_CTRL
Master4 4 KB boundary protect control bit
5 R/W 0x1
0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
M4_4KB_BDY_PRT_CTRL
4 R/W 0x1 Master4 4 KB boundary protect control bit
0: Disable 4 KB boundary protect
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Offset: 0x004C Register Name: IOMMU_4KB_BDY_PRT_CTRL_REG
Bit Read/Write Default/Hex Description
1: Enable 4 KB boundary protect
M3_4KB_BDY_PRT_CTRL
Master3 4 KB boundary protect control bit
3 R/W 0x1
0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
M2_4KB_BDY_PRT_CTRL
Master2 4 KB boundary protect control bit
2 R/W 0x1
0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
M1_4KB_BDY_PRT_CTRL
Master1 4 KB boundary protect control bit
1 R/W 0x1
0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
M0_4KB_BDY_PRT_CTRL
Master0 4 KB boundary protect control bit
0 R/W 0x1
0: Disable 4 KB boundary protect
1: Enable 4 KB boundary protect
3.11.6.8 0x0050 IOMMU Translation Table Base Register (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: IOMMU_TTB_REG
Bit Read/Write Default/Hex Description
TTB
Translation Table Base
Level1 page table starting address, aligned to 16 KB.
31:14 R/W 0x0 When operating the register, IOMMU address mapping function
must be closed, namely IOMMU_ENABLE_REG is 0; Or Bypass
function of all main equipment is set to 1, or no the state of
transfer bus commands (such as setting).
13:0 / / /
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3.11.6.9 0x0060 IOMMU TLB Enable Register (Default Value: 0x0003_007F)
Offset: 0x0060 Register Name: IOMMU_TLB_ENABLE_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PTW_CACHE_ENABLE
PTW Cache enable bit
17 R/W 0x1
0: Disable
1: Enable
MACRO_TLB_ENABLE
Macro TLB enable bit
16 R/W 0x1
0: Disable
1: Enable
15:7 / / /
MICRO_TLB6_ENABLE
Micro TLB6 enable bit
6 R/W 0x1
0: Disable
1: Enable
MICRO_TLB5_ENABLE
Micro TLB5 enable bit
5 R/W 0x1
0: Disable
1: Enable
MICRO_TLB4_ENABLE
Micro TLB4 enable bit
4 R/W 0x1
0: Disable
1: Enable
MICRO_TLB3_ENABLE
Micro TLB3 enable bit
3 R/W 0x1
0: Disable
1: Enable
MICRO_TLB2_ENABLE
Micro TLB2 enable bit
2 R/W 0x1
0: Disable
1: Enable
MICRO_TLB1_ENABLE
Micro TLB1 enable bit
1 R/W 0x1
0: Disable
1: Enable
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Offset: 0x0060 Register Name: IOMMU_TLB_ENABLE_REG
Bit Read/Write Default/Hex Description
MICRO_TLB0_ENABLE
Micro TLB0 enable bit
0 R/W 0x1
0: Disable
1: Enable
3.11.6.10 0x0070 IOMMU TLB Prefetch Register (Default Value: 0x0000_0000)
Offset: 0x0070 Register Name: IOMMU_TLB_PREFETCH_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PF_VL_PT_TO_PC
Prefetch Value Pagetable to PTW Cache
0: Disable
17 R/W 0x1
1: Enable
If the function is enabled, the prefetch function will not update
the invalid Level1 page table to PTW cache.
PF_VL_PT_TO_MT
Prefetch Value Pagetable to Macro TLB
0: Disable
16 R/W 0x1
1: Enable
If the function is enabled, the prefetch function will not update
the invalid Level2 page table to Macro TLB.
15:7 / / /
MI_TLB6_PF
Micro TLB6 prefetch enable
6 R/W 0x0
0: Disable
1: Enable
MI_TLB5_PF
Micro TLB5 prefetch enable
5 R/W 0x0
0: Disable
1: Enable
MI_TLB4_PF
Micro TLB4 prefetch enable
4 R/W 0x0
0: Disable
1: Enable
3 R/W 0x0 MI_TLB3_PF
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Offset: 0x0070 Register Name: IOMMU_TLB_PREFETCH_REG
Bit Read/Write Default/Hex Description
Micro TLB3 prefetch enable
0: Disable
1: Enable
Note: If G2D accesses DDR, it is suggested that disable the
prefetch function.
MI_TLB2_PF
Micro TLB2 prefetch enable
2 R/W 0x0
0: Disable
1: Enable
MI_TLB1_PF
Micro TLB1 prefetch enable
1 R/W 0x0
0: Disable
1: Enable
MI_TLB0_PF
Micro TLB0 prefetch enable
0 R/W 0x0
0: Disable
1: Enable
3.11.6.11 0x0080 IOMMU TLB Flush Enable Register (Default Value: 0x0000_0000)
When performing flush operations, all TLB/Cache access will be paused.
Before flush starts, the operation that has entered TLB continues to complete.
Offset: 0x0080 Register Name: IOMMU_TLB_FLUSH_ENABLE_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PC_FS
PTW Cache Flush
Clear PTW Cache
17 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MA_TLB_FS
Macro TLB Flush
16 R/WAC 0x0
Clear Macro TLB
0: No clear operation or clear operation is completed
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Offset: 0x0080 Register Name: IOMMU_TLB_FLUSH_ENABLE_REG
Bit Read/Write Default/Hex Description
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
15:7 / / /
MI_TLB6_FS
Micro TLB6 Flush
Clear Micro TLB6
6 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB5_FS
Micro TLB5 Flush
Clear Micro TLB5
5 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB4_FS
Micro TLB4 Flush
Clear Micro TLB4
4 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB3_FS
Micro TLB3 Flush
Clear Micro TLB3
3 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB2_FS
Micro TLB2 Flush
2 R/WAC 0x0 Clear Micro TLB2
0: No clear operation or clear operation is completed
1: Enable clear operation
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Offset: 0x0080 Register Name: IOMMU_TLB_FLUSH_ENABLE_REG
Bit Read/Write Default/Hex Description
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB1_FS
Micro TLB1 Flush
Clear Micro TLB1
1 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
MI_TLB0_FS
Micro TLB0 Flush
Clear Micro TLB0
0 R/WAC 0x0 0: No clear operation or clear operation is completed
1: Enable clear operation
After the Flush operation is completed, the bit can clear
automatically.
3.11.6.12 0x0084 IOMMU TLB Invalidation Mode Select Register (Default Value: 0x0000_0000)
Offset: 0x0084 Register Name: IOMMU_TLB_IVLD_MODE_SEL_REG
Bit Read/Write Default/Hex Description
31:1 / / /
TLB_IVLD_MODE_SEL
0 R/W 0x0 0: Invalidate TLB by using the Mask mode
1: Invalidate TLB by using the Start and End mode
3.11.6.13 0x0088 IOMMU TLB Invalidation Start Address Register (Default Value: 0x0000_0000)
Offset: 0x0088 Register Name: IOMMU_TLB_IVLD_STA_ADDR_REG
Bit Read/Write Default/Hex Description
TLB_IVLD_STA_ADDR
31:12 R/W 0x0
TLB invalid start address, 4 KB aligned.
11:0 / / /
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3.11.6.14 0x008C IOMMU TLB Invalidation End Address Register (Default Value: 0x0000_0000)
Offset: 0x008C Register Name: IOMMU_TLB_IVLD_END_ADDR_REG
Bit Read/Write Default/Hex Description
TLB_IVLD_END_ADDR
31:12 R/W 0x0
TLB invalid end address, 4 KB aligned.
11:0 / / /
3.11.6.15 0x0090 IOMMU TLB Invalidation Address Register (Default Value: 0x0000_0000)
Offset: 0x0090 Register Name: IOMMU_TLB_IVLD_ADDR_REG
Bit Read/Write Default/Hex Description
TLB_IVLD_ADDR
31:12 R/W 0x0
TLB invalid address, 4 KB aligned
11:0 / / /
Operation:
1) Set the virtual address that needs to be operated in IOMMU_TLB_IVLD_ADDR_REG.
2) Set the mask of virtual address that needs to be operated in IOMMU_TLB_IVLD_ADDR_MASK_REG.
3) Write ‘1’ to IOMMU_TLB_IVLD_ENABLE_REG[0].
4) Read IOMMU_TLB_IVLD_ENABLE_REG[0], when it is ‘0’, it indicates that invalidation behavior is finished.
NOTE
When performing invalidation operation, TLB/Cache operation has not affected.
After or before invalidation operation starts, there is no absolute relationship between the same address
switch operation and invalidation operation.
3.11.6.16 0x0094 IOMMU TLB Invalidation Address Mask Register (Default Value: 0x0000_0000)
Offset: 0x0094 Register Name: IOMMU_TLB_IVLD_ADDR_MASK_REG
Bit Read/Write Default/Hex Description
TLB_IVLD_ADDR_MASK
31:12 R/W 0x0
TLB invalid address mask register, 4 KB aligned
11:0 / / /
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3.11.6.17 0x0098 IOMMU TLB Invalidation Enable Register (Default Value: 0x0000_0000)
Offset: 0x0098 Register Name: IOMMU_TLB_IVLD_ENABLE_REG
Bit Read/Write Default/Hex Description
31:1 / / /
TLB_IVLD_ENABLE
Enable TLB invalidation operation
0: No operation or operation is completed
1: Enable invalidation operation
After invalidation operation is completed, the bit can clear
0 R/WAC 0x0 automatically.
When operating invalidation operation, TLB/Cache operation
has not affected.
After or before invalidation operation starts, there is no absolute
relationship between the same address switch operation and
invalidation operation.
3.11.6.18 0x009C IOMMU PC Invalidation Mode Select Register (Default Value: 0x0000_0000)
Offset: 0x009C Register Name: IOMMU_PC_IVLD_MODE_SEL_REG
Bit Read/Write Default/Hex Description
31:1 / / /
PC_IVLD_MODE_SEL
PTW Cache Invalid Mode Select
0 R/W 0x0
0: Invalidate PTW by using the Mask mode
1: Invalidate PTW by using the Start and End mode
3.11.6.19 0x00A0 IOMMU PC Invalidation Address Register (Default Value: 0x0000_0000)
Offset: 0x00A0 Register Name: IOMMU_PC_IVLD_ADDR_REG
Bit Read/Write Default/Hex Description
PC_IVLD_ADDR
31:20 R/W 0x0
PTW Cache invalid address, 1 MB aligned.
19:0 / / /
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3.11.6.20 0x00A4 IOMMU PC Invalidation Start Address Register (Default Value: 0x0000_0000)
Offset: 0x00A4 Register Name: IOMMU_PC_IVLD_STA_ADDR_REG
Bit Read/Write Default/Hex Description
PC_IVLD_SA
31:20 R/W 0x0
PTW Cache invalid start address, 1 MB aligned.
19:0 / / /
3.11.6.21 0x00A8 IOMMU PC Invalidation Enable Register (Default Value: 0x0000_0000)
Offset: 0x00A8 Register Name: IOMMU_PC_IVLD_ENABLE_REG
Bit Read/Write Default/Hex Description
31:1 / / /
PC_IVLD_ENABLE
Enable PTW Cache invalidation operation
0: No operation or operation is completed
1: Enable invalidation operation
0 R/WAC 0x0 After invalidation operation is completed, the bit can clear
automatically.
After or before invalidation operation starts, there is no absolute
relationship between the same address switch operation and
invalidation operation.
3.11.6.22 0x00AC IOMMU PC Invalidation End Address Register (Default Value: 0x0000_0000)
Offset: 0x00AC Register Name: IOMMU_PC_IVLD_END_ADDR_REG
Bit Read/Write Default/Hex Description
PC_IVLD_EA
31:20 R/W 0x0
PTW Cache invalid end address, 1 MB aligned.
19:0 / / /
3.11.6.23 0x00B0 IOMMU Domain Authority Control 0 Register (Default Value: 0x0000_0000)
Software can set 15 different permission control types in IOMMU_DM_AUT_CTRL_REG0–7. A default access
control type is DOMAIN0. The read/write operation of DOMAIN1–15 is unlimited by default.
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Software needs to set the index of the permission control domain corresponding to the page table item in the
bit[7:4] of the Level2 page table, the default value is 0 (use domian0), that is, the read/write operation is not
controlled.
Setting REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL_REG0–7. All Level2
page table type are covered by the type of REG_ARD_OVWT. The read/write operation is permitted by default.
Offset: 0x00B0 Register Name: IOMMU_DM_AUT_CTRL0_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM1_M6_WT_AUT_CTRL
Domain1 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM1_M6_RD_AUT_CTRL
Domain1 read permission control for master6
28 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM1_M5_WT_AUT_CTRL
Domain1 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM1_M5_RD_AUT_CTRL
Domain1 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM1_M4_WT_AUT_CTRL
Domain1 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM1_M4_RD_AUT_CTRL
Domain1 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM1_M3_WT_AUT_CTRL
Domain1 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
22 R/W 0x0 DM1_M3_RD_AUT_CTRL
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Offset: 0x00B0 Register Name: IOMMU_DM_AUT_CTRL0_REG
Bit Read/Write Default/Hex Description
Domain1 read permission control for master3
0: The read-operation is permitted
1: The read-operation is prohibited
DM1_M2_WT_AUT_CTRL
Domain1 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM1_M2_RD_AUT_CTRL
Domain1 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM1_M1_WT_AUT_CTRL
Domain1 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM1_M1_RD_AUT_CTRL
Domain1 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM1_M0_WT_AUT_CTRL
Domain1 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM1_M0_RD_AUT_CTRL
Domain1 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM0_M6_WT_AUT_CTRL
Domain0 write permission control for master6
13 R 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM0_M6_RD_AUT_CTRL
12 R 0x0 Domain0 read permission control for master6
0: The read-operation is permitted
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Offset: 0x00B0 Register Name: IOMMU_DM_AUT_CTRL0_REG
Bit Read/Write Default/Hex Description
1: The read-operation is prohibited
Note: The bit is not used.
DM0_M5_WT_AUT_CTRL
Domain0 write permission control for master5
11 R 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M5_RD_AUT_CTRL
Domain0 read permission control for master5
10 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM0_M4_WT_AUT_CTRL
Domain0 write permission control for master4
9 R 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M4_RD_AUT_CTRL
Domain0 read permission control for master4
8 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM0_M3_WT_AUT_CTRL
Domain0 write permission control for master3
7 R 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M3_RD_AUT_CTRL
Domain0 read permission control for master3
6 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM0_M2_WT_AUT_CTRL
Domain0 write permission control for master2
5 R 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M2_RD_AUT_CTRL
Domain0 read permission control for master2
4 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM0_M1_WT_AUT_CTRL
3 R 0x0
Domain0 write permission control for master1
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Offset: 0x00B0 Register Name: IOMMU_DM_AUT_CTRL0_REG
Bit Read/Write Default/Hex Description
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M1_RD_AUT_CTRL
Domain0 read permission control for master1
2 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM0_M0_WT_AUT_CTRL
Domain0 write permission control for master0
1 R 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM0_M0_RD_AUT_CTRL
Domain0 read permission control for master0
0 R 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.24 0x00B4 IOMMU Domain Authority Control 1 Register (Default Value: 0x0000_0000)
Offset: 0x00B4 Register Name: IOMMU_DM_AUT_CTRL1_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM3_M6_WT_AUT_CTRL
Domain3 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM3_M6_RD_AUT_CTRL
Domain3 read permission control for master6
28 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM3_M5_WT_AUT_CTRL
Domain3 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M5_RD_AUT_CTRL
26 R/W 0x0
Domain3 read permission control for master5
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Offset: 0x00B4 Register Name: IOMMU_DM_AUT_CTRL1_REG
Bit Read/Write Default/Hex Description
0: The read-operation is permitted
1: The read-operation is prohibited
DM3_M4_WT_AUT_CTRL
Domain3 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M4_RD_AUT_CTRL
Domain3 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM3_M3_WT_AUT_CTRL
Domain3 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M3_RD_AUT_CTRL
Domain3 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM3_M2_WT_AUT_CTRL
Domain3 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M2_RD_AUT_CTRL
Domain3 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM3_M1_WT_AUT_CTRL
Domain3 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M1_RD_AUT_CTRL
Domain3 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM3_M0_WT_AUT_CTRL
17 R/W 0x0
Domain3 write permission control for master0
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Offset: 0x00B4 Register Name: IOMMU_DM_AUT_CTRL1_REG
Bit Read/Write Default/Hex Description
0: The write-operation is permitted
1: The write-operation is prohibited
DM3_M0_RD_AUT_CTRL
Domain3 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM2_M6_WT_AUT_CTRL
Domain2 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM2_M6_RD_AUT_CTRL
Domain2 read permission control for master6
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM2_M5_WT_AUT_CTRL
Domain2 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM2_M5_RD_AUT_CTRL
Domain2 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM2_M4_WT_AUT_CTRL
Domain2 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM2_M4_RD_AUT_CTRL
Domain2 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM2_M3_WT_AUT_CTRL
7 R/W 0x0 Domain2 write permission control for master3
0: The write-operation is permitted
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Offset: 0x00B4 Register Name: IOMMU_DM_AUT_CTRL1_REG
Bit Read/Write Default/Hex Description
1: The write-operation is prohibited
DM2_M3_RD_AUT_CTRL
Domain2 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM2_M2_WT_AUT_CTRL
Domain2 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM2_M2_RD_AUT_CTRL
Domain2 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM2_M1_WT_AUT_CTRL
Domain2 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM2_M1_RD_AUT_CTRL
Domain2 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM2_M0_WT_AUT_CTRL
Domain2 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM2_M0_RD_AUT_CTRL
Domain2 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.25 0x00B8 IOMMU Domain Authority Control 2 Register (Default Value: 0x0000_0000)
Offset: 0x00B8 Register Name: IOMMU_DM_AUT_CTRL2_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29 R/W 0x0 DM5_M6_WT_AUT_CTRL
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Offset: 0x00B8 Register Name: IOMMU_DM_AUT_CTRL2_REG
Bit Read/Write Default/Hex Description
Domain5 write permission control for master6
0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM5_M6_RD_AUT_CTRL
Domain5 read permission control for master6
28 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM5_M5_WT_AUT_CTRL
Domain5 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM5_M5_RD_AUT_CTRL
Domain5 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM5_M4_WT_AUT_CTRL
Domain5 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM5_M4_RD_AUT_CTRL
Domain5 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM5_M3_WT_AUT_CTRL
Domain5 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM5_M3_RD_AUT_CTRL
Domain5 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM5_M2_WT_AUT_CTRL
Domain5 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
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Offset: 0x00B8 Register Name: IOMMU_DM_AUT_CTRL2_REG
Bit Read/Write Default/Hex Description
DM5_M2_RD_AUT_CTRL
Domain5 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM5_M1_WT_AUT_CTRL
Domain5 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM5_M1_RD_AUT_CTRL
Domain5 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM5_M0_WT_AUT_CTRL
Domain5 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM5_M0_RD_AUT_CTRL
Domain5 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM4_M6_WT_AUT_CTRL
Domain4 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM4_M6_RD_AUT_CTRL
Domain4 read permission control for master6
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM4_M5_WT_AUT_CTRL
Domain4 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
10 R/W 0x0 DM4_M5_RD_AUT_CTRL
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Offset: 0x00B8 Register Name: IOMMU_DM_AUT_CTRL2_REG
Bit Read/Write Default/Hex Description
Domain4 read permission control for master5
0: The read-operation is permitted
1: The read-operation is prohibited
DM4_M4_WT_AUT_CTRL
Domain4 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM4_M4_RD_AUT_CTRL
Domain4 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM4_M3_WT_AUT_CTRL
Domain4 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM4_M3_RD_AUT_CTRL
Domain4 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM4_M2_WT_AUT_CTRL
Domain4 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM4_M2_RD_AUT_CTRL
Domain4 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM4_M1_WT_AUT_CTRL
Domain4 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM4_M1_RD_AUT_CTRL
Domain4 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
1 R/W 0x0 DM4_M0_WT_AUT_CTRL
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Offset: 0x00B8 Register Name: IOMMU_DM_AUT_CTRL2_REG
Bit Read/Write Default/Hex Description
Domain4 write permission control for master0
0: The write-operation is permitted
1: The write-operation is prohibited
DM4_M0_RD_AUT_CTRL
Domain4 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.26 0x00BC IOMMU Domain Authority Control 3 Register (Default Value: 0x0000_0000)
Offset: 0x00BC Register Name: IOMMU_DM_AUT_CTRL3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM7_M6_WT_AUT_CTRL
Domain7 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM7_M6_RD_AUT_CTRL
Domain7 read permission control for master6
28 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM7_M5_WT_AUT_CTRL
Domain7 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM7_M5_RD_AUT_CTRL
Domain7 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM7_M4_WT_AUT_CTRL
Domain7 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
24 R/W 0x0 DM7_M4_RD_AUT_CTRL
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Offset: 0x00BC Register Name: IOMMU_DM_AUT_CTRL3_REG
Bit Read/Write Default/Hex Description
Domain7 read permission control for master4
0: The read-operation is permitted
1: The read-operation is prohibited
DM7_M3_WT_AUT_CTRL
Domain7 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM7_M3_RD_AUT_CTRL
Domain7 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM7_M2_WT_AUT_CTRL
Domain7 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM7_M2_RD_AUT_CTRL
Domain7 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM7_M1_WT_AUT_CTRL
Domain7 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM7_M1_RD_AUT_CTRL
Domain7 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM7_M0_WT_AUT_CTRL
Domain7 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM7_M0_RD_AUT_CTRL
Domain7 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
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Offset: 0x00BC Register Name: IOMMU_DM_AUT_CTRL3_REG
Bit Read/Write Default/Hex Description
DM6_M6_WT_AUT_CTRL
Domain6 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM6_M6_RD_AUT_CTRL
Domain6 read permission control for master6
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM6_M5_WT_AUT_CTRL
Domain6 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM6_M5_RD_AUT_CTRL
Domain6 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM6_M4_WT_AUT_CTRL
Domain6 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM6_M4_RD_AUT_CTRL
Domain6 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM6_M3_WT_AUT_CTRL
Domain6 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM6_M3_RD_AUT_CTRL
Domain6 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM6_M2_WT_AUT_CTRL
5 R/W 0x0 Domain6 write permission control for master2
0: The write-operation is permitted
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Offset: 0x00BC Register Name: IOMMU_DM_AUT_CTRL3_REG
Bit Read/Write Default/Hex Description
1: The write-operation is prohibited
DM6_M2_RD_AUT_CTRL
Domain6 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM6_M1_WT_AUT_CTRL
Domain6 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM6_M1_RD_AUT_CTRL
Domain6 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM6_M0_WT_AUT_CTRL
Domain6 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM6_M0_RD_AUT_CTRL
Domain6 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.27 0x00C0 IOMMU Domain Authority Control 4 Register (Default Value: 0x0000_0000)
Offset: 0x00C0 Register Name: IOMMU_DM_AUT_CTRL4_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM9_M6_WT_AUT_CTRL
Domain9 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM9_M6_RD_AUT_CTRL
Domain9 read permission control for master6
28 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
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Offset: 0x00C0 Register Name: IOMMU_DM_AUT_CTRL4_REG
Bit Read/Write Default/Hex Description
Note: The bit is not used.
DM9_M5_WT_AUT_CTRL
Domain9 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM9_M5_RD_AUT_CTRL
Domain9 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM9_M4_WT_AUT_CTRL
Domain9 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM9_M4_RD_AUT_CTRL
Domain9 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM9_M3_WT_AUT_CTRL
Domain9 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM9_M3_RD_AUT_CTRL
Domain9 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM9_M2_WT_AUT_CTRL
Domain9 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM9_M2_RD_AUT_CTRL
Domain9 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM9_M1_WT_AUT_CTRL
19 R/W 0x0 Domain9 write permission control for master1
0: The write-operation is permitted
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Offset: 0x00C0 Register Name: IOMMU_DM_AUT_CTRL4_REG
Bit Read/Write Default/Hex Description
1: The write-operation is prohibited
DM9_M1_RD_AUT_CTRL
Domain9 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM9_M0_WT_AUT_CTRL
Domain9 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM9_M0_RD_AUT_CTRL
Domain9 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM8_M6_WT_AUT_CTRL
Domain8 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM8_M6_RD_AUT_CTRL
Domain8 read permission control for master6
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM8_M5_WT_AUT_CTRL
Domain8 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM8_M5_RD_AUT_CTRL
Domain8 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM8_M4_WT_AUT_CTRL
Domain8 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
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Offset: 0x00C0 Register Name: IOMMU_DM_AUT_CTRL4_REG
Bit Read/Write Default/Hex Description
DM8_M4_RD_AUT_CTRL
Domain8 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM8_M3_WT_AUT_CTRL
Domain8 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM8_M3_RD_AUT_CTRL
Domain8 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM8_M2_WT_AUT_CTRL
Domain8 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM8_M2_RD_AUT_CTRL
Domain8 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM8_M1_WT_AUT_CTRL
Domain8 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM8_M1_RD_AUT_CTRL
Domain8 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM8_M0_WT_AUT_CTRL
Domain8 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM8_M0_RD_AUT_CTRL
Domain8 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
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3.11.6.28 0x00C4 IOMMU Domain Authority Control 5 Register (Default Value: 0x0000_0000)
Offset: 0x00C4 Register Name: IOMMU_DM_AUT_CTRL5_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM11_M6_WT_AUT_CTRL
Domain11 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM11_M6_RD_AUT_CTRL
Domain11 read permission control for master6
28 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM11_M5_WT_AUT_CTRL
Domain11 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M5_RD_AUT_CTRL
Domain11 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM11_M4_WT_AUT_CTRL
Domain11 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M4_RD_AUT_CTRL
Domain11 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM11_M3_WT_AUT_CTRL
Domain11 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M3_RD_AUT_CTRL
22 R/W 0x0
Domain11 read permission control for master3
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Offset: 0x00C4 Register Name: IOMMU_DM_AUT_CTRL5_REG
Bit Read/Write Default/Hex Description
0: The read-operation is permitted
1: The read-operation is prohibited
DM11_M2_WT_AUT_CTRL
Domain11 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M2_RD_AUT_CTRL
Domain11 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM11_M1_WT_AUT_CTRL
Domain11 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M1_RD_AUT_CTRL
Domain11 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM11_M0_WT_AUT_CTRL
Domain11 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM11_M0_RD_AUT_CTRL
Domain11 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM10_M6_WT_AUT_CTRL
Domain10 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM10_M6_RD_AUT_CTRL
Domain10 read permission control for master6
12 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
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Offset: 0x00C4 Register Name: IOMMU_DM_AUT_CTRL5_REG
Bit Read/Write Default/Hex Description
Note: The bit is not used.
DM10_M5_WT_AUT_CTRL
Domain10 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM10_M5_RD_AUT_CTRL
Domain10 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM10_M4_WT_AUT_CTRL
Domain10 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM10_M4_RD_AUT_CTRL
Domain10 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM10_M3_WT_AUT_CTRL
Domain10 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM10_M3_RD_AUT_CTRL
Domain10 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM10_M2_WT_AUT_CTRL
Domain10 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM10_M2_RD_AUT_CTRL
Domain10 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM10_M1_WT_AUT_CTRL
3 R/W 0x0 Domain10 write permission control for master1
0: The write-operation is permitted
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Offset: 0x00C4 Register Name: IOMMU_DM_AUT_CTRL5_REG
Bit Read/Write Default/Hex Description
1: The write-operation is prohibited
DM10_M1_RD_AUT_CTRL
Domain10 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM10_M0_WT_AUT_CTRL
Domain10 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM10_M0_RD_AUT_CTRL
Domain10 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.29 0x00C8 IOMMU Domain Authority Control 6 Register (Default Value: 0x0000_0000)
Offset: 0x00C8 Register Name: IOMMU_DM_AUT_CTRL6_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM13_M6_WT_AUT_CTRL
Domain13 write permission control for master6
29 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M6_RD_AUT_CTRL
Domain13 read permission control for master6
28 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM13_M5_WT_AUT_CTRL
Domain13 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M5_RD_AUT_CTRL
Domain13 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
25 R/W 0x0 DM13_M4_WT_AUT_CTRL
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Offset: 0x00C8 Register Name: IOMMU_DM_AUT_CTRL6_REG
Bit Read/Write Default/Hex Description
Domain13 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M4_RD_AUT_CTRL
Domain13 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM13_M3_WT_AUT_CTRL
Domain13 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M3_RD_AUT_CTRL
Domain13 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM13_M2_WT_AUT_CTRL
Domain13 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M2_RD_AUT_CTRL
Domain13 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM13_M1_WT_AUT_CTRL
Domain13 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM13_M1_RD_AUT_CTRL
Domain13 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM13_M0_WT_AUT_CTRL
Domain13 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
16 R/W 0x0 DM13_M0_RD_AUT_CTRL
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Offset: 0x00C8 Register Name: IOMMU_DM_AUT_CTRL6_REG
Bit Read/Write Default/Hex Description
Domain13 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM12_M6_WT_AUT_CTRL
Domain12 write permission control for master6
13 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M6_RD_AUT_CTRL
Domain12 read permission control for master6
12 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM12_M5_WT_AUT_CTRL
Domain12 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M5_RD_AUT_CTRL
Domain12 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM12_M4_WT_AUT_CTRL
Domain12 write permission control for master4
9 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M4_RD_AUT_CTRL
Domain12 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM12_M3_WT_AUT_CTRL
Domain12 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M3_RD_AUT_CTRL
Domain12 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
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Offset: 0x00C8 Register Name: IOMMU_DM_AUT_CTRL6_REG
Bit Read/Write Default/Hex Description
DM12_M2_WT_AUT_CTRL
Domain12 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M2_RD_AUT_CTRL
Domain12 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM12_M1_WT_AUT_CTRL
Domain12 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M1_RD_AUT_CTRL
Domain12 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM12_M0_WT_AUT_CTRL
Domain12 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM12_M0_RD_AUT_CTRL
Domain12 read permission control for master0
0 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.30 0x00CC IOMMU Domain Authority Control 7 Register (Default Value: 0x0000_0000)
Offset: 0x00CC Register Name: IOMMU_DM_AUT_CTRL7_REG
Bit Read/Write Default/Hex Description
31:30 / / /
DM15_M6_WT_AUT_CTRL
Domain15 write permission control for master6
29 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
28 R/W 0x0 DM15_M6_RD_AUT_CTRL
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Offset: 0x00CC Register Name: IOMMU_DM_AUT_CTRL7_REG
Bit Read/Write Default/Hex Description
Domain15 read permission control for master6
0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM15_M5_WT_AUT_CTRL
Domain15 write permission control for master5
27 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M5_RD_AUT_CTRL
Domain15 read permission control for master5
26 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM15_M4_WT_AUT_CTRL
Domain15 write permission control for master4
25 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M4_RD_AUT_CTRL
Domain15 read permission control for master4
24 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM15_M3_WT_AUT_CTRL
Domain15 write permission control for master3
23 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M3_RD_AUT_CTRL
Domain15 read permission control for master3
22 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM15_M2_WT_AUT_CTRL
Domain15 write permission control for master2
21 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M2_RD_AUT_CTRL
Domain15 read permission control for master2
20 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
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Offset: 0x00CC Register Name: IOMMU_DM_AUT_CTRL7_REG
Bit Read/Write Default/Hex Description
DM15_M1_WT_AUT_CTRL
Domain15 write permission control for master1
19 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M1_RD_AUT_CTRL
Domain15 read permission control for master1
18 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM15_M0_WT_AUT_CTRL
Domain15 write permission control for master0
17 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM15_M0_RD_AUT_CTRL
Domain15 read permission control for master0
16 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
15:14 / / /
DM14_M6_WT_AUT_CTRL
Domain14 write permission control for master6
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
DM14_M6_RD_AUT_CTRL
Domain14 read permission control for master6
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
DM14_M5_WT_AUT_CTRL
Domain14 write permission control for master5
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM14_M5_RD_AUT_CTRL
Domain14 read permission control for master5
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
9 R/W 0x0 DM14_M4_WT_AUT_CTRL
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Offset: 0x00CC Register Name: IOMMU_DM_AUT_CTRL7_REG
Bit Read/Write Default/Hex Description
Domain14 write permission control for master4
0: The write-operation is permitted
1: The write-operation is prohibited
DM14_M4_RD_AUT_CTRL
Domain14 read permission control for master4
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM14_M3_WT_AUT_CTRL
Domain14 write permission control for master3
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM14_M3_RD_AUT_CTRL
Domain14 read permission control for master3
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM14_M2_WT_AUT_CTRL
Domain14 write permission control for master2
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM14_M2_RD_AUT_CTRL
Domain14 read permission control for master2
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM14_M1_WT_AUT_CTRL
Domain14 write permission control for master1
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
DM14_M1_RD_AUT_CTRL
Domain14 read permission control for master1
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
DM14_M0_WT_AUT_CTRL
Domain14 write permission control for master0
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
0 R/W 0x0 DM14_M0_RD_AUT_CTRL
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Offset: 0x00CC Register Name: IOMMU_DM_AUT_CTRL7_REG
Bit Read/Write Default/Hex Description
Domain14 read permission control for master0
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.31 0x00D0 IOMMU Domain Authority Overwrite Register (Default Value: 0x0000_0000)
Setting the REG_ARD_OVWT can mask the Domain control defined by IOMMU_DM_AUT_CTRL_REG0–7. All
the property of Level2 are covered by the property defined in REG_ARD_OVWT. Allow read and write for all by
default.
Offset: 0x00D0 Register Name: IOMMU_DM_AUT_OVWT_REG
Bit Read/Write Default/Hex Description
DM_AUT_OVWT_ENABLE
Domain write/read permission overwrite enable
31 R/W 0x0
0: Disable
1: Enable
30:14 / / /
M6_WT_AUT_OVWT_CTRL
Master6 write permission overwrite control
13 R/W 0x0 0: The write-operation is permitted
1: The write-operation is prohibited
Note: The bit is not used.
M6_RD_AUT_OVWT_CTRL
Master6 read permission overwrite control
12 R/W 0x0 0: The read-operation is permitted
1: The read-operation is prohibited
Note: The bit is not used.
M5_WT_AUT_OVWT_CTRL
Master5 write permission overwrite control
11 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
M5_RD_AUT_OVWT_CTRL
Master5 read permission overwrite control
10 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
M4_WT_AUT_OVWT_CTRL
9 R/W 0x0
Master5 write permission overwrite control
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Offset: 0x00D0 Register Name: IOMMU_DM_AUT_OVWT_REG
Bit Read/Write Default/Hex Description
0: The write-operation is permitted
1: The write-operation is prohibited
M4_RD_AUT_OVWT_CTRL
Master5 read permission overwrite control
8 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
M3_WT_AUT_OVWT_CTRL
Master3 write permission overwrite control
7 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
M3_RD_AUT_OVWT_CTRL
Master3 read permission overwrite control
6 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
M2_WT_AUT_OVWT_CTRL
Master2 write permission overwrite control
5 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
M2_RD_AUT_OVWT_CTRL
Master2 read permission overwrite control
4 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
M1_WT_AUT_OVWT_CTRL
Master1 write permission overwrite control
3 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
M1_RD_AUT_OVWT_CTRL
Master1 read permission overwrite control
2 R/W 0x0
0: The read-operation is permitted
1: The read-operation is prohibited
M0_WT_AUT_OVWT_CTRL
Master0 write permission overwrite control
1 R/W 0x0
0: The write-operation is permitted
1: The write-operation is prohibited
M0_RD_AUT_OVWT_CTRL
0 R/W 0x0
Master0 read permission overwrite control
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Offset: 0x00D0 Register Name: IOMMU_DM_AUT_OVWT_REG
Bit Read/Write Default/Hex Description
0: The read-operation is permitted
1: The read-operation is prohibited
3.11.6.32 0x0100 IOMMU Interrupt Enable Register (Default Value: 0x0000_0000)
Invalid page table and permission error can not make one device or multi-devices in system work normally.
Permission error usually happens in MicroTLB. The error generates interrupt and waits for processing through
software.
Invalid page table usually happens in MacroTLB. The error can not influence the access of other devices. So the
error page table needs go back the way it comes, but the error should not be written in each level TLB.
Offset: 0x0100 Register Name: IOMMU_INT_ENABLE_REG
Bit Read/Write Default/Hex Description
31:21 / / /
DBG_PF_L2_IV_PT_EN.
Debug or Prefetch Invalid Page Table Enable
20 R/W 0x0
0: Mask interrupt
1: Enable interrupt
DBG_PF_PC_IV_L1_PT_EN.
Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable
19 R/W 0x0
0: Mask interrupt
1: Enable interrupt
DBG_PF_DRAM_IV_L1_PT_EN.
Debug or Prefetch DRAM Invalid Level1 Page Table Enable
18 R/W 0x0
0: Mask interrupt
1: Enable interrupt
L2_PAGE_TABLE_INVALID_EN
Level2 page table invalid interrupt enable
17 R/W 0x0
0: Mask interrupt
1: Enable interrupt
L1_PAGE_TABLE_INVALID_EN
Level1 page table invalid interrupt enable
16 R/W 0x0
0: Mask interrupt
1: Enable interrupt
15:7 / / /
6 R/W 0x0 MICRO_TLB6_INVALID_EN
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Offset: 0x0100 Register Name: IOMMU_INT_ENABLE_REG
Bit Read/Write Default/Hex Description
Micro TLB6 permission invalid interrupt enable
0: Mask interrupt
1: Enable interrupt
MICRO_TLB5_INVALID_EN
Micro TLB5 permission invalid interrupt enable
5 R/W 0x0
0: Mask interrupt
1: Enable interrupt
MICRO_TLB4_INVALID_EN
Micro TLB4 permission invalid interrupt enable
4 R/W 0x0
0: Mask interrupt
1: Enable interrupt
MICRO_TLB3_INVALID_EN
Micro TLB3 permission invalid interrupt enable
3 R/W 0x0
0: Mask interrupt
1: Enable interrupt
MICRO_TLB2_INVALID_EN
Micro TLB2 permission invalid interrupt enable
2 R/W 0x0
0: Mask interrupt
1: Enable interrupt
MICRO_TLB1_INVALID_EN
Micro TLB1 permission invalid interrupt enable
1 R/W 0x0
0: Mask interrupt
1: Enable interrupt
MICRO_TLB0_INVALID_EN
Micro TLB0 permission invalid interrupt enable
0 R/W 0x0
0: Mask interrupt
1: Enable interrupt
3.11.6.33 0x0104 IOMMU Interrupt Clear Register (Default Value: 0x0000_0000)
Offset: 0x0104 Register Name: IOMMU_INT_CLR_REG
Bit Read/Write Default/Hex Description
31:18 / / /
L2_PAGE_TABLE_INVALID_CLR
17 W 0x0 Level2 page table invalid interrupt clear bit
0: Invalid operation
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Offset: 0x0104 Register Name: IOMMU_INT_CLR_REG
Bit Read/Write Default/Hex Description
1: Clear interrupt
L1_PAGE_TABLE_INVALID_CLR
Level1 page table invalid interrupt clear bit
16 W 0x0
0: Invalid operation
1: Clear interrupt
15:7 / / /
MICRO_TLB6_INVALID_CLR
Micro TLB6 permission invalid interrupt clear bit
6 W 0x0 0: Invalid operation
1: Clear interrupt
Note: The bit is not used.
MICRO_TLB5_INVALID_CLR
Micro TLB5 permission invalid interrupt clear bit
5 W 0x0
0: Invalid operation
1: Clear interrupt
MICRO_TLB4_INVALID_CLR
Micro TLB4 permission invalid interrupt clear bit
4 W 0x0
0: Invalid operation
1: Clear interrupt
MICRO_TLB3_INVALID_CLR
Micro TLB3 permission invalid interrupt clear bit
3 W 0x0
0: Invalid operation
1: Clear interrupt
MICRO_TLB2_INVALID_CLR
Micro TLB2 permission invalid interrupt clear bit
2 W 0x0
0: Invalid operation
1: Clear interrupt
MICRO_TLB1_INVALID_CLR
Micro TLB1 permission invalid interrupt clear bit
1 W 0x0
0: Invalid operation
1: Clear interrupt
MICRO_TLB0_INVALID_CLR
Micro TLB0 permission invalid interrupt clear bit
0 W 0x0
0: Invalid operation
1: Clear interrupt
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3.11.6.34 0x0108 IOMMU Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0108 Register Name: IOMMU_INT_STA_REG
Bit Read/Write Default/Hex Description
31:18 / / /
L2_PAGE_TABLE_INVALID_STA
Level2 page table invalid interrupt status bit
17 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
L1_PAGE_TABLE_INVALID_STA
Level1 page table invalid interrupt status bit
16 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
15:7 / / /
MICRO_TLB6_INVALID_STA
Micro TLB6 permission invalid interrupt status bit
6 R 0x0 0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
Note: The bit is not used.
MICRO_TLB5_INVALID_STA
Micro TLB5 permission invalid interrupt status bit
5 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
MICRO_TLB4_INVALID_STA
Micro TLB4 permission invalid interrupt status bit
4 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
MICRO_TLB3_INVALID_STA
Micro TLB3 permission invalid interrupt status bit
3 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
MICRO_TLB2_INVALID_STA
Micro TLB2 permission invalid interrupt status bit
2 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
MICRO_TLB1_INVALID_STA
Micro TLB1 permission invalid interrupt status bit
1 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
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Offset: 0x0108 Register Name: IOMMU_INT_STA_REG
Bit Read/Write Default/Hex Description
MICRO_TLB0_INVALID_STA
Micro TLB0 permission invalid interrupt status bit
0 R 0x0
0: Interrupt does not happen or interrupt is cleared
1: Interrupt happens
3.11.6.35 0x0110 IOMMU Interrupt Error Address 0 Register (Default Value: 0x0000_0000)
Offset: 0x0110 Register Name: IOMMU_INT_ERR_ADDR0_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR0
31:0 R 0x0
Virtual address that caused Micro TLB0 to interrupt
3.11.6.36 0x0114 IOMMU Interrupt Error Address 1 Register (Default Value: 0x0000_0000)
Offset: 0x0114 Register Name: IOMMU_INT_ERR_ADDR1_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR1
31:0 R 0x0
Virtual address that caused Micro TLB1 to interrupt
3.11.6.37 0x0118 IOMMU Interrupt Error Address 2 Register (Default Value: 0x0000_0000)
Offset: 0x0118 Register Name: IOMMU_INT_ERR_ADDR2_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR2
31:0 R 0x0
Virtual address that caused Micro TLB2 to interrupt
3.11.6.38 0x011C IOMMU Interrupt Error Address 3 Register (Default Value: 0x0000_0000)
Offset: 0x011C Register Name: IOMMU_INT_ERR_ADDR3_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR3
31:0 R 0x0
Virtual address that caused Micro TLB3 to interrupt
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3.11.6.39 0x0120 IOMMU Interrupt Error Address 4 Register (Default Value: 0x0000_0000)
Offset: 0x0120 Register Name: IOMMU_INT_ERR_ADDR4_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR4
31:0 R 0x0
Virtual address that caused Micro TLB4 to interrupt
3.11.6.40 0x0124 IOMMU Interrupt Error Address 5 Register (Default Value: 0x0000_0000)
Offset: 0x0124 Register Name: IOMMU_INT_ERR_ADDR5_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR5
31:0 R 0x0
Virtual address that caused Micro TLB5 to interrupt
3.11.6.41 0x0128 IOMMU Interrupt Error Address 6 Register (Default Value: 0x0000_0000)
Offset: 0x0128 Register Name: IOMMU_INT_ERR_ADDR6_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR6
31:0 R 0x0
Virtual address that caused Micro TLB6 to interrupt
3.11.6.42 0x0130 IOMMU Interrupt Error Address 7 Register (Default Value: 0x0000_0000)
Offset: 0x0130 Register Name: IOMMU_INT_ERR_ADDR7_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR7
31:0 R 0x0
Virtual address that caused L1 page table to interrupt
3.11.6.43 0x0134 IOMMU Interrupt Error Address 8 Register (Default Value: 0x0000_0000)
Offset: 0x0134 Register Name: IOMMU_INT_ERR_ADDR8_REG
Bit Read/Write Default/Hex Description
INT_ERR_ADDR8
31:0 R 0x0
Virtual address that caused L2 page table to interrupt
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3.11.6.44 0x0150 IOMMU Interrupt Error Data 0 Register (Default Value: 0x0000_0000)
Offset: 0x0150 Register Name: IOMMU_INT_ERR_DATA0_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA0
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB0 to interrupt
3.11.6.45 0x0154 IOMMU Interrupt Error Data 1 Register (Default Value: 0x0000_0000)
Offset: 0x0154 Register Name: IOMMU_INT_ERR_DATA1_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA1
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB1 to interrupt
3.11.6.46 0x0158 IOMMU Interrupt Error Data 2 Register (Default Value: 0x0000_0000)
Offset: 0x0158 Register Name: IOMMU_INT_ERR_DATA2_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA2
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB2 to interrupt
3.11.6.47 0x015C IOMMU Interrupt Error Data 3 Register (Default Value: 0x0000_0000)
Offset: 0x015C Register Name: IOMMU_INT_ERR_DATA3_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA3
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB3 to interrupt
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3.11.6.48 0x0160 IOMMU Interrupt Error Data 4 Register (Default Value: 0x0000_0000)
Offset: 0x0160 Register Name: IOMMU_INT_ERR_DATA4_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA4
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB4 to interrupt
3.11.6.49 0x0164 IOMMU Interrupt Error Data 5 Register (Default Value: 0x0000_0000)
Offset: 0x0164 Register Name: IOMMU_INT_ERR_DATA5_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA5
31:0 R 0x0 Corresponding page table of virtual address that caused Micro
TLB5 to interrupt
3.11.6.50 0x0168 IOMMU Interrupt Error Data 6 Register (Default Value: 0x0000_0000)
Offset: 0x0168 Register Name: IOMMU_INT_ERR_DATA6_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA6
Corresponding page table of virtual address that caused Micro
31:0 R 0x0
TLB6 to interrupt
Note: This field is not used.
3.11.6.51 0x0170 IOMMU Interrupt Error Data 7 Register (Default Value: 0x0000_0000)
Offset: 0x0170 Register Name: IOMMU_INT_ERR_DATA7_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA7
31:0 R 0x0 Corresponding page table of virtual address that caused L1 page
table to interrupt
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3.11.6.52 0x0174 IOMMU Interrupt Error Data 8 Register (Default Value: 0x0000_0000)
Offset: 0x0174 Register Name: IOMMU_INT_ERR_DATA8_REG
Bit Read/Write Default/Hex Description
INT_ERR_DATA8
31:0 R 0x0 Corresponding page table of virtual address that caused L2 page
table to interrupt
3.11.6.53 0x0180 IOMMU L1 Page Table Interrupt Register (Default Value: 0x0000_0000)
Offset: 0x0180 Register Name: IOMMU_L1PG_INT_REG
Bit Read/Write Default/Hex Description
DBG_MODE_L1PG_INT
31 R 0x0 Debug mode address switch causes L1 page table to occur
interrupt.
30:7 / / /
MASTER6_L1PG_INT
6 R 0x0 Master6 address switch causes L1 page table to occur interrupt.
Note: The bit is not used.
MASTER5_L1PG_INT
5 R 0x0
Master5 address switch causes L1 page table to occur interrupt.
MASTER4_L1PG_INT
4 R 0x0
Master4 address switch causes L1 page table to occur interrupt.
MASTER3_L1PG_INT
3 R 0x0
Master3 address switch causes L1 page table to occur interrupt.
MASTER2_L1PG_INT
2 R 0x0
Master2 address switch causes L1 page table to occur interrupt.
MASTER1_L1PG_INT
1 R 0x0
Master1 address switch causes L1 page table to occur interrupt.
MASTER0_L1PG_INT
0 R 0x0
Master0 address switch causes L1 page table to occur interrupt.
3.11.6.54 0x0184 IOMMU L2 Page Table Interrupt Register (Default Value: 0x0000_0000)
Offset: 0x0184 Register Name: IOMMU_L2PG_INT_REG
Bit Read/Write Default/Hex Description
31 R 0x0 DBG_MODE_L2PG_INT
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Offset: 0x0184 Register Name: IOMMU_L2PG_INT_REG
Bit Read/Write Default/Hex Description
Debug mode address switch causes L2 page table to occur
interrupt.
30:7 / / /
MASTER6_L2PG_INT
6 R 0x0 Master6 address switch causes L2 page table to occur interrupt.
Note: The bit is not used.
MASTER5_L2PG_INT
5 R 0x0
Master5 address switch causes L2 page table to occur interrupt.
MASTER4_L2PG_INT
4 R 0x0
Master4 address switch causes L2 page table to occur interrupt.
MASTER3_L2PG_INT
3 R 0x0
Master3 address switch causes L2 page table to occur interrupt.
MASTER2_L2PG_INT
2 R 0x0
Master2 address switch causes L2 page table to occur interrupt.
MASTER1_L2PG_INT
1 R 0x0
Master1 address switch causes L2 page table to occur interrupt.
MASTER0_L2PG_INT
0 R 0x0
Master0 address switch causes L2 page table to occur interrupt.
3.11.6.55 0x0190 IOMMU Virtual Address Register (Default Value: 0x0000_0000)
Offset: 0x0190 Register Name: IOMMU_VA _REG
Bit Read/Write Default/Hex Description
VA
31:0 R/W 0x0
Virtual address of read/write
3.11.6.56 0x0194 IOMMU Virtual Address Data Register (Default Value: 0x0000_0000)
Offset: 0x0194 Register Name: IOMMU_VA_DATA _REG
Bit Read/Write Default/Hex Description
VA_DATA
31:0 R/W 0x0
Data corresponding to read/write virtual address
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3.11.6.57 0x0198 IOMMU Virtual Address Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0198 Register Name: IOMMU_VA_CONFIG _REG
Bit Read/Write Default/Hex Description
MODE_SEL
0: Prefetch
31 R/W 0x0
1: Debug Mode
It is used to chose prefetch mode or Debug mode.
31:9 / / /
VA_CONFIG
Virtual Address Configuration
8 R/W 0x0
0: Read operation
1: Write operation
7:1 / / /
VA_CONFIG_START
0: No operation or operation is completed
0 R/WAC 0x0
1: Start
After the operation is completed, the bit can clear automatically.
Read operation process:
a) Write IOMMU_VA_REG[31:0];
b) Write IOMMU_VA_CONFIG_REG[8] to 0;
c) Write IOMMU_VA_CONFIG_REG[0] to 1 to start read-process;
d) Query IOMMU_VA_CONFIG_REG[0] until it is 0;
e) Read IOMMU_VA_DATA_REG[31:0];
Write operation process:
a) Write IOMMU_VA_REG[31:0];
b) Write IOMMU_VA_DATA_REG[31:0];
c) Write IOMMU_VA_CONFIG_REG[8] to 1;
d) Write IOMMU_VA_CONFIG_REG[0] to 1 to start write-process;
e) Query IOMMU_VA_CONFIG_REG[0] until it is 0;
3.11.6.58 0x0200 IOMMU PMU Enable Register (Default Value: 0x0000_0000)
Offset: 0x0200 Register Name: IOMMU_PMU_ENABLE _REG
Bit Read/Write Default/Hex Description
31:1 / / /
0 R/W 0x0 PMU_ENABLE
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Offset: 0x0200 Register Name: IOMMU_PMU_ENABLE _REG
Bit Read/Write Default/Hex Description
0: Disable statistical function
1: Enable statistical function
3.11.6.59 0x0210 IOMMU PMU Clear Register (Default Value: 0x0000_0000)
Offset: 0x0210 Register Name: IOMMU_PMU_CLR _REG
Bit Read/Write Default/Hex Description
31:1 / / /
PMU_CLR
0: No clear operation or clear operation is completed
0 R/WAC 0x0
1: Clear counter data
After the operation is completed, the bit can clear automatically.
3.11.6.60 0x0230 IOMMU PMU Access Low 0 Register (Default Value: 0x0000_0000)
Offset: 0x0230 Register Name: IOMMU_PMU_ACCESS_LOW0_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW0
31:0 R 0x0
Record total number of Micro TLB0 access, lower 32-bit register
3.11.6.61 0x0234 IOMMU PMU Access High 0 Register (Default Value: 0x0000_0000)
Offset: 0x0234 Register Name: IOMMU_PMU_ACCESS_HIGH0_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH0
10:0 R 0x0
Record total number of Micro TLB0 access, higher 11-bit register
3.11.6.62 0x0238 IOMMU PMU Hit Low 0 Register (Default Value: 0x0000_0000)
Offset: 0x0238 Register Name: IOMMU_PMU_HIT_LOW0_REG
Bit Read/Write Default/Hex Description
31:0 R 0x0 PMU_HIT_LOW0
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Offset: 0x0238 Register Name: IOMMU_PMU_HIT_LOW0_REG
Bit Read/Write Default/Hex Description
Record total number of Micro TLB0 hit, lower 32-bit register
3.11.6.63 0x023C IOMMU PMU Hit High 0 Register (Default Value: 0x0000_0000)
Offset: 0x023C Register Name: IOMMU_PMU_HIT_HIGH0_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH0
10:0 R 0x0
Record total number of Micro TLB0 hit, higher 11-bit register
3.11.6.64 0x0240 IOMMU PMU Access Low 1 Register (Default Value: 0x0000_0000)
Offset: 0x0240 Register Name: IOMMU_PMU_ACCESS_LOW1_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW1
31:0 R 0x0
Record total number of Micro TLB1 access, lower 32-bit register
3.11.6.65 0x0244 IOMMU PMU Access High 1 Register (Default Value: 0x0000_0000)
Offset: 0x0244 Register Name: IOMMU_PMU_ACCESS_HIGH1_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH1
10:0 R 0x0
Record total number of Micro TLB1 access, higher 11-bit register
3.11.6.66 0x0248 IOMMU PMU Hit Low 1 Register (Default Value: 0x0000_0000)
Offset: 0x0248 Register Name: IOMMU_PMU_HIT_LOW1_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW1
31:0 R 0x0
Record total number of Micro TLB1 hit, lower 32-bit register
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3.11.6.67 0x024C IOMMU PMU Hit High 1 Register (Default Value: 0x0000_0000)
Offset: 0x024C Register Name: IOMMU_PMU_HIT_HIGH1_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH1
10:0 R 0x0
Record total number of Micro TLB1 hit, higher 11-bit register
3.11.6.68 0x0250 IOMMU PMU Access Low 2 Register (Default Value: 0x0000_0000)
Offset: 0x0250 Register Name: IOMMU_PMU_ACCESS_LOW2_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW2
31:0 R 0x0
Record total number of Micro TLB2 access, lower 32-bit register
3.11.6.69 0x0254 IOMMU PMU Access High 2 Register (Default Value: 0x0000_0000)
Offset: 0x0254 Register Name: IOMMU_PMU_ACCESS_HIGH2_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH2
10:0 R 0x0
Record total number of Micro TLB2 access, higher 11-bit register
3.11.6.70 0x0258 IOMMU PMU Hit Low 2 Register (Default Value: 0x0000_0000)
Offset: 0x0258 Register Name: IOMMU_PMU_HIT_LOW2_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW2
31:0 R 0x0
Record total number of Micro TLB2 hit, lower 32-bit register
3.11.6.71 0x025C IOMMU PMU Hit High 2 Register (Default Value: 0x0000_0000)
Offset: 0x025C Register Name: IOMMU_PMU_HIT_HIGH2_REG
Bit Read/Write Default/Hex Description
31:11 / / /
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Offset: 0x025C Register Name: IOMMU_PMU_HIT_HIGH2_REG
Bit Read/Write Default/Hex Description
PMU_HIT_HIGH2
10:0 R 0x0
Record total number of Micro TLB2 hit, higher 11-bit register
3.11.6.72 0x0260 IOMMU PMU Access Low 3 Register (Default Value: 0x0000_0000)
Offset: 0x0260 Register Name: IOMMU_PMU_ACCESS_LOW3_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW3
31:0 R 0x0
Record total number of Micro TLB3 access, lower 32-bit register
3.11.6.73 0x0264 IOMMU PMU Access High 3 Register (Default Value: 0x0000_0000)
Offset: 0x0264 Register Name: IOMMU_PMU_ACCESS_HIGH3_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH3
10:0 R 0x0
Record total number of Micro TLB3 access, higher 11-bit register
3.11.6.74 0x0268 IOMMU PMU Hit Low 3 Register (Default Value: 0x0000_0000)
Offset: 0x0268 Register Name: IOMMU_PMU_HIT_LOW3_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW3
31:0 R 0x0
Record total number of Micro TLB3 hit, lower 32-bit register
3.11.6.75 0x026C IOMMU PMU Hit High 3 Register (Default Value: 0x0000_0000)
Offset: 0x026C Register Name: IOMMU_PMU_HIT_HIGH3_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH3
10:0 R 0x0
Record total number of Micro TLB3 hit, higher 11-bit register
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3.11.6.76 0x0270 IOMMU PMU Access Low 4 Register (Default Value: 0x0000_0000)
Offset: 0x0270 Register Name: IOMMU_PMU_ACCESS_LOW4_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW4
31:0 R 0x0
Record total number of Micro TLB4 access, lower 32-bit register
3.11.6.77 0x0274 IOMMU PMU Access High 4 Register (Default Value: 0x0000_0000)
Offset: 0x0274 Register Name: IOMMU_PMU_ACCESS_HIGH4_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH4
10:0 R 0x0
Record total number of Micro TLB4 access, higher 11-bit register
3.11.6.78 0x0278 IOMMU PMU Hit Low 4 Register (Default Value: 0x0000_0000)
Offset: 0x0278 Register Name: IOMMU_PMU_HIT_LOW4_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW4
31:0 R 0x0
Record total number of Micro TLB4 hit, lower 32-bit register
3.11.6.79 0x027C IOMMU PMU Hit High 4 Register (Default Value: 0x0000_0000)
Offset: 0x027C Register Name: IOMMU_PMU_HIT_HIGH4_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH4
10:0 R 0x0
Record total number of Micro TLB4 hit, higher 11-bit register
3.11.6.80 0x0280 IOMMU PMU Access Low 5 Register (Default Value: 0x0000_0000)
Offset: 0x0280 Register Name: IOMMU_PMU_ACCESS_LOW5_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW5
31:0 R 0x0
Record total number of Micro TLB5 access, lower 32-bit register
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3.11.6.81 0x0284 IOMMU PMU Access High 5 Register (Default Value: 0x0000_0000)
Offset: 0x0284 Register Name: IOMMU_PMU_ACCESS_HIGH5_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH5
10:0 R 0x0
Record total number of Micro TLB5 access, higher 11-bit register
3.11.6.82 0x0288 IOMMU PMU Hit Low 5 Register (Default Value: 0x0000_0000)
Offset: 0x0288 Register Name: IOMMU_PMU_HIT_LOW5_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW5
31:0 R 0x0
Record total number of Micro TLB5 hit, lower 32-bit register
3.11.6.83 0x028C IOMMU PMU Hit High 5 Register (Default Value: 0x0000_0000)
Offset: 0x028C Register Name: IOMMU_PMU_HIT_HIGH5_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH5
10:0 R 0x0
Record total number of Micro TLB5 hit, higher 11-bit register
3.11.6.84 0x0290 IOMMU PMU Access Low 6 Register (Default Value: 0x0000_0000)
Offset: 0x0290 Register Name: IOMMU_PMU_ACCESS_LOW6_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW6
31:0 R 0x0 Record total number of Micro TLB6 access, lower 32-bit register
Note: The field is not used.
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3.11.6.85 0x0294 IOMMU PMU Access High 6 Register (Default Value: 0x0000_0000)
Offset: 0x0294 Register Name: IOMMU_PMU_ACCESS_HIGH6_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH6
10:0 R 0x0 Record total number of Micro TLB6 access, higher 11-bit register
Note: The field is not used.
3.11.6.86 0x0298 IOMMU PMU Hit Low 6 Register (Default Value: 0x0000_0000)
Offset: 0x0298 Register Name: IOMMU_PMU_HIT_LOW6_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW6
31:0 R 0x0 Record total number of Micro TLB6 hit, lower 32-bit register
Note: The field is not used.
3.11.6.87 0x029C IOMMU PMU Hit High 6 Register (Default Value: 0x0000_0000)
Offset: 0x029C Register Name: IOMMU_PMU_HIT_HIGH6_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH6
10:0 R 0x0 Record total number of Micro TLB6 hit, higher 11-bit register
Note: The field is not used.
3.11.6.88 0x02D0 IOMMU PMU Access Low 7 Register (Default Value: 0x0000_0000)
Offset: 0x02D0 Register Name: IOMMU_PMU_ACCESS_LOW7_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW7
31:0 R 0x0
Record total number of Micro TLB7 access, lower 32-bit register
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3.11.6.89 0x02D4 IOMMU PMU Access High 7 Register (Default Value: 0x0000_0000)
Offset: 0x02D4 Register Name: IOMMU_PMU_ACCESS_HIGH7_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_ACCESS_HIGH7
10:0 R 0x0
Record total number of Micro TLB7 access, higher 11-bit register
3.11.6.90 0x02D8 IOMMU PMU Hit Low 7 Register (Default Value: 0x0000_0000)
Offset: 0x02D8 Register Name: IOMMU_PMU_HIT_LOW7_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW7
31:0 R 0x0
Record total number of Micro TLB7 hit, lower 32-bit register
3.11.6.91 0x02DC IOMMU PMU Hit High 7 Register (Default Value: 0x0000_0000)
Offset: 0x02DC Register Name: IOMMU_PMU_HIT_HIGH7_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH7
10:0 R 0x0
Record total number of Micro TLB7 hit, higher 11-bit register
3.11.6.92 0x02E0 IOMMU PMU Access Low 8 Register (Default Value: 0x0000_0000)
Offset: 0x02E0 Register Name: IOMMU_PMU_ACCESS_LOW8_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_LOW8
31:0 R 0x0
Record total number of PTW Cache access, lower 32-bit register
3.11.6.93 0x02E4 IOMMU PMU Access High 8 Register (Default Value: 0x0000_0000)
Offset: 0x02E4 Register Name: IOMMU_PMU_ACCESS_HIGH8_REG
Bit Read/Write Default/Hex Description
31:11 / / /
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Offset: 0x02E4 Register Name: IOMMU_PMU_ACCESS_HIGH8_REG
Bit Read/Write Default/Hex Description
PMU_ACCESS_HIGH8
10:0 R 0x0
Record total number of PTW Cache access, higher 11-bit register
3.11.6.94 0x02E8 IOMMU PMU Hit Low 8 Register (Default Value: 0x0000_0000)
Offset: 0x02E8 Register Name: IOMMU_PMU_HIT_LOW8_REG
Bit Read/Write Default/Hex Description
PMU_HIT_LOW8
31:0 R 0x0
Record total number of PTW Cache hit, lower 32-bit register
3.11.6.95 0x02EC IOMMU PMU Hit High 8 Register (Default Value: 0x0000_0000)
Offset: 0x02EC Register Name: IOMMU_PMU_HIT_HIGH8_REG
Bit Read/Write Default/Hex Description
31:11 / / /
PMU_HIT_HIGH8
10:0 R 0x0
Record total number of PTW Cache hit, higher 11-bit register
3.11.6.96 0x0300 IOMMU Total Latency Low 0 Register (Default Value: 0x0000_0000)
Offset: 0x0300 Register Name: IOMMU_PMU_TL_LOW0_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW0
31:0 R 0x0
Record total latency of Master0, lower 32-bit register
3.11.6.97 0x0304 IOMMU Total Latency High 0 Register (Default Value: 0x0000_0000)
Offset: 0x0304 Register Name: IOMMU_PMU_TL_HIGH0_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH0
17:0 R 0x0
Record total latency of Master0, higher 18-bit register
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3.11.6.98 0x0308 IOMMU Max Latency 0 Register (Default Value: 0x0000_0000)
Offset: 0x0308 Register Name: IOMMU_PMU_ML0_REG
Bit Read/Write Default/Hex Description
PMU_ML0
31:0 R 0x0
Record the max latency of Master0.
3.11.6.99 0x0310 IOMMU Total Latency Low 1 Register (Default Value: 0x0000_0000)
Offset: 0x0310 Register Name: IOMMU_PMU_TL_LOW1_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW1
31:0 R 0x0
Record total latency of Master1, lower 32-bit register
3.11.6.100 0x0314 IOMMU Total Latency High 1 Register (Default Value: 0x0000_0000)
Offset: 0x0314 Register Name: IOMMU_PMU_TL_HIGH1_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH1
17:0 R 0x0
Record total latency of Master1, higher 18-bit register
3.11.6.101 0x0318 IOMMU Max Latency 1 Register (Default Value: 0x0000_0000)
Offset: 0x0318 Register Name: IOMMU_PMU_ML1_REG
Bit Read/Write Default/Hex Description
PMU_ML1
31:0 R 0x0
Record the max latency of Master1.
3.11.6.102 0x0320 IOMMU Total Latency Low 2 Register (Default Value: 0x0000_0000)
Offset: 0x0320 Register Name: IOMMU_PMU_TL_LOW2_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW2
31:0 R 0x0
Record total latency of Master2, lower 32-bit register
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3.11.6.103 0x0324 IOMMU Total Latency High 2 Register (Default Value: 0x0000_0000)
Offset: 0x0324 Register Name: IOMMU_PMU_TL_HIGH2_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH2
17:0 R 0x0
Record total latency of Master2, higher 18-bit register
3.11.6.104 0x0328 IOMMU Max Latency 2 Register (Default Value: 0x0000_0000)
Offset: 0x0328 Register Name: IOMMU_PMU_ML2_REG
Bit Read/Write Default/Hex Description
PMU_ML2
31:0 R 0x0
Record the max latency of Master2.
3.11.6.105 0x0330 IOMMU Total Latency Low 3 Register (Default Value: 0x0000_0000)
Offset: 0x0330 Register Name: IOMMU_PMU_TL_LOW3_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW3
31:0 R 0x0
Record total latency of Master3, lower 32-bit register
3.11.6.106 0x0334 IOMMU Total Latency High 3 Register (Default Value: 0x0000_0000)
Offset: 0x0334 Register Name: IOMMU_PMU_TL_HIGH3_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH3
17:0 R 0x0
Record total latency of Master3, higher 18-bit register
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3.11.6.107 0x0338 IOMMU Max Latency 3 Register (Default Value: 0x0000_0000)
Offset: 0x0338 Register Name: IOMMU_PMU_ML3_REG
Bit Read/Write Default/Hex Description
PMU_ML3
31:0 R 0x0
Record the max latency of Master3.
3.11.6.108 0x0340 IOMMU Total Latency Low 4 Register (Default Value: 0x0000_0000)
Offset: 0x0340 Register Name: IOMMU_PMU_TL_LOW4_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW4
31:0 R 0x0
Record total latency of Master4, lower 32-bit register
3.11.6.109 0x0344 IOMMU Total Latency High 4 Register (Default Value: 0x0000_0000)
Offset: 0x0344 Register Name: IOMMU_PMU_TL_HIGH4_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH4
17:0 R 0x0
Record total latency of Master4, higher 18-bit register
3.11.6.110 0x0348 IOMMU Max Latency 4 Register (Default Value: 0x0000_0000)
Offset: 0x0348 Register Name: IOMMU_PMU_ML4_REG
Bit Read/Write Default/Hex Description
PMU_ML4
31:0 R 0x0
Record the max latency of Master4.
3.11.6.111 0x0350 IOMMU Total Latency Low 5 Register (Default Value: 0x0000_0000)
Offset: 0x0350 Register Name: IOMMU_PMU_TL_LOW5_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW5
31:0 R 0x0
Record total latency of Master5, lower 32-bit register
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3.11.6.112 0x0354 IOMMU Total Latency High 5 Register (Default Value: 0x0000_0000)
Offset: 0x0354 Register Name: IOMMU_PMU_TL_HIGH5_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH5
17:0 R 0x0
Record total latency of Master5, higher 18-bit register
3.11.6.113 0x0358 IOMMU Max Latency 5 Register (Default Value: 0x0000_0000)
Offset: 0x0358 Register Name: IOMMU_PMU_ML5_REG
Bit Read/Write Default/Hex Description
PMU_ML5
31:0 R 0x0
Record the max latency of Master5.
3.11.6.114 0x0360 IOMMU Total Latency Low 6 Register (Default Value: 0x0000_0000)
Offset: 0x0360 Register Name: IOMMU_PMU_TL_LOW6_REG
Bit Read/Write Default/Hex Description
PMU_TL_LOW6
31:0 R 0x0 Record total latency of Master6, lower 32-bit register
Note: The field is not used.
3.11.6.115 0x0364 IOMMU Total Latency High 6 Register (Default Value: 0x0000_0000)
Offset: 0x0364 Register Name: IOMMU_PMU_TL_HIGH6_REG
Bit Read/Write Default/Hex Description
31:18 / / /
PMU_TL_HIGH6
17:0 R 0x0 Record total latency of Master6, higher 18-bit register
Note: The field is not used.
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3.11.6.116 0x0368 IOMMU Max Latency 6 Register (Default Value: 0x0000_0000)
Offset: 0x0368 Register Name: IOMMU_PMU_ML6_REG
Bit Read/Write Default/Hex Description
PMU_ML6
31:0 R 0x0 Record the max latency of Master6.
Note: The field is not used.
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3.12 RTC
3.12.1 Overview
The Real Time Clock (RTC) is used to implement time counter and timing wakeup functions. The RTC can display
the year, month, day, week, hour, minute, second in real time. The RTC has the independent power to continue
to work in system power-off.
The RTC has the following features:
Provides a 16-bit counter for counting day, 5-bit counter for counting hour, 6-bit counter for counting
minute, 6-bit counter for counting second
External connect a 32.768 kHz low-frequency oscillator for count clock
Timer frequency is 1 kHz
Configurable initial value by software anytime
Supports timing alarm, and generates interrupt and wakeup the external devices
Eight 32-bit user registers for storing power-off information
CAUTION
The register configuration of RTC is AHB bus, it only can support word operation, not byte operation and half-
word operation.
3.12.2 Block Diagram
The following figure shows the block diagram of the RTC.
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Figure 3-34 RTC Block Diagram
VCC_PLL Domain(1.8V)
PLL_TOP
DCXO_CLK24M
1.8V
Analog_rtc_dcxo
Rc16m
Clk24m
32K XTAL Clk32k
DCXO 0.9V
RC16M
RTCVIO SPI
POR LDO 0.9V RTC 0.9V RTC SYSCPUS
Timer Logic Interface
GPIO
P_RESETB
P_NMI
P_TEST
P_CLK32K_FANOUT
VCC_RTC Domain(1.8V) RTCVIO Domain(0.8V) VDD_SYS Domain(0.9V)
3.12.3 Functional Description
3.12.3.1 External Signals
Table 3-16 RTC External Signals
Signal Description
X32KIN 32.768 kHz oscillator input
X32KOUT 32.768 kHz oscillator output
VCC-RTC RTC high voltage, generated via external power
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3.12.3.2 Typical Application
Figure 3-35 RTC Application Diagram
AHBS1
SYSRTC_TOP
RTC_TOP_REG
SPI_MST
VDD_CPUS
X32KIN SPI_SLV
32K
crystal X32KOUT VCC-RTC
RTC VCC-RTC
DXIN
24M
crystal DXOUT
Alarm0_irq
3.12.3.3 Clock Tree
The following figure shows the clock tree of the RTC.
Figure 3-36 RTC Clock Tree
CLK16M_RC_EN
LOSC_SRC_SEL
16M RC /32 /N 0
CLK32K
SYSTEM
EXT LOSC 1
RTC_SRC_SEL
0
/32 RTC
EXT_LOSC_EN
1
Debounce circuit
LOSC_OUT_SRC_SEL
00 RTC_32K_FANOUT
01 PAD
DCXO 24MDIV32K 10
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LOSC
The LOSC has 2 clock sources: internal RC, external low frequency crystal. The LOSC selects the internal RC by
default, when the system starts, the LOSC can select by software the external low frequency crystal to provide
much accuracy clock. The clock accurate of the LOSC is related to the accurate of the external low frequency
crystal. Usually select 32.768 kHz crystal with ±20 ppm frequency tolerance. When using internal RC, the clock
can be changed by changing division ratio. When using external clock, the clock cannot be changed.
RTC
The clock sources of RTC can be selected by related switches, including 32K divided by internal 16 MHz RC, 32K
divided by external DCXO, and external 32.768 kHz crystal.
System 32K
The clock sources of system 32K are from external 32.768 kHz crystal and 32K divided by the internal 16 MHz
RC.
RTC_32K_FANOUT
The clock source of RTC_32K_FANOUT can select CLK32K, external 32.768 kHz crystal or 32K divided by external
DCXO.
3.12.3.4 Real Time Clock
Figure 3-37 RTC Counter
Clock
1K Counter 3FA 3FB 3FC 3FD 3FE 3FF 0000 0001 0002 0003 0004 0005
Second
The 1K counter adds 1 on each rising edge of the clock. When the clock number reaches 0x3FF, 1K counter
starts to count again from 0, and the second counter adds 1. The step structure of 1 kHz counter is as follows.
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Figure 3-38 RTC 1 kHz Counter Step Structure
Clock
1K
counter
Second Minute Hour Day
According to above implementation, the changing range of each counter is as follows.
Table 3-17 RTC Counter Changing Range
Counter Range
Second 0 to 59
Minute 0 to 59
Hour 0 to 23
Day 0 to 65535 (The year, month, day need be transformed by software according to
day counter)
CAUTION
Because there is no error correction mechanism in the hardware, note that each counter configuration should
not exceed a reasonable counting range.
3.12.3.5 Alarm 0
The principle of alarm0 is a comparator. When RTC timer reaches the scheduled time, the RTC generates the
interrupt, or outputs low level signal by NMI pin to wakeup power management chip.
The RTC only generates one interrupt when RTC timer reached the scheduled day, hour, minute and second
counter, then the RTC needs to be set a new scheduled time, the next interrupt can be generated.
3.12.3.6 Power-off Information Storage
The RTC provides eight 32-bit general purpose register to store power-off information.
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Because VCC-RTC always holds non-power-off state after VCC-RTC cold starts, when the system is in shutdown
or standby scene, the CPU can judge software process by the storing information.
3.12.3.7 RTC_VIO
The RTC module has a LDO, the input source of the LDO is VCC_RTC, the output of the LDO is RTC_VIO, the
value of RTC_VIO is adjustable, the RTC_VIO is mainly used for internal digital logic.
3.12.3.8 RC Calibration Usage Scenario
Power-on: Select non-accurate 32K divided by internal RC.
Normal scenario: Select external accurate 32K, or external calibrated 32K.
Standby or power-off scenario: Select external accurate 32K, or external calibrated 32K.
3.12.4 Programming Guidelines
3.12.4.1 RTC Clock Control
Step 1 Select clock source: Select clock source by the bit0 of LOSC_CTRL_REG, the clock source is the internal
RC oscillator by default. When the system starts, the clock source can be switched to the external 32K
oscillator by software.
Step 2 Auto switch: After enabled the bit[15:14] of LOSC_CTRL_REG, the RTC automatically switches clock
source to the internal oscillator when the external crystal could not output waveform, the switch
status can query by the bit[1] of LOSC_AUTO_SWT_STA_REG.
NOTE
If only configuring the bit[15] of LOSC_CTRL_REG, the clock source status bit cannot be changed after the auto
switch is valid, because the two functions are independent.
Here is the basic code samples.
Write (0x16aa4000,LOSC_Ctrl); //Write key field
Write (0x16aa4001,LOSC_Ctrl); //Select the external 32K clock
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3.12.4.2 RTC Calendar
Step 1 Write time initial value: Write the current time to RTC_DAY_REG and RTC_HH_MM_SS_REG.
Step 2 After updated time, the RTC restarts to count again. The software can read the current time anytime.
NOTE
The RTC can only provide day counter, so the current day counter need be converted to year, month, day
and week by software.
Ensure the bit[8:7] of LOSC_CTRL_REG is 0 before the next time configuration is performed.
Here is the basic code samples.
For example: set time to 21st, 07:08:09 and read it.
RTC_DAY_REG = 0x00000015;
RTC_HH_MM_SS_REG = 0x00070809; //0000 0000 000|0 0000(Hour) 00|00 0000(Minute) 00|00 0000(Second)
Read (RTC_DAY_REG);
Read (RTC_HH_MM_SS_REG);
3.12.4.3 Alarm0
Step 1 Enable alram0 interrupt by writing ALARM0_IRQ_EN.
Step 2 Set the counter comparator, write the count-down day, hour, minute, second number to
ALARM0_DAY_SET_REG and ALARM0_HH-MM-SS_SET_REG.
Step 3 Enable alarm0 function by writing ALARM0_ENABLE_REG, then the software can query alarm count
value in real time by ALARM0_DAY_SET_REG and ALARM0_HH-MM-SS_SET_REG. When the setting
time reaches, ALARM0_IRQ_STA_REG is set to 1 to generate interrupt.
Step 4 After enter the interrupt process, write ALARM0_IRQ_STA_REG to clear the interrupt pending, and
execute the interrupt process.
Step 5 Resume the interrupt and continue to execute the interrupted process.
Step 6 The power-off wakeup is generated via SoC hardware and PMIC, the software only needs to set the
pending condition of alarm0, and set ALARM_CONFIG_REG to 1.
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3.12.5 Register List
Module Name Base Address
RTC 0x07090000
Register Name Offset Description
LOSC_CTRL_REG 0x0000 Low Oscillator Control Register
LOSC_AUTO_SWT_STA_REG 0x0004 LOSC Auto Switch Status Register
INTOSC_CLK_PRESCAL_REG 0x0008 Internal OSC Clock Pre-scalar Register
RTC_DAY_REG 0x0010 RTC Year-Month-Day Register
RTC_HH_MM_SS_REG 0x0014 RTC Hour-Minute-Second Register
ALARM0_DAY_SET_REG 0x0020 Alarm 0 Day Setting Register
ALARM0_CUR_VLU_REG 0x0024 Alarm 0 Counter Current Value Register
ALARM0_ENABLE_REG 0x0028 Alarm 0 Enable Register
ALARM0_IRQ_EN 0x002C Alarm 0 IRQ Enable Register
ALARM0_IRQ_STA_REG 0x0030 Alarm 0 IRQ Status Register
ALARM_CONFIG_REG 0x0050 Alarm Configuration Register
32K_FOUT_CTRL_GATING_REG 0x0060 32K Fanout Control Gating Register
GP_DATA_REG 0x0100 + N*0x04 General Purpose Register (N=0 to 7)
FBOOT_INFO_REG0 0x0120 Fast Boot Information Register0
FBOOT_INFO_REG1 0x0124 Fast Boot Information Register1
DCXO_CTRL_REG 0x0160 DCXO Control Register
RTC_VIO_REG 0x0190 RTC_VIO Regulation Register
IC_CHARA_REG 0x01F0 IC Characteristic Register
VDD_OFF_GATING_CTRL_REG 0x01F4 VDD Off Gating Control Register
Efuse High Voltage Power Switch Control
EFUSE_HV_PWRSWT_CTRL_REG 0x0204 Register
RTC_SPI_CLK_CTRL_REG 0x0310 RTC SPI Clock Control Register
NOTE
The offset addresses less than 0x0300 are in VDD_RTC power domain, and the offset addresses large than or
equal to 0x300 are in VDD_SYS power domain.
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3.12.6 Register Description
3.12.6.1 0x0000 LOSC Control Register (Default Value: 0x0000_4010)
Offset:0x0000 Register Name: LOSC_CTRL_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 W 0x0
This field should be filled with 0x16AA, and then the bit0 and
bit1 can be written with the new value.
LOSC_AUTO_SWT_FUNCTION
LOSC auto switch function disable
15 R/W 0x0
0: Enable
1: Disable
LOSC_AUTO_SWT_32K_SEL_EN
LOSC auto switch 32K clk source select enable
0: Disable. When the losc losts, the 32k clk source will not
14 R/W 0x1
change to RC
1: Enable. When the losc losts, the 32k clk source will change
to RC (LOSC_SRC_SEL will be changed from 1 to 0)
13:9 / / /
RTC_HHMMSS_ACCE
RTC Hour Minute Second access
After writing the RTC HH-MM-SS Register, this bit is set and it
8 R/W 0x0 will be cleared until the real writing operation is finished.
After writing the RTC HH-MM-SS Register, the RTC HH-MM-SS
Register will be refreshed for at most one second.
Note: Make sure that the bit is 0 for time configuration.
RTC_DAY_ACCE
RTC DAY access
After writing the RTC DAY register, this bit is set and it will be
7 R/W 0x0 cleared until the real writing operation is finished.
After writing the RTC DAY register, the DAY register will be
refreshed for at most one second.
Note: Make sure that the bit is 0 for time configuration.
6:5 / / /
EXT_LOSC_EN
4 R/W 0x1
External 32.768 kHz Crystal Enable
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Offset:0x0000 Register Name: LOSC_CTRL_REG
Bit Read/Write Default/Hex Description
0: Disable
1: Enable
EXT_LOSC_GSM
External 32.768 kHz Crystal GSM
00: Low
01: /
10: /
11: High
When GSM is changed, the 32K oscillation circuit will arise
3:2 R/W 0x0 transient instability. If the autoswitch function (bit 15) is
enabled, 32K changes to RC16M with certain probability. The
GSM can influence the time of 32K starting oscillation, the
more the GSM, the shorter the time of starting oscillation. So
modifying GSM is not recommended.
If you need to modify the GSM, firstly disable the auto switch
function (bit 15), with a delay of 50 us, then change the GSM,
the 32K clock source is changed to external clock.
RTC_SRC_SEL
RTC_TIMER Clock Source Select
0: LOSC_SRC
1 R/W 0x0 1: 24MDIV32K
Before switching the bit, make sure that the 24MDIV32K
function is enabled, that is, the bit16 of the 32K Fanout Control
Register is 1.
LOSC_SRC_SEL
LOSC Clock Source Select
0 R/W 0x0
0: Low frequency clock from 16M RC
1: External 32.768 kHz OSC
NOTE
If the bit[8:7] of LOSC_CTRL_REG is set, the RTC HH-MM-SS, DD and ALARM DD-HH-MM-SS register cannot be
written.
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3.12.6.2 0x0004 LOSC Auto Switch Status Register (Default Value: 0x0000_0000)
Offset:0x0004 Register Name: LOSC_AUTO_SWT_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
EXT_LOSC_STA
Work only when the auto switch function is enabled.
2 R 0x0
0: External 32.768 kHz OSC work normally
1: External 32.768 kHz OSC work abnormally
LOSC_AUTO_SWT_PEND
LOSC auto switch pending
0: No effect
1 R/W1C 0x0
1: Auto switch pending, it means LOSC_SRC_SEL is changed
from 1 to 0.
Setting 1 to this bit will clear it.
LOSC_SRC_SEL_STA
Checking LOSC clock source status
0 R 0x0
0: Low frequency clock from 16M RC
1: External 32.768 kHz OSC
3.12.6.3 0x0008 Internal OSC Clock Prescalar Register (Default Value: 0x0000_000F)
Offset:0x0008 Register Name: INTOSC_CLK_PRESCAL_REG
Bit Read/Write Default/Hex Description
31:5 / / /
INTOSC_32K_CLK_PRESCAL
Internal OSC 32K Clock Prescalar value N.
The clock output = Internal RC/32/N.
00000: 1
4:0 R/W 0xF
00001: 2
00002: 3
............
11111: 32
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3.12.6.4 0x0010 RTC Year-Month-DAY Register (Default Value: UDF)
Offset:0x0010 Register Name: RTC_DAY_REG
Bit Read/Write Default/Hex Description
31:16 / / /
DAY
15:0 R/W UDF Set Day
Range from 0 to 65535.
3.12.6.5 0x0014 RTC Hour-Minute-Second Register (Default Value: UDF)
Offset:0x0014 Register Name: RTC_HH_MM_SS_REG
Bit Read/Write Default/Hex Description
31:21 / / /
HOUR
20:16 R/W UDF Set hour
Range from 0 to 23.
15:14 / / /
MINUTE
13:8 R/W UDF Set minute
Range from 0 to 59.
7:6 / / /
SECOND
5:0 R/W UDF Set second
Range from 0 to 59.
3.12.6.6 0x0020 Alarm 0 Day Setting Register (Default Value: 0x0000_0000)
Offset:0x0020 Register Name: ALARM0_DAY_SET_REG
Bit Read/Write Default/Hex Description
31:16 / / /
ALARM0_COUNTER
15:0 R/W 0x0
Alarm 0 Counter is based on Day.
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3.12.6.7 0x0024 Alarm 0 Counter Current Value Register (Default Value: UDF)
Offset:0x0024 Register Name: ALARM0_CUR_VLU_REG
Bit Read/Write Default/Hex Description
31:21 / / /
HOUR
20:16 R/W UDF Current hour
Range from 0 to 23.
15:14 / / /
MINUTE
13:8 R/W UDF Current minute
Range from 0 to 59.
7:6 / / /
SECOND
5:0 R/W UDF Current second
Range from 0 to 59.
3.12.6.8 0x0028 Alarm 0 Enable Register (Default Value: 0x0000_0000)
Offset:0x0028 Register Name: ALARM0_ENABLE_REG
Bit Read/Write Default/Hex Description
31:1 / / /
ALM_0_EN
Alarm 0 Enable
0 R/W 0x0
0: Disable
1: Enable
3.12.6.9 0x002C Alarm 0 IRQ Enable Register (Default Value: 0x0000_0000)
Offset:0x002C Register Name: ALARM0_IRQ_EN
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM0_IRQ_EN
Alarm 0 IRQ Enable
0 R/W 0x0
0: Disable
1: Enable
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3.12.6.10 0x0030 Alarm 0 IRQ Status Register (Default Value: 0x0000_0000)
Offset:0x0030 Register Name: ALARM0_IRQ_STA_REG
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM0_IRQ_PEND
Alarm 0 IRQ Pending bit
0: No effect
0 R/W1C 0x0
1: Pending, alarm 0 counter value is reached
If alarm 0 irq enable is set to 1, the pending bit will be sent to
the interrupt controller.
3.12.6.11 0x0050 Alarm Configuration Register (Default Value: 0x0000_0000)
Offset:0x0050 Register Name: ALARM_CONFIG_REG
Bit Read/Write Default/Hex Description
31:1 / / /
ALARM_WAKEUP
Configuration of alarm wake up output.
0 R/W 0x0
0: Disable alarm wake up output
1: Enable alarm wake up output
3.12.6.12 0x0060 32K Fanout Control Gating Register (Default Value: 0x0000_0000)
Offset:0x0060 Register Name: 32K_FOUT_CTRL_GATING_REG
Bit Read/Write Default/Hex Description
31:17 / / /
HOSC_TO_32K_DIVIDER_ENABLE
HOSC to 32k divider enable
16 R/W 0x0
0: Disable the hosc 24M to 32K divider circuit
1: Enable the hosc 24M to 32K divider circuit
15:3 / / /
LOSC_OUT_SRC_SEL
LOSC output source select
2:1 R/W 0x0 00: RTC_32K (select by RC_CLK_SRC_SEL & LOSC_SRC_SEL)
01: LOSC
10: HOSC divided 32K
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Offset:0x0060 Register Name: 32K_FOUT_CTRL_GATING_REG
Bit Read/Write Default/Hex Description
32K_FANOUT_GATING
LOSC out gating enable
Configuration of LOSC output, and there is no LOSC output by
0 R/W 0x0
default.
0: Mask LOSC output gating
1: Enable LOSC output gating
3.12.6.13 0x0100+N*0x0004 General Purpose Register (Default Value: 0x0000_0000)
Offset:0x0100+N*0x0004 (N=0 to 7) Register Name: GP_DATA_REGN
Bit Read/Write Default/Hex Description
GP_DATA
31:0 R/W 0x0
Data [31:0]
NOTE
General purpose register 0 to 7 value can be stored if the RTC-VIO is larger than 0.7 V.
3.12.6.14 0x0120 Fast Boot Information Register0 (Default Value: 0x0000_0000)
Offset:0x0120 Register Name: FBOOT_INFO_REG0
Bit Read/Write Default/Hex Description
FBOOT_INFO0
31:0 R/W 0x0 Fast Boot info
Fast Boot Information 0, refer to BROM spec.
3.12.6.15 0x0124 Fast Boot Information Register1 (Default Value: 0x0000_0000)
Offset:0x0124 Register Name: FBOOT_INFO_REG1
Bit Read/Write Default/Hex Description
FBOOT_INFO1
31:0 R/W 0x0 Fast Boot info
Fast Boot Information 1, refer to BROM spec.
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3.12.6.16 0x0160 DCXO Control Register (Default Value: 0x883F_10F7)
Offset:0x0160 Register Name: DCXO_CTRL_REG
Bit Read/Write Default/Hex Description
CLK_REQ_ENB
Clock REQ enable
31 R/W 0x1
0: Enable DCXO wake up function
1: Disable DCXO wake up function
30:28 / / /
DCXO_ICTRL
27:24 R/W 0x8
DCXO current control value
23 / / /
DCXO_TRIM
22:16 R/W 0x3F DCXO cap array value
The capacity cell is 55 fF.
15:13 / / /
DCXO_BG
12:8 R/W 0x10
DCXO bandgap output voltage
DCXO_LDO_INRUSHB
7 R/W 0x1
DCXO LDO driving capacity signal, active high
XTAL_MODE
Xtal mode enable signal, active high
6 R/W 0x1
0: For external clk input mode
1: For normal mode
DCXO_RFCLK_ENHANCE
DCXO rfclk enhance
5:4 R/W 0x3
Enhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5
pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF.
3 / / /
RSTO_DLY_SEL
2 R/W 0x1 For Debug Use Only.
It cannot configure to 0 in normal state.
DCXO_EN
DCXO enable
1 R/W 0x1
1: Enable
0: Disable
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Offset:0x0160 Register Name: DCXO_CTRL_REG
Bit Read/Write Default/Hex Description
CLK16M_RC_EN
1: Enable
0: Disable
The related register configuration is necessary to ensure the
reset debounce circuit has a stable clock source.
The first time SoC starts up, by default, the reset debounce
0 R/W 0x1 circuit of SoC uses 32K divided by RC16M. In power-off,
software reads the related bit to ensure whether EXT32K is
working normally, if it is normal, first switch the clock source
of debounce circuit to EXT32K, then close RC16M.
Without EXT32K scenario or external RTC scenario, software
confirms firstly whether EXT32K is working normally before
switching, or software does not close RC16M.
3.12.6.17 0x0190 RTC_VIO Regulation Register (Default Value: 0x0000_0004)
Offset:0x0190 Register Name:RTC_VIO_REG
Bit Read/Write Default/Hex Description
31:5 / / /
V_SEL
VDD Select
4 R/W 0x0
0: Resistance divider
1: Band gap
3 / / /
RTC_VIO_REGU
RTC_VIO Voltage Select
The RTC-VIO is provided power for RTC digital part.
These bits are useful for regulating the RTC_VIO from 0.65 V to
1.3 V.
000: 1.0 V
2:0 R/W 0x4 001: 0.65 V (the configuration can cause RTC reset)
010: 0.7 V
011: 0.8 V
100: 0.9 V
101: 1.1 V
110: 1.2 V
111: 1.3 V
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3.12.6.18 0x01F0 IC Characteristic Register (Default Value: 0x0000_0000)
Offset:0x01F0 Register Name: IC_CHARA_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 R/W 0x0
The field should be written as 0x16AA. Writing any other value
in this field aborts the write-operation.
ID_DATA
15:0 R/W 0x0 Return 0x16AA only if the KEY_FIELD is set as 0x16AA when
read those bits, otherwise return 0x0.
3.12.6.19 0x01F4 VDD Off Gating Control Register (Default Value: 0x0000_0021)
Offset:0x01F4 Register Name: VDD_OFF_GATING_CTRL_REG
Bit Read/Write Default/Hex Description
KEY_FIELD
Key Field
31:16 W 0x0
This field should be filled with 0x16AA, and then the bit 15 can
be configured.
PWROFF_GAT_RTC_CFG (For Debug Use Only)
Power off gating control signal
15 WAC 0x0
When use vdd_sys to RTC isolation software control, write this
bit to 1. It will only be cleared by resetb release.
14:12 / / /
VCCIO_DET_SPARE
Bit[7:5]: Reserved, default=0
Bit[4]: Bypass debounce circuit, defaule=0
Bit[3]: Enable control, defaule=0
0: Disable VCC-IO detection
11:4 R/W 0x2 1: Force the detection output
Bit[2:0]: Gear adjustment
000: Detection threshold is 2.5 V
001: Detection threshold is 2.6 V
010: Detection threshold is 2.7 V (default)
011: Detection threshold is 2.8 V
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Offset:0x01F4 Register Name: VDD_OFF_GATING_CTRL_REG
Bit Read/Write Default/Hex Description
100: Detection threshold is 2.9 V
101: Detection threshold is 3 V
110: N/A
111: N/A
3:1 / / /
VCCIO_DET_BYPASS_EN
0 R/W 0x1 0: not bypass
1: bypass
3.12.6.20 0x0204 Efuse High Voltage Power Switch Control Register (Default Value: 0x0000_0000)
Offset:0x0204 Register Name: EFUSE_HV_PWRSWT_CTRL_REG
Bit Read/Write Default/Hex Description
31:1 / / /
EFUSE_1.8V_POWER_SWITCH_CONTROL
0 R/W 0x0 1: Open power switch
0: Close power switch
3.12.6.21 0x0310 RTC SPI Clock Control Register (Default Value: 0x0000_0009)
Offset:0x0310 Register Name: RTC_SPI_CLK_CTRL_REG
Bit Read/Write Default/Hex Description
RTC Reg CFG SPI Clock Gating
0: Gating
1: Not Gating
Before configurating RTC register, the clock divider of SPI
31 R/W 0x0
needs be configured firstly, then clock gating needs be
enabled.
Note: Frequency division and clock gating can not be set at
the same time.
30:5 / / /
RTC Reg CFG SPI Clock Divider: M
Actual SPI Clock = AHBS1/(M+1), (0 to 15)
4:0 R/W 0x9
The default frequency of AHBS1 is 200 MHz, and the default
frequency of SPI Clock is 20 MHz.
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Offset:0x0310 Register Name: RTC_SPI_CLK_CTRL_REG
Bit Read/Write Default/Hex Description
Note: The SPI clock can not exceed 50 MHz, or else the RTC
register may be abnormal.
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Contents
4 Video and Graphics ................................................................................................................................................. 354
4.1 DE .................................................................................................................................................................... 354
4.2 DI ..................................................................................................................................................................... 356
4.3 G2D.................................................................................................................................................................. 357
4.4 Video Decoding ............................................................................................................................................... 358
4.4.1 Overview ............................................................................................................................................. 358
4.4.2 Block Diagram ..................................................................................................................................... 359
4.5 Video Encoding ............................................................................................................................................... 360
4.5.1 Overview ............................................................................................................................................. 360
4.5.2 Block Diagram ..................................................................................................................................... 360
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Figures
Figure 4-1 DE Block Diagram ............................................................................................................................................. 355
Figure 4-2 Video Decoding Block Diagram ........................................................................................................................ 359
Figure 4-3 JPGE Block Diagram ......................................................................................................................................... 361
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4 Video and Graphics
4.1 DE
The Display Engine (DE) is a hardware composer to transfer image layers from a local bus or a video buffer to
the LCD interface. The DE supports four overlay windows to blend, and supports image post-processing in the
video channel. The block diagram of DE is shown in Figure 4-1.
The DE has the following features:
Output size up to 2048 x 2048
Four alpha blending channels for main display, three channels for aux display
Four overlay layers in each channel, and has a independent scaler
Potter-duff compatible blending operation
Supports input format Semi-planar YUV422/YUV420/YUV411 and Planar YUV422/YUV420/YUV411,
ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565/palette
Supports SmartColor2.0 for excellent display experience
- Adaptive detail/edge enhancement
- Adaptive color enhancement
- Adaptive contrast enhancement and fresh tone rectify
Supports write back for aux display
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Figure 4-1 DE Block Diagram
DE
TCON0
RT-Mixer 0
MUX
M RT-Mixer 1
B TCON1
U
S
Write-Back
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4.2 DI
The De-interlacer (DI) converts the interlaced input video frame to progressive video frame.
The DI has the following features:
Supports YUV420 (Planar/NV12/NV21) and YUV422 (Planar/NV16/NV61) data format
Supports video resolution from 32x32 to 2048x1280 pixel
Supports Inter-field interpolation/motion adaptive de-interlace method
Performance: module clock 600M for 1080p@60Hz YUV420
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4.3 G2D
The Graphic 2D (G2D) engine is hardware accelerator for 2D graphic.
The G2D has the following features:
Supports layer size up to 2048 x 2048 pixels
Supports pre-multiply alpha image data
Supports color key
Supports two pipes Porter-Duff alpha blending
Supports multiple video formats 4:2:0, 4:2:2, 4:1:1 and multiple pixel formats (8/16/24/32 bits graphics
layer)
Supports memory scan order option
Supports any format convert function
Supports 1/16× to 32× resize ratio
Supports 32-phase 8-tap horizontal anti-alias filter and 32-phase 4-tap vertical anti-alias filter
Supports window clip
Supports FillRectangle, BitBlit, StretchBlit and MaskBlit
Supports horizontal and vertical flip, clockwise 0/90/180/270 degree rotate for normal buffer
Supports horizontal flip, clockwise 0/90/270 degree rotate for LBC buffer
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4.4 Video Decoding
4.4.1 Overview
The Video Decoding consists of Video Control Firmware (VCF) running on ARM processor and embedded
hardware Video Engine (VE). VCF gets the bitstream from topper software, parses bitstream, invokes the Video
Engine, and generates the decoding image sequence. The decoder image sequence is transmitted by the video
output controller to the display device under the control of the topper software.
The Video Decoding has the following features:
Supports H.265 [email protected]
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports H.264 BP/MP/[email protected]
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports H.263 BP
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports MPEG-4 SP/ASP L5
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports MPEG-2 MP/HL
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports MPEG-1 MP/HL
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports Xvid
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports Sorenson Spark
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- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports WMV9/VC1 SP/MP/AP
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@60fps
Supports MJPEG
- Maximum video resolution: 1920 x 1080
- Maximum decoding rate: 60 Mbit/s, 1080p@30fps
4.4.2 Block Diagram
The functional block diagram of the Video Decoding is as follows.
Figure 4-2 Video Decoding Block Diagram
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4.5 Video Encoding
4.5.1 Overview
The Video Encoding supports JPEG/MJPEG encoding (JPGE).
The JPGE is a high-performance JPEG encoder implemented by using hardware. It supports 64-megapixel
snapshot or HD MJPEG encoding.
The JPGE has the following features:
Supports ISO/IEC 10918-1 (CCITT T.81) baseline process (DCT sequential) encoding
Encodes the pictures in the chrominance sampling format of YCbCr4:2:0 and YCbCr4:2:2
Supports multiple input picture formats:
- Semi-planar YCbCr4:2:0
- Semi-planar YCbCr4:2:2
Supports JPEG encoding with the performance of 1080p@60fps
Supports configurable picture resolutions
- Minimum picture resolution: 192 x 96
- Maximum picture resolution: 4096 x 4096
Supports the picture width or height step of 8
Supports configurable quantization tables for the Y component, Cb component and Cr component
respectively
Supports OSD front-end overlapping
- OSD overlaying before encoding for a maximum of 16 regions
- OSD overlaying with any size and at any position (within the size and position range of the picture)
- 16-level alpha blending
- OSD overlaying control (enabled or disabled)
Supports the color-to-gray function
Supports the MJPEG output bit rate ranging from 2 kbit/s to 60 Mbit/s
4.5.2 Block Diagram
The functional block diagram of the JPGE is as follows.
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Figure 4-3 JPGE Block Diagram
ARM
Quant table Interrupt
Upper level software
config handling
Video Input Port
External Memory (DDR)
Input picture buffer bitstream buffer
JPGE INT
Level shift/DCT/Quant Scan VLC Quant table
The JPGE realizes various protocol processing with large computation such as OSD, level shift, DCT, quantization,
scanning, VLC encoding, and stream generation. The ARM software completes the encoding control processing
such as quantization table configuration and interrupt processing.
Before the JPGE starts encoding, the software allocates two types of buffers mainly in the external DDR SDRAM:
• Input picture buffer
The JPGE reads the source pictures to be encoded from this buffer during encoding. This buffer is generally
written by the Video Input Port module.
• Stream buffer
This buffer stores encoded streams. The JPGE writes streams to this buffer during encoding. This buffer is read
by software.
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Contents
5 Video Output Interfaces.......................................................................................................................................... 365
5.1 TCON LCD ........................................................................................................................................................ 365
5.1.1 Overview ............................................................................................................................................. 365
5.1.2 Block Diagram ..................................................................................................................................... 366
5.1.3 Functional Descriptions....................................................................................................................... 366
5.1.4 Programming Guidelines..................................................................................................................... 378
5.1.5 Register List ......................................................................................................................................... 385
5.1.6 Register Description ............................................................................................................................ 387
5.2 TCON TV .......................................................................................................................................................... 420
5.2.1 Overview ............................................................................................................................................. 420
5.2.2 Functional Descriptions....................................................................................................................... 420
5.2.3 Register List ......................................................................................................................................... 420
5.2.4 Register Description ............................................................................................................................ 421
5.3 TV Encoder ...................................................................................................................................................... 433
5.3.1 Overview ............................................................................................................................................. 433
5.3.2 Block Diagram ..................................................................................................................................... 433
5.3.3 Functional Descriptions....................................................................................................................... 433
5.3.4 Programming Guidelines..................................................................................................................... 435
5.3.5 Register List ......................................................................................................................................... 436
5.3.6 TVE_TOP Register Description ............................................................................................................ 438
5.3.7 TVE Register Description ..................................................................................................................... 442
5.4 MIPI DSI ........................................................................................................................................................... 462
5.4.1 Overview ............................................................................................................................................. 462
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Figures
Figure 5-1 TCON_LCD Block Diagram ................................................................................................................................ 366
Figure 5-2 HV Interface Vertical Timing ............................................................................................................................ 370
Figure 5-3 HV Interface Horizontal Timing........................................................................................................................ 371
Figure 5-4 i8080 Interface Timing ..................................................................................................................................... 373
Figure 5-5 LVDS Single Link JEDIA Mode Interface Timing................................................................................................ 374
Figure 5-6 LVDS Single Link NS Mode Interface Timing .................................................................................................... 374
Figure 5-7 LVDS Dual Link NS Mode Interface Timing ...................................................................................................... 375
Figure 5-8 CMAP Module .................................................................................................................................................. 377
Figure 5-9 FRM Module .................................................................................................................................................... 377
Figure 5-10 The Data Timing of MIPI DSI Video Mode...................................................................................................... 378
Figure 5-11 HV Mode Initial Process ................................................................................................................................. 378
Figure 5-12 LVDS Mode Configuration Process ................................................................................................................ 381
Figure 5-13 i8080 Mode Initial Process............................................................................................................................. 384
Figure 5-14 TVE Block Diagram ......................................................................................................................................... 433
Figure 5-15 Auto Detection Function ................................................................................................................................ 434
Figure 5-16 DAC Calibration Function ............................................................................................................................... 435
Figure 5-17 Operating TVE Module................................................................................................................................... 436
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Tables
Table 5-1 LCD External Signals .......................................................................................................................................... 366
Table 5-2 The Correspondence between LCD and RGB .................................................................................................... 367
Table 5-3 The Correspondence between LCD and LVDS................................................................................................... 368
Table 5-4 HV Panel Signals ................................................................................................................................................ 369
Table 5-5 BT656 Panel Signals........................................................................................................................................... 371
Table 5-6 EAV and SAV Sequence ..................................................................................................................................... 372
Table 5-7 CPU Panel Signals .............................................................................................................................................. 372
Table 5-8 LVDS Panel Signals ............................................................................................................................................ 373
Table 5-9 TCON_LCD Clock Sources .................................................................................................................................. 375
Table 5-10 RGB Gamma Correction Table ........................................................................................................................ 376
Table 5-11 TVE External Signals ........................................................................................................................................ 433
Table 5-12 TVE Clock Sources ........................................................................................................................................... 434
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5 Video Output Interfaces
5.1 TCON LCD
5.1.1 Overview
The Timing Controller_LCD (TCON_LCD) is a module that processes video signals received from system through
a complicated arithmetic and then generates control signals and transmits them to the LCD panel driver IC.
The TCON_LCD includes the following features:
Supports RGB interface with DE/SYNC mode, up to 1920 x 1080@60fps
Supports serial RGB/dummy RGB interface, up to 800 x 480@60fps
Supports LVDS interface with dual link, up to 1920 x 1080@60fps
Supports LVDS interface with single link, up to 1366 x 768@60fps
Supports i8080 interface, up to 800 x 480@60fps
Supports BT656 interface for NTSC and PAL
Supports RGB666 and RGB565 with dither function
Supports Gamma correction with R/G/B channel independence
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5.1.2 Block Diagram
Figure 5-1 TCON_LCD Block Diagram
CONTROL
VPLL
LOGIC
F RGB2
DATA
DE ASYNC FIFO1 R YUV Lcd data
FORMATTER
M (444)
LCD
HV TIMING Panel
FIFO FLAG DCLK Lcd ctlr
& BASIC TIMING
GENERATOR
CPU TIMING
CLK GEN
5.1.3 Functional Description
5.1.3.1 External Signals
The LCD external signals are used to connect to panel interface. The panel interface has various types.
Table 5-1 LCD External Signals
Signal Name Description Type
LCD0-D[23:0] LCD Data Output O
LCD Clock
LCD0-CLK O
The pixel data are synchronized by this clock
LCD Vertical Sync
LCD0-VSYNC O
It indicates one new frame
LCD Horizontal Sync
LCD0-HSYNC O
It indicates one new scan line
LCD0-DE LCD Data Output Enable O
TCON-TRIG LCD Sync (TCON outputs to LCD for sync) O
LVDS0-CKP LVDS0 Positive Port of Clock O
LVDS0-CKN LVDS0 Negative Port of Clock O
LVDS0-V[3:0]P LVDS0 Positive Port of Data Channel [3:0] O
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Signal Name Description Type
LVDS0-V[3:0]N LVDS0 Negative Port of Data Channel [3:0] O
LVDS1-CKP LVDS1 Positive Port of Clock O
LVDS1-CKN LVDS1 Negative Port of Clock O
LVDS1-V[3:0]P LVDS1 Positive Port of Data Channel [3:0] O
LVDS1-V[3:0]N LVDS1 Negative Port of Data Channel [3:0] O
For parallel RGB, the data of LCD is high-aligned. The correspondence is as follows.
Table 5-2 The Correspondence between LCD and RGB
Parallel RGB I/O
LCD I/O
RGB565 RGB666 RGB888
LCD0-D23 R4 R5 R7
LCD0-D22 R3 R4 R6
LCD0-D21 R2 R3 R5
LCD0-D20 R1 R2 R4
LCD0-D19 R0 R1 R3
LCD0-D18 - R0 R2
LCD0-D17 - - R1
LCD0-D16 - - R0
LCD0-D15 G5 G5 G7
LCD0-D14 G4 G4 G6
LCD0-D13 G3 G3 G5
LCD0-D12 G2 G2 G4
LCD0-D11 G1 G1 G3
LCD0-D10 G0 G0 G2
LCD0-D9 - - G1
LCD0-D8 - - G0
LCD0-D7 B4 B5 B7
LCD0-D6 B3 B4 B6
LCD0-D5 B2 B3 B5
LCD0-D4 B1 B2 B4
LCD0-D3 B0 B1 B3
LCD0-D2 - B0 B2
LCD0-D1 - - B1
LCD0-D0 - - B0
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The multiplex relationship between LCD and LVDS is shown as follows.
Table 5-3 The Correspondence between LCD and LVDS
LCD I/O LVDS I/O
LCD0-D2 LVDS0-V0P
LCD0-D3 LVDS0-V0N
LCD0-D4 LVDS0-V1P
LCD0-D5 LVDS0-V1N
LCD0-D6 LVDS0-V2P
LCD0-D7 LVDS0-V2N
LCD0-D10 LVDS0-CKP
LCD0-D11 LVDS0-CKN
LCD0-D12 LVDS0-V3P
LCD0-D13 LVDS0-V3N
LCD0-D14 LVDS1-V0P
LCD0-D15 LVDS1-V0N
LCD0-D18 LVDS1-V1P
LCD0-D19 LVDS1-V1N
LCD0-D20 LVDS1-V2P
LCD0-D21 LVDS1-V2N
LCD0-D22 LVDS1-CKP
LCD0-D23 LVDS1-CKN
LCD0-CLK LVDS1-V3P
LCD0-DE LVDS1-V3N
5.1.3.2 Control Signal and Data Port Mapping
CP- CP
U U CPU CPU CPU
SYNC RGB LVDS
Cm 18- 16bit 8bit 9bit
-d bit
Para CCIR Single
External Internal SerialRGB 25 256K 65 256K 65K 256K DualLink
RGB 656 Link
I/O pin 6K K
1st 2nd 3rd 1st 2nd 3rd 1st 2nd 1st 2nd 1st 2nd 3rd 1st 2n 1st 2n 1 2
LCD0_VSYN IO0 VSYNC CS d d
LCD0_HSYN
C IO1 HSYNC RD
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LCD0_CLK IO2 DCLK WR D3P2 D3P2
LCD0_DE IO3 DE RS D3N2 D3N2
LCD0_D23 D23 R7 D23 R5 R5 B5 G5 R5 R5 B5 R4 CKN2 CKN2
LCD0_D22 D22 R6 D22 R4 R4 B4 G4 R4 R4 B4 R3 CKP2 CKP2
LCD0_D21 D21 R5 D21 R3 R3 B3 G3 R3 R3 B3 R2 D2N2 D2N2
LCD0_D20 D20 R4 D20 R2 R2 B2 G2 R2 R2 B2 R1 D2P2 D2P2
LCD0_D19 D19 R3 D19 R1 R1 B1 G1 R1 R1 B1 R0 D1N2 D1N2
LCD0_D18 D18 R2 D18 R0 R0 B0 G0 R0 R0 B0 G5 D1P2 D1P2
LCD0_D17 D17 R1 D17
LCD0_D16 D16 R0 D16
LCD0_D15 D15 G7 D15 G5 G4 D0N2 D0N2
LCD0_D14 D14 G6 D14 G4 G3 D0P2 D0P2
LCD0_D13 D13 G5 D13 G3 D3N1 D3N1
LCD0_D12 D12 G4 D71 D72 D73 D7 D12 G2 G5 R5 B5 G5 B5 G5 G2 R5 G5 B5 R4 G2 R5 G2 D3P1 D3P1
LCD0_D11 D11 G3 D61 D62 D63 D6 D11 G1 G4 R4 B4 G4 B4 G4 G1 R4 G4 B4 R3 G1 R4 G1 CKN1 CKN1
—— —— ——
LCD0_D10 D10 G2 D51 D52 D53 D5 D10 G0 G3 R3 B3 G3 B3 G3 G0 R3 G3 B3 R2 G0 R3 G0 CKP1 CKP1
LCD0_D9 D9 G1 D9
LCD0_D8 D8 G0 D8
LCD0_D7 D7 B7 D41 D42 D43 D4 D7 B5 G2 R2 B2 G2 B2 G2 B4 R2 G2 B2 R1 B4 R2 B5 D2N1 D2N1
LCD0_D6 D6 B6 D31 D32 D33 D3 D6 B4 G1 R1 B1 G1 B1 G1 B3 R1 G1 B1 R0 B3 R1 B4 D2P1 D2P1
LCD0_D5 D5 B5 D21 D22 D23 D2 D5 B3 G0 R0 B0 G0 B0 G0 B2 R0 G0 B0 G5 B2 R0 B3 D1N1 D1N1
LCD0_D4 D4 B4 D11 D12 D13 D1 D4 B2 B1 G4 B1 G5 B2 D1P1 D1P1
LCD0_D3 D3 B3 D01 D02 D03 D0 D3 B1 B0 G3 B0 G4 B1 D0N1 D0N1
LCD0_D2 D2 B2 D2 B0 G3 B0 D0P1 D0P1
LCD0_D1 D1 B1 D1
LCD0_D0 D0 B0 D0
5.1.3.3 HV interface (Sync+DE mode)
HV I/F is also known as Sync + DE mode, which is widely used in TFT LCD module for PMP/MP4 applications.
Its signals are define as:
Table 5-4 HV Panel Signals
Signal Name Description Type
Vsync Vertical sync, indicates one new frame O
Hsync Horizontal sync, indicates one new scan line O
DCLK Dot clock, pixel data are sync by this clock O
DE LCD data enable O
D[23..0] 24-bit RGB output from input FIFO for panel O
The timing diagram of HV interface is as follows.
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Figure 5-2 HV Interface Vertical Timing
Vertial Timing
VT
VBP
VSPW
Vsync
Hsync
D[23..0] Vertical invalid data period DH1 DH2 DHy Vertical invalid data period
Odd/Even field
VT
VSPW
Vsync
VBP
1//2
H
Hsync
D[23..0] Vertical invalid data period DH1 DH2 DHy Vertical invalid data period
Even field
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Figure 5-3 HV Interface Horizontal Timing
HT
HBP
HSPW
Hsync
Tdclk
DCLK
D[23..0] Invalid D1 D2 D3 D320
DE
Parallel Mode Horizontal Timing
HT
HBP
HSPW
Hsync
Tdclk
DCLK
One Pixel
D[7..0] Invalid R0 G1 B2 R3 B959
DE
Serial Mode Horizontal Timing
5.1.3.4 BT656 Interface
In HV serial YUV output mode, its timing is BT656 compatible. SAV adds right before active area every line; EAV
adds right after active area every line.
Table 5-5 BT656 Panel Signals
Signal Name Description Type
DCLK Clock signal O
DATA[7:0] Data signal O
Its logic is:
F = “0” for Field 1 F = “1” for Field 2
V = “1” during vertical blanking
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H = “0” at SAV H = “1” at EAV
P3-P0 = protection bits
P3 = V ⊕ H
P2 = F ⊕ H
P1 = F ⊕ V
P0 = F ⊕ V ⊕ H
Where ⊕ represents the exclusive-OR function.
The 4 byte SAV/EAV sequence is as follows.
Table 5-6 EAV and SAV Sequence
8-bit Data 10-bit Data
D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1 1 1
Preamble 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
Status word 1 F V H P3 P2 P1 P0 0 0
5.1.3.5 i8080 Interface
The i8080 I/F LCD panel is most common interface for small size, low resolution LCD panels. The CPU control
signals are active low.
Table 5-7 CPU Panel Signals
Signal Name Description Type
CS Chip select, active low O
WR Write strobe, active low O
RD Read strobe, active low O
A1 Address bit, controlled by "LCD_CPUI/F" BIT26/25 O
D[23..0] Digital RGB output signal I/O
The following figure relationship between basic timing and CPU timing. WR is 180o delay of DCLK; CS is active
when pixel data is valid; RD is always set to 1; A1 is set by “LCD_CPUI/F”.
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Figure 5-4 i8080 Interface Timing
CS
A1
WR
D[23..0] Invalid data Command Valid data Invalid
RD
D[23..0] Invalid data Command Valid data Invalid
When CPU I/F is in IDLE state, it can generate WR/RD timing by setting “Lcd_CPUI/F”. The CS strobe is one DCLK
width, and the WR/RD strobe is half DCLK width.
5.1.3.6 LVDS Interface
Table 5-8 LVDS Panel Signals
Signal Name Description Type
CKP The positive port of clock O
CKN The negative port of clock O
D0P The positive port of data channel 0 O
D0N The negative port of data channel 0 O
D1P The positive port of data channel 1 O
D1N The negative port of data channel 1 O
D2P The positive port of data channel 2 O
D2N The negative port of data channel 2 O
D3P The positive port of data channel 3 O
D3N The negative port of data channel 3 O
The following figures show the timing of LVDS interface.
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Figure 5-5 LVDS Single Link JEDIA Mode Interface Timing
Previous Cycle Current Cycle Next Cycle
Clock
RIN0+
R3 R2 G2 R7 R6 R5 R4 R3 R2 G2
RIN0-
RIN1+
G4 G3 B3 B2 G7 G6 G5 G4 G3 B3
RIN1-
RIN2+
RIN2- B5 B4 DE VS HS B7 B6 B5 B4 DE
RIN3+
RIN3- R1 R0 NA B1 B0 G1 G0 R1 R0 NA
Figure 5-6 LVDS Single Link NS Mode Interface Timing
Previous Cycle Current Cycle Next Cycle
Clock
RIN0+
R1 R0 G0 R5 R4 R3 R2 R1 R0 G0
RIN0-
RIN1+
G2 G1 B1 B0 G5 G4 G3 G2 G1 B1
RIN1-
RIN2+
RIN2- B3 B2 DE VS HS B5 B4 B3 B2 DE
RIN3+
RIN3- R7 R6 NA B7 B6 G7 G6 R7 R6 NA
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Figure 5-7 LVDS Dual Link NS Mode Interface Timing
ORXCLK+
ORXCLK-
RIN0+
OR0 OG0 OR5 OR4 OR3 OR2 OR1 OR0 OG0
RIN0-
RIN1+
OG1 OB1 OB0 OG5 OG4 OG3 OG2 OG1 OB1
RIN1-
RIN2+
RIN2- OB2 DE VS HS OB5 OB4 OB3 OB2 DE
RIN3+
RIN3- OR6 OB7 OB6 OG7 OG6 OR7 OR6
ORXCLK+
ORXCLK-
RIN0+
ER0 EG0 ER5 ER4 ER3 ER2 ER1 ER0 EG0
RIN0-
RIN1+
EG1 EB1 EB0 EG5 EG4 EG3 EG2 EG1 EB1
RIN1-
RIN2+
RIN2- EB2 DE VS HS EB5 EB4 EB3 EB2 DE
RIN3+
RIN3- ER6 EB7 EB6 EG7 EG6 ER7 ER6
5.1.3.7 Clock Sources
The following table describes the clock sources of TCON_LCD. Table 5-9 describes the clock sources of
TCON_LCD.
Table 5-9 TCON_LCD Clock Sources
Clock Sources Description
PLL_VIDEO0(1X)
By default, PLL_VIDEO0(4X) is 1188 MHz, PLL_VIDEO0(1X) is 297 MHz
PLL_VIDEO0(4X)
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Clock Sources Description
PLL_VIDEO1(1X)
By default, PLL_VIDEO1(4X) is 1188 MHz, PLL_VIDEO1(1X) is 297 MHz
PLL_VIDEO1(4X)
PLL_PERI(2X) By default, PLL_PERI(2X) is 1.2 GHz
PLL_AUDIO1(DIV2) By default, PLL_AUDIO1 is 3072 MHz, PLL_AUDIO1(DIV2) is 1536 MHz
5.1.3.8 RGB Gamma Correction
Function: This module correct the RGB input data of DE.
A 256*8*3 Byte register file is used to store the gamma table.
Table 5-10 RGB Gamma Correction Table
Offset Value
0x400 { B0[7:0], G0[7:0], R0[7:0] }
0x404 { B1[7:0], G1[7:0], R1[7:0] }
...... ......
0x7FC { B255[7:0], G255[7:0], R255[7:0] }
5.1.3.9 CEU Module
This module enhances color data from DE .
R’ = Rr*R + Rg*G + Rb*B + Rc
G’ = Gr*R + Gg*G + Gb*B + Gc
B’ = Br*R + Bg*G + Bb*B + Bc
NOTE
Rr, Rg, Rb, Gr, Gg, Gb, Br, Bg, Bb s13 (-16, 16)
Rc, Gc, Bc s19 (-16384, 16384)
R, G, B u8 [0-255]
R’ has the range of [Rmin ,Rmax]
G’ has the range of [Rmin ,Rmax]
B’ has the range of [Rmin ,Rmax]
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5.1.3.10 CMAP Module
Function: This module map color data from DE.
Every 4 input pixels are as a unit. A unit is divided into 12 bytes. Output byte can select one of those 12 bytes.
Note that even line and odd line can be different, and output can be 12 bytes (4 pixels) or reduce to 6 bytes (2
pixels).
Figure 5-8 CMAP Module
Input Output
r0(2) r1(6) r2(a) r3(d) D23:16 odd0
g0(1) g1(5) g2(9) g3(c) D15:08 odd0 odd1 odd2 odd3
b0(0) b1(4) b2(8) b3(b) D07:00 odd0
In mode: 4 pixels
Out mode: 4 pixels/2 pixels eve0 eve1 eve2 eve3
5.1.3.11 FRM Module
Figure 5-9 FRM Module
D[7:3] D[7:3]
DCLK 25BIT LFSR 0 BIT[3:0]
(X25 +X3+1)
VSYNC 128
CLR
*
1
HSYNC 13BIT LFSR 1 BIT[3:0] ADDR[3:0]
(X13 + X4 +X3 +X1 +1) +
ADDR[6:4]
R
A
+ D2
VSYNC BIT[3:0]
4BIT COUNTER
D[2:0] D2 D[1:0]=0
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5.1.3.12 MIPI DSI
The requirements on MIPI DSI mode are as follows.
(1). When using MIPI DSI as display interface, the data clk of TCON needs be started firstly.
(2). When it is used with DSI video mode, the setting of block space needs to meet the following relationship.
Figure 5-10 The Data Timing of MIPI DSI Video Mode
HT
DRQ DRQ
ACTIVE HFP
DLY
DE SPACE
Line_set
DRQ < Line_set < HT
5.1.4 Programming Guidelines
5.1.4.1 HV Mode Configuration Process
Figure 5-11 HV Mode Initial Process
Select Work Mode Setup Timing
Setup Clock Enable ios
and I/F Params
Setup and Enable
Module Enable
Interrupt
(1) Parallel RGB
Step 1 Select HV interface type
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Configure LCD_CTL_REG[LCD_IF] (reg0x40) to 0 to select HV (Sync+DE) mode, and configure
LCD_HV_IF_REG[HV_MODE] (reg0x58) to 0 to select 24bit/1cycle parallel mode.
lcd_dev[sel]->lcd_ctl.lcd_if = HV(Sync+DE);
lcd_dev[sel]->lcd_ctl.src_sel = src; //src = DE/color/grayscale/...
lcd_dev[sel]->lcd_hv_ctl.hv_mode = 24bit/1cycle parallel mode;
Step 2 Clock configuration
NOTE
In parallel RGB mode, the displayed pixel clock (pixel_CLK) is required to be consistent with the
DCLK, the pixel_clk(pixel_clk=Ht*Vt*frame rate) is decided by external LCD.
When using phase adjustment function, the LCD_IO_POL_REG.DCLK_SEL (reg0x88) selects
dclk0–2 of different phase, and LCD_IO_POL_REG.IO2_INV can achieve 180°phase delay.
Configure corresponding frequency by setting PLL_VIDEO0/1 register, and configure TCON LCD0
Clock register.
Configure internal frequency division of TCON_LCD. Based on clock source of TCON and DCLK clock
ratio, configure LCD_DCLK_REG[LCD_DCLK_DIV]. If using phase adjustment function,
LCD_DCLK_REG[LCD_DCLK_EN] needs be set, usually is 0xf. When the dclk1 and dclk2 in
LCD_DCLK_REG[LCD_DCLK_EN] are used, the value of LCD_DCLK_REG[LCD_DCLK_DIV] needs no less
than 6.
lcd_dev[sel]->lcd_dclk.dclk_en = en;
lcd_dev[sel]->lcd_dclk.dclk_div = div;
Step 3 Set sequence parameters
The sequence parameters include x,ht,hbp,hspw,y,vt,vbp,vspw, and correspond to LCD_BASE_REG
from reg0x48 to reg 0x54. Note that hbp includes hspw, and vbp includes vspw. And
LCD_BASE2_REG.VT needs be set to the twice of the actual value.
lcd_dev[sel]->lcd_basic0.x = x-1;
lcd_dev[sel]->lcd_basic0.y = y-1;
lcd_dev[sel]->lcd_basic1.ht = ht-1;
lcd_dev[sel]->lcd_basic1.hbp = hbp-1;
lcd_dev[sel]->lcd_basic2.vt = vt*2;
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lcd_dev[sel]->lcd_basic2.vbp = vbp-1;
lcd_dev[sel]->lcd_basic3.hspw = hspw-1;
lcd_dev[sel]->lcd_basic3.vspw = vspw-1;
Step 4 Open IO output
Set the corresponding data IO enable and control signal IO enable of LCD_IO_TRI_REG (reg0x8C) to
0 to start enable. Note that except the internal IO of TCON_LCD, the external GPIO mapping needs
to be set to LCD mode.
When some control signals require polarity reversal, it can realize by setting
LCD_IO_POL_REG.IO0~3_INV (reg0x88).
Step 5 Set and open interrupt function
The LCD_GINT0_REG (reg0x4) controls interrupt mode and flag, and the LCD_GINT1_REG (reg0x8)
sets the interrupt line position of Line interrupt mode.
V interrupt:
lcd_dev[sel]->lcd_gint0.vb_en = 1;
Line interrupt:
lcd_dev[sel]->lcd_gint1.lcd_line_int_num = line;
lcd_dev[sel]->lcd_gint0.line_en = 1;
Step 6 Open module enable
Enable LCD_CTL_REG.LCD_EN (reg0x40) and LCD_GCTL_REG.LCD_EN (reg0x00).
lcd_dev[sel]->lcd_ctl.lcd_en = 1;
lcd_dev[sel]->lcd_gctl.lcd_en = 1;
(2) Serial RGB
The serial RGB mode is consistent with parallel RGB mode, the main difference is the definition of clock and
the sequence of serial data. The difference is as follows.
Step 1 Select HV interface type
Set LCD_CTL_REG.LCD_IF (reg0x40) to 0 to select HV(Sync+DE) mode; set LCD_HV_IF_REG.HV_MODE
(reg0x58) to select 8bit/3cycle RGB serial mode (RGB888), 8bit/4cycle Dummy RGB mode (DRGB) or
8bit/4cycle RGB Dummy mode (RGBD).
lcd_dev[sel]->lcd_ctl.lcd_if = HV(Sync+DE);
lcd_dev[sel]->lcd_ctl.src_sel = src; //src = DE/color/grayscale/...
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lcd_dev[sel]->lcd_hv_ctl.hv_mode = Serial mode;
Step2、Step3: Set clock and sequence parameters
In serial RGB mode, DCLK is the transfer clock of each byte data. In the same resolution, pixel_clk of
serial RGB is three times of its clock in parallel RGB, and ht,hbp,hspw own the same conversion
relation. When display is split into odd field and even field, LCD_BASE2_REG.VT needs not to be set
to the twice of the actual value.
lcd_dev[sel]->lcd_basic2.vt = vt;
Set LCD_HV_IF_REG.RGB888_ODD_ORDER/LCD_HV_IF_REG.RGB888_ODD_EVEN to select RGB
output sequence of the selected odd and even lines.
lcd_dev[lcd_sel]->lcd_hv_ctl.srgb_seq_even = seq_even;
lcd_dev[lcd_sel]->lcd_hv_ctl.srgb_seq_odd = seq_odd;
5.1.4.2 LVDS Mode Configuration Process
Figure 5-12 LVDS Mode Configuration Process
Select Work Setup Timing
Setup Clock Enable ios
Mode and I/F Params
LVDS Digital LVDS Analog Setup and Enable
Module Enable
Setup Setup Interrupt
The LVDS interface configuration process is similar to the parallel mode of HV mode, and adds the
digital/analog configuration of LVDS interface.
Step 1 Same as in step1 of parallel mode
Step 2 Clock configuration
NOTE
In parallel mode, the displayed pixel clock (pixel_CLK) is required to be consistent with the DCLK,
pixel_clk=Ht*Vt*frame rate.
Configure LCD_DCLK_REG.LCD_DCLK_DIV (reg0x44) to 7 after DCLK is determined;
Configure the PLL clock in CCU based on proportional relationship;
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Release the LVDS reset of TCON LCD BUS GATING RESET register;
Other configurations remain unchanged.
lcd_dev[sel]->lcd_dclk.dclk_en = en;
lcd_dev[sel]->lcd_dclk.dclk_div = 7;
Step 3 Same as in step3 of parallel mode
Step 4 Same as in step4 of parallel mode
Step 5 LVDS digital logic configuration
Includes clock source select of module, LVDS link number, data mode and bit width configuration.
Configure LCD_LVDS_IF_REG.LCD_LVDS_CLK_SEL (reg0x84) to set LCD CLK;
Configure LCD_LVDS_IF_REG.LCD_LVDS_LINK to set the required LVDS port number;
Configure LCD_LVDS_IF_REG.LCD_LVDS_MODE to set JEDIA and NS mode;
Configure LCD_LVDS_IF_REG.LCD_LVDS_BITWIDTH to select 24-bit or 18-bit width;
Lastly configure LCD_LVDS_IF_REG.LCD_LVDS_EN to start LVDS mode.
lcd_dev[sel]->lcd_lvds_ctl.lvds_link = link_num-1;
lcd_dev[sel]->lcd_lvds_ctl.lvds_mode = mode;
lcd_dev[sel]->lcd_lvds_ctl.lvds_bitwidth = bitwidth;
lcd_dev[sel]->lcd_lvds_ctl.lvds_clk_sel = clk_src;
lcd_dev[sel]->lcd_lvds_ctl.lvds_en = 1;
NOTE
If configuring the same source data output mode of dual link, except the reg0x84 register of
TCON_LCD0 needs be configured, the LCD_LVDS_IF_REG.LCD_LVDS_CLK_SEL,
LCD_LVDS_IF_REG.LCD_LVDS_LINK, LCD_LVDS_IF_REG.LCD_LVDS_MODE, and
LCD_LVDS_IF_REG.LCD_LVDS_BITWIDTH of the reg0x244 register need be configured.
Step 6 LVDS controller configuration
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NOTE
The TCON LCD0 PHY0 is controlled by COMBO_PHY_REG (reg0x1110, reg0x1114). The TCON LCD0
PHY1 is controlled by LCD_LVDS0_ANA_REG (reg0x220).
For PHY0:
Configure the reg_verf1p6 (differential mode voltage) in reg0x1114 to 4;
Configure the reg_vref0p8 reg0x1114 (common mode voltage) in reg0x1114 to 3;
Start en_cp, en_mipi, en_lvds, and en_comboldo in reg0x1110, in turn.
For PHY1:
The LVDS analog configuration process is to start clock and data channel, and set the common mode
and differential mode voltage, and start module power.
Configure LVDS_HPREN_DRVC and LVDS_HPREN_DRV. When LVDS signal is 18-bit,
LVDS_HPREN_DRV=0x7; when LVDS signal is 24-bit, LVDS_HPREN_DRV=0xF;
Configure LVDS0_REG_C (differential mode voltage) to 4;
Configure LVDS0_REG_V (common mode voltage) to 3;
Lastly, start module voltage, and enable EN_LVDS and EN_24M.
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.en_drvd = 0x7; //18-bit=0x7, 24-bit=0xf
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.en_drvc = 1;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.diff_level = diff;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.com_level = com;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.dual_src = link_src;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.en_24M = 1;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.en_lvds = 1;
lcd_dev[sel]->lcd_lvds_ana_ctl[lvds_num].bits.en_mb = 1;
Step 7 Same as in step5 of parallel mode
Step 8 Same as in step6 of parallel mode
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5.1.4.3 i8080 Mode Configuration Process
Figure 5-13 i8080 Mode Initial Process
Select Work Mode Setup Timing
Setup Clock Enable ios
and I/F Params
TRI Mode
Setup TRI INT or Setup TRI Mode Enable TRI FIFO and
Counter INT Params TRI mode
Select i8080 I/F and
Workmode
Setup V INT or Line
INT
AUTO Mode
Enable Interrupt Module Enable AUTO Mode
Enable Interrupt Module Enable TRI Start TRI Mode
Step 1 Select i8080 interface type.
Step 2 The step is the same as HV mode, but pulse adjustment function is invalid.
Step 3 The step is the same as HV mode. When using TRI mode, it is best to configure LCD timing parameters
in HV mode , or a handful of functions such as CMAP will not be able to apply.
Step 4 The step is the same as HV mode.
Step 5 Select type and operating mode of i8080, the operating mode includes TRI mode and AUTO mode,
and the two operating modes are different.
---------------------------------------------------------------For TRI mode----------------------------------------------------------------
Step 6 Open TRI FIFO switch, and TRI mode function.
Step 7 Set parameters of TRI mode, including block size, block space and block number.
NOTE
When output interface is parallel mode, then the setting value of block space parameter is not less
than 20.
When output interface is 2 cycle serial mode, then the setting value of block space parameter is not
less than 40.
When output interface is 3 cycle serial mode, then the setting value of block space parameter is not
less than 60.
When output interface is 4 cycle serial mode, then the setting value of block space parameter is not
less than 80.
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Step 8 Set the tri interrupt or counter interrupt. When using the two interrupts, mainly in the interrupt
service function the tri start operation need be operated (the bit1 of LCD_CPU_IF_REG is set to"1").
If using TE trigger interrupt, you select the external input pin as a trigger signal, the 24-bit for offset
0x8C register is set to "1", to open up input of pad.
Step 9 Open the total switch of interrupt.
Step 10 Open the total enable of interrupt.
Step 11 Operate “tri start” operation (the bit1 of LCD_CPU_IF_REG is set to "1").
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------For Auto mode----------------------------------------------------------------
Step 6 Set and open V interrupt or Line interrupt, the step is the same as HV mode.
Step 7 Open module total enable.
-------------------------------------------------------------------------------------------------------------------------------------------------
5.1.5 Register List
Module Name Base Address
TCON_LCD0 0x05461000
Register Name Offset Description
LCD_GCTL_REG 0x0000 LCD Global Control Register
LCD_GINT0_REG 0x0004 LCD Global Interrupt Register0
LCD_GINT1_REG 0x0008 LCD Global Interrupt Register1
LCD_FRM_CTL_REG 0x0010 LCD FRM Control Register
LCD_FRM_SEED_REG 0x0014+N*0x04 LCD FRM Seed Register (N=0,1,2,3,4,5)
LCD_FRM_TAB_REG 0x002C+N*0x04 LCD FRM Table Register (N=0,1,2,3)
LCD_3D_FIFO_REG 0x003C LCD 3D FIFO Register
LCD_CTL_REG 0x0040 LCD Control Register
LCD_DCLK_REG 0x0044 LCD Data Clock Register
LCD_BASIC0_REG 0x0048 LCD Basic Timing Register0
LCD_BASIC1_REG 0x004C LCD Basic Timing Register1
LCD_BASIC2_REG 0x0050 LCD Basic Timing Register2
LCD_BASIC3_REG 0x0054 LCD Basic Timing Register3
LCD_HV_IF_REG 0x0058 LCD HV Panel Interface Register
LCD_CPU_IF_REG 0x0060 LCD CPU Panel Interface Register
LCD_CPU_WR_REG 0x0064 LCD CPU Panel Write Data Register
LCD_CPU_RD0_REG 0x0068 LCD CPU Panel Read Data Register0
LCD_CPU_RD1_REG 0x006C LCD CPU Panel Read Data Register1
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Register Name Offset Description
LCD_LVDS_IF_REG 0x0084 LCD LVDS Configure Register
LCD_IO_POL_REG 0x0088 LCD IO Polarity Register
LCD_IO_TRI_REG 0x008C LCD IO Control Register
LCD_DEBUG_REG 0x00FC LCD Debug Register
LCD_CEU_CTL_REG 0x0100 LCD CEU Control Register
LCD_CEU_COEF_MUL_REG 0x0110+N*0x04 LCD CEU Coefficient Register0 (N=0–10)
LCD_CEU_COEF_ADD_REG 0x011C+N*0x10 LCD CEU Coefficient Register1 (N=0,1,2)
LCD_CEU_COEF_RANG_REG 0x0140+N*0x04 LCD CEU Coefficient Register2 (N=0,1,2)
LCD_CPU_TRI0_REG 0x0160 LCD CPU Panel Trigger Register0
LCD_CPU_TRI1_REG 0x0164 LCD CPU Panel Trigger Register1
LCD_CPU_TRI2_REG 0x0168 LCD CPU Panel Trigger Register2
LCD_CPU_TRI3_REG 0x016C LCD CPU Panel Trigger Register3
LCD_CPU_TRI4_REG 0x0170 LCD CPU Panel Trigger Register4
LCD_CPU_TRI5_REG 0x0174 LCD CPU Panel Trigger Register5
LCD_CMAP_CTL_REG 0x0180 LCD Color Map Control Register
LCD_CMAP_ODD0_REG 0x0190 LCD Color Map Odd Line Register0
LCD_CMAP_ODD1_REG 0x0194 LCD Color Map Odd Line Register1
LCD_CMAP_EVEN0_REG 0x0198 LCD Color Map Even Line Register0
LCD_CMAP_EVEN1_REG 0x019C LCD Color Map Even Line Register1
LCD_SAFE_PERIOD_REG 0x01F0 LCD Safe Period Register
LCD_LVDS0_ANA_REG 0x0220 LCD LVDS Analog Register 0
LCD_LVDS1_ANA_REG 0x0224 LCD LVDS Analog Register 1
LCD_SYNC_CTL_REG 0x0230 LCD Sync Control Register
LCD_SYNC_POS_REG 0x0234 LCD Sync Position Register
LCD_SLAVE_STOP_POS_REG 0x0238 LCD Slave Stop Position Register
LCD_GAMMA_TABLE_REG 0x0400-0x07FF LCD Gamma Table Register
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5.1.6 Register Description
5.1.6.1 0x0000 LCD Global Control Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: LCD_GCTL_REG
Bit Read/Write Default/Hex Description
LCD_EN
When it is disabled, the module will be reset to idle state.
31 R/W 0x0
0: Disable
1: Enable
LCD_GAMMA_EN
Enable the Gamma correction function.
30 R/W 0x0
0: Disable
1: Enable
29:0 / / /
5.1.6.2 0x0004 LCD Global Interrupt Register0 (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: LCD_GINT0_REG
Bit Read/Write Default/Hex Description
LCD_VB_INT_EN
Enable the Vb interrupt
31 R/W 0x0
0: Disable
1: Enable
30 / / /
LCD_LINE_INT_EN
Enable the line interrupt
29 R/W 0x0
0: Disable
1: Enable
28 / / /
LCD_TRI_FINISH_INT_EN
Enable the trigger finish interrupt
27 R/W 0x0
0: Disable
1: Enable
LCD_TRI_COUNTER_INT_EN
Enable the trigger counter interrupt
26 R/W 0x0
0: Disable
1: Enable
25:16 / / /
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Offset: 0x0004 Register Name: LCD_GINT0_REG
Bit Read/Write Default/Hex Description
LCD_VB_INT_FLAG
15 R/W0C 0x0 Asserted during vertical no-display period every frame
Write 0 to clear it.
14 / / /
LCD_LINE_INT_FLAG
13 R/W0C 0x0 Trigger when SY0 match the current LCD scan line
Write 0 to clear it.
12 / / /
LCD_TRI_FINISH_INT_FLAG
11 R/W0C 0x0 Trigger when cpu trigger mode finished
Write 0 to clear it.
LCD_TRI_COUNTER_INT_FLAG
10 R/W0C 0x0 Trigger when tri counter reaches this value
Write 0 to clear it.
LCD_TRI_UNDERFLOW_FLAG
9 R/W0C 0x0 Only used in dsi video mode, tri when sync by dsi but not finish
Write 0 to clear it.
8:3 / / /
FSYNC_INT_INV
Enable the fsync interrupt to set signal inverse polarity.
2 R/W0C 0x0
When FSYNC is positive, this bit must be 1.
And vice versa.
DE_INT_FLAG
1 R/W0C 0x0 Asserted at the first valid line in every frame
Write 0 to clear it.
FSYNC_INT_FLAG
0 R/W0C 0x0 Asserted at the fsync signal in every frame
Write 0 to clear it.
5.1.6.3 0x0008 LCD Global Interrupt Register1 (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: LCD_GINT1_REG
Bit Read/Write Default/Hex Description
31:28 / / /
LCD_LINE_INT_NUM
Scan line for LCD line trigger (including inactive lines).
27:16 R/W 0x0
Setting it for the specified line for trigger0.
Note: SY0 is writable only when LINE_TRG0 is disabled.
15:0 / / /
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5.1.6.4 0x0010 LCD FRM Control Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: LCD_FRM_CTL_REG
Bit Read/Write Default/Hex Description
LCD_FRM_EN
Enable the dither function
31 R/W 0x0
0: Disable
1: Enable
30:7 / / /
LCD_FRM_MODE_R
The R component output bits in dither function
6 R/W 0x0
0: 6-bit frm output
1: 5-bit frm output
LCD_FRM_MODE_G
The G component output bits in dither function
5 R/W 0x0
0: 6-bit frm output
1: 5-bit frm output
LCD_Frm_MODE_B
The B component output bits in dither function
4 R/W 0x0
0: 6-bit frm output
1: 5-bit frm output
3:2 / / /
LCD_FRM_TEST
Set the test mode of dither function
00: FRM
1:0 R/W 0x0
01: Half 5-/6-bit, half FRM
10: Half 8-bit, half FRM
11: Half 8-bit, half 5-/6-bit
5.1.6.5 0x0014+ N*0x04 (N=0–5) LCD FRM Seed Register (Default Value: 0x0000_0000)
Offset: 0x0014+N*0x04 (N=0–5) Register Name:
Bit Read/Write Default/Hex Description
31:25 / / /
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Offset: 0x0014+N*0x04 (N=0–5) Register Name:
Bit Read/Write Default/Hex Description
SEED_VALUE
Set the seed used in dither function
N=0: Pixel_Seed_R
N=1: Pixel_Seed_G
24:0 R/W 0x0 N=2: Pixel_Seed_B
N=3: Line_Seed_R
N=4: Line_Seed_G
N=5: Line_Seed_B
Note: Avoid setting it to 0.
5.1.6.6 0x002C+ N*0x04 (N=0–3) LCD FRM Table Register (Default Value: 0x0000_0000)
Offset: 0x002C+N*0x04 (N=0–3) Register Name: LCD_FRM_TAB_REG
Bit Read/Write Default/Hex Description
FRM_TABLE_VALUE
Set the data used in dither function
Usually set as follows:
31:0 R/W 0x0 Table0 = 0x01010000
Table1 = 0x15151111
Table2 = 0x57575555
Table3 = 0x7f7f7777
5.1.6.7 0x003C LCD 3D FIFO Register (Default Value: 0x0000_0000)
Offset: 0x003C Register Name: LCD_3D_FIFO_REG
Bit Read/Write Default/Hex Description
3D_FIFO_BIST_EN
Enable the 3D fifo bist test function
31 R/W 0x0
0: Disable
1: Enable
30:14 / / /
3D_FIFO_HALF_LINE_SIZE
13:4 R/W 0x0 The number of data in half line=3D_FIFO_HALF_LINE_SIZE+1,
only valid when 3D_FIFO_SETTING is set as 2.
3:2 / / /
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Offset: 0x003C Register Name: LCD_3D_FIFO_REG
Bit Read/Write Default/Hex Description
3D_FIFO_SETTING
Set the work mode of 3D FIFO
00: Bypass
1:0 R/W 0x0
01: Used as normal FIFO
10: Used as 3D interlace FIFO
11: Reserved
5.1.6.8 0x0040 LCD Control Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: LCD_CTL_REG
Bit Read/Write Default/Hex Description
LCD_EN
It executes at the beginning of the first blank line of LCD timing.
31 R/W 0x0
0: Disable
1: Enable
30:26 / / /
LCD_IF
Set the interface type of LCD controller.
25:24 R/W 0x0 00: HV(Sync+DE)
01: 8080 I/F
1x: Reserved
LCD_RB_SWAP
Enable the function to swap red data and blue data in fifo1.
23 R/W 0x0
0: Default
1: Swap RED and BLUE data at FIFO1
22 / / /
LCD_FIFO1_RST
21 R/W 0x0 Writing 1 and then 0 to this bit will reset FIFO 1
Note: 1 holding time must more than 1 DCLK
LCD_INTERLACE_EN
This flag is valid only when LCD_EN == 1
20 R/W 0x0
0: Disable
1: Enable
19:9 / / /
LCD_START_DLY
8:4 R/W 0x0 The unit of delay is Tline.
Note: Valid only when LCD_EN == 1
3 / / /
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Offset: 0x0040 Register Name: LCD_CTL_REG
Bit Read/Write Default/Hex Description
LCD_SRC_SEL
LCD Source Select
000: DE
001: Color Check
010: Grayscale Check
2:0 R/W 0x0
011: Black by White Check
100: Test Data all 0
101: Test Data all 1
110: Reversed
111: Gridding Check
5.1.6.9 0x0044 LCD Data Clock Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: LCD_DCLK_REG
Bit Read/Write Default/Hex Description
LCD_DCLK_EN
LCD clock enable
0000: dclk_en = 0; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;
0001: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;
31:28 R/W 0x0 0010: dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;
0011: dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;
0101: dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;
1111: dclk_en = 1; dclk1_en = 1; dclk2_en = 1; dclkm2_en = 1;
Others:Reversed
27:7 / / /
LCD_DCLK_DIV
Tdclk = Tsclk/DCLKDIV
6:0 R/W 0x0 Note:
1.If dclk1&dclk2 are used, DCLKDIV >=6
2.If only dclk is used, DCLKDIV >=1
5.1.6.10 0x0048 LCD Basic Timing Register0 (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: LCD_BASIC0_REG
Bit Read/Write Default/Hex Description
31:28 / / /
WIDTH_X
27:16 R/W 0x0
Panel width is X+1
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Offset: 0x0048 Register Name: LCD_BASIC0_REG
Bit Read/Write Default/Hex Description
15:12 / / /
HEIGHT_Y
11:0 R/W 0x0
Panel height is Y+1
5.1.6.11 0x004C LCD Basic Timing Register1 (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: LCD_BASIC1_REG
Bit Read/Write Default/Hex Description
31:29 / / /
HT
Thcycle = (HT+1) * Tdclk
Computation:
1) parallel: HT = X + BLANK
28:16 R/W 0x0
Limitation:
1) parallel: HT >= (HBP +1) + (X+1) +2
2) serial 1: HT >= (HBP +1) + (X+1) *3+2
3) serial 2: HT >= (HBP +1) + (X+1) *3/2+2
15:12 / / /
HBP
11:0 R/W 0x0 Horizontal back porch (in dclk)
Thbp = (HBP +1) * Tdclk
5.1.6.12 0x0050 LCD Basic Timing Register2 (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: LCD_BASIC2_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VT
28:16 R/W 0x0 TVT = (VT)/2 * Thsync
VT/2 >= (VBP+1 ) + (Y+1) +2
15:12 / / /
VBP
11:0 R/W 0x0
Tvbp = (VBP +1) * Thsync
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5.1.6.13 0x0054 LCD Basic Timing Register3 (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: LCD_BASIC3_REG
Bit Read/Write Default/Hex Description
31:26 / / /
HSPW
25:16 R/W 0x0 Thspw = (HSPW+1) * Tdclk
HT > (HSPW+1)
15:10 / / /
VSPW
9:0 R/W 0x0 Tvspw = (VSPW+1) * Thsync
VT/2 > (VSPW+1)
5.1.6.14 0x0058 LCD HV Panel Interface Register (Default Value: 0x0000_0000)
Offset: 0x0058 Register Name: LCD_HV_IF_REG
Bit Read/Write Default/Hex Description
HV_MODE
Set the HV mode of LCD controller
0000: 24-bit/1-cycle parallel mode
31:28 R/W 0x0 1000: 8-bit/3-cycle RGB serial mode (RGB888)
1010: 8-bit/4-cycle Dummy RGB (DRGB)
1011: 8-bit/4-cycle RGB Dummy (RGBD)
1100: 8-bit/2-cycle YUV serial mode (CCIR656)
RGB888_ODD_ORDER
Serial RGB888 mode Output sequence at odd lines of the panel
(line 1, 3, 5, 7…).
27:26 R/W 0x0 00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B
RGB888_EVEN_ORDER
Serial RGB888 mode Output sequence at even lines of the panel
(line 2, 4, 6, 8…).
25:24 R/W 0x0 00: R→G→B
01: B→R→G
10: G→B→R
11: R→G→B
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Offset: 0x0058 Register Name: LCD_HV_IF_REG
Bit Read/Write Default/Hex Description
YUV_SM
Serial YUV mode Output sequence 2-pixel-pair of every scan
line.
23:22 R/W 0x0 00: YUYV
01: YVYU
10: UYVY
11: VYUY
YUV_EAV_SAV_F_LINE_DLY
Set the delay line mode.
00: F toggle right after active video line
21:20 R/W 0x0
01: delay 2 line (CCIR PAL)
10: delay 3 line (CCIR NTSC)
11: reserved
CCIR_CSC_DIS
LCD convert source from RGB to YUV.
19 R/W 0x0 0: Enable
1: Disable
Only valid when HV mode is “1100”.
18:0 / / /
5.1.6.15 0x0060 LCD CPU Panel Interface Register (Default Value: 0x0000_0000)
Offset: 0x0060 Register Name: LCD_CPU_IF_REG
Bit Read/Write Default/Hex Description
CPU_MODE
Set the cpu interface work mode
0000: 18-bit/256K mode
0010: 16-bit mode0
0100: 16-bit mode1
31:28 R/W 0x0 0110: 16-bit mode2
1000: 16-bit mode3
1010: 9-bit mode
1100: 8-bit 256K mode
1110: 8-bit 65K mode
xxx1: 24-bit for DSI
27 / / /
DA
26 R/W 0x0
Pin A1 value in 8080 mode auto/flash states
CA
25 R/W 0x0
Pin A1 value in 8080 mode WR/RD execute
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Offset: 0x0060 Register Name: LCD_CPU_IF_REG
Bit Read/Write Default/Hex Description
24 / / /
WR_FLAG
The status of write operation.
23 R 0x0
0: Write operation is finishing
1: Write operation is pending
RD_FLAG
The status of read operation.
22 R 0x0
0: Read operation is finishing
1: Read operation is pending
21:18 / / /
AUTO
Auto transfer mode
17 R/W 0x0
If it is 1, all the valid data during this frame are written to panel.
Note: This bit is sampled by Vsync.
FLUSH
Direct transfer mode
16 R/W 0x0 If it is enabled, FIFO1 is regardless of the HV timing, the pixels
data keep being transferred unless the input FIFO was empty.
Data output rate is controlled by DCLK.
15:4 / / /
TRI_FIFO_BIST_EN
Entry address is 0xFF8
3 R/W 0x0
0: Disable
1: Enable
TRI_FIFO_EN
Enable the trigger FIFO
2 R/W 0x0
0: Disable
1: Enable
TRI_START
Software must make sure that write ‘1’ only when this flag is
1 R/W1S 0x0 ‘0’.
Writing ‘1’ starts a frame flush and writing ’0’ has no effect.
This flag indicates the frame flush is running.
TRI_EN
Enable trigger mode
0 R/W 0x0
0: Trigger mode disable
1: Trigger mode enable
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5.1.6.16 0x0064 LCD CPU Panel Write Data Register (Default Value: 0x0000_0000)
Offset: 0x0064 Register Name: LCD_CPU_WR_REG
Bit Read/Write Default/Hex Description
31:24 / / /
DATA_WR
23:0 W 0x0
Data write on 8080 bus, launch a write operation on 8080 bus.
5.1.6.17 0x0068 LCD CPU Panel Read Data Register0 (Default Value: 0x0000_0000)
Offset: 0x0068 Register Name: LCD_CPU_RD0_REG
Bit Read/Write Default/Hex Description
31:24 / / /
DATA_RD0
23:0 R 0x0 Data read on 8080 bus, launch a new read operation on 8080
bus.
5.1.6.18 0x006C LCD CPU Panel Read Data Register1 (Default Value: 0x0000_0000)
Offset: 0x006C Register Name: LCD_CPU_RD1_REG
Bit Read/Write Default/Hex Description
31:24 / / /
DATA_RD1
23:0 R 0x0 Data read on 8080 bus, without a new read operation on 8080
bus.
5.1.6.19 0x0084 LCD LVDS Interface Register (Default Value: 0x0000_0000)
Offset: 0x0084 Register Name: LCD_LVDS_IF_REG
Bit Read/Write Default/Hex Description
LCD_LVDS_EN
Enable LVDS interface
31 R/W 0
0: Disable
1: Enable
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Offset: 0x0084 Register Name: LCD_LVDS_IF_REG
Bit Read/Write Default/Hex Description
LCD_LVDS_LINK
Select work in single link mode or dual link mode
30 R/W 0
0: Single link
1: Dual link
LCD_LVDS_EVEN_ODD_DIR
Set the order of even field and odd field
29 R/W 0
0: normal
1: reverse
LCD_LVDS_DIR
Set the LVDS direction
28 R/W 0
0: Normal
1: Reverse
LCD_LVDS_MODE
Set the LVDS data mode
27 R/W 0
0: NS mode
1: JEIDA mode
LCD_LVDS_BITWIDTH
Set the bit width of data
26 R/W 0
0: 24-bit
1: 18-bit
LCD_LVDS_DEBUG_EN
Enable LVDS debug function
25 R/W 0
0: Disable
1: Enable
LCD_LVDS_DEBUG_MODE
Set the output signal in debug mode
24 R/W 0
0: Mode0—Random data
1: Mode1—Output CLK period=7/2 LVDS CLK period
LCD_LVDS_CORRECT_MODE
Set the LVDS correct mode
23 R/W 0
0: Mode0
1: Mode1
22:21 / / /
LCD_LVDS_CLK_SEL
Select the clock source of LVDS
20 R/W 0
0: Reserved
1: LCD CLK
19:5 / / /
LCD_LVDS_CLK_POL
Set the clock polarity of LVDS
4 R/W 0
0: Reverse
1: Normal
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Offset: 0x0084 Register Name: LCD_LVDS_IF_REG
Bit Read/Write Default/Hex Description
LCD_LVDS_DATA_POL
Set the data polarity of LVDS
3:0 R/W 0
0: Reverse
1: Normal
5.1.6.20 0x0088 LCD IO Polarity Register (Default Value: 0x0000_0000)
Offset: 0x0088 Register Name: LCD_IO_POL_REG
Bit Read/Write Default/Hex Description
IO_OUTPUT_SEL
When it is set as ‘1’, the d[23:0], io0, io1, io3 are sync to dclk.
31 R/W 0x0
0: Normal output
1: Register output
DCLK_SEL
Set the phase offset of clock and data in hv mode.
000: Used DCLK0 (normal phase offset)
001: Used DCLK1 (1/3 phase offset)
30:28 R/W 0x0
010: Used DCLK2 (2/3 phase offset)
100: DCLK0/2 phase 0
101: DCLK0/2 phase 90
Others: Reserved
IO3_INV
Enable invert function of IO3
27 R/W 0x0
0: Not invert
1: Invert
IO2_INV
Enable invert function of IO2
26 R/W 0x0
0: Not invert
1: Invert
IO1_INV
Enable invert function of IO1
25 R/W 0x0
0: Not invert
1: Invert
IO0_INV
Enable invert function of IO0
24 R/W 0x0
0: Not invert
1: Invert
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Offset: 0x0088 Register Name: LCD_IO_POL_REG
Bit Read/Write Default/Hex Description
Data_INV
LCD output port D[23:0] polarity control, with independent bit
23:0 R/W 0x0 control.
0: Normal polarity
1: Invert the specify output
5.1.6.21 0x008C LCD IO Control Register (Default Value: 0x0FFF_FFFF)
Offset: 0x008C Register Name: LCD_IO_TRI_REG
Bit Read/Write Default/Hex Description
31:29 / / /
RGB_ENDIAN
Set the endian of data bits
28 R/W 0x0
0: Normal
1: Bits_invert
IO3_OUTPUT_TRI_EN
Enable the output of IO3
27 R/W 0x1
1: Disable
0: Enable
IO2_OUTPUT_TRI_EN
Enable the output of IO2
26 R/W 0x1
1: Disable
0: Enable
IO1_OUTPUR_TRI_EN
Enable the output of IO1
25 R/W 0x1
1: Disable
0: Enable
IO0_OUTPUT_TRI_EN
Enable the output of IO0
24 R/W 0x1
1: Disable
0: Enable
DATA_OUTPUT_TRI_EN
LCD output port D[23:0] output enable, with independent bit
23:0 R/W 0xFFFFFF control.
1: Disable
0: Enable
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5.1.6.22 0x00FC LCD Debug Register (Default Value: 0x0000_0000)
Offset: 0x00FC Register Name: LCD_DEBUG_REG
Bit Read/Write Default/Hex Description
LCD_FIFO_UNDERFLOW
The flag shows whether the fifos in underflow status
31 R 0x0
0: Not underflow
1: Underflow
30 / / /
LCD_FIELD_POL
The flag indicates the current field polarity
29 R 0x0
0: Second field
1: First field
28 / / /
LCD_CURRENT_LINE
27:16 R 0x0
The current scan line
15:0 / / /
5.1.6.23 0x0100 LCD CEU Control Register (Default Value: 0x0000_0000)
Offset: 0x0100 Register Name: LCD_CEU_CTL_REG
Bit Read/Write Default/Hex Description
CEU_EN
Enable CEU function
31 R/W 0x0
0: Bypass
1: Enable
BT656_F_MASK
BT656 F Mask
30 R/W 0x0
0: Disable
1: Enable
BT656_F_MASK_VALUE
29 R/W 0x0
BT656 F Mask Value
28:0 / / /
5.1.6.24 0x0110+N*0x04 (N=0–10) LCD CEU Coefficient Register0 (Default Value: 0x0000_0000)
Offset: 0x0110+N*0x04 (N=0–10) Register Name: LCD_CEU_COEF_MUL_REG
Bit Read/Write Default/Hex Description
31:13 / / /
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Offset: 0x0110+N*0x04 (N=0–10) Register Name: LCD_CEU_COEF_MUL_REG
Bit Read/Write Default/Hex Description
CEU_COEF_MUL_VALUE
Signed 13-bit value, range of (-16,16).
N=0: Rr
N=1: Rg
N=2: Rb
12:0 R/W 0x0 N=4: Gr
N=5: Gg
N=6: Gb
N=8: Br
N=9: Bg
N=10: Bb
5.1.6.25 0x011C+N*0x10 (N=0–2) LCD CEU Coefficient Register1 (Default Value: 0x0000_0000)
Offset: 0x011C+N*0x10 (N=0–2) Register Name: LCD_CEU_COEF_ADD_REG
Bit Read/Write Default/Hex Description
31:19 / / /
CEU_COEF_ADD_VALUE
Signed 19-bit value, range of (-16384, 16384).
18:0 R/W 0x0 N=0: Rc
N=1: Gc
N=2: Bc
5.1.6.26 0x0140+N*0x04 (N=0–2) LCD CEU Coefficient Register2 (Default Value: 0x0000_0000)
Offset: 0x0140+N*0x04 (N=0–2) Register Name: LCD_CEU_COEF_RANG_REG
Bit Read/Write Default/Hex Description
31:24 / / /
CEU_COEF_RANGE_MIN
23:16 R/W 0x0
Unsigned 8-bit value, range of [0, 255].
15:8 / / /
CEU_COEF_RANGE_MAX
7:0 R/W 0x0
Unsigned 8-bit value, range of [0, 255].
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5.1.6.27 0x0160 LCD CPU Panel Trigger Register0 (Default Value: 0x0000_0000)
Offset: 0x0160 Register Name: LCD_CPU_TRI0_REG
Bit Read/Write Default/Hex Description
31:28 / / /
BLOCK_SPACE
27:16 R/W 0x0 The spaces between data blocks.
It should be set >20*pixel.
15:12 / / /
BLOCK_SIZE
11:0 R/W 0x0
The size of data block. It is usually set as X.
5.1.6.28 0x0164 LCD CPU Panel Trigger Register1 (Default Value: 0x0000_0000)
Offset: 0x0164 Register Name: LCD_CPU_TRI1_REG
Bit Read/Write Default/Hex Description
BLOCK_CURRENT_NUM
31:16 R 0x0
Shows the current data block transmitting to panel.
BLOCK_NUM
15:0 R/W 0x0
The number of data blocks. It is usually set as Y.
5.1.6.29 0x0168 LCD CPU Panel Trigger Register2 (Default Value: 0x0020_0000)
Offset: 0x0168 Register Name: LCD_CPU_TRI2_REG
Bit Read/Write Default/Hex Description
START_DLY
31:16 R/W 0x20
Tdly = (Start_Delay +1) * be_clk*8.
TRANS_START_MODE
Select the FIFOs used in CPU mode.
15 R/W 0x0
0: ECC_FIFO+TRI_FIFO
1: TRI_FIFO
SYNC_MODE
Set the sync mode in CPU interface.
14:13 R/W 0x0 0x: Auto
10: 0
11: 1
TRANS_START_SET
12:0 R/W 0x0
Usual set as the length of a line.
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5.1.6.30 0x016C LCD CPU Panel Trigger Register3 (Default Value: 0x0000_0000)
Offset: 0x016C Register Name: LCD_CPU_TRI3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
TRI_INT_MODE
When set as 01, the Tri_Counter_Int occurs in cycle of
(Count_N+1)×(Count_M+1)×4 dclk.
When set as 10 or 11, the io0 is map as TE input.
29:28 R/W 0x0
00: Disable
01: Counter mode
10: Te rising mode
11: Te falling mode
27:24 / / /
COUNTER_N
23:8 R/W 0x0
The value of counter factor
COUNTER_M
7:0 R/W 0x0
The value of counter factor
5.1.6.31 0x0170 LCD CPU Panel Trigger Register4 (Default Value: 0x0000_0000)
Offset: 0x0170 Register Name: LCD_CPU_TRI4_REG
Bit Read/Write Default/Hex Description
31:29 / / /
PLUG_MODE_EN
Enable the plug mode used in dsi command mode.
28 R/W 0x0
0: Disable
1: Enable
27:25 / / /
A1_First_Valid
24 R/W 0x0
Valid in first Block.
D23_TO_D0_First_Valid
23:0 R/W 0x0
Valid in first Block.
5.1.6.32 0x0174 LCD CPU Panel Trigger Register5 (Default Value: 0x0000_0000)
Offset: 0x0174 Register Name: LCD_CPU_TRI5_REG
Bit Read/Write Default/Hex Description
31:25 / / /
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Offset: 0x0174 Register Name: LCD_CPU_TRI5_REG
Bit Read/Write Default/Hex Description
A1_NON_First_Valid
24 R/W 0x0
Valid in Block except first.
D23_TO_D0_NON_First_Valid
23:0 R/W 0x0
Valid in Block except first.
5.1.6.33 0x0180 LCD Color Map Control Register (Default Value: 0x0000_0000)
Offset: 0x0180 Register Name: LCD_CMAP_CTL_REG
Bit Read/Write Default/Hex Description
COLOR_MAP_EN
Enable the color map function.
31 R/W 0x0 This module only works when X is divided by 4.
0: Bypass
1: Enable
30:1 / / /
OUT_FORMAT
Set the pixel output format in color map function.
0 R/W 0x0
0: 4 pixel output mode: Out0 -> Out1 -> Out2 -> Out3
1: 2 pixel output mode: Out0 -> Out1
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5.1.6.34 0x0190 LCD Color Map Odd Line Register0 (Default Value: 0x0000_0000)
Offset: 0x0190 Register Name: LCD_CMAP_ODD0_REG
Bit Read/Write Default/Hex Description
OUT_ODD1
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
31:16 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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Offset: 0x0190 Register Name: LCD_CMAP_ODD0_REG
Bit Read/Write Default/Hex Description
OUT_ODD0
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
15:0 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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5.1.6.35 0x0194 LCD Color Map Odd Line Register1 (Default Value: 0x0000_0000)
Offset: 0x0194 Register Name: LCD_CMAP_ODD1_REG
Bit Read/Write Default/Hex Description
OUT_ODD3
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
31:16 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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Offset: 0x0194 Register Name: LCD_CMAP_ODD1_REG
Bit Read/Write Default/Hex Description
OUT_ODD2
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
15:0 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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5.1.6.36 0x0198 LCD Color Map Even Line Register0 (Default Value: 0x0000_0000)
Offset: 0x0198 Register Name: LCD_CMAP_EVEN0_REG
Bit Read/Write Default/Hex Description
OUT_EVEN1
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
31:16 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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Offset: 0x0198 Register Name: LCD_CMAP_EVEN0_REG
Bit Read/Write Default/Hex Description
OUT_EVEN0
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
15:0 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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5.1.6.37 0x019C LCD Color Map Even Line Register1 (Default Value: 0x0000_0000)
Offset: 0x019C Register Name: LCD_CMAP_EVEN1_REG
Bit Read/Write Default/Hex Description
OUT_EVEN3
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
31:16 R/W 0x0
0101: in_g1
0110: in_r1
0111:Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
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Offset: 0x019C Register Name: LCD_CMAP_EVEN1_REG
Bit Read/Write Default/Hex Description
OUT_EVEN2
Indicates the output order of components.
bit15-12: Reserved
bit11-08: Out_Odd0[23:16]
bit07-04: Out_Odd0[15:8]
bit03-00: Out_Odd0[7:0]
0000: in_b0
0001: in_g0
0010: in_r0
0011: Reserved
0100: in_b1
15:0 R/W 0x0
0101: in_g1
0110: in_r1
0111: Reserved
1000: in_b2
1001: in_g2
1010: in_r2
1011: Reserved
1100: in_b3
1101: in_g3
1110: in_r3
1111: Reserved
5.1.6.38 0x01F0 LCD Safe Period Register (Default Value: 0x0000_0000)
Offset: 0x01F0 Register Name: LCD_SAFE_PERIOD_REG
Bit Read/Write Default/Hex Description
31:29 / / /
SAFE_PERIOD_FIFO_NUM
When the data length in line buffer is more than
28:16 R/W 0x0
SAFE_PERIOD_FIFO_NUM, the LCD controller will allow dram
controller to stop working to change frequency.
SAFE_PERIOD_LINE
Set a fixed line and during the line time, the LCD controller allow
15:4 R/W 0x0
dram controller to change frequency. The fixed line should be
set in the blanking area.
3 / / /
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Offset: 0x01F0 Register Name: LCD_SAFE_PERIOD_REG
Bit Read/Write Default/Hex Description
SAFE_PERIOD_MODE
Select the save mode
000: unsafe
2:0 R/W 0x0 001: safe
010: safe at FIFO_CURR_NUM > SAFE_PERIOD_FIFO_NUM
011: safe at 2 and safe at sync active
100: safe at line
5.1.6.39 0x0220 LCD LVDS Analog Register0 (Default Value: 0x0000_0000)
Offset: 0x0220 Register Name: LCD_LVDS_ANA0_REG
Bit Read/Write Default/Hex Description
LVDS_EN_MB
Enable the bias circuit of the LVDS_Ana module.
31 R/W 0x0
0: Disable
1: Enable
30 R/W 0x0 Reserved
EN_LVDS
29 R/W 0x0
Enable LVDS
EN_24M
28 R/W 0x0
Enable the 24M clock
27:25 / / /
LVDS_HPREN_DRVC
Enable clock channel drive
24 R/W 0x0
0: Disable
1: Enable
LVDS_HPREN_DRV
Enable data channel[3:0] drive
23:20 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0220 Register Name: LCD_LVDS_ANA0_REG
Bit Read/Write Default/Hex Description
LVDS_REG_C
Adjust current flowing through Rload of Rx to change the
differential signals amplitude.
000: 216 mV
001: 252 mV
19:17 R/W 0x0 010: 276 mV
011: 312 mV
100: 336 mV
101: 372 mV
110: 395 mV
111: 432 mV
LVDS_REG_DENC
16 R/W 0x0
Choose data output or PLL test clock output in LVDS_tx.
LVDS_REG_DEN
15:12 R/W 0x0
Choose data output or PLL test clock output in LVDS_tx.
11 / / /
LVDS_REG_R
Adjust current flowing through Rload of Rx to change the
common signals amplitude.
000: 0.925 V
001: 0.950 V
10:8 R/W 0x0 010: 0.975 V
011: 1.000 V
100: 1.025 V
101: 1.050 V
110: 1.075 V
111: 1.100 V
7:5 / / /
LVDS_REG_PLRC
LVDS clock channel direction.
4 R/W 0x0
0: Normal
1: Reverse
LVDS_REG_PLR
LVDS data channel [3:0] direction.
3:0 R/W 0x0
0: Normal
1: Reverse
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5.1.6.40 0x0228 LCD FSYNC Generate Control Register (Default Value: 0x0000_0000)
Offset: 0x0228 Register Name: FSYNC_GEN_CTRL_REG
Bit Read/Write Default/Hex Description
31:19 / / /
SENSOR_DIS_TIME
Delay 0–2047 Hsync Period
18:8 R/W 0x0
When hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.
When hsync_pol_sel is 1, the actual delay is sensor_dis_time.
7 / / /
SENSOR_ACT1_VALUE
Sensor Active1 Value
6 R/W 0x0
0: Fsync active_1 period output 0
1: Fsync active_1 period output 1
SENSOR_ACT0_VALUE
Sensor Active0 Value
5 R/W 0x0
0: Fsync active_0 period output 0
1: Fsync active_0 period output 1
SENSOR_DIS_VALUE
Sensor Disable Value
4 R/W 0x0
0: Fsync disable period output 0
1: Fsync disable period output 1
3 / / /
HSYNC_POL_SEL
Hsync Polarity Select
2 R/W 0x0
0: Normal
1: Opposite hsync to hysnc counter
SEL_VSYNC_EN
Select Vsync Enable
1 R/W 0x0
0: Select vsync falling edge to start state machine
1: Select vsync rising edge to start state machine
FSYNC_GEN_EN
Fsync Generate Enable
0 R/W 0x0
0: Disable
1: Enable
5.1.6.41 0x022C LCD FSYNC Generate Delay Register (Default Value: 0x0000_0000)
Offset: 0x022C Register Name: FSYNC_GEN_DLY_REG
Bit Read/Write Default/Hex Description
31:28 / / /
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Offset: 0x022C Register Name: FSYNC_GEN_DLY_REG
Bit Read/Write Default/Hex Description
SENSOR_ACT0_TIME
27:16 R/W 0x0 Delay 0–4095 Pixel clk Period
The actual delay is sensor_act0_time+1.
15:12 / / /
SENSOR_ACT1_TIME
11:0 R/W 0x0 Delay 0–4095 Pixel clk Period
The actual delay is sensor_act1_time+1.
5.1.6.42 0x0230 LCD Sync Control Register (Default Value: 0x0000_0000)
Offset: 0x0230 Register Name: LCD_SYNC_CTL_REG
Bit Read/Write Default/Hex Description
31:9 / / /
LCD_CTRL_WORK_MODE
LCD Controller Work mode
8 R/W 0x0
0: Single DSI mode
1: Dual DSI mode
7:5 / / /
LCD_CYRL_SYNC_MASTER_SLAVE
LCD Controller Sync Master Slave
4 R/W 0x0 0: Master
1: Slave
Note: Only use in Single DSI mode.
3:1 / / /
LCD_CTRL_SYNC_MODE
LCD Controller Sync Mode
0 R/W 0x0 0: Sync in the first time
1: Sync every frame
Note: Only use in Single DSI mode.
5.1.6.43 0x0234 LCD Sync Position Register (Default Value: 0x0000_0000)
Offset: 0x0234 Register Name: LCD_SYNC_POS_REG
Bit Read/Write Default/Hex Description
31:28 / / /
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Offset: 0x0234 Register Name: LCD_SYNC_POS_REG
Bit Read/Write Default/Hex Description
LCD_Sync_Pixel_Num
Set the pixel number of master LCD controller which is used to
trigger the slave LCD controller to start working.This value is the
number of pixels between the trigger point and the end of the
27:16 R/W 0x0
line.
Tri pos =
Tline*LCD_Sync_Line_Num+Tpixel*(HT-LCD_Sync_Pixel_Num)
Note: Only use in Single DSI mode.
15:12 / / /
LCD_Sync_Line_Num
Set the line number of master LCD controller which is used to
trigger the slave LCD controller to start working.
Note:It is only set in master LCD controller.It is not necessarily
11:0 R/W 0x0
to set in slave LCD controller.
Tri pos =
Tline*LCD_Sync_Line_Num+Tpixel*(HT-LCD_Sync_Pixel_Num)
Note: Only use in Single DSI mode.
5.1.6.44 0x0238 LCD Slave Stop Position Register (Default Value: 0x0000_0000)
Offset: 0x0238 Register Name: LCD_SLAVE_STOP_POS_REG
Bit Read/Write Default/Hex Description
31:8 / / /
STOP_VAL
Set the stop position of the slave LCD. This value is the number
of pixels between the stop position and the end of the HFP.
7:0 R/W 0x0
Stop_pos = HFP - Stop_val.
0<Stop_pos<HFP-2
Note: Only use in Single DSI mode.
5.1.6.45 0x0400-0x07FF LCD Gamma Table Registers (Default Value: 0x0000_0000)
Offset: 0x0400–0x07FF Register Name: LCD_GAMMA_TABLE_REG
Bit Read/Write Default/Hex Description
31:24 / / /
RED_COMP
23:16 R/W 0x0
Red Component
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Offset: 0x0400–0x07FF Register Name: LCD_GAMMA_TABLE_REG
Bit Read/Write Default/Hex Description
GREEN_COMP
15:8 R/W 0x0
Green Component
BLUE_COMP
7:0 R/W 0x0
Blue Component
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5.2 TCON TV
5.2.1 Overview
The Timing Controller_TV (TCON_TV) is a module that processes video signals received from systems using a
complicated arithmetic and then generates control signals and transmits them to the TV panel driver IC.
The TCON_TV includes the following features:
Supports 10-bit pixel depth YUV444, and HV format output up to 4K@60Hz
Supports 8-bit pixel depth YUV444, and HV format output up to 4K@60Hz
5.2.2 Functional Description
5.2.2.1 CEU Module
Function: This module enhance color data from DE .
R’ = Rr*R + Rg*G + Rb*B
G’ = Gr*R + Gg*G + Gb*B
B’ = Br*R + Bg*G + Bb*B
Rr, Rg, Rb, ,Gr, Gg, Gb, Br, Bg, Bb bool 0,1
R, G, B u10 [0-1023]
R’ have the range of [Rmin, Rmax]
G’ have the range of [Rmin, Rmax]
B’ have the range of [Rmin, Rmax]
5.2.3 Register List
Module Name Base Address
TCON_TV0 0x05470000
Register Name Offset Description
TV_GCTL_REG 0x0000 TV Global Control Register
TV_GINT0_REG 0x0004 TV Global Interrupt Register0
TV_GINT1_REG 0x0008 TV Global Interrupt Register1
TV_SRC_CTL_REG 0x0040 TV Source Control Register
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Register Name Offset Description
TV_CTL_REG 0x0090 TV Control Register
TV_BASIC0_REG 0x0094 TV Basic Timing Register0
TV_BASIC1_REG 0x0098 TV Basic Timing Register1
TV_BASIC2_REG 0x009C TV Basic Timing Register2
TV_BASIC3_REG 0x00A0 TV Basic Timing Register3
TV_BASIC4_REG 0x00A4 TV Basic Timing Register4
TV_BASIC5_REG 0x00A8 TV Basic Timing Register5
TV_IO_POL_REG 0x0088 TV SYNC Signal Polarity Register
TV_IO_TRI_REG 0x008C TV SYNC Signal IO Control Register
TV_DEBUG_REG 0x00FC TV Debug Register
TV_CEU_CTL_REG 0x0100 TV CEU Control Register
TV_CEU_COEF_MUL_REG 0x0110+N*0x04(N=0–10) TV CEU Coefficient Register0
TV_CEU_COEF_RANG_REG 0x0140+N*0x04(N=0–2) TV CEU Coefficient Register2
TV_SAFE_PERIOD_REG 0x01F0 TV Safe Period Register
TV_FILL_CTL_REG 0x0300 TV Fill Data Control Register
TV_FILL_BEGIN_REG 0x0304+N*0x0C(N=0–2) TV Fill Data Begin Register
TV_FILL_END_REG 0x0308+N*0x0C(N=0–2) TV Fill Data End Register
TV_FILL_DATA_REG 0x030C+N*0x0C(N=0–2) TV Fill Data Value Register
TV_DATA_IO_POL0_REG 0x0330 TCON Data IO Polarity Control0
TV_DATA_IO_POL1_REG 0x0334 TCON Data IO Polarity Control1
TV_DATA_IO_TRI0_REG 0x0338 TCON Data IO Enable Control0
TV_DATA_IO_TRI1_REG 0x033C TCON Data IO Enable Control1
TV_PIXELDEPTH_MODE_REG 0x0340 TV Pixeldepth Mode Control Register
5.2.4 Register Description
5.2.4.1 0x0000 TV Global Control Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TV_GCTL_REG
Bit Read/Write Default/Hex Description
TV_EN
When it is disabled, the module will be reset to idle state.
31 R/W 0x0
0: Disable
1: Enable
30:2 / / /
CEC_DDC_PAD_SEL
CEC DDC PAD Select
1 R/W 0x0
1: TCON_TV internal pad for cec scl sal
0: GPIO pad for cec scl sal
0 / / /
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5.2.4.2 0x0004 TV Global Interrupt Register0 (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: TV_GINT0_REG
Bit Read/Write Default/Hex Description
31 / / /
TV_VB_INT_EN
TV Vb Interrupt Enable
30 R/W 0x0
0: Disable
1: Enable
29 / / /
TV_Line_Int_En
TV Line Interrupt Enable
28 R/W 0x0
0: Disable
1: Enable
27:15 / / /
TV_VB_INT_FLAG
TV Vb Interrupt Flag
14 R/W 0x0
Asserted during vertical no-display period every frame.
Write 0 to clear it.
13 / / /
TV_Line_Int_Flag
TV Line Interrupt Flag
12 R/W 0x0
Trigger when SY1 match the current TV scan line
Write 0 to clear it.
11:0 / / /
5.2.4.3 0x0008 TV Global Interrupt Register1 (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: TV_GINT1_REG
Bit Read/Write Default/Hex Description
31:12 / / /
TV_Line_Int_Num
Scan line for TV line trigger(including inactive lines)
11:0 R/W 0
Setting it for the specified line for trigger 1.
Note: SY1 is writable only when LINE_TRG1 is disabled.
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5.2.4.4 0x0040 TV Source Control Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: TV_SRC_CTL_REG
Bit Read/Write Default/Hex Description
31:3 / / /
TV_SRC_SEL
TV Source Select
000: DE
001: Color Check
2:0 R/W 0 010: Grayscale Check
011: Black by White Check
100: Reserved
101: Reserved
111: Gridding Check
5.2.4.5 0x0090 TV Control Register (Default Value: 0x0000_0000)
Offset: 0x0090 Register Name: TV_CTL_REG
Bit Read/Write Default/Hex Description
TV_EN
When enable TCON_TV, this bit and the 0x0000[bit31] need to
31 R/W 0x0 be enabled.
0: Disable
1: Enable
30:9 / / /
START_DELAY
8:4 R/W 0x0
This is for DE0 and DE1.
3:2 / / /
TV_SRC_SEL
TV Source Select
0: Reserved
1 R/W 0x0
1: BLUE data
Note: The priority of this bit is higher than
TV_SRC_SEL(bit[2:0]) in TV_SRC_CTL_REG.
0 / / /
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5.2.4.6 0x0094 TV Basic Timing Register0 (Default Value: 0x0000_0000)
Offset: 0x0094 Register Name: TV_BASIC0_REG
Bit Read/Write Default/Hex Description
31:28 / / /
WIDTH_XI
27:16 R/W 0x0
Source Width Is X+1
15:12 / / /
HEIGHT_YI
11:0 R/W 0x0
Source Height Is Y+1
5.2.4.7 0x0098 TV Basic Timing Register1 (Default Value: 0x0000_0000)
Offset: 0x0098 Register Name: TV_BASIC1_REG
Bit Read/Write Default/Hex Description
31:28 / / /
LS_XO
27:16 R/W 0x0
Width Is LS_XO+1
15:12 / / /
LS_YO
11:0 R/W 0x0 Width Is LS_YO+1
Note: This version LS_YO = TV_YI
5.2.4.8 0x009C TV Basic Timing Register2 (Default Value: 0x0000_0000)
Offset: 0x009C Register Name: TV_BASIC2_REG
Bit Read/Write Default/Hex Description
31:28 / / /
TV_XO
27:16 R/W 0x0
Width is TV_XO+1
15:12 / / /
TV_YO
11:0 R/W 0x0
Height is TV_YO+1
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5.2.4.9 0x00A0 TV Basic Timing Register3 (Default Value: 0x0000_0000)
Offset: 0x00A0 Register Name: TV_BASIC3_REG
Bit Read/Write Default/Hex Description
31:29 / / /
H_T
28:16 R/W 0x0 Horizontal total time
Thcycle = (HT+1) * Thdclk
15:12 / / /
H_BP
11:0 R/W 0x0 Horizontal back porch
Thbp = (HBP +1) * Thdclk
5.2.4.10 0x00A4 TV Basic Timing Register4 (Default Value: 0x0000_0000)
Offset: 0x00A4 Register Name: TV_BASIC4_REG
Bit Read/Write Default/Hex Description
31:29 / / /
V_T
28:16 R/W 0x0 horizontal total time (in HD line)
Tvt = VT/2 * Th
15:12 / / /
V_BP
11:0 R/W 0x0 horizontal back porch (in HD line)
Tvbp = (VBP +1) * Th
5.2.4.11 0x00A8 TV Basic Timing Register5 (Default Value: 0x0000_0000)
Offset: 0x00A8 Register Name: TV_BASIC5_REG
Bit Read/Write Default/Hex Description
31:26 / / /
H_SPW
Horizontal Sync Pulse Width (in dclk)
25:16 R/W 0x0
Thspw = (HSPW+1) * Tdclk
Note: HT> (HSPW+1)
15:10 / / /
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Offset: 0x00A8 Register Name: TV_BASIC5_REG
Bit Read/Write Default/Hex Description
V_SPW
Vertical Sync Pulse Width (in lines)
9:0 R/W 0x0
Tvspw = (VSPW+1) * Th
Note: VT/2 > (VSPW+1)
5.2.4.12 0x0088 TV SYNC Signal Polarity Register (Default Value: 0x0000_0000)
Offset: 0x0088 Register Name: TV_IO_POL_REG
Bit Read/Write Default/Hex Description
31:28 / / /
IO3_INV
IO3 Invert
27 R/W 0x0
0: Not invert
1: Invert
IO2_INV
IO2 Invert
26 R/W 0x0
0: Not invert
1: Invert
IO1_INV
IO1 Invert
25 R/W 0x0
0: Not invert
1: Invert
IO0_INV
IO0 Invert
24 R/W 0x0
0: Not invert
1: Invert
23:0 / / /
5.2.4.13 0x008C TV SYNC Signal IO Control Register (Default Value: 0x0F00_0000)
Offset: 0x008C Register Name: TV_IO_TRI_REG
Bit Read/Write Default/Hex Description
31:28 / / /
IO3_OUTPUT_TRI_EN
IO3 Output Trigger Enable
27 R/W 0x1
1: Disable
0: Enable
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Offset: 0x008C Register Name: TV_IO_TRI_REG
Bit Read/Write Default/Hex Description
IO2_OUTPUT_TRI_EN
IO2 Output Trigger Enable
26 R/W 0x1
1: Disable
0: Enable
IO1_OUTPUT_TRI_EN
IO1 Output Trigger Enable
25 R/W 0x1
1: Disable
0: Enable
IO0_OUTPUT_TRI_EN
IO0 Output Trigger Enable
24 R/W 0x1
1: Disable
0: Enable
23:0 / / /
5.2.4.14 0x00FC TV Debug Register (Default Value: 0x0000_0000)
Offset: 0x00FC Register Name: TV_DEBUG_REG
Bit Read/Write Default/Hex Description
31 / / /
TV_FIFO_U
30 R/W 0x0
TV FIFO Underflow
29 / / /
TV_FIELD_POL
TV Field Polarity
28 R 0x0
0: Second field
1: First field
27:12 / / /
LINE_BUF_BYPASS
Line Buffer Bypass
13 R/W 0x0
0: Used
1: Bypass
12 / / /
TV_CURRENT_LINE
11:0 R 0x0
TV Current Line
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5.2.4.15 0x0100 TV CEU Control Register (Default Value: 0x0000_0000)
Offset: 0x0100 Register Name: TV_CEU_CTL_REG
Bit Read/Write Default/Hex Description
CEU_EN
CEU Enable
31 R/W 0x0
0: Bypass
1: Enable
30:0 / / /
5.2.4.16 0x0110+N*0x04 (N=0–10) TV CEU Coefficient Register0 (Default Value: 0x0000_0000)
Offset: 0x110+N*0x04 (N=0–10) Register Name: TV_CEU_COEF_MUL_REG
Bit Read/Write Default/Hex Description
31:9 / / /
CEU_COEF_MUL_VALUE
Note:
1. CEU_Coef_Mul_Value only can be 0 or 1.
2. REG Map:
N=0: Rr
N=1: Rg
8 R/W 0x0 N=2: Rb
N=4: Gr
N=5: Gg
N=6: Gb
N=8: Br
N=9: Bg
N=10: Bb
7:0 / / /
5.2.4.17 0x0140+N*0x04 (N=0–2) TV CEU Coefficient Register2 (Default Value: 0x0000_0000)
Offset: 0x0140+N*0x04 (N=0–2) Register Name: TV_CEU_COEF_RANG_REG
Bit Read/Write Default/Hex Description
31:26 / / /
CEU_COEF_RANGE_MIN
25:16 R/W 0
Unsigned 10-bit Value, range of [0, 1023]
15:10 / / /
CEU_COEF_RANGE_MAX
9:0 R/W 0
Unsigned 10-bit Value, range of [0, 1023]
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5.2.4.18 0x01F0 TV Safe Period Register (Default Value: 0x0000_0000)
Offset: 0x01F0 Register Name: TV_SAFE_PERIOD_REG
Bit Read/Write Default/Hex Description
31:29 / / /
SAFE_PERIOD_FIFO_NUM
28:16 R/W 0x0
Safe Period FIFO Number
Safe_Period_Line
15:4 R/W 0x0
Safe Period Line
3 / / /
Safe_Period_Mode
Safe Period Mode
000: unsafe
2:0 R/W 0x0 001: safe
010: safe at line_buf_curr_num > safe_period_fifo_num
011: safe at 2 and safe at sync active
100: safe at line
5.2.4.19 0x0300 TV Fill Data Control Register (Default Value: 0x0000_0000)
Offset: 0x0300 Register Name: TV_FILL_CTL_REG
Bit Read/Write Default/Hex Description
TV_Fill_En
TV Fill Enable
31 R/W 0x0
0: Bypass
1: Enable
30:0 / / /
5.2.4.20 0x0304+N*0x0C (N=0–2) TV Fill Data Begin Register (Default Value: 0x0000_0000)
Offset: 0x0304+N*0x0C (N=0–2) Register Name: TV_FILL_BEGIN_REG
Bit Read/Write Default/Hex Description
31:24 / / /
FILL_BEGIN
23:0 R/W 0
Fill Begin
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5.2.4.21 0x0308+N*0x0C (N=0–2) TV Fill Data End Register (Default Value: 0x0000_0000)
Offset: 0x0308+N*0x0C (N=0–2) Register Name: TV_FILL_END_REG
Bit Read/Write Default/Hex Description
31:24 / / /
FILL_END
23:0 R/W 0x0
Fill End
5.2.4.22 0x030C+N*0x0C (N=0–2) TV Fill Data Value Register (Default Value: 0x0000_0000)
Offset: 0x030C+N*0x0C (N=0–2) Register Name: TV_FILL_DATA_REG
Bit Read/Write Default/Hex Description
31:30 / / /
FILL_VALUE
29:0 R/W 0x0
Fill Value
5.2.4.23 0x0330 TCON Data IO Polarity Control0 (Default Value: 0x0000_0000)
Offset: 0x0330 Register Name: TV_DATA_IO_POL0_REG
Bit Read/Write Default/Hex Description
31:26 / / /
R_CB_CH_DATA_INV
R CB Channel Data Inv
25:16 R/W 0x0
0: normal polarity
1: invert the specify output
15:10 / / /
G_Y_CH_DATA_INV
G Y Channel Data Inv
9:0 R/W 0x0
0: normal polarity
1: invert the specify output
5.2.4.24 0x0334 TCON Data IO Polarity Control1 (Default Value: 0x0000_0000)
Offset: 0x0334 Register Name: TV_DATA_IO_POL1_REG
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x0334 Register Name: TV_DATA_IO_POL1_REG
Bit Read/Write Default/Hex Description
B_CR_CH_DATA_INV
B CR CHANNE DATA INV
25:16 R/W 0x0
0: Normal polarity
1: Invert the specify output
15:0 / / /
5.2.4.25 0x0338 TCON Data IO Enable Control0 (Default Value: 0x03FF_03FF)
Offset: 0x0338 Register Name: TV_DATA_IO_TRI0_REG
Bit Read/Write Default/Hex Description
31:26 / / /
R_CB_CH_DATA_OUT_TRI_EN
R CB Channel Data Output Trigger Enable
25:16 R/W 0x3ff
1: Disable
0: Enable
15:10 / / /
G_Y_CH_DATA_OUT_TRI_EN
G Y Channel Data Output Trigger Enable
9:0 R/W 0x3ff
1: Disable
0: Enable
5.2.4.26 0x033C TCON Data IO Enable Control1 (Default Value: 0x03FF_0000)
Offset: 0x033C Register Name: TV_DATA_IO_TRI1_REG
Bit Read/Write Default/Hex Description
31:26 / / /
B_CR_CH_DATA_OUT_TRI_EN
B CR Channel Data Output Trigger Enable
25:16 R/W 0x3ff
1: Disable
0: Enable
15:0 / / /
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5.2.4.27 0x0340 TV Pixeldepth Mode Control Register (Default Value: 0x0000_0000)
Offset: 0x0340 Register Name: TV_PIXELDEPTH_MODE_REG
Bit Read/Write Default/Hex Description
31:1 / / /
COLORBAR_PD_MODE
Colorbar Pixeldepth mode
0: 8-bit mode
When data source is the embedded colorbar, the 8-bit colorbar
0 R/W 0x0
pattern is transmitted.
1: 10-bit mode
When data source is the embedded colorbar, the 10-bit
colorbar pattern is transmitted.
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5.3 TV Encoder
5.3.1 Overview
The TV Encoder (TVE) module is a highly programmable digital video encoder supporting worldwide video
standards Composite Video Broadcast Signal (CVBS).
The TVE includes the following features:
1-channel CVBS output, supporting PAL-D and NTSC-M
Plug status auto detecting
10 bits DAC output
5.3.2 Block Diagram
Figure 5-14 shows a block diagram of the TVE.
Figure 5-14 TVE Block Diagram
digital analog
De-
Y noise
Peaking Y LPF1 DELAY Y
SIN Up DAC
CVBS
U LPF2 sample 10bit 216MSPS
De-flick
C
U DELAY
V LPF2
Burst
V DELAY COS
Plug Detect
DDFS
5.3.3 Functional Description
5.3.3.1 External Signals
Table 5-11 describes the external signals of TVE.
Table 5-11 TVE External Signals
Port Name Description Type
TVOUT0 TV CVBS output AO
VCC-TVOUT TV DAC power P
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5.3.3.2 Clock Sources
The TVE module requires one clock with 50% duty. Digital circuit and Analog circuit work by this clock. Mode
and Clock frequency is shown below.
Table 5-12 TVE Clock Sources
Mode TVE Clock Frequency
NTSC 216 MHz
PAL 216 MHz
5.3.3.3 Auto Detection Function
Figure 5-15 Auto Detection Function
Insert DAC
Pulse cycle
Detect Status Filter Detect Signal time
75R 75R
comparator
Pulse
Start
Ref voltage
Pull out DAC
Detect Status Filter Detect Signal
75R 75R
comparator
Ref voltage
DAC outputs constant current, when insert, external load is 37.5Ω; when pull out, external load is 75Ω. The
method that comparator judges pin level can detect plug action.
Because plug action may exist jitter, then there need be a filter to filter jitter, the debounce time of filter is set
through the bit[3:0] of TV Encoder Auto Detection de-bounce Setting Register.
The pulse cycle time can be set through the bit[30:16] of TV Encoder Auto Detect Configuration Register1, the
pulse start time can be set through the bit[14:0] of TV Encoder Auto Detect Configuration Register1. The clock
sources of the two time are 32KHz clock.
Pulse width is cycle time of 4 clock sources.
Pulse amplitude can be set through the bit[9:0] of TV Encoder Auto Detect Configuration Register0.
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5.3.3.4 DAC Calibration Function
Figure 5-16 DAC Calibration Function
EFUSE
BIAS Current
Generator
……
10 switch
Get Value (10 bits) to
control switchs
DAC Vout
37.5R
After FT, 10-bit calibration value is burned into efuse. Every time software can read the 10-bit calibration value
from efuse, to control BIAS current and BIAS current switch, then a specific BIAS current is generated to
calibrate maximum output voltage of DAC.
5.3.4 Programming Guidelines
5.3.4.1 Operating TVE Module
Operate TVE module by the following steps, Figure 5-17 shows the process diagram.
Step 1 Set CCU clock source for TVE, and release AHB bus, and module reset.
Step 2 Initial DAC amplitude value from efuse calibration value which has burned.
Step 3 Enable the plug-in detect function, and detect plug-in status every 200 ms.
Step 4 When the plug-in has detected, configure TVE module to output mode setting by application.
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Figure 5-17 Operating TVE Module
Set clock Release reset
Initial DAC and TVE
Enable Plug-In Detection
Delay 200 ms
No
Plug-In？
Yes
Configure TVE output
5.3.5 Register List
Module Name Base Address
TVE_TOP 0x05600000
TVE 0x05604000
Register Name Offset Description
TVE_TOP
TVE_DAC_MAP 0x0020 TV Encoder DAC MAP Register
TVE_DAC_STATUS 0x0024 TV Encoder DAC STAUTS Register
TVE_DAC_CFG0 0x0028 TV Encoder DAC CFG0 Register
TVE_DAC_CFG1 0x002C TV Encoder DAC CFG1 Register
TVE_DAC_CFG2 0x0030 TV Encoder DAC CFG2 Register
TVE_DAC_CFG3 0x0034 TV Encoder DAC CFG2 Register
TVE_DAC_TEST 0x00F0 TV Encoder DAC TEST Register
TVE
TVE_000_REG 0x0000 TV Encoder Clock Gating Register
TVE_004_REG 0x0004 TV Encoder Configuration Register
TVE_008_REG 0x0008 TV Encoder DAC Register1
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Register Name Offset Description
TVE_00C_REG 0x000C TV Encoder Notch and DAC Delay Register
TVE_010_REG 0x0010 TV Encoder Chroma Frequency Register
TVE_014_REG 0x0014 TV Encoder Front/Back Porch Register
TVE_018_REG 0x0018 TV Encoder HD Mode VSYNC Register
TVE_01C_REG 0x001C TV Encoder Line Number Register
TVE_020_REG 0x0020 TV Encoder Level Register
TVE_024_REG 0x0024 TV Encoder DAC Register2
TVE_030_REG 0x0030 TV Encoder Auto Detection Enable Register
TV Encoder Auto Detection Interrupt Status
TVE_034_REG 0x0034
Register
TVE_038_REG 0x0038 TV Encoder Auto Detection Status Register
TV Encoder Auto Detection De-bounce Setting
TVE_03C_REG 0x003C
Register
TVE_0F8_REG 0x00F8 TV Encoder Auto Detect Configuration Register0
TVE_0FC_REG 0x00FC TV Encoder Auto Detect Configuration Register1
TV Encoder Color Burst Phase Reset
TVE_100_REG 0x0100
Configuration Register
TVE_104_REG 0x0104 TV Encoder VSYNC Number Register
TVE_108_REG 0x0108 TV Encoder Notch Filter Frequency Register
TVE_10C_REG 0x010C TV Encoder Cb/Cr Level/Gain Register
TVE_110_REG 0x0110 TV Encoder Tint and Color Burst Phase Register
TVE_114_REG 0x0114 TV Encoder Burst Width Register
TVE_118_REG 0x0118 TV Encoder Cb/Cr Gain Register
TVE_11C_REG 0x011C TV Encoder Sync and VBI Level Register
TVE_120_REG 0x0120 TV Encoder White Level Register
TVE_124_REG 0x0124 TV Encoder Video Active Line Register
TV Encoder Video Chroma BW and CompGain
TVE_128_REG 0x0128
Register
TVE_12C_REG 0x012C TV Encoder Register
TVE_130_REG 0x0130 TV Encoder Re-sync Parameters Register
TVE_134_REG 0x0134 TV Encoder Slave Parameter Register
TVE_138_REG 0x0138 TV Encoder Configuration Register0
TVE_13C_REG 0x013C TV Encoder Configuration Register1
TVE_380_REG 0x0380 TV Encoder Low Pass Control Register
TVE_384_REG 0x0384 TV Encoder Low Pass Filter Control Register
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Register Name Offset Description
TVE_388_REG 0x0388 TV Encoder Low Pass Gain Register
TVE_38C_REG 0x038C TV Encoder Low Pass Gain Control Register
TVE_390_REG 0x0390 TV Encoder Low Pass Shoot Control Register
TVE_394_REG 0x0394 TV Encoder Low Pass Coring Register
TVE_3A0_REG 0x03A0 TV Encoder Noise Reduction Register
5.3.6 TVE_TOP Register Description
5.3.6.1 0x0020 TV Encoder DAC MAP Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: TVE_DAC_MAP
Bit Read/Write Default/Hex Description
31:7 / / /
DAC_MAP
6:4 R/W 0x0 000: OUT0
Others: Reserved
3:2 / / /
DAC_SEL
00: Reserved
1:0 R/W 0x0 01: TVE0
10: Reserved
11: Reserved
5.3.6.2 0x0024 TV Encoder DAC Status Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: TVE_DAC_STATUS
Bit Read/Write Default/Hex Description
31:2 / / /
DAC_Status
00: Unconnected
1:0 R 0x0 01: Connected
11: Short to ground
10: Reserved
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5.3.6.3 0x0028 TV Encoder DAC Configuration0 Register (Default Value: 0x8000_4200)
Offset: 0x0028 Register Name: TVE_DAC_CFG0
Bit Read/Write Default/Hex Description
DAC_CLOCK_INVERT
31 R/W 0x1 0: Not invert
1: Invert
30:26 / / /
25:16 R/W 0x0 CALI_IN
LOW_BIAS
15:12 R/W 0x4
500 uA to 4 mA
11:10 / / /
BIAS_EXT_SEL
0: Disable
9 R/W 0x1
1: Enable
(A_SEL_BIAS_ADDA)
BIAS_INT_SEL
0: Disable
8 R/W 0x0
1: Enable
(A_SEL_BIAS_RES)
7:5 / / /
BIAS_REF_INT_EN
0: Disable
4 R/W 0x0
1: Enable
(A_EN_RESREF)
3:1 / / /
DAC_EN
0 R/W 0x0 0: Disable
1: Enable
5.3.6.4 0x002C TV Encoder DAC Configuration1 Register (Default Value: 0x0000_023A)
Offset: 0x002C Register Name: TVE_DAC_CFG1
Bit Read/Write Default/Hex Description
31:10 / / /
REF_EXT_SEL
9 R/W 0x1
0: Disable
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Offset: 0x002C Register Name: TVE_DAC_CFG1
Bit Read/Write Default/Hex Description
1: Enable
(A_SEL_DETREF_LDO)
REF_INT_SEL
0: Disable
8 R/W 0x0
1: Enable
(A_SEL_DETREF_RES)
7:6 / / /
REF2_SEL
00: 0.25 V
01: 0.30 V
5:4 R/W 0x3
10: 0.35 V
11: 0.40 V
(a_refslct2<1:0>)
REF1_SEL
0000: 0.50 V
0001: 0.55 V
0010: 0.60 V
0011: 0.65 V
0100: 0.70 V
0101: 0.75 V
0110: 0.80 V
0111: 0.85 V
3:0 R/W 0xA 1000: 0.90 V
1001: 0.95 V
1010: 1.00 V
1011: 1.05 V
1100: 1.10 V
1101: 1.15 V
1110: 1.20 V
1111: 1.25 V
(a_refslct1<3:0>)
The reference voltage is used for hot plug detect function.
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5.3.6.5 0x0030 TV Encoder DAC Configuration2 Register (Default Value: 0x0000_0010)
Offset: 0x0030 Register Name: TVE_DAC_CFG2
Bit Read/Write Default/Hex Description
31:13 / / /
AB
12:8 R/W 0x0
( I config output current for different peak voltage)
7:6 R/W 0x0 S2S1
5:0 R/W 0x10 R_SET
5.3.6.6 0x0034 TV Encoder DAC Configuration3 Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: TVE_DAC_CFG3
Bit Read/Write Default/Hex Description
31:26 / / /
FORCE_DATA_SET
25:16 R/W 0x0
Force DAC input data
15:1 / / /
FORCE_DATA_EN
0 R/W 0x0 0: DAC input data from TVE
1: DAC input data from FORCE_DATA_SET
5.3.6.7 0x00F0 TV Encoder DAC Test Register (Default Value: 0x0000_0000)
Offset: 0x00F0 Register Name: TVE_DAC_TEST
Bit Read/Write Default/Hex Description
31:26 / / /
DAC_TEST_LENGTH
25:16 R/W 0x0
DAC TEST DATA LENGTH
15:6 / / /
DAC_TEST_SEL
5:4 R/W 0x0 00: DAC0
Others: Reserved
3:1 / / /
DAC_TEST_ENABLE
0 R/W 0x0
0: Reserved
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Offset: 0x00F0 Register Name: TVE_DAC_TEST
Bit Read/Write Default/Hex Description
1: Repeat DAC data from DAC sram
5.3.7 TVE Register Description
5.3.7.1 0x0000 TV Encoder Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TVE_000_REG
Bit Read/Write Default/Hex Description
CLOCK_GATE_DIS
31 R/W 0x0 0: Enable
1: Disable
30:29 / / /
BIST_EN
28 R/W 0x0 0: Normal mode
1: Bist mode
27:23 / / /
UPSAMPLE_FOR_YPBPR
22 R/W 0x0 0: 1x
1: 2x
UPSAMPLE_FOR_CVBS
Out up sample
00: 27 MHz
21:20 R/W 0x0
01: 54 MHz
10: 108 MHz
11: 216 MHz
19:1 / / /
TVE_EN
0: Disable
0 R/W 0x0 1: Enable
Video Encoder enable, default disable, write 1 to take it out
of the reset state
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5.3.7.2 0x0004 TV Encoder Configuration Register (Default Value: 0x0001_0000)
Offset: 0x0004 Register Name: TVE_004_REG
Bit Read/Write Default/Hex Description
31:30 / / /
BYPASS_TV
29 R/W 0x0 0: Disable
1: Enable
DAC_Src_Sel
00: TV Encoder
01: LCD controller, override all other TV encoder setting, the
28:27 R/W 0x0
DAC clock can from LCD controller.
10: DAC test mode, DAC using DAC clock
11: DAC test mode, DAC using AHB clock
DAC_Control_Logic_Clock_Sel
0: Using 27 MHz clock or 74.25 MHz clock depend on CCU
26 R/W 0x0 setting
1: Using 54 MHz clock or 148.5 MHz clock depend on CCU
setting
Core_Datapath_Logic_Clock_Sel
0: Using 27 MHz clock or 74.25 MHz clock depend on CCU
25 R/W 0x0 setting
1: Using 54 MHz clock or 148.5 MHz clock depend on CCU
setting
Core_Control_Logic_Clock_Sel
0: Using 27 MHz clock or 74.25 MHz clock depend on CCU
24 R/W 0x0 setting
1: Using 54 MHz clock or 148.5 MHz clock depend on CCU
setting
23:21 / / /
Cb_Cr_Seq_For_422_Mode
20 R/W 0x0 0: Cb first
1: Cr first
Input_Chroma_Data_Sampling_Rate_Sel
19 R/W 0x0 0: 4:4:4
1: 4:2:2
YUV_RGB_Output_En
18 R/W 0x0 0: CVBS
1: Reserved
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Offset: 0x0004 Register Name: TVE_004_REG
Bit Read/Write Default/Hex Description
YC_EN
S-port Video enable Selection.
0: Y/C is disable
17 R/W 0x0
1: Reserved
This bit selects whether the S-port(Y/C) video output is
enabled or disabled.
CVBS_EN
Composite video enables selection
0: Composite video is disabled, Only Y/C is enabled
16 R/W 0x1
1: Composite video is enabled., CVBS and Y/C are enabled
This bit selects whether the composite video output (CVBS)
is enabled or disabled.
15:10 / / /
Color_BAR_TYPE
9 R/W 0x0 0: 75/7.5/75/7.5 (NTSC), 100/0/75/0(PAL)
1: 100/7.5/100/7.5(NTSC), 100/0/100/0(PAL)
Color_BAR_MODE
Standard Color bar input selection
0: The Video Encoder input is coming from the Display
Engineer
8 R/W 0x0
1: The Video Encoder input is coming from an internal
standard color bar generator.
This bit selects whether the Video Encoder video data input
is replaced by an internal standard color bar generator or not.
7:5 / / /
Mode_1080i_1250Line_Sel
4 R/W 0x0 0: 1125 Line mode
1: 1250 Line mode
TVMode_Select
0000: NTSC
0001: PAL
0010: Reserved
3:0 R/W 0x0 0011: Reserved
01xx: Reserved
100x: Reserved
101x: Reserved
110x: Reserved
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Offset: 0x0004 Register Name: TVE_004_REG
Bit Read/Write Default/Hex Description
111x: Reserved
Note: Changing this register value will cause some relative
register setting to relative value.
5.3.7.3 0x0008 TV Encoder DAC Register1 (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: TVE_008_REG
Bit Read/Write Default/Hex Description
31:7 / / /
DAC0_Src_Sel
6:4 R/W 0x0 000: Composite
Others: Reserved
3:0 / / /
5.3.7.4 0x000C TV Encoder Notch and DAC Delay Register (Default Value: 0x0201_4924)
Offset: 0x000C Register Name: TVE_00C_REG
Bit Read/Write Default/Hex Description
Chroma_Filter_Active_Valid
31 R/W 0x0 0: Disable
1: Enable
Luma_filter_lti_enable
30 R/W 0x0 0: Disable Luma filter lti
1: Enable Luma filter lti
27:25 R/W 0x1 Y_DELAY_BEFORE_DITHER
HD_Mode_CB_Filter_Bypass
24 R/W 0x0 0: Bypass Enable
1: Bypass Disable
HD_Mode_CR_Filter_Bypass
23 R/W 0x0 0: Bypass Enable
1: Bypass Disable
Chroma_Filter_1_444_En
22 R/W 0x0 0: Chroma Filter 1 444 Disable
1: Chroma Filter 1 444 Enable
21 R/W 0x0 Chroma_HD_Mode_Filter_En
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Offset: 0x000C Register Name: TVE_00C_REG
Bit Read/Write Default/Hex Description
0: Chroma HD Filter Disable
1: Chroma HD Filter Enable
Chroma_Filter_Stage_1_Bypass
20 R/W 0x0 0: Chroma Filter Stage 1 Enable
1: Chroma Filter Stage 1 bypass
Chroma_Filter_Stage_2_Bypass
19 R/W 0x0 0: Chroma Filter Stage 2 Enable
1: Chroma Filter Stage 2 bypass
Chroma_Filter_Stage_3_Bypass
18 R/W 0x0 0: Chroma Filter Stage 3 Enable
1: Chroma Filter Stage 3 bypass
Luma_Filter_Bypass
17 R/W 0x0 0: Luma Filter Enable
1: Luma Filter bypass
Notch_En
0: The luma notch filter is bypassed
1: The luma notch filter is operating
16 R/W 0x1
Luma notch filter on/off selection
Note: This bit selects if the luma notch filter is operating or
bypassed.
15:12 R/W 0x4 C_DELAY_BEFORE_DITHER
11:0 R/W 0x924 Reserved
5.3.7.5 0x0010 TV Encoder Chroma Frequency Register (Default Value: 0x21F0_7C1F)
Offset: 0x0010 Register Name: TVE_010_REG
Bit Read/Write Default/Hex Description
Chroma_Freq
Specify the ratio between the color burst frequency. 32 bits
unsigned fraction. The default value is h21f07c1f, which is
compatible with NTSC spec.
31:0 R/W 0x21f07c1f
3.5795455 MHz (X‘21F07C1F’): NTSC-M, NTSC-J
4.43361875 MHz(X‘2A098ACB’): PAL-B, D, G, H,I, N
3.582056 MHz (X‘21F69446’): PAL-N(Argentina)
3.579611 MHz (X‘21E6EFE3’): PAL-M
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5.3.7.6 0x0014 TV Encoder Front/Back Porch Register (Default Value: 0x0076_0020)
Offset: 0x0014 Register Name: TVE_014_REG
Bit Read/Write Default/Hex Description
31:25 / / /
Back_Porch
Specify the width of the back porch in encoder clock cycles.
Min value is (burst_width+breeze_way+17). 8 bits unsigned
24:16 R/W 0x76 integer.
The default value is 118.
For 720p mode, the value is 260.
For 1080i/p mode, the value is 192.
15:12 / / /
Front_Porch
Must be even
Specify the width of the front porch in encoder clock cycles.
11:0 R/W 0x20
6 bits unsigned even integer. Allowed range is form 10 to 62.
The default value is 32.
For 1080i mode, the value is 44.
5.3.7.7 0x0018 TV Encoder HD Mode VSYNC Register (Default Value: 0x0000_0016)
Offset: 0x0018 Register Name: TVE_018_REG
Bit Read/Write Default/Hex Description
31:28 / / /
27:16 R/W 0x0 Broad_Plus_Cycle_Number_In_HD_Mode_VSYNC
15:12 / / /
11:0 R/W 0x16 Front_Porch_Like_In_HD_Mode_VSYNC
5.3.7.8 0x001C TV Encoder Line Number Register (Default Value: 0x0016_020D)
Offset: 0x001C Register Name: TVE_01C_REG
Bit Read/Write Default/Hex Description
31:24 / / /
First_Video_Line
23:16 R/W 0x16 Specify the index of the first line in a field/frame to have
active video. 8 bits unsigned integer.
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Offset: 0x001C Register Name: TVE_01C_REG
Bit Read/Write Default/Hex Description
For interlaced video: When VSync5=B‘0’, FirstVideoLine is
restricted to be greater than 7. When VSync5=B‘1’,
FirstVideoLine is restricted to be greater than 9.
15:11 / / /
Num_Lines
Specify the total number of lines in a video frame. 11 bits
unsigned integer. Allowed range is 0 to 2048.
For interlaced video: When NTSC, and FirstVideoLine is
greater than 20, then NumLines is restricted to be greater
than 2*(FirstVideoLine+18).
When NTSC, and FirstVideoLine is not greater than 20, then
10:0 R/W 0x20D NumLines is restricted to be greater than 77. When PAL, and
FirstVideoLine is greater than 22, then NumLines is restricted
to be greater than 2*(FirstVideoLine+18). When PAL, and
FirstVideoLine is not greater than 22, then NumLines is
restricted to be greater than 81.
If NumLines is even, then it is restricted to be divisible by 4. If
NumLines is odd, then it is restricted to be divisible by 4 with
a remainder of 1.
5.3.7.9 0x0020 TV Encoder Level Register (Default Value: 0x00F0_011A)
Offset: 0x0020 Register Name: TVE_020_REG
Bit Read/Write Default/Hex Description
31:26 / / /
Blank_Level
25:16 R/W 0xf0 Specify the blank level setting for active lines. This is 10 bits
unsigned integer. Allowed range is from 0 to 1023.
15:10 / / /
Black_Level
9:0 R/W 0x11a Specify the black level setting. This is 10 bits unsigned
integer. Allowed range is from 240 to 1023.
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5.3.7.10 0x0030 TV Encoder Auto Detection Enable Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: TVE_030_REG
Bit Read/Write Default/Hex Description
DAC_AUTO_DETECT_MODE_SEL
31 R/W 0x0 0: Old Mode
1: New Mode
30:17 / / /
16 R/W 0x0 DAC0_Auto_Detect_Interrupt_En
15:1 / / /
0 R/W 0x0 DAC0_Auto_Detect_Enable
5.3.7.11 0x0034 TV Encoder Auto Detection Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: TVE_034_REG
Bit Read/Write Default/Hex Description
31:1 / / /
DAC0_Auto_Detect_Interrupt_Active_Flag
0 R/W1C 0x0
Write 1 to inactive DAC0 auto detection interrupt
5.3.7.12 0x0038 TV Encoder Auto Detection Status Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: TVE_038_REG
Bit Read/Write Default/Hex Description
31:2 / / /
DAC0_Status
00: Unconnected
1:0 R 0x0 01: Connected
11: Short to ground
10: Reserved
5.3.7.13 0x003C TV Encoder Auto Detection Debounce Setting Register (Default Value: 0x0000_0000)
Offset: 0x003C Register Name: TVE_03C_REG
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x003C Register Name: TVE_03C_REG
Bit Read/Write Default/Hex Description
DAC_TEST_REGISTER
25:16 R/W 0x0
DAC test register.
15:4 / / /
DAC0_De_Bounce_Times
3:0 R/W 0x0
The de_bounce time for hot plug detect function.
5.3.7.14 0x00F8 TV Encoder Auto Detection Configuration Register0 (Default Value: 0x0000_0000)
Offset: 0x00F8 Register Name: TVE_0F8_REG
Bit Read/Write Default/Hex Description
31:10 / / /
DETECT_Pulse_Value
9:0 R/W 0x0 Use for DAC data input at auto detect pluse. Set the pulse
amplitude.
5.3.7.15 0x00FC TV Encoder Auto Detection Configuration Register1 (Default Value: 0x0000_0000)
Offset: 0x00FC Register Name: TVE_0FC_REG
Bit Read/Write Default/Hex Description
31 / / /
DETECT_Pulse_Periods
30:16 R/W 0x0
Use 32K clock
15 / / /
DETECT_Pulse_Start
14:0 R/W 0x0
Detect signal start time
5.3.7.16 0x0100 TV Encoder Color Burst Phase Reset Configuration Register (Default Value: 0x0000_0001)
Offset: 0x0100 Register Name: TVE_100_REG
Bit Read/Write Default/Hex Description
31:2 / / /
Color_Phase_Reset
1:0 R/W 0x1
Color burst phase period selection
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Offset: 0x0100 Register Name: TVE_100_REG
Bit Read/Write Default/Hex Description
These bits select the number of fields or lines after which the
color burst phase is reset to its initial value as specified by the
ChromaPhase parameter, This parameter is application only
for interlaced video.
00: 8 field
01: 4 field
10: 2 lines
11: only once
5.3.7.17 0x0104 TV Encoder VSYNC Number Register (Default Value: 0x0000_0000)
Offset: 0x0104 Register Name: TVE_104_REG
Bit Read/Write Default/Hex Description
31:1 / / /
VSync5
Number of equalization pulse selection
This bit selects whether the number of equalization pulses is
0 R/W 0x0
5 or 6. This parameter is applicable only for interlaced video.
0: 5 equalization pulse(default)
1: 6 equalization pulses
5.3.7.18 0x0108 TV Encoder Notch Filter Frequency Register (Default Value: 0x0000_0002)
Offset: 0x0108 Register Name: TVE_108_REG
Bit Read/Write Default/Hex Description
31:3 / / /
Notch_Freq
Luma notch filter center frequency selection
These bits select the luma notch filter (which is a band-reject
filter) center frequency. In two of the selections, the filter
width affects also the selection of the center frequency.
2:0 R/W 0x2
000: 1.1875
001: 1.1406
010: 1.0938. When notch_wide value is B‘1’ (this selection is
proper for CCIR-NTSC), or 1.0000 when notch_wide value is
B‘0’.
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Offset: 0x0108 Register Name: TVE_108_REG
Bit Read/Write Default/Hex Description
011: 0.9922. This selection is proper for NTSC with square
pixels.
100: 0.9531. This selection is proper for PAL with square
pixel.
101: 0.8359 when notch_wide value is B‘1’ (this selection is
proper for CCIR-PAL), or 0.7734 when notch_wide value is
B‘0’.
110: 0.7813
111: 0.7188
5.3.7.19 0x010C TV Encoder Cb/Cr Level/Gain Register (Default Value: 0x0000_004F)
Offset: 0x010C Register Name: TVE_10C_REG
Bit Read/Write Default/Hex Description
31:16 / / /
Cr_Burst_Level
15:8 R/W 0x0 Specify the amplitude of the Cr burst. 8 bit 2’s complement
integer. Allowed range is from (-127) to 127.
Cb_Burst_Level
7:0 R/W 0x4f Specify the amplitude of the Cb burst. 8 bit 2’s complement
integer. Allowed range is from (-127) to 127.
5.3.7.20 0x0110 TV Encoder Tint and Color Burst Phase Register (Default Value: 0x0000_0000)
Offset: 0x0110 Register Name: TVE_110_REG
Bit Read/Write Default/Hex Description
31:24 / / /
Tint
Specify the tint adjustment of the chroma signal for CVBS and
23:16 R/W 0x0 Y/C outputs. The adjustment is effected by setting the sub-
carrier phase to the value of this parameter. 8.8 bit unsigned
fraction. Units are cycles of the color burst frequency.
15:8 / / /
7:0 R/W 0x0 Chroma_Phase
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Offset: 0x0110 Register Name: TVE_110_REG
Bit Read/Write Default/Hex Description
Specify the color burst initial phase (ChromaPhase). 8.8 bit
unsigned fraction. Units are cycles of the color burst
frequency.
The color burst is set to this phase at the first HSYNC and then
reset to the same value at further HSYNCs as specified by the
CPhaseRset bits of the EncConfig5 parameter (see above)
5.3.7.21 0x0114 TV Encoder Burst Width Register (Default Value: 0x0016_447E)
Offset: 0x0114 Register Name: TVE_114_REG
Bit Read/Write Default/Hex Description
Back_Porch
Breezeway like in HD mode VSync
31:24 R/W 0x0
For 720p mode, the value is 220
For 2080i/p mode, the value is 88 (default)
23 / / /
Breezeway
Must be even
Specify the width of the breezeway in encoder clock cycles. 5
22:16 R/W 0x16 bit unsigned integer. Allowed range is 0 to 31.
For 1080i mode, the value is 44.
For 1080p mode, the value is 44.
For 720p mode, the value is 40.
15 / / /
Burst_Width
Specify the width of the color frequency burst in encoder
14:8 R/W 0x44
clock cycles. 7 bit unsigned integer. Allowed range is 0 to 127.
In hd mode, it is ignored.
HSync_Width
Specify the width of the horizontal sync pulse in encoder
clock cycles. Min value is 16. Max value is (FrontPorch +
7:0 R/W 0x7e ActiveLine - BackPorch). Default value is 126. The sum of
HSyncSize and BackPorch is restricted to be divisible by 4.
For 720p mode, the value is 40.
For 1080i/p mode, the value is 44.
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5.3.7.22 0x0118 TV Encoder Cb/Cr Gain Register (Default Value: 0x0000_A0A0)
Offset: 0x0118 Register Name: TVE_118_REG
Bit Read/Write Default/Hex Description
31:16 / / /
Cr_Gain
15:8 R/W 0xa0
Specify the Cr color gain. 8-bit unsigned fraction.
Cb_Gain
7:0 R/W 0xa0
Specify the Cb color gain. 8-bit unsigned fraction.
5.3.7.23 0x011C TV Encoder Sync and VBI Level Register (Default Value: 0x0010_00F0)
Offset: 0x011C Register Name: TVE_11C_REG
Bit Read/Write Default/Hex Description
31:26 / / /
Sync_Level
Specify the sync pulse level setting. 8-bit unsigned integer.
25:16 R/W 0x10
Allowed range is from 0 to ABlankLevel-1 or VBlankLevel-1
(whichever is smaller).
15:10 / / /
VBlank_Level
9:0 R/W 0xf0 Specify the blank level setting for non active lines. 10-bit
unsigned integer. Allow range is from 0 to 1023.
5.3.7.24 0x0120 TV Encoder White Level Register (Default Value: 0x01E8_0320)
Offset: 0x0120 Register Name: TVE_120_REG
Bit Read/Write Default/Hex Description
31:26 / / /
HD_Sync_Breezeway_Level
25:16 R/W 0x1e8 Specify the breezeway level setting. 10-bit unsigned integer.
Allowed range is from 0 to 1023.
15:10 / / /
White_Level
Specify the white level setting. 10-bit unsigned integer.
9:0 R/W 0x320
Allowed range is from black_level+1 or vbi_blank_level +1
(whichever is greater) to 1023.
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5.3.7.25 0x0124 TV Encoder Video Active Line Register (Default Value: 0x0000_05A0)
Offset: 0x0124 Register Name: TVE_124_REG
Bit Read/Write Default/Hex Description
31:12 / / /
Active_Line
Specify the width of the video line in encoder clock cycles. 12-
11:0 R/W 0x5A0
bit unsigned multiple of 4 integer. Allowed range is from 0 to
4092.
5.3.7.26 0x0128 TV Encoder Video Chroma BW and CompGain Register (Default Value: 0x0000_0000)
Offset: 0x0128 Register Name: TVE_128_REG
Bit Read/Write Default/Hex Description
31:18 / / /
Chroma_BW
Chroma filter bandwidth selection
This bit specifies whether the bandwidth of the chroma filter
is:
17:16 R/W 0x0
00: Narrow width 0.6 MHz
01: Wide width 1.2 MHz
10: Extra width 1.8 MHz
11: Ultra width 2.5 MHz
15:2 / / /
Comp_Ch_Gain
Chroma gain selection for the composite video signal.
These bits specify the gain of the chroma signal for
composing with the luma signal to generate the composite
1:0 R/W 0x0 video signal:
00: 100%
01: 25%
10: 50%
11: 75%
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5.3.7.27 0x012C TV Encoder Register (Default Value: 0x0000_0101)
Offset: 0x012C Register Name: TVE_12C_REG
Bit Read/Write Default/Hex Description
31:9 / / /
Notch_Width
Luma notch filter width selection
This bit selects the luma notch filter (which is a band-reject
8 R/W 0x1
filter) width.
0: Narrow
1: Wide
7:1 / / /
Comp_YUV_EN
This bit selects if the components video output are the RGB
components or the YUV components.
0 R/W 0x1
0: The three component outputs are the RGB components.
1: The three component outputs are the YUV components,
(i.e. the color conversion unit is bypassed)
5.3.7.28 0x0130 TV Encoder Re-sync Parameters Register (Default Value: 0x0010_0001)
Offset: 0x0130 Register Name: TVE_130_REG
Bit Read/Write Default/Hex Description
Re_Sync_Field
31 R/W 0x0
Re-sync field
Re_Sync_Dis
30 R/W 0x0 0: Re-Sync Enable
1: Re-Sync Disable
29:27 / / /
Re_Sync_Line_Num
26:16 R/W 0x10
Re-sync line number from TCON
15:11 / / /
Re_Sync_Pixel_Num
10:0 R/W 0x1
Re-sync line pixel from TCON
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5.3.7.29 0x0134 TV Encoder Slave Parameter Register (Default Value: 0x0000_0000)
Offset: 0x0134 Register Name: TVE_134_REG
Bit Read/Write Default/Hex Description
31:9 / / /
Slave_Thresh
Horizontal line adjustment threshold selection
This bit selects whether the number of lines after which the
8 R/W 0x0 Video Encoder starts the horizontal line length adjustment is
slave mode is 0 or 30.
0: Number of lines is 0
1: Number of lines is 30
7:1 / / /
Slave_Mode
Slave mode selection
This bit selects whether the Video Encoder is sync slave,
0 R/W 0x0 partial slave or sync master. It should be set to B‘0’.
0: The Video Encoder is not a full sync slave (i.e. it is a partial
sync slave or a sync master)
1: Reserved
5.3.7.30 0x0138 TV Encoder Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0138 Register Name: TVE_138_REG
Bit Read/Write Default/Hex Description
31:9 / / /
Invert_Top
Field parity input signal (top_field) polarity selection.
This bit selects whether the top field is indicated by a high
level of the field parity signal or by the low level. The bit is
8 R/W 0x0
applicable both when the Video Encoder is the sync master
and when the Video Encoder is the sync slave.
0: Top field is indicated by low level
1: Top field is indicated by high level
7:1 / / /
UV_Order
This bit selects if the sample order at the chroma input to the
0 R/W 0x0
Video Encoder is Cb first (i.e. Cb 0 Cr 0 Cb 1 Cr 1) or Cr first
(i.e. Cr 0 Cb 0 Cr 1 Cb 1).
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Offset: 0x0138 Register Name: TVE_138_REG
Bit Read/Write Default/Hex Description
0: The chroma sample input order is Cb first
1: The chroma sample input order is Cr first
5.3.7.31 0x013C TV Encoder Configuration Register (Default Value: 0x0000_0001)
Offset: 0x013C Register Name: TVE_13C_REG
Bit Read/Write Default/Hex Description
31:27 / / /
RGB_Sync
R, G and B signals sync embedding selection.
These bits specify whether the sync signal is added to each
of the R, G and B components (b‘1’) or not (b‘0’). The bit[26]
specify if the R signal has embedded syncs, the bit[25]
26:24 R/W 0x0
specify if the G signal has embedded syncs and the bit[24]
specify if the B signal has embedded syncs. When
comp_yuv is equal to b‘1’, these bits are N.A. and should be
set to b‘000’. When the value is different from b‘000’,
RGB_Setup should be set to b‘1’.
23:17 / / /
RGB_Setup
“Set-up” enable for RGB outputs.
This bit specifies if the “set-up” implied value (black_level –
16 R/W 0x0 blank_level) specified for the CVBS signal is used also for
the RGB signals.
0: The “set-up” is not used, or i.e. comp_yuv is equal to b‘1’.
1: The implied “set-up” is used for the RGB signals
15:1 / / /
Bypass_YClamp
Y input clamping selection
This bit selects whether the Video Encoder Y input is
clamped to 64 to 940 or not. When not clamped the
0 R/W 0x1
expected range is 0 to 1023. The U and V inputs are always
clamped to the range 64 to 960.
0: The Video Encoder Y input is clamped
1: The Video Encoder Y input is not clamped
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5.3.7.32 0x0380 TV Encoder Low Pass Control Register (Default Value: 0x0000_0000)
Offset: 0x0380 Register Name: TVE_380_REG
Bit Read/Write Default/Hex Description
31:14 / / /
User_deflicker_coef
up: coef/32
13:10 R/W 0x0
Center: 1-coef/16
Down: coef/32
Fix_coef_deflicker
9 R/W 0x0 0: Auto deflicker
1: User deflicker
Enable_deflicker
8 R/W 0x0 0: Disable deflicker
1: Enable deflicker
7:1 / / /
EN
LP function enable
0 R/W 0x0
0: Disable
1: Enable
5.3.7.33 0x0384 TV Encoder Low Pass Filter Control Register (Default Value: 0x0000_0000)
Offset: 0x0384 Register Name: TVE_384_REG
Bit Read/Write Default/Hex Description
31:22 / / /
HP_RATIO
21:16 R/W 0x0 Default high-pass filter ratio
In two complement, the range is from -31 to 31.
15:14 / / /
BP0_RATIO
13:8 R/W 0x0 Default band-pass filter0 ratio
In two complement, the range is from -31 to 31.
7:6 / / /
BP1_RATIO
5:0 R/W 0x0 Default band-pass filter1 ratio
In two complement, the range is from -31 to 31.
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5.3.7.34 0x0388 TV Encoder Low Pass Gain Register (Default Value: 0x0000_0000)
Offset: 0x0388 Register Name: TVE_388_REG
Bit Read/Write Default/Hex Description
31:8 / / /
GAIN
7:0 R/W 0x0
Peaking gain setting.
5.3.7.35 0x038C TV Encoder Low Pass Gain Control Register (Default Value: 0x0000_0000)
Offset: 0x038C Register Name: TVE_38C_REG
Bit Read/Write Default/Hex Description
31:24 / / /
DIF_UP
23:16 R/W 0x0
Gain control: limitation threshold.
15:8 / / /
BETA
4:0 R/W 0x0
Gain control: large gain limitation.
5.3.7.36 0x0390 TV Encoder Low Pass Shoot Control Register (Default Value: 0x0000_0000)
Offset: 0x0390 Register Name: TVE_390_REG
Bit Read/Write Default/Hex Description
31:6 / / /
NEG_GAIN
5:0 R/W 0x0
Undershoot gain control.
5.3.7.37 0x0394 TV Encoder Low Pass Coring Register (Default Value: 0x0000_0000)
Offset: 0x0394 Register Name: TVE_394_REG
Bit Read/Write Default/Hex Description
31:8 / / /
CORTHR
7:0 R/W 0x0
Coring threshold.
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5.3.7.38 0x03A0 TV Encoder Noise Reduction Register (Default Value: 0x0000_0000)
Offset: 0x03A0 Register Name: TVE_3A0_REG
Bit Read/Write Default/Hex Description
31:24 / / /
23:16 R/W 0x0 T_Value
15:1 / / /
0 R/W 0x0 EN
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5.4 MIPI DSI
5.4.1 Overview
The Display Serial Interface is a high-speed interface between a host processor and peripheral devices that
adhere to MIPI Alliance specifications for mobile device interfaces. This DSI module is composed of a DSI
controller which is compliance with MIPI DSI specification V1.01 and a D-PHY module which is compliance with
MIPI DPHY specification V1.00.
The MIPI DSI includes the following features:
Compliance with MIPI DSI v1.01
Up to 4 lanes
Supports 1280 x 720@60fps and 1920 x 1200@60fps
Supports non-burst mode with sync pulse/sync event and burst mode
Supports pixel format: RGB888, RGB666, RGB666 loosely packed and RGB565
Supports continuous lane clock mode and non-continuous lane clock mode
Compliance with MIPI DCS v1.01, bidirectional communication in LP through data lane 0
Supports bidirectional communication of all generic commands in LP through data lane 0
Supports low power data transmission
Supports ULPS and Escape modes
Hardware checksum capabilities
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Contents
6 Video Input Interfaces............................................................................................................................................. 467
6.1 CSIC ................................................................................................................................................................. 467
6.1.1 Overview ............................................................................................................................................. 467
6.1.2 Block Diagram ..................................................................................................................................... 467
6.1.3 Functional Descriptions....................................................................................................................... 468
6.1.4 Register List ......................................................................................................................................... 470
6.1.5 CCU Register Description .................................................................................................................... 474
6.1.6 CSIC Top Register Description ............................................................................................................. 475
6.1.7 Parser Register Description ................................................................................................................. 480
6.1.8 CSIC DMA Register Description ........................................................................................................... 501
6.2 TV Decoder ...................................................................................................................................................... 516
6.2.1 Overview ............................................................................................................................................. 516
6.2.2 Block Diagram ..................................................................................................................................... 516
6.2.3 Functional Descriptions....................................................................................................................... 517
6.2.4 Register List ......................................................................................................................................... 517
6.2.5 Register Description ............................................................................................................................ 519
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Figures
Figure 6-1 CSIC Block Diagram .......................................................................................................................................... 467
Figure 6-2 RAW-10 Format ............................................................................................................................................... 468
Figure 6-3 RAW-12 Format ............................................................................................................................................... 468
Figure 6-4 YUV-10 Format................................................................................................................................................. 469
Figure 6-5 RGB888 Format ................................................................................................................................................ 469
Figure 6-6 PRGB888 Format .............................................................................................................................................. 469
Figure 6-7 RGB565 Format ................................................................................................................................................ 469
Figure 6-8 TVD Block Diagram........................................................................................................................................... 516
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Tables
Table 6-1 CSIC External Signals ......................................................................................................................................... 468
Table 6-2 CSIC FIFO Distribution ....................................................................................................................................... 468
Table 6-3 TVD External Signals .......................................................................................................................................... 517
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6 Video Input Interfaces
6.1 CSIC
6.1.1 Overview
The CMOS Sensor Interface Controller (CSIC) is an image or video data receiver, which can receive image or
video data via camera interface and store the data in memory directly.
The CSIC includes the following features:
Supports 8-bit digital camera interface
Supports BT656 Interface
- Supports time-multiplexed format
- Supports dual data rate sample mode with pixel clock up to 148.5 MHz
Supports BT601 Interface
Supports crop function
Supports frame rate down
Supports 2 DMA for 2 video stream storage
- Supports de-interlacing for interlace video input
- Supports conversion from YUV422 to YUV420, YUV422 to YUV400, YUV420 to YUV400
- Supports horizontal and vertical flip
6.1.2 Block Diagram
Figure 6-1 shows block diagram of the CSIC.
Figure 6-1 CSIC Block Diagram
DMA0
DC Input
GPIO Nmlcsi Memory
ncsi Parser0
DMA1
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6.1.3 Functional Description
6.1.3.1 External Signals
Table 6-1 CSIC External Signals
Port Name Description Type
NCSI0-PCLK Parallel CSI Pixel Clock I
NCSI0-MCLK Parallel CSI Master Clock O
NCSI0-HSYNC Parallel CSI Horizontal Sync I
NCSI0-VSYNC Parallel CSI Vertical Sync I
NCSI0-D[7:0] Parallel CSI Data Bit I
NCSI0-FIELD Parallel CSI Field Index I
6.1.3.2 CSIC FIFO Distribution
Table 6-2 CSIC FIFO Distribution
Interface MIPI Interface
Input format YUV422 Raw
Output format Planar UV combined Raw/RGB/PRGB
CH0_FIFO0 Y Y All pixels data
CH0_FIFO1 Cb (U) CbCr (UV) -
CH0_FIFO2 Cr (V) - -
6.1.3.3 Pixel Format Arrangement
Figure 6-2 RAW-10 Format
Dummy1[5:0] Raw data 1[9:0] Dummy 0[5:0] Raw data 0[9:0]
MSB LSB
Figure 6-3 RAW-12 Format
Dummy1[3:0] Raw data 1[11:0] Dummy 0[3:0] Raw data 0[11:0]
MSB LSB
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Figure 6-4 YUV-10 Format
Dummy1[5:0] Y1[9:0] Dummy 0[5:0] Y 0[9:0]
MSB LSB
Dummy1[5:0] V/U 0[9:0] Dummy 0[5:0] U/V 0[9:0]
MSB LSB
Figure 6-5 RGB888 Format
B1[7:0] R0[7:0] G0[7:0] B0[7:0]
G2[7:0] B2[7:0] R1[7:0] G1[7:0]
R3[7:0] G3[7:0] B3[7:0] R2[7:0]
MSB
Figure 6-6 PRGB888 Format
PAD[7:0] R0[7:0] G0[7:0] B0[7:0]
MSB LSB
Figure 6-7 RGB565 Format
R1[4:0] G1[5:0] B1[4:0] R0[4:0] G0[5:0] B0[4:0]
MSB LSB
6.1.3.4 Offset Definition
Offset in horizontal and vertical can be added when receiving image. Unit is pixel.
For YUV422 format, pixel unit is a YU/YV combination.
For YUV420 format, pixel unit is a YU/YV combination in YC line, and only a Y in Y line.
For Bayer and RAW format, pixel unit is a R/G/B single component.
For RGB565, pixel unit is 2 bytes of RGB565 package.
For RGB888, pixel unit is 3 bytes of RGB combination.
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6.1.3.5 Flip Definition
Both horizontal and vertical flip are supported at the same time. This function is implemented in the process
of each FIFO writing data to memory, only flipping the data of separate FIFO, not changing component to FIFO
distribution.
If horizontal flip is enabled, one or more pixels will be took as a unit:
For YUV format, a unit of Y0U0Y1V1 will parser and flip the Y component in one channel, and UV will be treated
as a whole. In planar output mode, U and V will be flipped separately. In UV combined output mode, UV will
be flipped as a whole. So, a sequence of Y1U0Y0V1 will be.
For Bayer_raw format, situation is much like. A GR/BG sequence will be changed to BG/RG. A unit of square
has four pixels.
For RGB565/RGB888, one unit of two/three bytes of component will be flipped with original sequence.
6.1.4 Register List
Module Name Base Address
CSIC_CCU 0x05800000
CSIC_TOP 0x05800800
CSIC_PARSER0 0x05801000
CSIC_DMA0 0x05809000
CSIC_DMA1 0x05809200
CCU register list:
Register Name Offset Register Description
CCU_CLK_MODE_REG 0x0000 CCU Clock Mode Register
CCU_PARSER_CLK_EN_REG 0x0004 CCU Parser Clock Enable Register
CCU_POST0_CLK_EN_REG 0x000C CCU Post0 Clock Enable Register
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CSIC TOP register list:
Register Name Offset Register Description
CSIC_TOP_EN_REG 0x0000 CSIC TOP Enable Register
CSIC_PTN_GEN_EN_REG 0x0004 CSIC Pattern Generation Enable Register
CSIC_PTN_CTRL_REG 0x0008 CSIC Pattern Control Register
CSIC_PTN_LEN_REG 0x0020 CSIC Pattern Generation Length Register
CSIC_PTN_ADDR_REG 0x0024 CSIC Pattern Generation Address Register
CSIC_PTN_ISP_SIZE_REG 0x0028 CSIC Pattern ISP Size Register
CSIC_DMA0_INPUT_SEL_REG 0x00A0 CSIC DMA0 Input Select Register
CSIC_DMA1_INPUT_SEL_REG 0x00A4 CSIC DMA1 Input Select Register
CSIC_BIST_CS_REG 0x00DC CSIC BIST CS Register
CSIC_BIST_CONTROL_REG 0x00E0 CSIC BIST Control Register
CSIC_BIST_START_REG 0x00E4 CSIC BIST Start Register
CSIC_BIST_END_REG 0x00E8 CSIC BIST End Register
CSIC_BIST_DATA_MASK_REG 0x00EC CSIC BIST Data Mask Register
CSIC_MBUS_REQ_MAX_REG 0x00F0 CSIC MBUS REQ MAX Register
CSIC_MULF_MOD_REG 0x0100 CSIC Multi-Frame Mode Register
CSIC_MULF_INT_REG 0x0104 CSIC Multi-Frame Interrupt Register
PARSER0 register list:
Register Name Offset Register Description
PRS_EN_REG 0x0000 Parser Enable Register
PRS_NCSIC_IF_CFG_REG 0x0004 Parser NCSIC Interface Configuration Register
PRS_CAP_REG 0x000C Parser Capture Register
CSIC_PRS_SIGNAL_STA_REG 0x0010 CSIC Parser Signal Status Register
CSIC_PRS_NCSIC_BT656_HEAD_CFG_ CSIC Parser NCSIC BT656 Header Configuration
0x0014
REG Register
PRS_C0_INFMT_REG 0x0024 Parser Channel_0 Input Format Register
Parser Channel_0 Output Horizontal Size
PRS_C0_OUTPUT_HSIZE_REG 0x0028
Register
PRS_C0_OUTPUT_VSIZE_REG 0x002C Parser Channel_0 Output Vertical Size Register
PRS_C0_INPUT_PARA0_REG 0x0030 Parser Channel_0 Input Parameter0 Register
PRS_C0_INPUT_PARA1_REG 0x0034 Parser Channel_0 Input Parameter1 Register
PRS_C0_INPUT_PARA2_REG 0x0038 Parser Channel_0 Input Parameter2 Register
PRS_C0_INPUT_PARA3_REG 0x003C Parser Channel_0 Input Parameter3 Register
PRS_C0_INT_EN_REG 0x0040 Parser Channel_0 Interrupt Enable Register
PRS_C0_INT_STA_REG 0x0044 Parser Channel_0 Interrupt Status Register
PRS_CH0_LINE_TIME_REG 0x0048 Parser Channel_0 Line Time Register
PRS_C1_INFMT_REG 0x0124 Parser Channel_1 Input Format Register
Parser Channel_1 Output Horizontal Size
PRS_C1_OUTPUT_HSIZE_REG 0x0128
Register
PRS_C1_OUTPUT_VSIZE_REG 0x012C Parser Channel_1 Output Vertical Size Register
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Register Name Offset Register Description
PRS_C1_INPUT_PARA0_REG 0x0130 Parser Channel_1 Input Parameter0 Register
PRS_C1_INPUT_PARA1_REG 0x0134 Parser Channel_1 Input Parameter1 Register
PRS_C1_INPUT_PARA2_REG 0x0138 Parser Channel_1 Input Parameter2 Register
PRS_C1_INPUT_PARA3_REG 0x013C Parser Channel_1 Input Parameter3 Register
PRS_C1_INT_EN_REG 0x0140 Parser Channel_1 Interrupt Enable Register
PRS_C1_INT_STA_REG 0x0144 Parser Channel_1 Interrupt Status Register
PRS_CH1_LINE_TIME_REG 0x0148 Parser Channel_1 Line Time Register
PRS_C2_INFMT_REG 0x0224 Parser Channel_2 Input Format Register
Parser Channel_2 Output Horizontal Size
PRS_C2_OUTPUT_HSIZE_REG 0x0228
Register
PRS_C2_OUTPUT_VSIZE_REG 0x022C Parser Channel_2 Output Vertical Size Register
PRS_C2_INPUT_PARA0_REG 0x0230 Parser Channel_2 Input Parameter0 Register
PRS_C2_INPUT_PARA1_REG 0x0234 Parser Channel_2 Input Parameter1 Register
PRS_C2_INPUT_PARA2_REG 0x0238 Parser Channel_2 Input Parameter2 Register
PRS_C2_INPUT_PARA3_REG 0x023C Parser Channel_2 Input Parameter3 Register
PRS_C2_INT_EN_REG 0x0240 Parser Channel_2 Interrupt Enable Register
PRS_C2_INT_STA_REG 0x0244 Parser Channel_2 Interrupt Status Register
PRS_CH2_LINE_TIME_REG 0x0248 Parser Channel_2 Line Time Register
PRS_C3_INFMT_REG 0x0324 Parser Channel_3 Input Format Register
Parser Channel_3 Output Horizontal Size
PRS_C3_OUTPUT_HSIZE_REG 0x0328
Register
PRS_C3_OUTPUT_VSIZE_REG 0x032C Parser Channel_3 Output Vertical Size Register
PRS_C3_INPUT_PARA0_REG 0x0330 Parser Channel_3 Input Parameter0 Register
PRS_C3_INPUT_PARA1_REG 0x0334 Parser Channel_3 Input Parameter1 Register
PRS_C3_INPUT_PARA2_REG 0x0338 Parser Channel_3 Input Parameter2 Register
PRS_C3_INPUT_PARA3_REG 0x033C Parser Channel_3 Input Parameter3 Register
PRS_C3_INT_EN_REG 0x0340 Parser Channel_3 Interrupt Enable Register
PRS_C3_INT_STA_REG 0x0344 Parser Channel_3 Interrupt Status Register
PRS_CH3_LINE_TIME_REG 0x0348 Parser Channel_3 Line Time Register
CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ 0x0500 CSIC Parser NCSIC RX Signal0 Delay Adjust
ADJ_REG Register
CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ 0x0514 CSIC Parser NCSIC RX Signal5 Delay Adjust
ADJ_REG Register
CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ 0x0518 CSIC Parser NCSIC RX Signal6 Delay Adjust
ADJ_REG Register
DMA0/1 register list:
Register Name Offset Register Description
CSIC_DMA_EN_REG 0x0000 CSIC DMA Enable Register
CSIC_DMA_CFG_REG 0x0004 CSIC DMA Configuration Register
CSIC_DMA_HSIZE_REG 0x0010 CSIC DMA Horizontal Size Register
CSIC_DMA_VSIZE_REG 0x0014 CSIC DMA Vertical Size Register
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Register Name Offset Register Description
CSIC_DMA_F0_BUFA_REG 0x0020 CSIC DMA FIFO 0 Output Buffer-A Address
Register
CSIC DMA FIFO 0 Output Buffer-A Address
CSIC_DMA_F0_BUFA_RESULT_REG 0x0024
Result Register
CSIC_DMA_F1_BUFA_REG 0x0028 CSIC DMA FIFO 1 Output Buffer-A Address
Register
CSIC DMA FIFO 1 Output Buffer-A Address
CSIC_DMA_F1_BUFA_RESULT_REG 0x002C
Result Register
CSIC_DMA_F2_BUFA_REG 0x0030 CSIC DMA FIFO 2 Output Buffer-A Address
Register
CSIC DMA FIFO 2 Output Buffer-A Address
CSIC_DMA_F1_BUFA_RESULT_REG 0x0034
Result Register
CSIC_DMA_BUF_LEN_REG 0x0038 CSIC DMA Buffer Length Register
CSIC_DMA_FLIP_SIZE_REG 0x003C CSIC DMA Flip Size Register
CSIC DMA Video Input Timeout Threshold0
CSIC_DMA_VI_TO_TH0_REG 0x0040
Register
CSIC DMA Video Input Timeout Threshold1
CSIC_DMA_VI_TO_TH1_REG 0x0044
Register
CSIC DMA Video Input Timeout Counter Value
CSIC_DMA_VI_TO_CNT_VAL_REG 0x0048
Register
CSIC_DMA_CAP_STA_REG 0x004C CSIC DMA Capture Status Register
CSIC_DMA_INT_EN_REG 0x0050 CSIC DMA Interrupt Enable Register
CSIC_DMA_INT_STA_REG 0x0054 CSIC DMA Interrupt Status Register
CSIC_DMA_LINE_CNT_REG 0x0058 CSIC DMA LINE Counter Register
CSIC_DMA_FRM_CNT_REG 0x005C CSIC DMA Frame Counter Register
CSIC_DMA_FRM_CLK_CNT_REG 0x0060 CSIC DMA Frame Clock Counter Register
CSIC_DMA_ACC_ITNL_CLK_CNT_REG 0x0064 CSIC DMA Accumulated And Internal Clock
Counter Register
CSIC_DMA_FIFO_STAT_REG 0x0068 CSIC DMA FIFO Statistic Register
CSIC_DMA_FIFO_THRS_REG 0x006C CSIC DMA FIFO Threshold Register
CSIC_DMA_PCLK_STAT_REG 0x0070 CSIC DMA PCLK Statistic Register
CSIC_DMA_BUF_ADDR_FIFO0_ENTR 0x0080 CSIC DMA BUF Address FIFO0 Entry Register
Y_REG
CSIC_DMA_BUF_ADDR_FIFO1_ENTR 0x0084 CSIC DMA BUF Address FIFO1 Entry Register
Y_REG
CSIC_DMA_BUF_ADDR_FIFO2_ENTR 0x0088 CSIC DMA BUF Address FIFO2 Entry Register
Y_REG
CSIC_DMA_BUF_TH_REG 0x008C CSIC DMA BUF Threshold Register
CSIC_DMA_BUF_ADDR_FIFO_CON_R 0x0090 CSIC DMA BUF Address FIFO Content Register
EG
CSIC_DMA_STORED_FRM_CNT_REG 0x0094 CSIC DMA Stored Frame Counter Register
CSIC_FEATURE_REG 0x01F4 CSIC DMA Feature List Register
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6.1.5 CCU Register Description
6.1.5.1 0x0000 CCU Clock Mode Register(Default Value:0x8000_0000)
Offset: 0x0000 Register Name: CCU_CLK_MODE_REG
Bit Read/Write Default/Hex Description
CCU_CLK_GATING_DISABLE
31 R/W 0x1 0: CCU Clock Gating Registers(0x0004~0x0010) effect
1: CCU Clock Gating Registers(0x0004~0x0010) not effect
30:0 / / /
6.1.5.2 0x0004 CCU Parser Clock Enable Register(Default Value:0x0000_0000)
Offset: 0x0004 Register Name: CCU_PARSER_CLK_EN_REG
Bit Read/Write Default/Hex Description
31:1 / / /
MCSI_PARSER0_CLK_ENABLE
0 R/W 0x0 0: CSI Parser0 clock disable
1: CSI Parser0 clock enable
6.1.5.3 0x000C CCU Post0 Clock Enable Register(Default Value:0x0000_0000)
Offset: 0x000C Register Name: CCU_POST0_CLK_EN_REG
Bit Read/Write Default/Hex Description
31:17 / / /
MCSI_POST0_CLK_ENABLE
16 R/W 0x0 0: POST0 clock disable
1: POST0 clock enable
15:2 / / /
MCSI_BK1_CLK_ENABLE
1 R/W 0x0 0: BK1 clock disable
1: BK1 clock enable,when MCSI_POST0_CLK_ENABLE is 1
MCSI_BK0_CLK_ENABLE
0 R/W 0x0 0: BK0 clock disable
1: BK0 clock enable,when MCSI_POST0_CLK_ENABLE is 1
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6.1.6 CSIC Top Register Description
6.1.6.1 0x0000 CSIC TOP Enable Register (Default Value:0x0000_0000)
Offset: 0x0000 Register Name: CSIC_TOP_EN_REG
Bit Read/Write Default/Hex Description
31:3 / / /
BIST_MODE_EN
2 R/W 0x0 0: Closed
1: EN BIST TEST
1 / / /
CSIC_TOP_EN
0 R/W 0x0 0: Reset and disable the CSIC module
1: Enable the CSIC module
6.1.6.2 0x0004 CSIC Pattern Generation Enable Register (Default Value:0x0000_0000)
Offset: 0x0004 Register Name: CSIC_PTN_GEN_EN_REG
Bit Read/Write Default/Hex Description
31:24 / / /
PTN_CYCLE
Pattern generating cycle counter.
23:16 R/W 0x0
The pattern in dram will be generated in cycles of
PTN_CYCLE+1.
15:5 / / /
PTN_START
CSIC Pattern Generating Start
0: Finish
4 R/WAC 0x0 1: Start
Software writes this bit to “1” to start pattern generating from
DRAM. When finished, the hardware will clear this bit to “0”
automatically. Generating cycles depends on PTN_CYCLE.
3:1 / / /
PTN_GEN_EN
0 R/W 0x0
Pattern Generation Enable
6.1.6.3 0x0008 CSIC Pattern Control Register (Default Value:0x0000_000F)
Offset: 0x0008 Register Name: CSIC_PTN_CTRL_REG
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x0008 Register Name: CSIC_PTN_CTRL_REG
Bit Read/Write Default/Hex Description
PTN_PORT_SEL
Pattern Generator output port selection
25:24 R/W 0x0
10:NCSIC0
others:reserved
23:22 / / /
PTN_GEN_DATA_WIDTH
00:8-bit
21:20 R/W 0x0 01:10-bit
10:12-bit
11:reserved
PTN_MODE
Pattern mode selection
0000~0011:reserved
0100:NCSIC YUV 8 bits width
0101:NCSIC YUV 16 bits width
0110:reserved
0111:reserved
19:16 R/W 0x0 1000:BT656 8 bits width
1001:BT656 16 bits width
1010:reserved
1011:reserved
1100:BAYER 12 bits for ISPFE
1101:UYVY422 12 bits for ISPFE
1110:UYVY420 12 bits for ISPFE
1111:reserved
15:10 / / /
PTN_GEN_CLK_DIV
9:8 R/W 0x0
Packet generator clock divider
PTN_GEN_DLY
7:0 R/W 0xF
Clocks delayed before pattern generating start.
6.1.6.4 0x0020 CSIC Pattern Generation Length Register (Default Value:0x0000_0000)
Offset: 0x0020 Register Name: CSIC_PTN_LEN_REG
Bit Read/Write Default/Hex Description
PTN_LEN
31:0 R/W 0x0
The pattern length in byte when generating pattern.
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6.1.6.5 0x0024 CSIC Pattern Generation Address Register (Default Value:0x0000_0000)
Offset: 0x0024 Register Name: CSIC_PTN_ADDR_REG
Bit Read/Write Default/Hex Description
PTN_ADDR
31:0 R/W 0x0
The pattern DRAM address when generating pattern.
6.1.6.6 0x0028 CSIC Pattern ISP Size Register (Default Value:0x0000_0000)
Offset: 0x0028 Register Name: CSIC_PTN_ISP_SIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
Height
28:16 R/W 0x0
Vertical size, only valid for ISP mode pattern generation.
15:13 / / /
Width
12:0 R/W 0x0
Horizontal size, only valid for ISP mode pattern generation.
6.1.6.7 0x00A0 CSIC DMA0 Input Select Register (Default Value:0x0000_0000)
Offset: 0x00A0 Register Name: CSIC_DMA0_INPUT_SEL_REG
Bit Read/Write Default/Hex Description
31:4 / / /
DMA0 Input Select
0000: input from ISP0 CH0
3:0 0001: input from ISP0 CH1
R/W 0x0
0010: input from ISP0 CH2
0011: input from ISP0 CH3
Others: Reserved
6.1.6.8 0x00A4 CSIC DMA1 Input Select Register (Default Value:0x0000_0000)
Offset: 0x00A4 Register Name: CSIC_DMA1_INPUT_SEL_REG
Bit Read/Write Default/Hex Description
31:4 / / /
DMA1 Input Select
0000: input from ISP0 CH0
3:0 R/W 0x0
0001: input from ISP0 CH1
0010: input from ISP0 CH2
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Offset: 0x00A4 Register Name: CSIC_DMA1_INPUT_SEL_REG
Bit Read/Write Default/Hex Description
0011: input from ISP0 CH3
Others: Reserved
6.1.6.9 0x00DC CSIC BIST CS Register (Default Value:0x0000_0000)
Offset: 0x00DC Register Name: CSIC_BIST_CS_REG
Bit Read/Write Default/Hex Description
31:3 / / /
BIST_CS
2:0 R/W 0x0 000: Set when BK0 memory bist
001: Set when BK1 memory bist
Others: Reserved
6.1.6.10 0x00E0 CSIC BIST Control Register (Default Value:0x0000_0200)
Offset :0x00E0 Register Name: CSIC_BIST_CTRL_REG
Bit Read/Write Default/Hex Description
31:16 / / /
BIST_ERR_STA
BIST Error Status
15 R 0x0
0: No effect
1: Error
BIST_ERR_PAT
14:12 R 0x0
BIST Error Pattern
BIST_ERR_CYC
11:10 R 0x0
BIST Error Cycle
BIST_STOP
BIST STOP
9 R 0x1
0: Running
1: Stop
BIST_BUSY
BIST Busy
8 R 0x0
0: Idle
1: Busy
BIST_REG_SEL
7:5 R/W 0x0
BIST REG select
BIST_ADDR_Mode_SEL
4 R/W 0x0
BIST Address Mode Select
3:1 R/W 0x0 BIST_WDATA_PAT
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Offset :0x00E0 Register Name: CSIC_BIST_CTRL_REG
Bit Read/Write Default/Hex Description
BIST Write Data Pattern
000: 0x00000000
001: 0x55555555
010: 0x33333333
011: 0x0F0F0F0F
100: 0x00FF00FF
101: 0x0000FFFF
others: Reserved
BIST_EN
0 R/W 0x0 BIST Enable
A positive will trigger the BIST to start.
6.1.6.11 0x00E4 CSIC BIST Start Address Register (Default Value:0x0000_0000)
Offset :0x00E4 Register Name: CSIC_BIST_START_ADDR_REG
Bit Read/Write Default/Hex Description
BIST Start Address
31:0 R/W 0x0
BIST Start Address. It is 32-bit aligned.
6.1.6.12 0x00E8 CSIC BIST End Address Register (Default Value:0x0000_0000)
Offset :0x00E8 Register Name: CSIC_BIST_END_ADDR_REG
Bit Read/Write Default/Hex Description
BIST END Address
31:0 R/W 0x0
BIST END Address. It is 32-bit aligned.
6.1.6.13 0x00EC CSIC BIST Data Mask Register (Default Value:0x0000_0000)
Offset :0x00EC Register Name: CSIC_BIST_DATA_MASK_REG
Bit Read/Write Default/Hex Description
BIST_DATA_MASK
BIST Data Mask
31:0 R/W 0x0
0: Unmask
1: Mask
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6.1.6.14 0x00F0 CSIC MBUS REQ MAX Register (Default Value:0x000F_0F0F)
Offset: 0x00F0 Register Name: CSIC_MBUS_REQ_MAX_REG
Bit Read/Write Default/Hex Description
31:5 / / /
MCSI_MEM_REQ_MAX
4:0 R/W 0x0F Maximum of request commands for the master granted in
MCSI_MEM arbiter is N+1.
6.1.6.15 0x0100 CSIC Multi-Frame Mode Register (Default Value:0x0000_0000)
Offset: 0x0100 Register Name: CSIC_MULF_MOD_REG
Bit Read/Write Default/Hex Description
31:24 R 0x0 MULF_STATUS
23:16 / / /
15:8 R/W 0x0 MULF_CS
7:1 / / /
0 R/W 0x0 MULF_EN
6.1.6.16 0x0104 CSIC Multi-Frame Interrupt Register (Default Value:0x0000_0000)
Offset: 0x0104 Register Name: CSIC_MULF_INT_REG
Bit Read/Write Default/Hex Description
31:18 / / /
17 R/W1C 0x0 MULF_ERR_PD
16 R/W1C 0x0 MULF_DONE_PD
15:2 / / /
1 R/W 0x0 MULF_ERR_EN
0 R/W 0x0 MULF_DONE_EN
6.1.7 Parser Register Description
6.1.7.1 0x0000 Parser Enable Register (Default Value:0x0000_0000)
Offset: 0x0000 Register Name: PRS_EN_REG
Bit Read/Write Default/Hex Description
31:17 / / /
NCSIC_EN
16 R/W 0x0
0: Reset and disable the NCSIC module
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Offset: 0x0000 Register Name: PRS_EN_REG
Bit Read/Write Default/Hex Description
1: Enable the NCSIC module
PCLK_EN
15 R/W 0x0 0: Gate pclk input
1: Enable pclk input
14:3 / / /
PRS_CH_MODE
0: Parser output channel 0–3 corresponding from input channel
2 R/W 0x0 0–3
1: Parser output channel 0–3 all from input channel 0 (MIPI
SEHDR)
PRS_MODE
1 R/W 0x0 0: Reserved
1: MCSI
PRS_EN
0 R/W 0x0 0: Reset and disable the parser module
1: Enable the parser module
6.1.7.2 0x0004 Parser NCSIC Interface Configuration Register (Default Value:0x0105_0080)
Offset: 0x0004 Register Name: PRS_NCSI_IF_CFG_REG
Bit Read/Write Default/Hex Description
YUV420_LINE_ORDER
31 R/W 0x0 0: YUV420 input in Y-YC-Y-YC Line Order
1: YUV420 input in YC-Y-YC-Y Line Order
30:28 / / /
FIELD_DT_PCLK_SHIFT
27:24 R/W 0x1 Only for vsync detected field mode, the odd field permitted pclk
shift = 4* FIELD_DT_PCLK_SHIFT
Source type
Bit 20–23 corresponding to the SRC_TYPEs for channel0–3
23:20 R/W 0x0
0: Progressed
1: Interlaced
FIELD
Field polarity (For YUV HV timing)
0: negative (field=0 indicates odd, field=1 indicates even )
19 R/W 0x0 1: positive (field=1 indicates odd, field=0 indicates even )
Field sequence (For BT656 timing)
0: Normal sequence (field 0 first)
1: Inverse sequence (field 1 first)
VREF_POL
18 R/W 0x1
Vref polarity
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Offset: 0x0004 Register Name: PRS_NCSI_IF_CFG_REG
Bit Read/Write Default/Hex Description
0: negative
1: positive
This register is not applied to CCIR656 interface.
HERF_POL
Href polarity
17 R/W 0x0 0: negative
1: positive
This register is not applied to CCIR656 interface.
CLK_POL
Data clock type
16 R/W 0x1
0: active in rising edge
1: active in falling edge
Field_DT_MODE (only valid when CSI_IF is YUV and source type
is interlaced)
00: by both field and vsync
15:14 R/W 0x0
01: by field
10: by vsync
11: reserved
DDR_SAMPLE_MODE_EN
13 R/W 0x0 0: disable
1: enable
SEQ_8PLUS2
When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte
at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual
CSI data bus according to these sequences:
12:11 R/W 0x0
00: 6’bx+D[9:8], D[7:0]
01: D[9:2], 6’bx+D[1:0]
10: D[7:0], D[9:8]+6’bx
11: D[7:0], 6’bx+D[9:8]
IF_DATA_WIDTH
000: 8 bit data bus
001: 10 bit data bus
10:8 R/W 0x0 010: 12 bit data bus
011: 8+2bit data bus
100: 2x8bit data bus
Others: Reserved
INPUT_SEQ
Input data sequence, only valid for YUV422 and YUV420 input
format.
7:6 R/W 0x2
All data interleaved in one channel:
00: YUYV
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Offset: 0x0004 Register Name: PRS_NCSI_IF_CFG_REG
Bit Read/Write Default/Hex Description
01: YVYU
10: UYVY
11: VYUY
Y and UV in separated channel:
x0: UV
x1: VU
5 / / /
CSI_IF
YUV (separate syncs):
00000: RAW or YUV420/YUYV422 (each cycle one component
input)
Others: Reserved
4:0 R/W 0x0
CCIR656 (embedded syncs):
00100: BT656 1 channel
01100: BT656 2 channels (All data interleaved in one data bus)
01110: BT656 4 channels (All data interleaved in one data bus)
Others: Reserved
6.1.7.3 0x000C Parser Capture Register (Default Value:0x0000_0000)
Offset: 0x000C Register Name: PRS_CAP_REG
Bit Read/Write Default/Hex Description
31:30 / / /
CH3_FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
29:26 R/W 0x0 2: 1/3 fps, only receives the first frame every 3 frames
3: 1/4 fps, only receives the first frame every 4 frames
4: 1/5 fps, only receives the first frame every 4 frames
……
15: 1/16 fps, only receives the first frame every 16 frames
CH3_VCAP_ON
Video capture control: Capture the video image data stream on
channel 3.
25 R/W 0x0 0: Disable video capture
If video capture is in progress, the CSI stops capturing image data
at the end of the current frame, and all of the current frame data
is written to output FIFO.
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Offset: 0x000C Register Name: PRS_CAP_REG
Bit Read/Write Default/Hex Description
1: Enable video capture
The CSI starts capturing image data at the start of the next
frame.
CH3_SCAP_ON
Still capture control: Capture a single still image frame on
channel 3.
0: Disable still capture
24 RC/W 0x0
1: Enable still capture
The CSI module starts capturing image data at the start of the
next frame. The CSI module captures only one frame of image
data. This bit is self cleared and always reads as a 0.
13:12 / / /
CH2_FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
21:18 R/W 0x0 2: 1/3 fps, only receives the first frame every 3 frames
3: 1/4 fps, only receives the first frame every 4 frames
4: 1/5 fps, only receives the first frame every 4 frames
……
15: 1/16 fps, only receives the first frame every 16 frames
CH2_VCAP_ON
Video capture control: Capture the video image data stream on
channel 2.
0: Disable video capture
If video capture is in progress, the CSI stops capturing image data
17 R/W 0x0 at the end of the current frame, and all of the current frame data
is written to output FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next
frame.
CH2_SCAP_ON
Still capture control: Capture a single still image frame on
channel 2.
0: Disable still capture
16 RC/W 0x0
1: Enable still capture
The CSI module starts capturing image data at the start of the
next frame. The CSI module captures only one frame of image
data. This bit is self cleared and always reads as a 0.
15:14 / / /
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Offset: 0x000C Register Name: PRS_CAP_REG
Bit Read/Write Default/Hex Description
CH1_FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
13:10 R/W 0x0 2: 1/3 fps, only receives the first frame every 3 frames
3: 1/4 fps, only receives the first frame every 4 frames
4: 1/5 fps, only receives the first frame every 4 frames
……
15: 1/16 fps, only receives the first frame every 16 frames
CH1_VCAP_ON
Video capture control: Capture the video image data stream on
channel 1.
0: Disable video capture
If video capture is in progress, the CSI stops capturing image data
9 R/W 0x0 at the end of the current frame, and all of the current frame data
is written to output FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next
frame.
CH1_SCAP_ON
Still capture control: Capture a single still image frame on
channel 1.
0: Disable still capture
8 RC/W 0x0
1: Enable still capture
The CSI module starts capturing image data at the start of the
next frame. The CSI module captures only one frame of image
data. This bit is self cleared and always reads as a 0.
7:6 / / /
CH0_FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
5:2 R/W 0x0 2: 1/3 fps, only receives the first frame every 3 frames
3: 1/4 fps, only receives the first frame every 4 frames
4: 1/5 fps, only receives the first frame every 4 frames
……
15: 1/16 fps, only receives the first frame every 16 frames
CH0_VCAP_ON
Video capture control: Capture the video image data stream on
1 R/W 0x0
channel 0.
0: Disable video capture
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Offset: 0x000C Register Name: PRS_CAP_REG
Bit Read/Write Default/Hex Description
If video capture is in progress, the CSI stops capturing image data
at the end of the current frame, and all of the current frame data
is written to output FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next
frame.
CH0_SCAP_ON
Still capture control: Capture a single still image frame on
channel 0.
0: Disable still capture.
0 RC/W 0x0
1: Enable still capture
The CSI module starts capturing image data at the start of the
next frame. The CSI module captures only one frame of image
data. This bit is self cleared and always reads as a 0.
6.1.7.4 0x0010 Parser Signal Status Register (Default Value:0x0000_0000)
Offset: 0x0010 Register Name: CSIC_PRS_SIGNAL_STA_REG
Bit Read/Write Default/Hex Description
31:25 / / /
PCLK_STA
Indicates the pclk status
24 R 0x0
0: low
1: high
DATA_STA
Indicates the Dn status (n=0–23), MSB for D23, LSB for D0
23:0 R 0x0
0: low
1: high
6.1.7.5 0x0014 Parser NCSIC BT656 Header Configuration Register (Default Value:0x0302_0100)
Offset: 0x0014 Register Name: CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG
Bit Read/Write Default/Hex Description
31:28 / / /
CH3_ID
27:24 R/W 0x3 The low 4-bit of BT656 header for channel 3
Only valid in BT656 multi-channel mode
23:20 / / /
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Offset: 0x0014 Register Name: CSIC_PRS_NCSIC_BT656_HEAD_CFG_REG
Bit Read/Write Default/Hex Description
CH2_ID
19:16 R/W 0x2 The low 4-bit of BT656 header for channel 2
Only valid in BT656 multi-channel mode
15:12 / / /
CH1_ID
11:8 R/W 0x1 The low 4-bit of BT656 header for channel 1
Only valid in BT656 multi-channel mode
7:4 / / /
CH0_ID
3:0 R/W 0x0 The low 4-bit of BT656 header for channel 0
Only valid in BT656 multi-channel mode
6.1.7.6 0x0024 Parser Channel_0 Input Format Register (Default Value:0x0000_0003)
Offset: 0x0024 Register Name: PRS_CH0_INFMT_REG
Bit Read/Write Default/Hex Description
31:4 / / /
INPUT_FMT
Input data format
0000: RAW stream
0001: reserved
3:0 R/W 0x3
0010: reserved
0011: YUV422
0100: YUV420
Others: reserved
6.1.7.7 0x0028 Parser Channel_0 Output Horizontal Size Register (Default Value:0x0500_0000)
Offset: 0x0028 Register Name: PRS_CH0_OUTPUT_HSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
28:16 R/W 0x500 HOR_LEN
Horizontal pixel unit length. Valid pixel of a line.
15:13 / / /
12:0 R/W 0x0 HOR_START
Horizontal pixel unit start. Pixel is valid from this pixel.
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6.1.7.8 0x002C Parser Channel_0 Output Vertical Size Register (Default Value:0x02D0_0000)
Offset: 0x002C Register Name: PRS_CH0_OUTPUT_VSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2D0
Valid line number of a frame.
15:13 / / /
VER_START
12:0 R/W 0x0
Vertical line start. data is valid from this line.
6.1.7.9 0x003C Parser Channel_0 Input Parameter0 Register (Default Value:0x0000_0000)
Offset: 0x0030 Register Name: PRS_CH0_INPUT_PARA0_REG
Bit Read/Write Default/Hex Description
31:1 / / /
INPUT_SRC_TYPE
0 R 0x0 0: Progress
1: Interlace
6.1.7.10 0x0034 Parser Channel_0 Input Parameter1 Register (Default Value:0x0000_0000)
Offset: 0x0034 Register Name: PRS_CH0_INPUT_PARA1_REG
Bit Read/Write Default/Hex Description
31:30 / / /
INPUT_VT
29:16 R 0x0
INPUT_VT = INPUT_VB+INPUT_Y
15:14 / / /
INPUT_HT
13:0 R 0x0
INPUT_HT = INPUT_HB+INPUT_X
6.1.7.11 0x0038 Parser Channel_0 Input Parameter2 Register (Default Value:0x0000_0000)
Offset: 0x0038 Register Name: PRS_CH0_INPUT_PARA2_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_VB
15:14 / / /
13:0 R 0x0 INPUT_HB
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6.1.7.12 0x003C Parser Channel_0 Input Parameter3 Register (Default Value:0x0000_0000)
Offset: 0x003C Register Name: PRS_CH0_INPUT_PARA3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_Y
15:14 / / /
13:0 R 0x0 INPUT_X
6.1.7.13 0x0040 Parser Channel_0 Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0040 Register Name: PRS_CH0_INT_EN_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ERR_INT_EN
Multi-channel writing error
2 R/W 0x0
Indicates error has been detected for writing data to a wrong
channel.
INPUT_PARA1_INT_EN
1 R/W 0x0 0: disable
1: enable
INPUT_PARA0_INT_EN
0 R/W 0x0 0: disable
1: enable
6.1.7.14 0x0044 Parser Channel_0 Interrupt Status Register (Default Value:0x0000_0000)
Offset: 0x0044 Register Name: PRS_CH0_INT_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ ERR_PD
2 R/W1C 0x0
Multi-channel writing error
INPUT_SRC_PD1
1 R/W1C 0x0 When the parser input parameter0 register update,this flag set
to 1. Write 1 to clear.
INPUT_SRC_PD0
When the parser input parameter1 register, parser input
0 R/W1C 0x0
parameter2 register or parser input parameter3 register update,
this flag set to 1. Write 1 to clear.
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6.1.7.15 0x0048 Parser Channel_0 Line Time Register (Default Value:0x0000_0000)
Offset: 0x0048 Register Name: PRS_CH0_LINE_TIME_REG
Bit Read/Write Default/Hex Description
PRS_CH0_HBLK_TIME
31:16 RO 0x0 Time of H Blanking when vsync is valid
The unit is csi_top_clk cycle
PRS_CH0_HSYN_TIME
15:0 RO 0x0 Time of H SYNC when vsync is valid
The unit is csi_top_clk cycle
6.1.7.16 0x0124 Parser Channel_1 Input Format Register (Default Value:0x0000_0003)
Offset: 0x0124 Register Name: PRS_CH1_INFMT_REG
Bit Read/Write Default/Hex Description
31:4 / / /
INPUT_FMT
Input data format
0000: RAW stream
3:0 R/W 0x3 0001: reserved
0010: reserved
0011: YUV422
0100: YUV420
Others: reserved
6.1.7.17 0x0128 Parser Channel_1 Output Horizontal Size Register (Default Value:0x0500_0000)
Offset: 0x0128 Register Name: PRS_CH1_OUTPUT_HSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
HOR_LEN
28:16 R/W 0x500
Horizontal pixel unit length. Valid pixel of a line.
15:13 / / /
HOR_START
12:0 R/W 0x0
Horizontal pixel unit start. Pixel is valid from this pixel.
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6.1.7.18 0x012C Parser Channel_1 Output Vertical Size Register (Default Value:0x02D0_0000)
Offset: 0x012C Register Name: PRS_CH1_OUTPUT_VSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2d0
Valid line number of a frame.
15:13 / / /
VER_START
12:0 R/W 0x0 Vertical line start.
Data is valid from this line.
6.1.7.19 0x0130 Parser Channel_1 Input Parameter0 Register (Default Value:0x0000_0000)
Offset: 0x0130 Register Name: PRS_CH1_INPUT_PARA0_REG
Bit Read/Write Default/Hex Description
31:1 / / /
INPUT_SRC_TYPE
0 R 0x0 0: Progress
1: Interlace
6.1.7.20 0x0134 Parser Channel_1 Input Parameter1 Register (Default Value:0x0000_0000)
Offset: 0x0134 Register Name: PRS_CH1_INPUT_PARA1_REG
Bit Read/Write Default/Hex Description
31:30 / / /
INPUT_VT
29:16 R 0x0
INPUT_VT = INPUT_VB+INPUT_Y
15:14 / / /
INPUT_HT
13:0 R 0x0
INPUT_HT = INPUT_HB+INPUT_X
6.1.7.21 0x0138 Parser Channel_1 Input Parameter2 Register (Default Value:0x0000_0000)
Offset: 0x0138 Register Name: PRS_CH1_INPUT_PARA2_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_VB
15:14 / / /
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Offset: 0x0138 Register Name: PRS_CH1_INPUT_PARA2_REG
Bit Read/Write Default/Hex Description
13:0 R 0x0 INPUT_HB
6.1.7.22 0x013C Parser Channel_1 Input Parameter3 Register (Default Value:0x0000_0000)
Offset: 0x013C Register Name: PRS_CH1_INPUT_PARA3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_Y
15:14 / / /
13:0 R 0x0 INPUT_X
6.1.7.23 0x0140 Parser Channel_1 Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0140 Register Name: PRS_CH1_INT_EN_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ERR_INT_EN
2 Multi-channel writing error
R/W 0x0
Indicates error has been detected for writing data to a wrong
channel.
INPUT_PARA1_INT_EN
1 R/W 0x0 0: Disable
1: Enable
INPUT_PARA0_INT_EN
0 R/W 0x0 0: Disable
1: Enable
6.1.7.24 0x0144 Parser Channel_1 Interrupt Status Register (Default Value:0x0000_0000)
Offset: 0x0144 Register Name: PRS_CH1_INT_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ ERR_PD
2 R/W1C 0x0
Multi-channel writing error
INPUT_SRC_PD1
1 R/W1C 0x0 When the parser input parameter0 register update, this flag is
set to 1. Write 1 to clear.
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Offset: 0x0144 Register Name: PRS_CH1_INT_STA_REG
Bit Read/Write Default/Hex Description
INPUT_SRC_PD0
When the parser input parameter1 register, parser input
0 R/W1C 0x0
parameter2 register or parser input parameter3 register
update, this flag is set to 1. Write 1 to clear.
6.1.7.25 0x0148 Parser Channel_1 Line Time Register (Default Value:0x0000_0000)
Offset: 0x0148 Register Name: PRS_CH1_LINE_TIME_REG
Bit Read/Write Default/Hex Description
PRS_CH1_HBLK_TIME
31:16 RO 0x0 Time of H Blanking when vsync is valid
The unit is csi_top_clk cycle.
PRS_CH1_HSYN_TIME
15:0 RO 0x0 Time of H SYNC when vsync is valid
The unit is csi_top_clk cycle.
6.1.7.26 0x0224 Parser Channel_2 Input Format Register (Default Value:0x0000_0003)
Offset: 0x0224 Register Name: PRS_CH2_INFMT_REG
Bit Read/Write Default/Hex Description
31:4 / / /
INPUT_FMT
Input data format
0000: RAW stream
0001: reserved
3:0 R/W 0x3
0010: reserved
0011: YUV422
0100: YUV420
Others: reserved
6.1.7.27 0x0228 Parser Channel_2 Output Horizontal Size Register (Default Value:0x0500_0000)
Offset: 0x0228 Register Name: PRS_CH2_OUTPUT_HSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
HOR_LEN
28:16 R/W 0x500
Horizontal pixel unit length. Valid pixel of a line.
15:13 / / /
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Offset: 0x0228 Register Name: PRS_CH2_OUTPUT_HSIZE_REG
Bit Read/Write Default/Hex Description
HOR_START
12:0 R/W 0x0
Horizontal pixel unit start. Pixel is valid from this pixel.
6.1.7.28 0x022C Parser Channel_2 Output Vertical Size Register (Default Value:0x02D0_0000)
Offset: 0x022C Register Name: PRS_CH2_OUTPUT_VSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2D0
Valid line number of a frame.
15:13 / / /
VER_START
12:0 R/W 0x0
Vertical line start. Data is valid from this line.
6.1.7.29 0x0230 Parser Channel_2 Input Parameter0 Register (Default Value:0x0000_0000)
Offset: 0x0230 Register Name: PRS_CH2_INPUT_PARA0_REG
Bit Read/Write Default/Hex Description
31:1 / / /
INPUT_SRC_TYPE
0 R 0x0 0:Progress
1:Interlace
6.1.7.30 0x0234 Parser Channel_2 Input Parameter1 Register (Default Value:0x0000_0000)
Offset: 0x0234 Register Name: PRS_CH2_INPUT_PARA1_REG
Bit Read/Write Default/Hex Description
31:30 / / /
INPUT_VT
29:16 R 0x0
INPUT_VT = INPUT_VB+INPUT_Y
15:14 / / /
INPUT_HT
13:0 R 0x0
INPUT_HT = INPUT_HB+INPUT_X
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6.1.7.31 0x0238 Parser Channel_2 Input Parameter2 Register (Default Value:0x0000_0000)
Offset: 0x0238 Register Name: PRS_CH2_INPUT_PARA2_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_VB
15:14 / / /
13:0 R 0x0 INPUT_HB
6.1.7.32 0x023C Parser Channel_2 Input Parameter3 Register (Default Value:0x0000_0000)
Offset: 0x023C Register Name: PRS_CH2_INPUT_PARA3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_Y
15:14 / / /
13:0 R 0x0 INPUT_X
6.1.7.33 0x0240 Parser Channel_2 Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0240 Register Name: PRS_CH2_INT_EN_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ERR_INT_EN
Multi-channel writing error
2 R/W 0x0
Indicates error has been detected for writing data to a wrong
channel.
INPUT_PARA1_INT_EN
1 R/W 0x0 0: disable
1: enable
INPUT_PARA0_INT_EN
0 R/W 0x0 0: disable
1: enable
6.1.7.34 0x0244 Parser Channel_2 Interrupt Status Register (Default Value:0x0000_0000)
Offset: 0x0244 Register Name: PRS_CH2_INT_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
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Offset: 0x0244 Register Name: PRS_CH2_INT_STA_REG
Bit Read/Write Default/Hex Description
2 R/W1C 0x0 MUL_ERR_PD
Multi-channel writing error
INPUT_SRC_PD1
1 R/W1C 0x0 When the parser input parameter0 register update, this flag set
to 1. Write 1 to clear.
INPUT_SRC_PD0
0 R/W1C 0x0 When the parser input parameter1 register, parser input
parameter2 register or parser input parameter3 register update,
this flag set to 1. Write 1 to clear.
6.1.7.35 0x0248 Parser Channel_2 Line Time Register (Default Value:0x0000_0000)
Offset: 0x0248 Register Name: PRS_CH2_LINE_TIME_REG
Bit Read/Write Default/Hex Description
PRS_CH2_HBLK_TIME
31:16 RO 0x0 Time of H Blanking when vsync is valid
The unit is csi_top_clk cycle
PRS_CH2_HSYN_TIME
15:0 RO 0x0 Time of H SYNC when vsync is valid
The unit is csi_top_clk cycle
6.1.7.36 0x0324 Parser Channel_3 Input Format Register (Default Value:0x0000_0003)
Offset: 0x0324 Register Name: PRS_CH3_INFMT_REG
Bit Read/Write Default/Hex Description
31:4 / / /
INPUT_FMT
Input data format
0000: RAW stream
0001: reserved
3:0 R/W 0x3
0010: reserved
0011: YUV422
0100: YUV420
Others: reserved
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6.1.7.37 0x0328 Parser Channel_3 Output Horizontal Size Register (Default Value:0x0500_0000)
Offset: 0x0328 Register Name: PRS_CH3_OUTPUT_HSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
HOR_LEN
28:16 R/W 0x500
Horizontal pixel unit length. Valid pixel of a line.
15:13 / / /
HOR_START
12:0 R/W 0x0
Horizontal pixel unit start. Pixel is valid from this pixel.
6.1.7.38 0x032C Parser Channel_3 Output Vertical Size Register (Default Value:0x02D0_0000)
Offset: 0x032C Register Name: PRS_CH3_OUTPUT_VSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2d0
Valid line number of a frame.
15:13 / / /
VER_START
12:0 R/W 0x0 Vertical line start.
Data is valid from this line.
6.1.7.39 0x0330 Parser Channel_3 Input Parameter0 Register (Default Value:0x0000_0000)
Offset: 0x0330 Register Name: PRS_CH3_INPUT_PARA0_REG
Bit Read/Write Default/Hex Description
31:1 / / /
INPUT_SRC_TYPE
0 R 0x0 0:Progress
1:Interlace
6.1.7.40 Parser Channel_3 Input Parameter1 Register (Default Value:0x0000_0000)
Offset: 0x0334 Register Name: PRS_CH3_INPUT_PARA1_REG
Bit Read/Write Default/Hex Description
31:30 / / /
INPUT_VT
29:16 R 0x0
INPUT_VT = INPUT_VB+INPUT_Y
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Offset: 0x0334 Register Name: PRS_CH3_INPUT_PARA1_REG
Bit Read/Write Default/Hex Description
15:14 / / /
INPUT_HT
13:0 R 0x0
INPUT_HT = INPUT_HB+INPUT_X
6.1.7.41 0x0338 Parser Channel_3 Input Parameter2 Register (Default Value:0x0000_0000)
Offset: 0x0338 Register Name: PRS_CH3_INPUT_PARA2_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_VB
15:14 / / /
13:0 R 0x0 INPUT_HB
6.1.7.42 0x033C Parser Channel_3 Input Parameter3 Register(Default Value:0x0000_0000)
Offset: 0x033C Register Name: PRS_CH3_INPUT_PARA3_REG
Bit Read/Write Default/Hex Description
31:30 / / /
29:16 R 0x0 INPUT_Y
15:14 / / /
13:0 R 0x0 INPUT_X
6.1.7.43 0x0340 Parser Channel_3 Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0340 Register Name: PRS_CH3_INT_EN_REG
Bit Read/Write Default/Hex Description
31:3 / / /
MUL_ERR_INT_EN
Multi-channel writing error
2 R/W 0x0
Indicates error has been detected for writing data to a wrong
channel.
INPUT_PARA1_INT_EN
1 R/W 0x0 0:disable
1:enable
INPUT_PARA0_INT_EN
0 R/W 0x0 0:disable
1:enable
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6.1.7.44 0x0344 Parser Channel_3 Interrupt Status Register (Default Value:0x0000_0000)
Offset: 0x0344 Register Name: PRS_CH3_INT_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
2 R/W1C 0x0 MUL_ERR_PD
Multi-channel writing error
INPUT_SRC_PD1
1 R/W1C 0x0 When the parser input parameter0 register update, this flag is
set to 1. Write 1 to clear.
INPUT_SRC_PD0
0 R/W1C 0x0 When the parser input parameter1 register, parser input
parameter2 register or parser input parameter3 register update,
this flag is set to 1. Write 1 to clear.
6.1.7.45 0x0348 Parser Channel_3 Line Time Register (Default Value:0x0000_0000)
Offset: 0x0348 Register Name: PRS_CH3_LINE_TIME_REG
Bit Read/Write Default/Hex Description
PRS_CH3_HBLK_TIME
31:16 RO 0x0 Time of H Blanking when vsync is valid
The unit is csi_top_clk cycle
PRS_CH3_HSYN_TIME
15:0 RO 0x0 Time of H SYNC when vsync is valid
The unit is csi_top_clk cycle
6.1.7.46 0x0500 CSIC Parser NCSIC RX Signal0 Delay Adjust Register (Default Value:0x0000_0000)
Offset: 0x0500 Register Name: CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG
Bit Read/Write Default/Hex Description
31:29 / / /
Filed_dly
28:24 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
23:21 / / /
Vsync_dly
20:16 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
15:13 / / /
Hsync_dly
12:8 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
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Offset: 0x0500 Register Name: CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG
Bit Read/Write Default/Hex Description
7:5 / / /
Pclk_dly
4:0 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
6.1.7.47 0x0514 CSIC Parser NCSIC RX Signal5 Delay Adjust Register (Default Value:0x0000_0000)
Offset: 0x0514 Register Name: CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_REG
Bit Read/Write Default/Hex Description
31:29 / / /
D7_dly
28:24 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
23:21 / / /
D6_dly
20:16 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
15:13 / / /
D5_dly
12:8 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
7:5 / / /
D4_dly
4:0 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
6.1.7.48 0x0518 CSIC Parser NCSIC RX Signal6 Delay Adjust Register (Default Value:0x0000_0000)
Offset: 0x0518 Register Name: CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_REG
Bit Read/Write Default/Hex Description
31:29 / / /
D3_dly
28:24 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
23:21 / / /
D2_dly
20:16 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
15:13 / / /
D1_dly
12:8 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
7:5 / / /
D0_dly
4:0 R/W 0x0
32 Step for adjust, 1 step = 0.2 ns
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6.1.8 CSIC DMA Register Description
6.1.8.1 0x0000 CSIC DMA Enable Register (Default Value:0x7000_0000)
Offset:0x0000 Register Name: CSIC_DMA_EN_REG
Bit Read/Write Default/Hex Description
31 R/W 0x0 VER_EN
VFLIP_BUF_ADDR_CFG_MODE
Vflip buffer address set by software or calculated by hardware
30 R/W 0x1
0: Hardware
1: Software
BUF_LENGTH_CFG_MODE
Buffer length set by software or calculated by hardware
29 R/W 0x1
0: Hardware
1: Software
FLIP_SIZE_CFG_MODE
FLIP SIZE set by software or calculated by hardware
28 R/W 0x1
0: Hardware
1: Software
27:8 / / /
BUF_ADDR_MODE
7 R/W 0x0 0: Buffer Address Register Mode
1: Buffer Address FIFO Mode
VI_TO_CNT_EN
Enable Video Input Timeout counter, add 1 when there is no
effective video input in a 12M clock, clear to 0 when detecting
6 R/W 0x0
effective video input.
0: Disable
1: Enable
FRAME_CNT_EN
When BK_TOP_EN is enabled, setting 1 to this bit indicates the
5 R/W 0x0 Frame counter starts to add.
0: Disable
1: Enable
DMA_EN
When BK_TOP_EN is enabled, setting 1 to this bit indicates the
4 R/W 0x0 module works in DMA mode.
0: Disable
1: Enable
3 / / /
CLK_CNT_SPL
Sampling time for clk counter per frame
2 R/W 0x0
0: Sampling clock counter every frame done
1: Sampling clock counter every vsync
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Offset:0x0000 Register Name: CSIC_DMA_EN_REG
Bit Read/Write Default/Hex Description
CLK_CNT_EN
1 R/W 0x0
clk count per frame enable
BK_TOP_EN
0 R/W 0x0 0: Disable
1: Enable
6.1.8.2 0x0004 CSIC DMA Configuration Register (Default Value:0x0000_0000)
Offset: 0x0004 Register Name: CSIC_DMA_CFG_REG
Bit Read/Write Default/Hex Description
PAD_VAL
31:24 R/W 0x0 Padding value when OUTPUT_FMT is prgb888
0x00–0xff
23:22 / / /
YUV 10-bit input cut to 8-bit
21 R/W 0x0 0: Disable
1: Enable
YUV 10-bit store configuration
20 R/W 0x0 0: YUV 10-bit stored in low 10-bit of a 16-bit word
1: YUV 10-bit stored in high 10-bit of a 16-bit word
OUTPUT_FMT
Output data format
When the input format is set to RAW stream
0000: field-raw-8
0001: field-raw-10
0010: field-raw-12
0011: reserved
0100: field-rgb565
0101: field-rgb888
0110: field-prgb888
19:16 R/W 0x0 0111: reserved
1000: frame-raw-8
1001: frame-raw-10
1010: frame-raw-12
1011: reserved
1100: frame-rgb565
1101: frame-rgb888
1110: frame-prgb888
1111: reserved
When the input format is set to YUV422
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Offset: 0x0004 Register Name: CSIC_DMA_CFG_REG
Bit Read/Write Default/Hex Description
0000: field planar YCbCr 422
0001: field planar YCbCr 420
0010: frame planar YCbCr 420
0011: frame planar YCbCr 422
0100: field planar YCbCr 422 UV combined (UV sequence)
0101: field planar YCbCr 420 UV combined (UV sequence)
0110: frame planar YCbCr 420 UV combined (UV sequence)
0111: frame planar YCbCr 422 UV combined (UV sequence)
1000: filed planar YCbCr 422 UV combined (VU sequence)
1001: field planar YCbCr 420 UV combined (VU sequence)
1010: frame planar YCbCr 420 UV combined (VU sequence)
1011: frame planar YCbCr 422 UV combined (VU sequence)
1100: reserved
1101: field YCbCr 400
1110: reserved
1111: frame YCbCr 400
When the input format is set to YUV420
0000: reserved
0001: field planar YCbCr 420
0010: frame planar YCbCr 420
0011: reserved
0100: reserved
0101: field planar YCbCr 420 UV combined (UV sequence)
0110: frame planar YCbCr 420 UV combined (UV sequence)
0111~1000: reserved
1001: field planar YCbCr 420 UV combined (VU sequence)
1010: frame planar YCbCr 420 UV combined (VU sequence)
1011~1100: reserved
1101: field YCbCr 400
1110: reserved
1111: frame YCbCr 400
15:14 / / /
VFLIP_EN
Vertical flip enable
13 R/W 0x0 When enabled, the received data will be arranged in vertical flip.
0: Disable
1: Enable
HFLIP_EN
Horizontal flip enable
12 R/W 0x0 When enabled, the received data will be arranged in horizontal
flip.
0: Disable
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Offset: 0x0004 Register Name: CSIC_DMA_CFG_REG
Bit Read/Write Default/Hex Description
1: Enable
FIELD_SEL
Field selection
00: Capturing with field 0
11:10 R/W 0x0
01: Capturing with field 1
10: Capturing with either field
11: Reserved
FPS_DS
Fps down sample
0: no down sample
1: 1/2 fps, only receives the first frame every 2 frames
9:6 R/W 0x0 2: 1/3 fps, only receives the first frame every 3 frames
3: 1/4 fps, only receives the first frame every 4 frames
4: 1/5 fps, only receives the first frame every 4 frames
……
15: 1/16 fps, only receives the first frame every 16 frames
5:2 / / /
MIN_SDR_WR_SIZE
Minimum size of SDRAM block write
00: 256 bytes (if hflip is enabled, always select 256 bytes)
1:0 R/W 0x0
01: 512 bytes
10: 1K bytes
11: 2K bytes
6.1.8.3 0x0010 CSIC DMA Horizontal Size Register (Default Value:0x0500_0000)
Offset: 0x0010 Register Name: CSIC_DMA_HSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
HOR_LEN
When BK_TOP_EN is enabled, DMA_EN is enabled, these bits
28:16 R/W 0x500
indicate Horizontal pixel unit length. Valid pixel of a line in DMA
mode.
15:13 / / /
HOR_START
12:0 R/W 0x0 Horizontal pixel unit start.
Pixel is valid from this pixel.
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6.1.8.4 0x0014 CSIC DMA Vertical Size Register (Default Value:0x02D0_0000)
Offset: 0x0014 Register Name: CSIC_DMA_VSIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2D0 When BK_TOP_EN is enabled, DMA_EN is enabled, these bits
indicate Valid line number of a frame in DMA mode.
15:13 / / /
VER_START
12:0 R/W 0x0 Vertical line start
Data is valid from this line.
6.1.8.5 0x0020 CSIC DMA FIFO 0 Output Buffer-A Address Register (Default Value:0x0000_0000)
Offset: 0x0020 Register Name: CSIC_DMA_F0_BUFA_REG
Bit Read/Write Default/Hex Description
F0_BUFA
When BK_TOP_EN is enabled, FBC_EN is enabled, DMA_EN is
disabled, these bits indicate output address of overhead data in
FBC mode.
When BK_TOP_EN is enabled, FBC_EN is disabled, DMA_EN is
31:0 R/W 0x0
enabled, LBC_EN is disabled, these bits indicate FIFO 0 output
buffer-A address in DMA mode.
When BK_TOP_EN is enabled, FBC_EN is disabled, DMA_EN is
enabled, LBC_EN is enabled, these bits indicate the output
buffer address in LBC mode.
6.1.8.6 0x0024 CSIC DMA FIFO 0 Output Buffer-A Address Result Register (Default Value:0x0000_0000)
Offset: 0x0024 Register Name: CSIC_DMA_F0_BUFA_RESULT_REG
Bit Read/Write Default/Hex Description
F0_BUFA_RESULT
Indicate the final F0_BUFA address used for DMA or FBC after
31:0 RO 0x0
software configuration or hardware calculation from Buffer-A
address register or buffer address fifo. Only used for debug.
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6.1.8.7 0x0028 CSIC DMA FIFO 1 Output Buffer-A Address Register (Default Value:0x0000_0000)
Offset: 0x0028 Register Name: CSIC_DMA_F1_BUFA_REG
Bit Read/Write Default/Hex Description
F1_BUFA
When BK_TOP_EN is enabled, FBC_EN is enabled, DMA_EN is
disabled, these bits indicate the output address of compressed
31:0 R/W 0x0 data in FBC mode.
When BK_TOP_EN is enabled, FBC_EN is disabled, DMA_EN is
enabled, these bits indicate the FIFO 1 output buffer-A address
in DMA mode.
6.1.8.8 0x002C CSIC DMA FIFO 1 Output Buffer-A Address Result Register (Default Value:0x0000_0000)
Offset: 0x002C Register Name: CSIC_DMA_F1_BUFA_RESULT_REG
Bit Read/Write Default/Hex Description
F1_BUFA_RESULT
Indicate the final F1_BUFA address used for DMA or FBC after
31:0 RO 0x0
software configuration or hardware calculation from Buffer-A
address register or buffer address fifo. Only used for debug.
6.1.8.9 0x0030 CSIC DMA FIFO 2 Output Buffer-A Address Register (Default Value:0x0000_0000)
Offset: 0x0030 Register Name: CSIC_DMA_F2_BUFA_REG
Bit Read/Write Default/Hex Description
F2_BUFA
31:0 R/W 0x0
FIFO 2 output buffer-A address.
6.1.8.10 0x0034 CSIC DMA FIFO 2 Output Buffer-A Address Result Register (Default Value:0x0000_0000)
Offset: 0x0034 Register Name: CSIC_DMA_F2_BUFA_RESULT_REG
Bit Read/Write Default/Hex Description
F2_BUFA_RESULT
Indicate the final F2_BUFA address used for DMA or FBC after
31:0 RO 0x0
software configuration or hardware calculation from Buffer-A
address register or buffer address fifo. Only used for debug.
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6.1.8.11 0x0038 CSIC DMA Buffer Length Register (Default Value:0x0280_0500)
Offset: 0x0038 Register Name: CSIC_DMA_BUF_LEN_REG
Bit Read/Write Default/Hex Description
31:30 / / /
BUF_LEN_C
DMA_MODE: Buffer length of chroma C in a line. Unit is byte.
29:16 R/W 0x280 LBC_MODE: Buffer length Stride of luminance Y in ONLY Y line.
Unit is byte.
Only Readable when BUF_LENGTH_CFG_MODE is set 0.
15:14 / / /
BUF_LEN
DMA_MODE:Buffer length of luminance Y in a line. Unit is byte.
13:0 R/W 0x500 LBC_MODE: Buffer length Stride of luminance Y and chroma C in
YC line. Unit is byte.
Only Readable when BUF_LENGTH_CFG_MODE is set 0.
6.1.8.12 0x003C CSIC DMA Flip Size Register (Default Value:0x02D0_0500)
Offset: 0x003C Register Name: CSIC_DMA_FLIP_SIZE_REG
Bit Read/Write Default/Hex Description
31:29 / / /
VER_LEN
28:16 R/W 0x2d0 Vertical line number when in VFLIP mode. Unit is line.
Only Readable when FLIP_SIZE_CFG_MODE is set to 0.
15:14 / / /
VALID_LEN
Valid components of a line when in HFLIP mode. Unit is pixel
13:0 R/W 0x500
component.
Only Readable when FLIP_SIZE_CFG_MODE is set to 0.
6.1.8.13 0x0040 CSIC DMA Video Input Timeout Threshold0 Register (Default Value:0x0000_0000)
Offset: 0x0040 Register Name: CSIC_DMA_VI_TO_TH0_REG
Bit Read/Write Default/Hex Description
Video Input Timeout Threshold0
31:0 R/W 0x0 Set VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH0
after VI_TO_CNT_EN is set, the Time Unit is a 12M clock period.
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6.1.8.14 0x0044 CSIC DMA Video Input Timeout Threshold1 Register(Default Value:0x0000_0000)
Offset: 0x0044 Register Name: CSIC_DMA_VI_TO_TH1_REG
Bit Read/Write Default/Hex Description
Video Input Timeout Threshold1
Set VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH1
31:0 R/W 0x0
after getting the first frame has been input, the Time Unit is a
12M clock period.
6.1.8.15 0x0048 CSIC DMA Video Input Timeout Counter Value Register (Default Value:0x0000_0000)
Offset: 0x0048 Register Name: CSIC_DMA_VI_TO_CNT_VAL_REG
Bit Read/Write Default/Hex Description
Video Input Timeout Counter Value
31:0 R 0x0
Indicate the current value of Video Input Timeout Counter
6.1.8.16 0x004C CSIC DMA Capture Status Register (Default Value:0x0000_0000)
Offset: 0x004C Register Name: CSIC_DMA_CAP_STA_REG
Bit Read/Write Default/Hex Description
31:3 / / /
FIELD_STA
The status of the received field
2 R 0x0
0: Field 0
1: Field 1
VCAP_STA
Video capture in progress
Indicates the CSI is capturing video image data (multiple frames).
1 R 0x0
The bit is set at the start of the first frame after enabling video
capture. When software disables video capture, it clears itself
after the last pixel of the current frame is captured.
SCAP_STA
Still capture in progress
Indicates the CSI is capturing still image data (single frame). The
bit is set at the start of the first frame after enabling still frame
0 R 0x0 capture. It clears itself after the last pixel of the first frame is
captured.
For CCIR656 interface, if the output format is frame planar YCbCr
420 mode, the frame end means the field2 end, the other frame
end means filed end.
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6.1.8.17 0x0050 CSIC DMA Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0050 Register Name: CSIC_DMA_INT_EN_REG
Bit Read/Write Default/Hex Description
31:16 / / /
FRM_LOST_INT_EN
15 R/W 0x0 Set an INT when frame starts with empty Buffer Address FIFO,
only use in BUF Address FIFO MODE.
STORED_FRM_CNT_INT_EN
Set an INT when the value of CSIC_DMA_STORED_FRM_CNT
14 R/W 0x0
reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF
Address FIFO MODE.
BUF_ADDR_FIFO_INT_EN
Set an INT when content in BUF Address FIFO less than
13 R/W 0x0
CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address
FIFO MODE.
VIDEO_INPUT_TO_INT_EN
12 R/W 0x0 Set an INT when no video input exceeds the setting threshold
time
CLR_FRAME_CNT_INT_EN
11 R/W 0x0
Set a INT when clear Frame cnt.
10:8 / / /
VS_INT_EN
vsync flag
7 R/W 0x0 The bit is set when vsync come. And at this time load the buffer
address for the coming frame. So after this irq come, changing
the buffer address could only effect next frame
HB_OF_INT_EN
6 R/W 0x0 Hblank FIFO overflow
The bit is set when 3 FIFOs still overflow after the hblank.
LC_INT_EN
Line counter flag
5 R/W 0x0
The bit is set when the specific line has been written to dram
every frame. The line number is set in the line counter register.
FIFO2_OF_INT_EN
4 R/W 0x0 FIFO 2 overflow
The bit is set when the FIFO 2 became overflow.
FIFO1_OF_INT_EN
3 R/W 0x0 FIFO 1 overflow
The bit is set when the FIFO 1 became overflow.
FIFO0_OF_INT_EN
2 R/W 0x0 FIFO 0 overflow
The bit is set when the FIFO 0 became overflow.
1 R/W 0x0 FD_INT_EN
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Offset: 0x0050 Register Name: CSIC_DMA_INT_EN_REG
Bit Read/Write Default/Hex Description
Frame done
Indicates the CSI has finished capturing an image frame. Applies
to video capture mode. The bit is set after each completed frame
capturing data is written to buffer as long as video capture
remains enabled.
CD_INT_EN
Capture done
Indicates the CSI has completed capturing the image data.
For still capture, the bit is set when one frame data has been
written to buffer.
0 R/W 0x0
For video capture, the bit is set when the last frame has been
written to buffer after video capture has been disabled.
For CCIR656 interface, if the output format is frame planar YCbCr
420 mode, the frame end means the field2 end, the other frame
end means field end.
6.1.8.18 0x0054 CSIC DMA Interrupt Status Register (Default Value:0x0000_0000)
Offset: 0x0054 Register Name: CSIC_DMA_INT_STA_REG
Bit Read/Write Default/Hex Description
31:16 / / /
FRM_LOST_INT_PD
15 R/W1C 0x0 Set an INT when frame starts with empty Buffer Address FIFO,
only use in BUF Address FIFO MODE.
STORED_FRM_CNT_INT_PD
Set an INT when the value of CSIC_DMA_STORED_FRM_CNT
14 R/W1C 0x0
reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF
Address FIFO MODE.
BUF_ADDR_FIFO_INT_PD
Set an INT when content in BUF Address FIFO less than
13 R/W1C 0x0
CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address
FIFO MODE.
VIDEO_INPUT_TO_INT_PD
12 R/W1C 0x0 Set an INT Pending when no video input exceeds the setting
threshold time.
CLR_FRAME_CNT_INT
11 R/W1C 0x0
Set a INT when clear Frame cnt.
10:8 / / /
VS_PD
7 R/W1C 0x0
vsync flag
6 R/W1C 0x0 LI_OF_PD
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Offset: 0x0054 Register Name: CSIC_DMA_INT_STA_REG
Bit Read/Write Default/Hex Description
Line information FIFO (16 lines) overflow
LC_PD
5 R/W1C 0x0
Line counter flag
FIFO2_OF_PD
4 R/W1C 0x0
FIFO 2 overflow
FIFO1_OF_PD
3 R/W1C 0x0
FIFO 1 overflow
FIFO0_OF_PD
2 R/W1C 0x0
FIFO 0 overflow
FD_PD
1 R/W1C 0x0
Frame done
CD_PD
0 R/W1C 0x0
Capture done
6.1.8.19 0x0058 CSIC DMA Line Counter Register (Default Value:0x0000_0000)
Offset: 0x0058 Register Name: CSIC_DMA_LINE_CNT_REG
Bit Read/Write Default/Hex Description
31:13 / / /
LINE_CNT_NUM
12:0 R/W 0x0 The LINE_CNT_NUM value is set by user,when internal line
counter reach the set value, the LC_PD will be set.
6.1.8.20 0x005C CSIC DMA Frame Counter Register (Default Value:0x0001_0000)
Offset: 0x005C Register Name: CSIC_DMA_FRM_CNT_REG
Bit Read/Write Default/Hex Description
FRM_CNT_CLR
31 R/W1C 0x0
When the bit set to 1, Frame cnt is cleared to 0.
PCLK_DMA_CLR_DISTANCE
30:16 R/W 0x1 Frame cnt clear cycle
N*TSYNC
FRM_CNT
Counter value of frame. When frame done comes, the internal
15:0 R 0x0
counter value add 1, and when the reg full, it is cleared to 0 .
When parser sent a sync signal, it is cleared to 0.
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6.1.8.21 0x0060 CSIC DMA Frame Clock Counter Register (Default Value:0x0000_0000)
Offset: 0x0060 Register Name: CSIC_DMA_FRM_CLK_CNT_REG
Bit Read/Write Default/Hex Description
31:24 / / /
FRM_CLK_CNT
Counter value between every frame. For instant hardware frame
rate statics.
23:0 R 0x0
The internal counter is added by one every 12 MHz clock cycle.
When frame done or vsync comes, the internal counter value is
sampled to FRM_CLK_CNT, and cleared to 0.
6.1.8.22 0x0064 CSIC DMA Accumulated and Internal Clock Counter Register (Default Value:0x0000_0000)
Offset: 0x0064 Register Name: CSIC_DMA_ACC_ITNL_CLK_CNT_REG
Bit Read/Write Default/Hex Description
ACC_CLK_CNT
The accumulated value of FRM_CLK_CNT for software frame
rate statics. Every interrupt of frame is done, the software
checks this accumulated value and clears it to 0. If the
31:24 R/WC 0x0
ACC_CLK_CNT is larger than 1, the software has lost frame.
When frame done or vsync comes, ACC_CLK_CNT =
ACC_CLK_CNT + 1, and cleared to 0 when writing this register.
ITNL_CLK_CNT
The instant value of internal frame clock counter.
23:0 R 0x0 When frame done interrupt comes, the software can query this
counter for judging whether it is the time for updating the
double buffer address registers.
6.1.8.23 0x0068 CSIC DMA FIFO Statistic Register (Default Value:0x0000_0000)
Offset: 0x0068 Register Name: CSIC_DMA_FIFO_STAT_REG
Bit Read/Write Default/Hex Description
31:30 / / /
Line Index
29:16 R 0x0
Indicates the line index in current vsync.
15:13 / / /
FIFO_FRM_MAX
12:0 R 0x0 Indicates the maximum depth of FIFO being occupied for whole
frame. Update at every vsync or framedone.
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6.1.8.24 0x006C CSIC DMA FIFO Threshold Register (Default Value:0x0000_0400)
Offset: 0x006C Register Name: CSIC_DMA_FIFO_THRS_REG
Bit Read/Write Default/Hex Description
31:12 / / /
FIFO_THRS
11:0 R/W 0x400 When FIFO occupied memory exceed the threshold, dram
frequency can not change.
6.1.8.25 0x0070 CSIC DMA PCLK Statistic Register (Default Value:0x0000_7FFF)
Offset: 0x0070 Register Name: CSIC_DMA_PCLK_STAT_REG
Bit Read/Write Default/Hex Description
31 / / /
PCLK_CNT_LINE_MAX
30:16 R 0x0 Indicates maximum pixel clock counter value for each line.
Update at every vsync or framedone.
15 / / /
PCLK_CNT_LINE_MIN
14:0 R 0x7FFF Indicates minimum pixel clock counter value for each line.
Update at every vsync or framedone.
6.1.8.26 0x0080 CSIC DMA BUF Address FIFO0 Entry Register (Default Value:0x0000_0000)
Offset: 0x0080 Register Name: CSIC_DMA_BUF_ADDR_FIFO0_ENTRY_REG
Bit Read/Write Default/Hex Description
CSIC_DMA_BUF_ADDR_FIFO0_ENTRY
31:0 R/W 0x0 FIFO Entry of Buffer Address FIFO0 for input frames to be stored,
only used in Buffer Addr FIFO Mode
6.1.8.27 0x0084 CSIC DMA BUF Address FIFO1 Entry Register (Default Value:0x0000_0000)
Offset: 0x0084 Register Name: CSIC_DMA_BUF_ADDR_FIFO1_ENTRY_REG
Bit Read/Write Default/Hex Description
CSIC_DMA_BUF_ADDR_FIFO1_ENTRY
31:0 R/W 0x0 FIFO Entry of Buffer Address FIFO1 for input frames to be stored,
only used in Buffer Addr FIFO Mode.
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6.1.8.28 0x0088 CSIC DMA BUF Address FIFO2 Entry Register (Default Value:0x0000_0000)
Offset: 0x0088 Register Name: CSIC_DMA_BUF_ADDR_FIFO2_ENTRY_REG
Bit Read/Write Default/Hex Description
CSIC_DMA_BUF_ADDR_FIFO2_ENTRY
31:0 R/W 0x0 FIFO Entry of Buffer Address FIFO2 for input frames to be stored,
only used in Buffer Addr FIFO Mode.
6.1.8.29 0x008C CSIC DMA BUF Threshold Register (Default Value:0x0020_0000)
Offset: 0x008C Register Name: CSIC_DMA_BUF_TH_REG
Bit Read/Write Default/Hex Description
31:21 / / /
CSIC_DMA_STORED_FRM_THRESHOLD
21:16 R/W 0x20 when stored frame counter value reaches the threshold ,
counter is cleared to 0 , only used in Buffer Addr FIFO Mode.
15:6 / / /
CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD
5:0 R/W 0x0 when content in Buffer Address FIFO less than the threshold, an
interrupt is set, only used in Buffer Addr FIFO Mode.
6.1.8.30 0x0090 CSIC DMA BUF Address FIFO Content Register (Default Value:0x0000_0000)
Offset: 0x0090 Register Name: CSIC_DMA_BUF_ADDR_FIFO_CON_REG
Bit Read/Write Default/Hex Description
31:22 / / /
CSIC_DMA_BUF_ADDR_FIFO2_CONTENT
21:16 RO 0x0 FIFO Content of address buffered in Buffer Address FIFO2, only
used in Buffer Addr FIFO Mode.
15:14 / / /
CSIC_DMA_BUF_ADDR_FIFO1_CONTENT
13:8 RO 0x0 FIFO Content of address buffered in Buffer Address FIFO1, only
used in Buffer Addr FIFO Mode.
7:6 / / /
CSIC_DMA_BUF_ADDR_FIFO0_CONTENT
5:0 RO 0x0 FIFO Content of address buffered in Buffer Address FIFO0, only
used in Buffer Addr FIFO Mode.
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6.1.8.31 0x0094 CSIC DMA Stored Frame Counter Register (Default Value:0x0000_0000)
Offset: 0x0094 Register Name: CSIC_DMA_STORED_FRM_CNT_REG
Bit Read/Write Default/Hex Description
31:8 / / /
CSIC_DMA_STORED_FRM_CNT
Indicates value of stored frames counter. When the counter
7:0 RO 0x0
value reaches CSIC_DMA_STORED_FRM_THRESHOLD, the
counter is cleared to 0. Only used in Buffer Addr FIFO Mode.
6.1.8.32 0x01F4 CSIC DMA Feature List Register(Default Value:0x0000_0000)
Offset: 0x01F4 Register Name: CSIC_FEATURE_REG
Bit Read/Write Default/Hex Description
31:2 / / /
DMA0_EMBEDDED_LBC
1 R 0x0 0: No Embedded LBC
1: Embedded LBC
DMA0_EMBEDDED_FBC
0 R 0x0 0: No Embedded DMA
1: Embedded FBC
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6.2 TV Decoder
6.2.1 Overview
The Television Decoder (TVD) is an interface that transforms Composite Video Broadcast Signal (CVBS) or
component signal into YUV data.
Features:
2-channel CVBS input and 1-channel CVBS decoder
CVBS input, NTSC and PAL supported
Supports YUV422, YUV420 format
With 1 channel 3D comb filter
Detection for signal locked and 625 lines
Programmable brightness, contrast, saturation
10-bit video ADCs
NOTE
Only F133-B supports TVD module.
6.2.2 Block Diagram
Figure 6-8 shows a block diagram of the TVD.
Figure 6-8 TVD Block Diagram
Analog Digital
Chroma
TVIN0
demodulate MBUS
Sync YC
TVIN1 clamp PGA ADC WB DMA
detect seperation
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6.2.3 Functional Description
6.2.3.1 External Signals
Table 6-3 describes the external signals of TVD.
Table 6-3 TVD External Signals
Port Name Description Type
TVIN0 TV CVBS Input 0 AI
TVIN1 TV CVBS Input 1 AI
TVIN-VRP TV CVBS ADC Positive Reference Voltage P
TVIN-VRN TV CVBS ADC Negative Reference Voltage P
VCC-TVIN TV CVBS ADC Power P
6.2.4 Register List
Module Name Base Address
TVD_TOP 0x05C00000
TVD0 0x05C01000
Register Name Offset Description
TVD_TOP
TVD_TOP_MAP 0x0000 TVD TOP MAP Register
TVD_3D_CTL1 0x0008 TVD 3D DMA CONTROL Register1
TVD_3D_CTL2 0x000C TVD 3D DMA CONTROL Register2
TVD_3D_CTL3 0x0010 TVD 3D DMA CONTROL Register3
TVD_3D_CTL4 0x0014 TVD 3D DMA CONTROL Register4
TVD_3D_CTL5 0x0018 TVD 3D DMA CONTROL Register5
TVD_TOP_CTL 0x0024+0x20*N (N=0–3) TVD TOP CONTROL Register
TVD_ADC_CTL 0x0028+0x20*N (N=0–3) TVD ADC CONTROL Register
TVD_ADC_CFG 0x002C+0x20*N (N=0–3) TVD ADC CONFIGURATION Register
TVD0
TVD_EN 0x0000 TVD MODULE CONTROL Register
TVD_MODE 0x0004 TVD MODE CONTROL Register
TVD_CLAMP_AGC1 0x0008 TVD CLAMP & AGC CONTROL Register1
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Register Name Offset Description
TVD_CLAMP_AGC2 0x000C TVD CLAMP & AGC CONTROL Register2
TVD_HLOCK1 0x0010 TVD HLOCK CONTROL Register1
TVD_HLOCK2 0x0014 TVD HLOCK CONTROL Register2
TVD_HLOCK3 0x0018 TVD HLOCK CONTROL Register3
TVD_HLOCK4 0x001C TVD HLOCK CONTROL Register4
TVD_HLOCK5 0x0020 TVD HLOCK CONTROL Register5
TVD_VLOCK1 0x0024 TVD VLOCK CONTROL Register1
TVD_VLOCK2 0x0028 TVD VLOCK CONTROL Register2
TVD_CLOCK1 0x0030 TVD CHROMA LOCK CONTROL Register1
TVD_CLOCK2 0x0034 TVD CHROMA LOCK CONTROL Register2
TVD_YC_SEP1 0x0040 TVD YC SEPERATION CONROL Register1
TVD_YC_SEP2 0x0044 TVD YC SEPERATION CONROL Register2
TVD_ENHANCE1 0x0050 TVD ENHANCEMENT CONTROL Register1
TVD_ENHANCE2 0x0054 TVD ENHANCEMENT CONTROL Register2
TVD_ENHANCE3 0x0058 TVD ENHANCEMENT CONTROL Register3
TVD_WB1 0x0060 TVD WB DMA CONTROL Register1
TVD_WB2 0x0064 TVD WB DMA CONTROL Register2
TVD_WB3 0x0068 TVD WB DMA CONTROL Register3
TVD_WB4 0x006C TVD WB DMA CONTROL Register4
TVD_IRQ_CTL 0x0080 TVD DMA Interrupt Control Register
TVD_IRQ_STATUS 0x0090 TVD DMA Interrupt Status Register
TVD_DEBUG1 0x0100 TVD DEBUG CONTROL Register1
TVD_STATUS1 0x0180 TVD DEBUG STATUS Register1
TVD_STATUS2 0x0184 TVD DEBUG STATUS Register2
TVD_STATUS3 0x0188 TVD DEBUG STATUS Register3
TVD_STATUS4 0x018C TVD DEBUG STATUS Register4
TVD_STATUS5 0x0190 TVD DEBUG STATUS Register5
TVD_STATUS6 0x0194 TVD DEBUG STATUS Register6
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6.2.5 Register Description
6.2.5.1 0x0000 TVD TOP MAP Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TVD_TOP_MAP
Bit Read/Write Default/Hex Description
31:5 / / /
TVIN_SEL
TVIN Select
4 R/W 0x0
0:TVIN0
1:TVIN1
3:2 / / /
TVD_ADC_MAP
TVD ADC Map
1:0 R/W 0x0
01: CVBS_MODE
Others: Reserved
6.2.5.2 0x0008 TVD 3D DMA CONTROL Register1 (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: TVD_3D_CTL1
Bit Read/Write Default/Hex Description
31:6 / / /
COMB_3D_SEL
Comb 3D Select
5:4 R/W 0x0
00: TVD0
Others: Reserved
3:2 / / /
COMB_3D_EN
Comb 3D Enable
1 R/W 0x0
0: Disable
1: Enable
TVD_EN_3D_DMA
TVD Enable 3D DMA
0 R/W 0x0 0: Disable
1: Enable
Set 0x1 when enable 3D comb filter.
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6.2.5.3 0x000C TVD 3D DMA CONTROL Register2 (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: TVD_3D_CTL2
Bit Read/Write Default/Hex Description
DRAM_TRIG
31:0 R/W 0x0
DRAM Trigger
6.2.5.4 0x0010 TVD 3D DMA CONTROL Register3 (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: TVD_3D_CTL3
Bit Read/Write Default/Hex Description
COMB_3D_ADDR0
31:0 R/W 0x0
Comb 3D Address0
6.2.5.5 0x0014 TVD 3D DMA CONTROL Register4 (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: TVD_3D_CTL4
Bit Read/Write Default/Hex Description
COMB_3D_ADDR1
31:0 R/W 0x0
Comb 3D Address1
6.2.5.6 0x0018 TVD 3D DMA CONTROL Register5 (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: TVD_3D_CTL5
Bit Read/Write Default/Hex Description
COMB_3D_SIZE
31:0 R/W 0x0
Comb 3D Size
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6.2.5.7 0x0024+0x20*N(N=0~3) TVD TOP CONTROL Register (Default Value: 0x0000_0000)
Offset: 0x0024+0x20*N(N=0~3) Register Name: TVD_TOP_CTL
Bit Read/Write Default/Hex Description
31:25 / / /
LPF_DIG_SEL
Low Pass Filter Digital Select
24 R/W 0x0
0: 6M
1: 8M
23:5 / / /
LPF_DIG_EN
Low Pass Filter Digital Enable
4 R/W 0x0
0: Disable
1: Enable
3:0 / / /
6.2.5.8 0x0028+0x20*N(N=0~3) TVD ADC CONTROL Register (Default Value: 0x0000_0000)
Offset: 0x0028+0x20*N(N=0~3) Register Name: TVD_ADC_CTL
Bit Read/Write Default/Hex Description
31:5 / / /
LPF_SEL
Low Pass Filter Select
4:3 R/W 0x0
00: 11M
01: 16M
LPF_EN
Low Pass Filter Enable
2 R/W 0x0
0: Disable LPF circuit
1: Enable LPF circuit
AFE_EN
AFE Enable
1 R/W 0x0
0: Disable AFE circuit
1: Enable AFE circuit
ADC_EN
ADC Enable
0 R/W 0x0
0: Disable ADC circuit
1: Enable ADC circuit
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6.2.5.9 0x002C+0x20*N(N=0~3) TVD ADC CONFIGURATION Register (Default Value: 0x0000_0000)
Offset: 0x002C+0x20*N(N=0~3) Register Name: TVD_ADC_CFG
Bit Read/Write Default/Hex Description
ADC_TEST
ADC Test Mode Configuration
31 R/W 0x0
0: Normal mode
1: For ADC test
30:29 / / /
DATA_DLY
Data Delay Configuration
28 R/W 0x0
0: No delay
1: Delay ADC output data for half circle
27:19 / / /
CLP_STEP
18:16 R/W 0x0 CLAMP Step Configuration
DC level size step for up and down.
STAGE8_IBIAS
15:14 R/W 0x0
Stage8 Ibias Configuration
STAGE7_IBIAS
13:12 R/W 0x0
Stage7 Ibias Configuration
STAGE6_IBIAS
11:10 R/W 0x0
Stage6 Ibias Configuration
STAGE5_IBIAS
9:8 R/W 0x0
Stage5 Ibias Configuration
STAGE4_IBIAS
7:6 R/W 0x0
Stage4 Ibias Configuration
STAGE3_IBIAS
5:4 R/W 0x0
Stage3 Ibias Configuration
STAGE2_IBIAS
3:2 R/W 0x0
Stage2 Ibias Configuration
STAGE1_IBIAS
1:0 R/W 0x0
Stage1 Ibias Configuration
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6.2.5.10 0x0000 TVD MODULE CONTROL Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TVD_EN
Bit Read/Write Default/Hex Description
31:27 / / /
EN_LOCK_DISABLE_WB2
26 R/W 0x0
Enable Lock Disable WB2
EN_LOCK_DISABLE_WB1
25 R/W 0x0
Enable Lock Disable WB1
24:16 / / /
CLR_RSMP_FIFO
Clear Resample FIFO
15 R/W 0x0 0: Release
1: Clear
Set 0x1 then 0x0 to reset resample FIFO.
14:1 / / /
TVD_EN_CH
TVD Enable CH
0 R/W 0x0
0: Disable
1: Enable
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6.2.5.11 0x0004 TVD MODE CONTROL Register (Default Value: 0x0000_0020)
Offset: 0x0004 Register Name: TVD_MODE
Bit Read/Write Default/Hex Description
31:9 / / /
BLUE_MODE_COLOR
Blue Mode Color
8 R/W 0x0
0: Blue
1: Black
7:6 / / /
BLUE_DISPLAY_MODE
Blue Display Mode
00 : Disabled
5:4 R/W 0x2
01 : Enabled
10 : Auto
11 : Reserved
3 / / /
PROGRESSIVE_MODE
Progressive Mode
2 R/W 0x0
0: Interlace mode
1: Progressive mode
SVIDEO_MODE
Svideo Mode
1 R/W 0x0
0 : CVBS
1 : S-Video
YPBPR_MODE
Ypbpr Mode
0 R/W 0x0
0 : Disable the component input
1 : Enable the component input
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6.2.5.12 0x0008 TVD CLAMP & AGC CONTROL Register1 (Default Value: 0xA001_DD02)
Offset: 0x0008 Register Name: TVD_CLAMP_AGC1
Bit Read/Write Default/Hex Description
CAGC_TARGET
31:24 R/W 0xA0 Cagc Target
These bits set the chroma AGC target
23:17 / / /
CAGC_EN
Cagc Enable
16 R/W 0x1
0 : OFF
1 : ON
AGC_TARGET
Auto Gain Control Target
When AGC_EN = 1 , the AGC_TARGET is used to directly digital AGC
15:8 R/W 0xDD circuit.
When AGC_EN = 0 , the AGC_TARGET is used to directly drive the
analog PGA.
(64 represents 1x, 32 represents 0.5x).
7:2 / / /
AGC_FREQUENCE
Auto Gain Control Freqence
1 R/W 0x1
0 : AGC gain update once per line
1 : AGC gain update once per frame
AGC_EN
Auto Gain Control Enable
0 R/W 0x0
0 : AGC disable
1 : AGC enable
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6.2.5.13 0x000C TVD CLAMP & AGC CONTROL Register2 (Default Value: 0x8682_6440)
Offset: 0x000C Register Name: TVD_CLAMP_AGC2
Bit Read/Write Default/Hex Description
BLACK_LVL_CLP
Black Level Clamp
31 R/W 0x1
0: subtraction 0
1: subtraction 16
30:29 / / /
AGC_GATE_BEGIN
28:16 R/W 0x682 AGC Gate Begin
Count from hsync to the next line AGC gate
AGC_BACKPORCH_DLY
15:8 R/W 0x64 AGC Backporch Delay
Count from sync tip to back porch gate
7 / / /
AGC_GATE_WIDTH
6:0 R/W 0x40
AGC Gate Width
6.2.5.14 0x0010 TVD HLOCK CONTROL Register1 (Default Value: 0x2000_0000)
Offset: 0x0010 Register Name: TVD_HLOCK1
Bit Read/Write Default/Hex Description
H_SAMPLE_STEP
31:0 R/W 0x20000000 H Sample Step
H_SAMPLE_STEP = Fout/Fin X 2^30
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6.2.5.15 0x0014 TVD HLOCK CONTROL Register2 (Default Value: 0x4ED6_0000)
Offset: 0x0014 Register Name: TVD_HLOCK2
Bit Read/Write Default/Hex Description
HS_FILTER_GATE_END_TIME
HSYNC Filter Gate End Time
31:24 R/W 0x4E
These bits specify the end of the horizontal-blank-interval window.
Default/Hex = 78
HS_FILTER_GATE_START_TIME
HSYNC Filter Gate Start Time
23:16 R/W 0xD6 These bits specify the beginning of the horizontal-blank-interval
window.
Default/Hex = -42
15:4 / / /
HTOL
Horizontal Total Pixels Per Line
3:0 R/W 0x0 0: 858
1: 864
2~7: Reserved
6.2.5.16 0x0018 TVD HLOCK CONTROL Register3 (Default Value: 0x0FE9_502D)
Offset: 0x0018 Register Name: TVD_HLOCK3
Bit Read/Write Default/Hex Description
HS_TIP_DET_WIN_END_TIME
31:24 R/W 0x0F
HSYNC Tip Detect Window End Time
HS_TIP_DET_WIN_START_TIME
23:16 R/W 0xE9
HSYNC Tip Detect Window Start Time
HS_RISING_DET_WIN_END_TIME
15:8 R/W 0x50
HSYNC Rising Detect Window End Time
HS_RISING_DETECT_WINDOW_START_TIME
7:0 R/W 0x2D
HSYNC Rising Detect Window Start Time
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6.2.5.17 0x001C TVD HLOCK CONTROL Register4 (Default Value: 0x3E3E_8000)
Offset: 0x001C Register Name: TVD_HLOCK4
Bit Read/Write Default/Hex Description
HS_FINE_TO_COARSE_OFFSET
31:24 R/W 0x3E
HSYNC Fine To Coarse Offset
HS_RISING_TIME_FOR_FINE_DET
23:16 R/W 0x3E
HSYNC Rising Time For Fine Detect
HS_DET_WIN_END_TIME_FOR_CORASE_DET
15:8 R/W 0x80
HSYNC Detect Window End Time For Corase Detect
HS_DET_WIN_START_TIME_FOR_COARSE_DET
7:0 R/W 0x00
HSYNC Detect Window Start Time For Coarse Detect
6.2.5.18 0x0020 TVD HLOCK CONTROL Register5 (Default Value: 0x4E22_5082)
Offset: 0x0020 Register Name: TVD_HLOCK5
Bit Read/Write Default/Hex Description
BACKPORCH_DET_WIN_END_TIME
31:24 R/W 0x4E
Backporch Detect Window End Time
BACKPORCH_DET_WIN_START_TIME
23:16 R/W 0x22
Backporch Detect Window Start Time
HACT_WIDTH
15:8 R/W 0x50
Hactive Width
HACT_START
7:0 R/W 0x82
Hactive Start
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6.2.5.19 0x0024 TVD VLOCK CONTROL Register1 (Default Value: 0x0061_0220)
Offset: 0x0024 Register Name: TVD_VLOCK1
Bit Read/Write Default/Hex Description
31:27 / / /
VACT_HEIGHT
26:16 R/W 0x61
Vactive Height
15 / / /
VACTIVE_START
14:4 R/W 0x22
VACT START
3 / / /
VTOL
Vertical Total Line Per Frame
2:0 R/W 0x0
0 : 525 line
1 : 625 line
6.2.5.20 0x0028 TVD VLOCK CONTROL Register2 (Default Value: 0x000E_0070)
Offset: 0x0028 Register Name: TVD_VLOCK2
Bit Read/Write Default/Hex Description
31:21 / / /
HS_DET_DISABLE_END_LINE
20:16 R/W 0xE
Hsync Detector Disable End Line
15:7 / / /
HS_DET_DISABLE_START_LINE
6:0 R/W 0x70
Hsync Dectector Disable Start Line
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6.2.5.21 0x0030 TVD CHROMA LOCK CONTROL Register1 (Default Value: 0x0046_3201)
Offset: 0x0030 Register Name: TVD_CLOCK1
Bit Read/Write Default/Hex Description
31:29 / / /
COLOR_STD_NTSC
Color Standard Ntsc
28 R/W 0x0 0: NTSC358
1: NTSC443
Only valid when COLOR_STD set as NTSC
CHROMA_LPF
CHROMA Low Pass Filter
00: Narrow
27:26 R/W 0x0
01: Middle
10: Wide
11: Reserved
25 / / /
WIDE_BURST_GATE
Wide Burst_Gate
24 R/W 0x0
0: Narrow burst gate
1: Wide burst gate
BURST_GATE_END_TIME
23:16 R/W 0x46
Burst Gate End Time
BURST_GATE_START_TIME
15:8 R/W 0x32
Burst Gate Start Time
7:4 / / /
COLOR_STD
COLOR Standard
000: NTSC
3:1 R/W 0x0 001: PAL (I,B,G,H,D,N)
010: PAL (M)
011: PAL (CN)
100: SECAM
COLOR_KILLER_EN
0 R/W 0x1 Color Killer Enable
1: Disable color when chroma unlock
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6.2.5.22 0x0034 TVD CHROMA LOCK CONTROL Register2 (Default Value: 0x21F0_7C1F)
Offset: 0x0034 Register Name: TVD_CLOCK2
Bit Read/Write Default/Hex Description
C_SAMPLE_STEP
31:0 R/W 0x21F07C1F C Sample Step
C_SAMPLE_STEP = Fsc/Fin X 2^30
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6.2.5.23 0x0040 TVD YC SEPERATION CONROL Register1 (Default Value: 0x0000_4209)
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Offset: 0x0040 Register Name: TVD_YC_SEP1
Bit Read/Write Default/Hex Description
31:30 / / /
CHROMA_CORING_EN
29 R/W 0x0
Chroma Coring Enable
3D_COMB_FACTOR
28:26 R/W 0x0
3D Comb Factor
2D_COMB_FACTOR
25:23 R/W 0x0
2D Comb Factor
NOTCH_FACTOR
22:20 R/W 0x0
Notch Factor
19:17 / / /
COMB_FILTER_BUF_CLR
Comb Filter Buffer Clear
16 R/W 0x0
0: Not clear
1: Clear
PAL_CHROMA_LVL
15:10 R/W 0x10 PAL Chroma Level
Chroma level threshold for chroma comb filter select
CHROMA_BANDPASS_FILTER_EN
Chroma Bandpass Filter Enable
9 R/W 0x1
0: Disable
1: Enable
SECAM_NOTCH_WIDE
Notch bandwidth
8 R/W 0x0
0 : Narrow
1 : Wide
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2D_COMB_FILTER_MODE
2D Comb Filter Mode
For NTSC:
0000: 2D comb
0001~0010: Reserved
0011: 1D comb
0100~1000: Reserved
For PAL:
7:4 R/W 0x0
0000:2D comb filter1
0001: 1D comb filter1
0010: 2D comb filter2
0011: 1D comb filter2
0100: 1D comb filter3
0101: Reserved
0110: 2D comb filter3
0111~1000:Reserved
3D_COMB_FILTER_DIS
3D Comb Filter Disable
3 R/W 0x1
0: Enable 3D comb filter
1: Disable 3D comb filter
3D_COMB_FILTER_MODE
3D Comb_Filter Mode
000: 2D mode
2:0 R/W 0x1
001: 3D YC separation mode1
010~011: reserved
0100: 3D YC separation mode2
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6.2.5.24 0x0044 TVD YC SEPERATION CONROL Register2 (Default Value: 0xFF64_40AF)
Offset: 0x0044 Register Name: TVD_YC_SEP2
Bit Read/Write Default/Hex Description
V_NOISE_FACTOR
31:30 R/W 0x3
Vertical Noise Factor
BURST_NOISE_FACTOR
29:28 R/W 0x3
Burst Noise Factor
CHROMA_NOISE_FACTOR
27:26 R/W 0x3
Chroma Noise Factor
LUMA_NOISE_FACTOR
25:24 R/W 0x3
Luma Noise Factor
NOISE_THRESHOLD
23:17 R/W 0x32
Noise Threshold
NOISE_DET_EN
16 R/W 0x0
Noise Detect Enable
MOTION_DET_NOISE_THRESHOLD
15:9 R/W 0x20
Motion Detect Noise Threshold
MOTION_DET_NOISE_DET_EN
8 R/W 0x0
Motion Detect Noise Detect Enable
CHROMA_V_FILTER_GAIN
7:6 R/W 0x2
Chroma Vertical Filter Gain
LUMA_V_FILTER_GAIN
5:4 R/W 0x2
Luma Vertical Filter Gain
H_CHROMA_FILTER_GAIN
3:2 R/W 0x3
Horizontal Chroma Filter Gain
H_LUMA_FILTER_GAIN
1:0 R/W 0x3
Horizontal Luma Filter Gain
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6.2.5.25 0x0050 TVD ENHANCEMENT CONTROL Register1 (Default Value: 0x1420_8000)
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Offset: 0x0050 Register Name: TVD_ENHANCE1
Bit Read/Write Default/Hex Description
31:30 / / /
SHARP_COEF2
29:28 R/W 0x1
Sharp Coef2
SHARP_COEF1
27:25 R/W 0x2 Sharp Coef1
Ysharp = Y + YH *(SHARP_COEF1/ SHARP_COEF2)
SHARP_EN
Sharp Enable
24 R/W 0x0
0: Disable
1: Enable
BRIGHT_OFFSET
Bright Offset
23:16 R/W 0x20 Set 0x00, brightness offset is -32;
Set 0x20, brightness offset is 0.
Set 0xFF, brightness offset is max.
CONTRAST_GAIN
Contrast Gain
15:8 R/W 0x80 Set 0x00, contrast gain is min ;
Set 0x80, contrast gain is 1.
Set 0xFF, contrast gain is max.
7:4 / / /
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YC_DLY
YC Delay
0000: Y and C no delay
0001: Y delay 1 cycle to C
0010: Y delay 2 cycle to C
0011: Y delay 3 cycle to C
0100: Y delay 4 cycle to C
0101: Y delay 5 cycle to C
0110: Y delay 6 cycle to C
3:0 R/W 0x0
0111: Y delay 7 cycle to C
1000: Reserved
1001: Reserved
1010: Reserved
1011: C delay 5 cycle to Y
1100: C delay 4 cycle to Y
1101: C delay 3 cycle to Y
1110: C delay 2 cycle to Y
1111: C delay 1 cycle to Y
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6.2.5.26 0x0054 TVD ENHANCEMENT CONTROL Register2 (Default Value: 0x0000_0680)
Offset: 0x0054 Register Name: TVD_ENHANCE2
Bit Read/Write Default/Hex Description
31:11 / / /
CHROMA_ENHANCE_STRENGTH
Chroma Enhance Strength
00: Mild
10:9 R/W 0x3
01: Low
10: Middle
11: High
CHROMA_ENHANCE_EN
Chroma Enhance Enable
8 R/W 0x0
0: Disable
1: Enable
SATURATION_GAIN
Saturation Gain
7:0 R/W 0x80 Set 0x00, saturation gain is min ;
Set 0x80, saturation gain is 1.
Set 0xFF, saturation gain is max.
6.2.5.27 0x0058 TVD ENHANCEMENT CONTROL Register3 (Default Value: 0x0000_0000)
Offset: 0x0058 Register Name: TVD_ENHANCE3
Bit Read/Write Default/Hex Description
31:29 / / /
CB_CR_GAIN_EN
28 R/W 0x0
Cb Cr Gain Enable
CR_GAIN
27:16 R/W 0x0
Cr Gain
15:12 / / /
CB_GAIN
11:0 R/W 0x00
Cb Gain
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6.2.5.28 0x0060 TVD WB DMA CONTROL Register1 (Default Value: 0x02D0_0020)
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Offset: 0x0060 Register Name: TVD_WB1
Bit Read/Write Default/Hex Description
UV_SEQ
UV Sequence
31 R/W 0x0
0: UVUV
1: VUVU
30:29 / / /
YUV420_FILTER_EN
YUV420 Filter Enable
28 R/W 0x0
0: disable YUV420 WB data from YUV422 without chroma filter
1: enable YUV420 WB data from YUV422 with chroma filter
HACT_STRIDE
27:16 R/W 0x2D0 Hactive Stride
Horizontal active line stride
15:9 / / /
WB_ADDR_VALID
WB Address Valid
8 R/W 0x0
0: Invalid
1: Valid
7 / / /
FLIP_FIELD
6 R/W 0x0 Flip Field
This bit flips even/odd fields
WB_FRAME_MODE
WB Frame Mode
5 R/W 0x1
0: Odd field or even field (decided by bit2)
1: Frame
WB_MB_MODE
WB MB Mode
4 R/W 0x0
0: Planar mode
1: Mb mode
HYSCALE_EN
3 R/W 0x0
Hyscale_Enable
FIELD_SEL
Field_Select
2 R/W 0x0
0: field 0 only
1: filed 1 only
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WB_FMT
WB Format
1 R/W 0x0
0: YUV420
1: YUV422
WB_EN
WB Enable
0 R/W 0x0
0: Disable
1: Enable
6.2.5.29 0x0064 TVD WB DMA CONTROL Register2 (Default Value: 0x00F0_02D0)
Offset: 0x0064 Register Name: TVD_WB2
Bit Read/Write Default/Hex Description
31:27 / / /
VACT_NUM
26:16 R/W 0xF0
Vertical active line number
15:12 / / /
HACT_NUM
11:0 R/W 0x2D0
Horizontal active pixel number
6.2.5.30 0x0068 TVD WB DMA CONTROL Register3 (Default Value: 0x0000_0000)
Offset: 0x0068 Register Name: TVD_WB3
Bit Read/Write Default/Hex Description
CH1_Y_ADDR
31:0 R/W 0x0
Ch1 Y Address
6.2.5.31 0x006C TVD WB DMA CONTROL Register4 (Default Value: 0x0000_0000)
Offset: 0x006C Register Name: TVD_WB4
Bit Read/Write Default/Hex Description
CH1_C_ADDR
31:0 R/W 0x0
Ch1 C Address
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6.2.5.32 0x0080 TVD DMA Interrupt Control Register (Default Value: 0x0000_0000)
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Offset: 0x0080 Register Name: TVD_IRQ_CTL
Bit Read/Write Default/Hex Description
FIFO_3D_TX_O_EN
FIFO 3D TX Overflow Enable
31 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_3D_TX_U_EN
FIFO 3D TX Underflow Enable
30 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_3D_RX_O_EN
FIFO 3D RX Overflow ENable
29 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_3D_RX_U_EN
FIFO 3D RX Underflow Enable
28 R/W 0x0
0: IRQ disable
1: IRQ enable
27:25 / / /
FRAME_END_EN
Frame End Enable
24 R/W 0x0
0: IRQ disable
1: IRQ enable
23:9 / / /
FIFO_Y_U_EN
FIFO Y Underflow Enable
8 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_PB_U_EN
FIFO PB Underflow ENable
7 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_PR_U_EN
FIFO PR Underflow Enable
6 R/W 0x0
0: IRQ disable
1: IRQ enable
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FIFO_Y_O_EN
FIFO Y Overflow Enable
5 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_PB_O_EN
FIFO PB Overflow Enable
4 R/W 0x0
0: IRQ disable
1: IRQ enable
FIFO_PR_O_EN
FIFO PR Overflow Enable
3 R/W 0x0
0: IRQ disable
1: IRQ enable
2 / / /
UNLOCK_EN
Unlock Enable
1 R/W 0x0
0: IRQ disable
1: IRQ enable
LOCK_EN
Lock Enable
0 R/W 0x0
0: IRQ disable
1: IRQ enable
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6.2.5.33 0x0090 TVD DMA Interrupt Status Register (Default Value: 0x0000_0000)
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Offset: 0x0090 Register Name: TVD_IRQ_STATUS
Bit Read/Write Default/Hex Description
FIFO_3D_TX_O
FIFO 3D TX Overflow
31 R/W 0x0 0: FIFO work normal
1: FIFO overflow
Write 0x1 to clear this bit.
FIFO_3D_TX_U
FIFO 3D TX Underflow
30 R/W 0x0 0: FIFO work normal
1: FIFO underflow
Write 0x1 to clear this bit.
FIFO_3D_RX_O
FIFO 3D RX Overflow
29 R/W 0x0 0: FIFO work normal
1: FIFO overflow
Write 0x1 to clear this bit.
FIFO_3D_RX_U
FIFO 3D RX Underflow
28 R/W 0x0 0: FIFO work normal
1: FIFO underflow
Write 0x1 to clear this bit.
27:25 / / /
FRAME_END
24 R/W 0x0 Frame End
This bit is auto set every write back frame. Set 0x1 to clear this bit.
23:17 / / /
WB_ADDR_CHANGE_ERR
16 R/W 0x0 WB Address Change_Error
Write back address change error
15:9 / / /
FIFO_Y_U
FIFO Y Underflow
8 R/W 0x0 0: FIFO work normal
1: FIFO underflow
Write 0x1 to clear this bit.
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FIFO_C_U
FIFO C Underflow
7 R/W 0x0 0: FIFO work normal
1: FIFO underflow
Write 0x1 to clear this bit.
6 / / /
FIFO_Y_O
FIFO Y Overflow
5 R/W 0x0 0: FIFO work normal
1: FIFO overflow
Write 0x1 to clear this bit.
FIFO_C_O
FIFO C Overflow
4 R/W 0x0 0: FIFO work normal
1: FIFO overflow
Write 0x1 to clear this bit.
3:2 / / /
UNLOCK
Unlock
1 R/W 0x0
0: TVD status no change
1: TVD status change from lock to unlock
LOCK
Lock
0 R/W 0x0
0: TVD status no change
1: TVD status change from unlock to lock
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6.2.5.34 0x0100 TVD DEBUG CONTROL Register1 (Default Value: 0x0010_0000)
Offset: 0x0100 Register Name: TVD_DEBUG1
Bit Read/Write Default/Hex Description
CLAMP_UPDN_CYCLES
31:25 R/W 0x0
Clamp Updn Cycles
CLAMP_DN_START
Clamp Dn Start
24 R/W 0x0 Write 0x1 to make clamp up, clamp up value is determine by
CLAMP_UPDN_CYCLES. Note that this bit is only valid when
CLAMP_MODE is set as 0x1.
CLAMP_UP_START
Clamp Up Start
23 R/W 0x0 Write 0x1 to make clamp up, clamp up value is determine by
CLAMP_UPDN_CYCLES. Note that this bit is only valid when
CLAMP_MODE is set as 0x1.
CLAMP_MODE
Clamp Mode
22 R/W 0x0
0: Normal, auto clamp control
1: Debug mode, clamp control by register
AFE_GAIN_MODE
Afe Gain Mode
21 R/W 0x0
0: Auto gain mode
1: Debug mode, AFE gain is determine by AFE_GAIN_VALUE
UNLOCK_RST_GAIN_EN
20 R/W 0x1
Unlock Reset Gain Enable
TRUNCATION_RST_GAIN_EN
19 R/W 0x0
Truncation Reset Gain Enable
TRUNCATION2_RST_GAIN_EN
18 R/W 0x0
Truncation2 Reset Gain Enable
TVIN_LOCK_HIGH
17 R/W 0x0
TVIN Lock High
TVIN_LOCK_DEBUG
16 R/W 0x0
TVIN Lock Debug
AFE_GAIN_VALUE
15:8 R/W 0x0
AFE Gain Value
7:0 / / /
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6.2.5.35 0x0180 TVD DEBUG STATUS Register1 (Default Value: 0x0000_0020)
Offset: 0x0180 Register Name: TVD_STATUS1
Bit Read/Write Default/Hex Description
31:24 / / /
CHROMA_MAGNITUDE_STATUS
23:16 R 0x0
These bits contain the chroma magnitude.
AGC_DEGITAL_GAIN_STATUS
15:8 R 0x0
These bits contain the digital AGC gain value.
AGC_ANALOG_GAIN_STATUS
7:0 R 0x20
These bits contain the analog AGC gain value.
6.2.5.36 0x0184 TVD DEBUG STATUS Register2 (Default Value: 0x21F0_7C1F)
Offset: 0x0184 Register Name: TVD_STATUS2
Bit Read/Write Default/Hex Description
31:0 R 0x21f07c1f CHROMA_SYNC_DTO_STATUS
6.2.5.37 0x0188 TVD DEBUG STATUS Register3 (Default Value: 0x2000_0000)
Offset: 0x0188 Register Name: TVD_STATUS3
Bit Read/Write Default/Hex Description
31:30 / / /
H_SYNC_DTO_STS
29:0 R 0x20000000
Horizontal Sync Dto Status
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6.2.5.38 0x018C TVD DEBUG STATUS Register4 (Default Value: 0x0000_0001)
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Offset: 0x018C Register Name: TVD_STATUS4
Bit Read/Write Default/Hex Description
31:24 / / /
VCR_REW
23 R 0x0
VCR Rewind Detected
VCR_FF
22 R 0x0
VCR Fast-Forward Detected
VCR_TRICK
21 R 0x0
VCR Trick-Mode Detected
VCR
20 R 0x0
VCR Detected
NOISY
Noisy Signal Detected. This bit is set when the detected noise value
19 R 0x0
(status register 7Fh) is greater than the value programmed into the
“noise_thresh” register (05h).
DET_625_LINE
Detect 625 Line
18 R 0x0
0: 525 lines
1: 625 lines
SECAM_DET
17 R 0x0
SECAM Colour Mode Detected
PAL_DET
16 R 0x0
PAL Colour Mode Detected
15:11 / / /
VNON_STANDARD
10 R 0x0
Vertical Frequency Non-Standard Input Signal Detected
HNON_STANDARD
9 R 0x0
Horizontal Frequency Non-Standard Input Signal Detected
PROSCAN_DET
8 R 0x0
Progressive Scan Detected
MACROVISION_COLOR_STRIPES_DET
7:5 R 0x0 The Number Indicates The Number Of Color Stripe
lines in each group
MACROVISION_VBI_PSEUDO_SYNC_PULSES_DET
Macrovision Vbi Pseudo Sync Pulses Detect
4 R 0x0
0: Undetected
1: Detected
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CHROMA_PLL_LOCKED_TO_COLOR_BURST
Chroma Pll Locked To Color Burst
3 R 0x0
0: Unlock
1: Locked
V_LOCK
Vertical Lock
2 R 0x0
0: Unlock
1: Locked
H_LINE_LOCK
Horizontal line locked
1 R 0x0
0: Unlock
1: Locked
NO_SIG_DET
No Signal Detected
0 R 0x1
0 : Signal Detected
1 :No Signal Detected
6.2.5.39 0x0190 TVD DEBUG STATUS Register5 (Default Value: 0x0000_0000)
Offset: 0x0190 Register Name: TVD_STATUS5
Bit Read/Write Default/Hex Description
BLK_LVL
31:22 R 0x0
Blank Level
SYNC_LVL
21:12 R 0x0
Sync Level
ADC_DAT_SH
11 R/W 0x0
ADC Data Show
10 / / /
ADC_DAT_VAL
9:0 R 0x0
ADC Data Value
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6.2.5.40 0x0194 TVD DEBUG STATUS Register6 (Default Value: 0x0000_0000)
Offset: 0x0194 Register Name: TVD_STATUS6
Bit Read/Write Default/Hex Description
31:11 / / /
MASK_UNKNOWN
10 R/W 0x0
Mask Unknown
MASK_SECAM
9 R/W 0x0
Mask Secam
MASK_NTSC443
8 R/W 0x0
Mask NTSC443
MASK_PAL60
7 R/W 0x0
Mask PAL60
MASK_PALCN
6 R/W 0x0
Mask Palcn
MASK_PALM
5 R/W 0x0
Mask Palm
AUTO_DET_EN
Auto Detect Enable
4 R/W 0x0
0: Disable
1: Enable
TV_STD
TV Standard
001: V525_NTSC
010: V625_PAL
3:1 R 0x0 011: V525_PALM
100: V625_PALN
101: V525_PAL60
110: V525_NTSC443
111: V625_SECAM
AUTO_DET_FINISH
0 R 0x0
Auto Detect Finish
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Contents
7 Memory................................................................................................................................................................... 558
7.1 SDRAM Controller (DRAMC) ........................................................................................................................... 558
7.2 SD/MMC Host Controller (SMHC) ................................................................................................................... 559
7.2.1 Overview ............................................................................................................................................. 559
7.2.2 Block Diagram ..................................................................................................................................... 559
7.2.3 Functional Descriptions....................................................................................................................... 560
7.2.4 Programming Guidelines..................................................................................................................... 573
7.2.5 Register List ......................................................................................................................................... 578
7.2.6 Register Description ............................................................................................................................ 580
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Figures
Figure 7-1 SMHC Block Diagram ....................................................................................................................................... 560
Figure 7-2 Command Token Format ................................................................................................................................. 563
Figure 7-3 Response Token Format .................................................................................................................................. 563
Figure 7-4 Data Packet Format for SDR ............................................................................................................................ 564
Figure 7-5 Data Packet Format for DDR ............................................................................................................................ 565
Figure 7-6 Data Packet Format for DDR in HS400 Mode .................................................................................................. 566
Figure 7-7 Single-Block and Multi-Block Read Operation ................................................................................................. 567
Figure 7-8 Single-Block and Multi-Block Read Operation ................................................................................................. 567
Figure 7-9 Phase Offset of Command and Data in SDR Mode .......................................................................................... 568
Figure 7-10 Phase Offset of Command and Data in DDR4 Mode (SMHC_NTSR[31] = 0) ................................................. 569
Figure 7-11 Phase Offset of Command and Data in DDR4 Mode ..................................................................................... 569
Figure 7-12 Phase Offset of Command and Data in DDR4 (2x Mode) (SMHC_NTSR[31] = 1) .......................................... 570
Figure 7-13 IDMAC Descriptor Structure Diagram ............................................................................................................ 571
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Tables
Table 7-1 SMHC Sub-blocks .............................................................................................................................................. 560
Table 7-2 SMHC External Signals....................................................................................................................................... 561
Table 7-3 SMHC0/1 Clock Sources .................................................................................................................................... 561
Table 7-4 SMHC2 Clock Sources........................................................................................................................................ 561
Table 7-5 Speed Modes Supported by SD 3.0 ................................................................................................................... 567
Table 7-6 Speed Modes Supported by eMMC 5.1 ............................................................................................................ 568
Table 7-7 Phase Offset of Command and Data in SDR Mode ........................................................................................... 569
Table 7-8 Phase Offset of Command and Data in DDR4 (2x) Mode ................................................................................. 570
Table 7-9 DES0 Definition ................................................................................................................................................. 571
Table 7-10 DES1 Definition ............................................................................................................................................... 572
Table 7-11 DES2 Definition ............................................................................................................................................... 572
Table 7-12 DES3 Definition ............................................................................................................................................... 572
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7 Memory
7.1 SDRAM Controller (DRAMC)
The DRAMC is embedded with 64 MB DDR2.
The DRAMC has the following features:
Embedded with 64 MB DDR2
Supports clock frequency up to 533 MHz for DDR2
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7.2 SD/MMC Host Controller (SMHC)
7.2.1 Overview
The SMHC controls the read/write operations on the secure digital (SD) cards, multimedia cards (MMC), and
various extended devices that is based on the secure digital input/output (SDIO) protocol. The processor
provides three SMHC interfaces for controlling the SD cards, MMCs, and SDIO devices.
The SMHC has the following features:
Supports Command Completion signals and interrupts to host processor, and Command Completion signal
disable feature
The SMHC0 controls the devices that comply with the Secure Digital Memory (SD mem-version 3.0)
The SMHC1 controls the device that complies with the protocol Secure Digital I/O (SDIO-version 3.0)
The SMHC2 controls the device that complies with the Multimedia Card (eMMC-version 5.0)
Maximum performance:
- SDR mode: 150 [email protected] V IO pad
- DDR mode: 50 [email protected] V IO pad
- DDR mode: 50 [email protected] V IO pad
Supports 1-bit or 4-bit data width
Hardware CRC generation and error detection
Programmable baud rate
Supports SDIO interrupt in 1-bit and 4-bit modes
Block size of 1 to 65535 bytes
Descriptor-based internal DMA controller
Internal 1 KB RXFIFO and 1 KB TXFIFO
7.2.2 Block Diagram
The following figure shows a block diagram of the SMHC.
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Figure 7-1 SMHC Block Diagram
AHB
S
Y
Register CMD Path
N
C
CLK
CMD
SD/SDIO/eMMC
Data Path DATA0
...
Data RX
DMAC FIFO
Data TX
SMHC contains the following sub-blocks:
Table 7-1 SMHC Sub-blocks
Sub-block Description
Used to configure the control signal for reading or writing the
Register
SD/SDIO/eMMC.
The DMA controller that controls the data transfer between the memory
DMAC
and SMHC.
A buffer for the data stream between the memory and the SMHC
FIFO
asynchronous clock domain.
Synchronizes the signals from the AHB clock domain to the SMHC clock
SYNC
domain.
CMD Path Sends commands to or receives commands from the SD/SDIO/eMMC.
Consists of Data TX and Data RX sub-modules. The Data TX sends data
Data Path blocks and the CRC codes to the SD/SDIO/eMMC. The Data RX receives
data blocks and the CRC codes from the SD/SDIO/eMMC.
7.2.3 Functional Description
7.2.3.1 External Signals
The following table describes the external signals of SMHC.
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Table 7-2 SMHC External Signals
Port Name Type Description
SDC0-CMD I/O, OD Command Signal for SD Card
SDC0-CLK O Clock for SD Card
SDC0-D[3:0] I/O Data Input and Output for SD Card
SDC0-RST O Reset for SD Card
SDC1-CMD I/O, OD Command Signal for SDIO Wi-Fi
SDC1-CLK O Clock for SDIO Wi-Fi
SDC1-D[3:0] I/O Data Input and Output for SDIO Wi-Fi
SDC2-CMD I/O, OD Command Signal for eMMC
SDC2-CLK O Clock for eMMC
SDC2-D[3:0] I/O Data Input and Output for eMMC
7.2.3.2 Clock Sources
The SMHC0/1 has 4 different clock sources. The SMHC2 has 5 different clock sources. You can select one of
them as the SMHC clock source. The following table describes the clock sources of the SMHC.
For clock setting, configurations, and gating information, refer to section 3.3 “CCU”.
Table 7-3 SMHC0/1 Clock Sources
Clock Sources Description
HOSC 24 MHz Crystal
PLL_PERI(1X) Peripheral Clock, the default value is 600 MHz
PLL_PERI(2X) Peripheral Clock, the default value is 1.2 GHz
PLL_AUDIO1(DIV2) Audio clock, the default value is 1536 MHz
Table 7-4 SMHC2 Clock Sources
Clock Sources Description
HOSC 24 MHz Crystal
PLL_PERI(1X) Peripheral Clock, the default value is 600 MHz
PLL_PERI(2X) Peripheral Clock, the default value is 1.2 GHz
PLL_PERI(800M) Peripheral Clock, the default value is 800 MHz
PLL_AUDIO1(DIV2) Audio clock, the default value is 1536 MHz
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7.2.3.3 Timing Diagram
Refer to the following relative specifications:
Physical Layer Specification Ver3.00 Final
SDIO Specification Ver2.00
Multimedia Cards (MMC – version 4.2)
JEDEC Standard – JESD84-44, Embedded Multimedia Card (eMMC) Card Product Standard
JEDEC Standard – JESD84-B45, Embedded Multimedia Card (eMMC) Electrical Standard (4.5 Device)
JEDEC Standard – JESD84-B50, Embedded Multimedia Card (eMMC) Electrical Standard (5.0)
7.2.3.4 Data Path
The SMHC and SD/SDIO/eMMC contains the following interface buses: CLK, CMD, and DATA 1/4. During one
clock cycle, the SMHC can transmit one bit command with one or two bits data in 1-ch DATA mode, or four or
eight bits data in 4-ch DATA mode. The CMD is a bidirection channel for initializing the SD/SDIO/eMMC and
transmitting commands. It can work in both the open-drain mode and push-pull mode. The DATA is also a
bidirection channel. It works in the push-pull mode.
Reading Data from the SD/SDIO/eMMC
The register configures the signals for the read operation, and synchronize the signals to the SMHC clock
domain. Then the Data RX reads data from the SD/SDIO/eMMC via the CLK/CMD/DATA interface buses and
writes the data in the FIFO. After that, the DMAC transfers the data from the FIFO to the memory.
Writing Data to the SD/SDIO/eMMC
The register configures the signals for the write operation, and synchronize the signals to the SMHC clock
domain. Then the DMAC reads data from the memory and writes the data to the FIFO. After that, the Data TX
reads the data from the FIFO and writes the data to the SD/SDIO/eMMC via the CLK/CMD/DATA interface buses.
7.2.3.5 Package Format
Data transfer over the SD/eMMC bus is based on command and data bitstreams that are initiated by a start bit
and terminated by a stop bit. There are three types of SD/eMMC packets: command token, response token,
and data packet.
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Command Tokens
The command token starts an operation. A command is sent from the host to a device. It is transferred serially
on the CMD line. Command tokens have the following coding scheme:
Figure 7-2 Command Token Format
Transmitter bit: Command content: command and address information or
‘1’= Host command parameter, protected by 7-bit CRC checksum End bit:
Start bit: Always‘1’
Always‘0’
0 1 Content CRC 1
Total Length = 48 bits
Each command token has 48 bits, preceded by a start bit (‘0’) and succeeded by an end bit (‘1‘). To detect
transmission errors, each token is protected by CRC bits.
Response Tokens
After receiving a command, the card returns a 48-bit or 136-bit response based on the command type.
A response token is sent from the device to the host as an answer to a previously received command. It is
transferred serially on the CMD line.
Figure 7-3 Response Token Format
Transmitter bit: Response content: mirrored command and status information
‘0’= Card response (R1 response), OCR register (R3 response) or RCA (R4 and R5 in
eMMC, R6 in SD), protected by 7-bit CRC checksum End bit:
Start bit: Always‘1’
Always‘0’
Short response 0 0 Content CRC 1
Total Length = 48 bits
Long response 0 0 Content = CID or CSD CRC 1
Total Length = 136 bits
Data Packets
Data can be transferred from the device to the host or vice versa. Data are transferred via the data lines.
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NOTE
F133 does not support the bus width of 8 bits.
Figure 7-4 Data Packet Format for SDR
1 Bit Bus (only DAT0 used) 8 Bits Bus (DAT7–DAT0 used)
End bit, always‘1’. Sent when
Start bit: transfer is interrupted by a CMD
Always‘0’ LSByte MSByte
LSBytes MSBytes
DAT0 0 b7 b6 ... b1 b0 ... b7 b6 ... b1 b0 1 DAT7 0 b7 ... b7 b7 CRC 1
Start bit:
DAT6 0 b6 ... b6 b6 CRC 1
Always‘0’
LSBytes MSBytes
DAT0 0 b7 b6 ... b1 b0 ... b7 b6 ... b1 b0 CRC 1 DAT5 0 b5 ... b5 b5 CRC 1
Block Length * 8 DAT4 0 b4 ... b4 b4 CRC 1
DAT3 0 b3 ... b3 b3 CRC 1
4 Bits Bus (DAT3–DAT0 used)
DAT2 0 b2 ... b2 b2 CRC 1
LSByte (High nibble) MSByte (Low nibble) DAT1 0 b1 ... b1 b1 CRC 1
DAT3 0 b7 b3 ... b7 b3 CRC 1 DAT0 0 b0 ... b0 b0 CRC 1
Block Length
DAT2 0 b6 b2 ... b6 b2 CRC 1
DAT1 0 b5 b1 ... b5 b1 CRC 1
DAT0 0 b4 b0 ... b4 b0 CRC 1
Block Length * 2
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Figure 7-5 Data Packet Format for DDR
4 Bits Bus DDR (DAT3–DAT0 used)
CLK
LSByte (High nibble) MSByte-1 (Low nibble)
LSByte+1 (High nibble) MSByte (Low nibble)
b15 b0 b0
0 b7 b7 b3 b3 1
DAT3 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b6 b6 b2 b2 1
DAT2 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b5 b5 b1 b1 b15 b0 b0
DAT1 0 X ... (CRC ... (CRC (CRC
1 X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b4 b4 b0 b0 1
DAT0 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
Block Length CRC
8 Bits Bus DDR (DAT7–DAT0 used)
CLK
LSByte MSByte-1
LSByte+1 MSByte
b15 b0 b0
0 b7 b7 b7 b7 1
DAT7 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b6 b6 b6 b6 1
DAT6 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b5 b5 b5 b5 b15 b0 b0
DAT5 0 X ... (CRC ... (CRC (CRC
1 X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b4 b4 b4 b4 1
DAT4 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b3 b3 b3 b3 1
DAT3 X ... (CRC ... (CRC (CRC X
(start) (odd) (odd) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b2 b2 b2 b2 1
DAT2 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b1 b1 b1 b1 b15 b0 b0
DAT1 0 X ... (CRC ... (CRC (CRC 1 X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 b0 b0 b0 b0 1
DAT0 X ... (CRC ... (CRC (CRC X
(start) (odd) (even) (odd) (even) (end)
odd) odd) even)
Block Length/2 CRC
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NOTE
Bytes data are not interleaved but CRCs are interleaved.
Start and end bits are only valid on the rising edge (“X” indicates “undefined”).
Figure 7-6 Data Packet Format for DDR in HS400 Mode
8 Bits Bus DDR for HS400 Output (DAT7–DAT0 used)
DS
LSByte MSByte-1
LSByte+1 MSByte
b15 b0 b0
0 0 b7 b7 b7 b7 1
DAT7 ... (CRC ... (CRC (CRC X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 0 b6 b6 b6 b6 1
DAT6 ... (CRC ... (CRC (CRC X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b5 b5 b5 b5 b15 b0 b0
DAT5 0 0 ... (CRC ... (CRC (CRC 1 X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 0 b4 b4 b4 b4 1
DAT4 (start) (start)
... (CRC ... (CRC (CRC X
(odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 0 b3 b3 b3 b3 1
DAT3 ... (CRC ... (CRC (CRC X
(start) (start) (odd) (odd) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 0 b2 b2 b2 b2 1
DAT2 ... (CRC ... (CRC (CRC X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b1 b1 b1 b1 b15 b0 b0
DAT1 0 0 ... (CRC ... (CRC (CRC 1 X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
b15 b0 b0
0 0 b0 b0 b0 b0 1
DAT0 X ... (CRC ... (CRC (CRC X
(start) (start) (odd) (even) (odd) (even) (end)
odd) odd) even)
Block Length/2 CRC
NOTE
Bytes data are not interleaved but CRCs are interleaved.
Start bits are valid when Data Strobe is High and Low.
End bits are only valid when Data Strobe is High (“X” indicates “undefined”).
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7.2.3.6 Data Transfer
Data transfers to or from the SD/eMMC card are done in blocks. Single and multiple block operations are widely
used during data transfer.
The following figure shows the single-block and multi-block read operation.
Figure 7-7 Single-Block and Multi-Block Read Operation
From host From card Data from
Stop command stops data transfer
to card to host card to host
CMD Command Response Command Response
DAT Data Block CRC Data Block CRC Data Block CRC
Block Read Operation Data Stop Operation
Multi-Block Operation
The following figure shows the single-block and multi-block write operation.
Figure 7-8 Single-Block and Multi-Block Read Operation
From host From card Data from CRC OK response
and busy from Stop command stops data transfer
to card to host card to host
card to host
CMD Command Response Command Response
DAT Data Block CRC Busy Data Block CRC Busy
Block Read Operation Data Stop Operation
Multi-Block Operation
7.2.3.7 Bus Speed Modes
The following table shows the bus speed modes supported by SD 3.0.
Table 7-5 Speed Modes Supported by SD 3.0
Mode I/O Voltage Bus Width Frequency Throughput
SDR104 1.8 V 1, 4 bits 0 to 208 MHz 0 to 104 MB/s
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Mode I/O Voltage Bus Width Frequency Throughput
SDR50 1.8 V 1, 4 bits 0 to 100MHz 0 to 50 MB/s
DDR50 1.8 V 1, 4 bits 0 to 50 MHz 0 to 50 MB/s
SDR25 1.8 V 1, 4 bits 0 to 50 MHz 0 to 25 MB/s
SDR12 1.8 V 1, 4 bits 0 to 25 MHz 0 to 12 MB/s
High Speed Mode (HS) 3.3 V 1, 4 bits 0 to 50 MHz 0 to 25 MB/s
Default Speed Mode (DS) 3.3 V 1, 4 bits 0 to 25 MHz 0 to 12 MB/s
The following table shows the bus speed modes supported by eMMC 5.0.
Table 7-6 Speed Modes Supported by eMMC 5.0
Mode Data Rate I/O Voltage Bus Width Frequency Throughput
Backwards Compatibility
Single 3.3 V/1.8 V 1, 4 bits 0 to 26 MHz 0 to 26 MB/s
with legacy MMC card
High Speed SDR Single 3.3 V/1.8 V 1, 4 bits 0 to 52 MHz 0 to 52 MB/s
High Speed DDR Dual 3.3 V/1.8 V 4 bits 0 to 52 MHz 0 to 104 MB/s
HS200 Single 1.8 V 4 bits 0 to 200 MHz 0 to 200 MB/s
7.2.3.8 Phase Offset of the Command and Data
You can configure the phase offset of the command and data by the SMHC_DRV_DL register.
SDR Mode
The following figure shows the phase offset of SDR command and data.
Figure 7-9 Phase Offset of Command and Data in SDR Mode
SDR Drive Delay = 0 SDR Drive Delay = 1
0 45 90 180 0 45 90 180
CLK CLK
CMD, DATA CMD, DATA
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Table 7-7 Phase Offset of Command and Data in SDR Mode
Drive Delay Command Data
The command is updated in 90° clock The data is updated in 90° clock
0
position position
The command is updated in 180° clock The data is updated in 180° clock
1
position position
DDR4 Mode
The following figure shows the phase offset of DDR4 command and data.
Figure 7-10 Phase Offset of Command and Data in DDR4 Mode (SMHC_NTSR[31] = 0)
DDR4 Drive Delay = 0
0 45 90 180 0 45 90 180 225 270
CLK CLK
CMD DATA
DDR4 Drive Delay = 1
0 45 90 180 0 45 90 180 225 270
CLK CLK
CMD DATA
Figure 7-11 Phase Offset of Command and Data in DDR4 Mode
Drive Delay Command Data
The command is updated in 90° clock The data is updated in 90° clock
0
position position
The command is updated in 180° clock The data is updated in 0° or 180° clock
1
position position
DDR4 (2x) Mode
The following figure shows the phase offset of DDR4 (2x mode) command and data.
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Figure 7-12 Phase Offset of Command and Data in DDR4 (2x Mode) (SMHC_NTSR[31] = 1)
DDR4 (2x mode) Drive Delay = 0
0 45 90 180 0 45 90 180 225 270
CLK CLK
CMD DATA
DDR4 (2x mode) Drive Delay = 1
0 45 90 180 0 45 90 180 225 270
CLK CLK
CMD DATA
Table 7-8 Phase Offset of Command and Data in DDR4 (2x) Mode
Drive Delay Command Data
The command is updated in 45° clock The data is updated in 45° clock
0
position position
The command is updated in 90° clock The data is updated in 90° clock
1
position position
7.2.3.9 Internal DMA Controller Description
The SMHC has an internal DMA controller (IDMAC) to transfer data between the host memory and SMHC port.
With a descriptor, the IDMAC can efficiently move data from the source to destination by automatically loading
the next DMA transfer arguments, which needs less CPU intervention. Before transferring data in the IDMAC,
the host driver should construct a descriptor list, configure arguments of every DMA transfer, and then launch
the descriptor and start the DMA.
The IDMAC has an interrupt controller. When enabled, it generates an interrupt to the HOST CPU in situations
such as data transmission is completed or some error is happened.
IDMAC Descriptor Structure
The IDMAC uses a descriptor with a chain structure, and each descriptor points to a unique buffer and the next
descriptor.
The following figure shows the internal formats of a descriptor.
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Figure 7-13 IDMAC Descriptor Structure Diagram
...
DES0 DES0 DES0
DES1 DES1 DES1
DES2 DES2 DES2
DES3 DES3 DES3
This figure illustrates the internal formats of a descriptor. The descriptor address must be aligned to the bus
width used for 32-bit buses. Each descriptor contains 16 bytes of control and status information.
DES0 corresponds to the [31:0] bits, DES1 corresponds to the [63:32] bits, DES2 corresponds to the [95:64] bits,
and DES3 corresponds the [127:96] bits in a descriptor.
The following table shows the bit definition of DES0.
Table 7-9 DES0 Definition
Bits Name Description
DES_OWN_FLAG
When set, this bit indicates that the descriptor is owned by the
31 HOLD
IDMAC. When this bit is reset, it indicates that the descriptor is owned
by the host. This bit is cleared when the transfer is over.
ERR_FLAG
30 ERROR
When some errors happen in transfer, this bit will be set to 1.
29:5 / /
CHAIN_MOD
4 Chain Flag When set to 1, this bit indicates that the second address in the
descriptor is the next descriptor address. It must be set to 1.
FIRST_FLAG
3 First DES Flag When set to 1, this bit indicates that this descriptor contains the first
buffer of data. It must be set to 1 in the first DES.
LAST_FLAG
2 Last DES Flag When set to 1, this bit indicates that the buffers this descriptor points
to are the last data buffer.
CUR_TXRX_OVER_INT_DIS
Disable Interrupt on When set to 1, this bit will prevent the setting of the TX/RX interrupt
1
completion bit of the IDMAC status register for data that ends in the buffer the
descriptor points to.
0 / /
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The following table shows the bit definition of DES1.
Table 7-10 DES1 Definition
Bits Name Description
31:13 / /
BUFF_SIZE
The bits indicate the data buffer byte size, which must be a multiple
12:0 Buffer size
of 4 bytes. If this field is 0, the DMA ignores this buffer and proceeds
to the next descriptor.
The following table shows the bit definition of DES2.
Table 7-11 DES2 Definition
Bits Name Descriptor
BUFF_ADDR
Buffer address
31:0 The bits indicate the physical address of the data buffer.
pointer
It is a word address.
The following table shows the bit definition of DES3.
Table 7-12 DES3 Definition
Bits Name Descriptor
NEXT_DESP_ADDR
Next descriptor The bits indicate the pointer to the physical memory where the next
31:0
address descriptor is present.
It is a word address.
7.2.3.10 Calibrating the Delay Chain
There are two delay chains in SMHC: data strobe delay chain and sample delay chain.
Data strobe delay chain: used to generate delay to make proper timing between Data Strobe and data signals.
Sample delay chain: used to generate delay to make proper timing between the internal card clock signal and
data signals.
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Each delay chain is made up with 64 delay cells. The delay time of one delay cell can be estimated through
delay chain calibration.
Follow the steps below to calibrate the delay chain:
Step 1 Enable SMHC. In order to calibrate the delay chain by the operation registers in SMHC, the SMHC must
be enabled through SMHC Bus Gating Reset Register and SMHCx Clock Register.
Step 2 Configure a proper clock for SMHC. The delay chain calibration is based on the clock for SMHC from
Clock Control Unit (CCU). The delay chain calibration is an internal function in SMHC and needs no
devices. So it is unnecessary to open the clock signal for devices. The recommended clock frequency
is 200 MHz.
Step 3 Set proper initial delay value. Writing 0xA0 to delay control register enables Delay Software Enable
(bit[7]) and sets initial delay value 0x20 to Delay chain (bit[5:0]). Then write 0x0 to delay control
register to clear the value.
Step 4 Write 0x8000 to delay control register to start calibrating the delay chain.
Step 5 Wait until the flag (bit14 in delay control register) of calibration done is set. The number of delay cells
is shown at bit[13:8] in delay control register. The delay time generated by these delay cells is equal
to the cycle of the SMHC clock nearly. This value is the result of calibration.
Step 6 Calculate the delay time of one delay cell according to the cycle of the SMHC clock and the result of
calibration.
7.2.4 Programming Guidelines
7.2.4.1 Initializing SMHC
Before data and commands are exchanged between a card and the SMHC, the SMHC needs to be initialized.
Follow the steps below to initialize the SMHC:
Step 1 Configure the corresponding GPIO register as an SMHC by Port Controller module; reset clock by
writing 1 to SMHC_BGR_REG[SMHCx_RST], and open clock gating by writing 1 to
SMHC_BGR_REG[SMHCx_GATING]; select clock sources and set the division factor by configuring the
SMHCx_CLK_REG (x = 0, 1) register.
Step 2 Configure SMHC_CTRL to reset the FIFO and controller, and enable the global interrupt; configure
SMHC_INTMASK to 0xFFCE to enable normal interrupts and error abnormal interrupts, and then
register the interrupt function.
Step 3 Configure SMHC_CLKDIV to open clock for devices; configure SMHC_CMD as the change clock
command (for example 0x80202000); send the update clock command to deliver clocks to devices.
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Step 4 Configure SMHC_CMD as a normal command. Configure SMHC_CMDARG to set command
parameters. Configure SMHC_CMD to set parameters like whether to send the response, the response
type, and the response length and then send the commands. According to the initialization process in
the protocol, you can finish SMHC initialization by sending the corresponding command one by one.
7.2.4.2 Writing a Single Data Block
To write a single data block, follow the steps below:
Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To write one block data to sector1, configure SMHC_BYTCNT[BYTE_CNT] to 0x200 and configure the
descriptor according to the data size; set the data sector address of CMD24 (Single Data Block Write)
to 0x1, write 0x80002758 to SMHC_CMD, and send CMD24 command to write data to the device.
Step 4 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successfully; otherwise, continue
to wait until timeout, and then exit the process.
Step 5 Check whether SMHC_IDST[TX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 6 Check whether SMHC_RINTSTS[DTC] is 1. If yes, the data transfer and CMD24 writing operations are
completed. Otherwise, abnormity exists. Read SMHC_RINTSTS and SMHC_STATUS to query the
existing abnormity.
Step 7 Send CMD13 command to query whether the device writing operation is completed and returns to
the idle status. For example, device RCA is 0x1234, first set SMHC_CMDARG to 0x12340000, write
0x8000014D to SMHC_CMD, go to step4 to ensure command transfer completed, and then check
whether the highest bit of SMHC_RESP0 (CMD13 response) is 1. If yes, the device is in the idle status,
and the next command can be sent. Otherwise, the device is in the busy status. Continue to send
CMD13 to wait for the device to enter the idle status until timeout.
7.2.4.3 Reading a Single Data Block
To read a single data block, follow the steps below:
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Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To read one block data from sector1, configure SMHC_BYTCNT[BYTE_CNT] to 0x200 and configure the
descriptor according to the data size; set the data sector address of CMD17 command (Single Data
Block Read) to 0x1, write 0x80002351 to SMHC_CMD, and send CMD17 command to read data from
the device to DRAM/SRAM.
Step 4 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successfully; otherwise, continue
to wait until timeout, and then exit the process.
Step 5 Check whether SMHC_IDST[RX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 6 Check whether SMHC_RINTSTS[DTC] is 1. If yes, data transfer and CMD17 reading operation are
completed. Otherwise, abnormity exists. Read SMHC_RINTSTS and SMHC_STATUS to query the
existing abnormity.
7.2.4.4 Writing Open-Ended Multiple Data Blocks (CMD25 + Auto CMD12)
To write open-ended multiple data blocks, follow the steps below:
Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To write three blocks of data to sectors begin with sector0, configure SMHC_BYTCNT[BYTE_CNT] to
0x600 and configure the descriptor according to the data size; set the data sector address of CMD25
command (Multiple Data Blocks Write) to 0x0, write 0x80003759 to SMHC_CMD, and send CMD25
command to read data from the device to DRAM/SRAM.
Step 4 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successfully; otherwise, continue
to wait until timeout, and then exit the process.
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Step 5 Check whether SMHC_IDST[RX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 6 Check whether SMHC_RINTSTS[ACD] and SMHC_RINTSTS[DTC] are both 1. If yes, the data transfer,
CMD12 transfer, and CMD25 writing operations are completed. Otherwise, abnormity exists. Read
SMHC_RINTSTS and SMHC_STATUS to query the existing abnormity.
Step 7 Send CMD13 command to query whether the device writing operation is completed and returns to
the idle status. For example, device RCA is 0x1234, first set SMHC_CMDARG to 0x12340000, write
0x8000014D to SMHC_CMD, go to step4 to ensure command transfer completed, and then check
whether the highest bit of SMHC_RESP0 (CMD13 response) is 1. If yes, the device is in the idle status,
and the next command can be sent. Otherwise, the device is in the busy status. Continue to send
CMD13 to wait for the device to enter the idle status until timeout.
7.2.4.5 Reading Open-Ended Multiple Data Blocks (CMD18 + Auto CMD12)
To read open-ended multiple data blocks, follow the steps below:
Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To read three blocks of data from sectors begin with sector0, configure SMHC_BYTCNT[BYTE_CNT] to
0x600 and configure the descriptor according to the data size; set the data sector address of CMD18
command (Multiple Data Blocks Read) to 0x0, write 0x80003352 to SMHC_CMD, and send CMD18
command to read data to the device. When the data transfer is completed, CMD12 will be sent
automatically.
Step 4 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successfully; otherwise, continue
to wait until timeout, and then exit the process.
Step 5 Check whether SMHC_IDST[RX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 6 Check whether SMHC_RINTSTS[ACD] and SMHC_RINTSTS[DTC] are both 1. If yes, data transfer,
CMD12 transfer, and CMD18 reading operation are completed. Otherwise, abnormity exists. Read
SMHC_RINTSTS and SMHC_STATUS to query the existing abnormity.
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7.2.4.6 Writing Pre-Defined Multiple Data Blocks (CMD23 + CMD25)
To write pre-defined multiple data blocks, follow the steps below:
Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To write three blocks of data, configure SMHC_CMDARG to 0x3 to specify the number of data blocks
as three. Then write 0x80000157 to SMHC_CMD to send the CMD23 command. Check whether
SMHC_RINTSTS[CC] is 1. If yes, the command is sent successful; otherwise, continue to wait until
timeout, and then exit the process.
Step 4 Configure SMHC_BYTCNT[BYTE_CNT] to 0x600 and configure the descriptor according to the data size;
set the data sector address of CMD25 command (Multiple Data Blocks Write) to 0x0, write 0x80002759
to SMHC_CMD, and send CMD25 command to write data to the device.
Step 5 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successful; otherwise, continue
to wait until timeout, and then exit the process.
Step 6 Check whether SMHC_IDST[TX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 7 Check whether SMHC_RINTSTS[DTC] is 1. If yes, the data transfer and CMD25 writing operations are
completed. Otherwise, abnormity exists. Read SMHC_RINTSTS and SMHC_STATUS to query the
existing abnormity.
Step 8 Send CMD13 command to query whether the device writing operation is completed and returns to
the idle status. For example, device RCA is 0x1234, first set SMHC_CMDARG to 0x12340000, write
0x8000014D to SMHC_CMD, go to step4 to ensure command transfer completed, and then check
whether the highest bit of SMHC_RESP0 (CMD13 response) is 1. If yes, the device is in the idle status,
and the next command can be sent. Otherwise, the device is in the busy status. Continue to send
CMD13 to wait for the device to enter the idle status until timeout.
7.2.4.7 Reading Pre-Defined Multiple Data Blocks (CMD23 + CMD18)
To read pre-defined multiple data blocks, follow the steps below:
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Step 1 Write 0x1 to SMHC_CTRL[DMA_RST] to reset the internal DMA controller; write 0x82 to
SMHC_IDMAC to enable the IDMAC interrupt and configure AHB master burst transfers; configure
SMHC_IDIE to enable the transfer interrupt, receive interrupt, and abnormal interrupt.
Step 2 Configure SMHC_FIFOTH to determine the burst size and TX/RX trigger level. For example, if
SMHC_FIFOTH is configured as 0x300F00F0, it indicates the burst size is 16, TX_TL is 15, and RX_TL is
240. Configure SMHC_DLBA to determine the start address of the DMA descriptor.
Step 3 To read three blocks of data, configure SMHC_CMDARG to 0x3 to specify the number of data blocks
as three. Then write 0x80000157 to SMHC_CMD to send the CMD23 command. Check whether
SMHC_RINTSTS[CC] is 1. If yes, the command is sent successful; otherwise, continue to wait until
timeout, and then exit the process.
Step 4 Configure SMHC_BYTCNT[BYTE_CNT] to 0x600 and configure the descriptor according to the data size;
set the data sector address of CMD18 (Multiple Data Blocks Read) to 0x0, write 0x80002352 to
SMHC_CMD, and send CMD18 command to read data from device to DRAM/SRAM.
Step 5 Check whether SMHC_RINTSTS[CC] is 1. If yes, the command is sent successful; otherwise, continue
to wait until timeout, and then exit the process.
Step 6 Check whether SMHC_IDST[TX_INT] is 1. If yes, the data transfer for writing DMA is completed. Write
0x337 to SMHC_IDST to clear the interrupt flag. Otherwise, continue to wait until timeout, and then
exit the process.
Step 7 Check whether SMHC_RINTSTS[DTC] is 1. If yes, the data transfer and CMD18 writing operations are
completed. Otherwise, abnormity exists. Read SMHC_RINTSTS and SMHC_STATUS to query the
existing abnormity.
7.2.5 Register List
Module Name Base Address
SMHC0 0x04020000
SMHC1 0x04021000
SMHC2 0x04022000
Register Name Offset Description
SMHC_CTRL 0x0000 Control Register
SMHC_CLKDIV 0x0004 Clock Control Register
SMHC_TMOUT 0x0008 Time Out Register
SMHC_CTYPE 0x000C Bus Width Register
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Register Name Offset Description
SMHC_BLKSIZ 0x0010 Block Size Register
SMHC_BYTCNT 0x0014 Byte Count Register
SMHC_CMD 0x0018 Command Register
SMHC_CMDARG 0x001C Command Argument Register
SMHC_RESP0 0x0020 Response 0 Register
SMHC_RESP1 0x0024 Response 1 Register
SMHC_RESP2 0x0028 Response 2 Register
SMHC_RESP3 0x002C Response 3 Register
SMHC_INTMASK 0x0030 Interrupt Mask Register
SMHC_MINTSTS 0x0034 Masked Interrupt Status Register
SMHC_RINTSTS 0x0038 Raw Interrupt Status Register
SMHC_STATUS 0x003C Status Register
SMHC_FIFOTH 0x0040 FIFO Water Level Register
SMHC_FUNS 0x0044 FIFO Function Select Register
SMHC_TCBCNT 0x0048 Transferred Byte Count between Controller and Card
Transferred Byte Count between Host Memory and
SMHC_TBBCNT 0x004C
Internal FIFO
SMHC_DBGC 0x0050 Current Debug Control Register
SMHC_CSDC 0x0054 CRC Status Detect Control Registers
SMHC_A12A 0x0058 Auto Command 12 Argument Register
SMHC_NTSR 0x005C SD New Timing Set Register
SMHC_HWRST 0x0078 Hardware Reset Register
SMHC_IDMAC 0x0080 IDMAC Control Register
SMHC_DLBA 0x0084 Descriptor List Base Address Register
SMHC_IDST 0x0088 IDMAC Status Register
SMHC_IDIE 0x008C IDMAC Interrupt Enable Register
SMHC_THLD 0x0100 Card Threshold Control Register
SMHC_SFC 0x0104 Sample FIFO Control Register
SMHC_A23A 0x0108 Auto Command 23 Argument Register
EMMC_DDR_SBIT_DET 0x010C eMMC4.5 DDR Start Bit Detection Control Register
SMHC_EXT_CMD 0x0138 Extended Command Register
SMHC_EXT_RESP 0x013C Extended Response Register
SMHC_DRV_DL 0x0140 Drive Delay Control Register
SMHC_SMAP_DL 0x0144 Sample Delay Control Register
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Register Name Offset Description
SMHC_DS_DL 0x0148 Data Strobe Delay Control Register
SMHC_HS400_DL 0x014C HS400 Delay Control Register
SMHC_FIFO 0x0200 Read/Write FIFO
7.2.6 Register Description
7.2.6.1 0x0000 SMHC Global Control Register (Default Value: 0x0000_0100)
Offset: 0x0000 Register Name: SMHC_CTRL
Bit Read/Write Default/Hex Description
FIFO_AC_MOD
FIFO Access Mode
31 R/W 0x0
0: DMA bus
1: AHB bus
30:13 / / /
TIME_UNIT_CMD
Time unit for command line
The time unit is used to calculate the command line time out value
12 R/W 0x0
defined in RTO_LMT.
0: 1 card clock period
1: 256 card clock period
TIME_UNIT_DAT
Time unit for data line
Time unit is used to calculate the data line time out value defined
11 R/W 0x0
in DTO_LMT.
0: 1 card clock period
1: 256 card clock period
DDR_MOD_SEL
DDR Mode Select
Although the HS400 speed mode of eMMC is 8-bit DDR, this field
10 R/W 0x0
should be cleared when HS400_MD_EN is set.
0: SDR mode
1: DDR mode
9 / / /
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Offset: 0x0000 Register Name: SMHC_CTRL
Bit Read/Write Default/Hex Description
CD_DBC_ENB
Card Detect (Data[3] status) De-bounce Enable
8 R/W 0x1
0: Disable de-bounce
1: Enable de-bounce
7:6 / / /
DMA_ENB
DMA Global Enable
5 R/W 0x0
0: Disable DMA to transfer data via AHB bus
1: Enable DMA to transfer data
INT_ENB
Global Interrupt Enable
4 R/W 0x0
0: Disable interrupts
1: Enable interrupts
3 / / /
DMA_RST
2 R/W 0x0
DMA Reset
FIFO_RST
FIFO Reset
1 R/W 0x0 0: No effect
1: Reset the FIFO
This bit is auto-cleared after the completion of the reset operation.
SOFT_RST
Software Reset
0 R/W 0x0 0: No effect
1: Reset SD/MMC controller
This bit is auto-cleared after the completion of reset operation.
7.2.6.2 0x0004 SMHC Clock Control Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: SMHC_CLKDIV
Bit Read/Write Default/Hex Description
MASK_DATA0
31 R/W 0x0 0: Do not mask data0 when update clock
1: Mask data0 when update clock
30:18 / / /
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Offset: 0x0004 Register Name: SMHC_CLKDIV
Bit Read/Write Default/Hex Description
CCLK_CTRL
Card Clock Output Control
17 R/W 0x0
0: Card clock is always on.
1: Turn off card clock when FSM is in IDLE state.
CCLK_ENB
Card Clock Enable
16 R/W 0x0
0: Card Clock is off.
1: Card Clock is on.
15:8 / / /
CCLK_DIV
Card Clock Divider
7:0 R/W 0x0
n: Source clock is divided by 2*n. (n = 0 to 255)
When HS400_MD_EN is set, this field must be cleared.
7.2.6.3 0x0008 SMHC Timeout Register (Default Value: 0xFFFF_FF40)
Offset: 0x0008 Register Name: SMHC_TMOUT
Bit Read/Write Default/Hex Description
DTO_LMT
Data Timeout Limit
This field can set the time that the host waits for the data from
the device.
Ensure to communicate with the device, this field must be set
to the maximum that is greater than the time N AC .
About the N AC , the explanation is as follows:
31:8 R/W 0xffffff
When Host read data, data transmission from the Device starts
after the access time delay N AC beginning from the end bit of
the read command (ACMD51, CMD8, CMD17, and CMD18).
When the host reads multiple block (CMD18), a next block’s
data transmission from the Device starts after the access time
delay N AC beginning from the end bit of the previous block.
When the host writes data, the value is no effect.
RTO_LMT
7:0 R/W 0x40
Response Timeout Limit
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7.2.6.4 0x000C SMHC Bus Width Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: SMHC_CTYPE
Bit Read/Write Default/Hex Description
31:2 / / /
CARD_WID
Card Width
1:0 R/W 0x0 00: 1-bit width
01: 4-bit width
1x: 8-bit width
7.2.6.5 0x0010 SMHC Block Size Register (Default Value: 0x0000_0200)
Offset: 0x0010 Register Name: SMHC_BLKSIZ
Bit Read/Write Default/Hex Description
31:16 / / /
BLK_SZ
15:0 R/W 0x200
Block Size
7.2.6.6 0x0014 SMHC Byte Count Register (Default Value: 0x0000_0200)
Offset: 0x0014 Register Name: SMHC_BYTCNT
Bit Read/Write Default/Hex Description
BYTE_CNT
Byte counter
31:0 R/W 0x200
The number of bytes to be transferred. It must be integer
multiple of Block Size (BLK_SZ) for block transfers.
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7.2.6.7 0x0018 SMHC Command Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: SMHC_CMD
Bit Read/Write Default/Hex Description
CMD_LOAD
Start Command
This bit is automatically cleared when the current command is
31 R/W 0x0 sent. If there is no response error happens, a command
complete interrupt bit (CMD_OVER) will be set in the interrupt
register. Do not write any other commands until this bit is
cleared.
30:29 / / /
VOL_SW
Voltage Switch
28 R/W 0x0
0: Normal command
1: Voltage switch command, set for CMD11 only.
BOOT_ABT
27 R/W 0x0 Boot Abort
Setting this bit will terminate the boot operation.
EXP_BOOT_ACK
Expect Boot Acknowledge
26 R/W 0x0 When the software sets this bit along in mandatory boot
operation, the controller expects a boot acknowledge start
pattern of 0-1-0 from the selected card.
BOOT_MOD
Boot Mode
00: Normal command
25:24 R/W 0x0
01: Mandatory Boot operation
10: Alternate Boot operation
11: Reserved
23:22 / / /
PRG_CLK
Change Clock
0: Normal command
21 R/W 0x0
1: Change Card Clock
When this bit is set, the controller will change the clock domain
and clock output. No commands will be sent.
20:16 / / /
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Offset: 0x0018 Register Name: SMHC_CMD
Bit Read/Write Default/Hex Description
SEND_INIT_SEQ
Send Initialization
15 R/W 0x0
0: Normal command sending
1: Send initialization sequence before sending this command.
STOP_ABT_CMD
Stop Abort Command
0: Normal command sending
14 R/W 0x0
1: Send Stop or Abort command to stop the current data
transfer in progress. (CMD12, CMD52 for writing “I/O Abort” in
SDIO CCCR)
WAIT_PRE_OVER
Wait for Data Transfer Over
0: Send command at once, does not care about data
13 R/W 0x0
transferring.
1: Wait for data transfer completion before sending the current
command.
STOP_CMD_FLAG
Send Stop CMD Automatically (CMD12)
0: Do not send stop command at the end of the data transfer.
12 R/W 0x0 1: Send stop command automatically at the end of the data
transfer.
If set, the SMHC_RESP1 will record the response of auto
CMD12.
TRANS_MODE
Transfer Mode
11 R/W 0x0
0: Block data transfer command
1: Stream data transfer command
TRANS_DIR
Transfer Direction
10 R/W 0x0
0: Read operation
1: Write operation
DATA_TRANS
Data Transfer
9 R/W 0x0
0: Without data transfer
1: With data transfer
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Offset: 0x0018 Register Name: SMHC_CMD
Bit Read/Write Default/Hex Description
CHK_RESP_CRC
Check Response CRC
8 R/W 0x0
0: Do not check response CRC
1: Check response CRC
LONG_RESP
Response Type
7 R/W 0x0
0: Short Response (48 bits)
1: Long Response (136 bits)
RESP_RCV
Response Receive
6 R/W 0x0
0: Command without response
1: Command with response
CMD_IDX
5:0 R/W 0x0 CMD Index
Command index value
7.2.6.8 0x001C SMHC Command Argument Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: SMHC_CMDARG
Bit Read/Write Default/Hex Description
CMD_ARG
31:0 R/W 0x0
Command argument
7.2.6.9 0x0020 SMHC Response 0 Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: SMHC_RESP0
Bit Read/Write Default/Hex Description
CMD_RESP0
31:0 R 0x0 Response 0
Bit[31:0] of response
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7.2.6.10 0x0024 SMHC Response 1 Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: SMHC_RESP1
Bit Read/Write Default/Hex Description
CMD_RESP1
31:0 R 0x0 Response 1
Bit[63:31] of response
7.2.6.11 0x0028 SMHC Response 2 Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: SMHC_RESP2
Bit Read/Write Default/Hex Description
CMD_RESP2
31:0 R 0x0 Response 2
Bit[95:64] of response
7.2.6.12 0x002C SMHC Response 3 Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: SMHC_RESP3
Bit Read/Write Default/Hex Description
CMD_RESP3
31:0 R 0x0 Response 3
Bit[127:96] of response
7.2.6.13 0x0030 SMHC Interrupt Mask Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: SMHC_INTMASK
Bit Read/Write Default/Hex Description
CARD_REMOVAL_INT_EN
31 R/W 0x0
Card Removed Interrupt Enable
CARD_INSERT_INT_EN
30 R/W 0x0
Card Inserted Interrupt Enable
29:17 / / /
SDIO_INT_EN
16 R/W 0x0
SDIO Interrupt Enable
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Offset: 0x0030 Register Name: SMHC_INTMASK
Bit Read/Write Default/Hex Description
DEE_INT_EN
15 R/W 0x0
Data End-bit Error Interrupt Enable
ACD_INT_EN
14 R/W 0x0
Auto Command Done Interrupt Enable
DSE_BC_INT_EN
13 R/W 0x0
Data Start Error Interrupt Enable
CB_IW_INT_EN
12 R/W 0x0
Command Busy and Illegal Write Interrupt Enable
FU_FO_INT_EN
11 R/W 0x0
FIFO Underrun/Overflow Interrupt Enable
DSTO_VSD_INT_EN
10 R/W 0x0
Data Starvation Timeout/V1.8 Switch Done Interrupt Enable
DTO_BDS_INT_EN
9 R/W 0x0
Data Timeout/Boot Data Start Interrupt Enable
RTO_BACK_INT_EN
8 R/W 0x0
Response Timeout/Boot ACK Received Interrupt Enable
DCE_INT_EN
7 R/W 0x0
Data CRC Error Interrupt Enable
RCE_INT_EN
6 R/W 0x0
Response CRC Error Interrupt Enable
DRR_INT_EN
5 R/W 0x0
Data Receive Request Interrupt Enable
DTR_INT_EN
4 R/W 0x0
Data Transmit Request Interrupt Enable
DTC_INT_EN
3 R/W 0x0
Data Transfer Complete Interrupt Enable
CC_INT_EN
2 R/W 0x0
Command Complete Interrupt Enable
RE_INT_EN
1 R/W 0x0
Response Error Interrupt Enable
0 / / /
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7.2.6.14 0x0034 SMHC Masked Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: SMHC_MINTSTS
Bit Read/Write Default/Hex Description
M_CARD_REMOVAL_INT
31 R 0x0
Card Removed
M_CARD_INSERT
30 R 0x0
Card Inserted
29:17 / / /
M_SDIO_INT
16 R 0x0
SDIO Interrupt
M_DEE_INT
Data End-bit Error
When the bit is set during receiving data, it means that the host
15 R 0x0 controller does not receive the valid data end bit.
When the bit is set during transmitting data, it means that the
host controller does not receive the CRC status token.
This is a write-1-to-clear bit.
M_ACD_INT
14 R 0x0 Auto Command Done
When set, it means auto-stop command (CMD12) completed.
M_DSE_BC_INT
Data Start Error/Busy Clear
When set during receiving data, it means that the host
13 R 0x0
controller found an error start bit.
When the bit is set during transmitting data, it means that the
busy signal is cleared after the last block.
M_CB_IW_INT
12 R 0x0
Command Busy and Illegal Write
M_FU_FO_INT
11 R 0x0
FIFO Underrun/Overflow
M_DSTO_VSD_INT
10 R 0x0
Data Starvation Timeout/V1.8 Switch Done
M_DTO_BDS_INT
9 R 0x0
Data Timeout/Boot Data Start
M_RTO_BACK_INT
8 R 0x0
Response Timeout/Boot ACK Received
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Offset: 0x0034 Register Name: SMHC_MINTSTS
Bit Read/Write Default/Hex Description
M_DCE_INT
Data CRC Error
When the bit is set during receiving data, it means that the
7 R 0x0
received data have data CRC error.
When the bit is set during transmitting data, it means that the
received CRC status taken is negative.
M_RCE_INT
6 R 0x0
Response CRC Error
M_DRR_INT
Data Receive Request
5 R 0x0
When set, it means that there are enough data in FIFO during
receiving data.
M_DTR_INT
Data Transmit Request
4 R 0x0
When set, it means that there is enough space in FIFO during
transmitting data.
M_DTC_INT
3 R 0x0
Data Transfer Complete
M_CC_INT
2 R 0x0
Command Complete
M_RE_INT
Response Error
1 R 0x0
When set, Transmit Bit error or End Bit error or CMD Index error
may occurs.
0 / / /
7.2.6.15 0x0038 SMHC Raw Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: SMHC_RINTSTS
Bit Read/Write Default/Hex Description
CARD_REMOVAL
31 R/W1C 0x0 Card Removed
Write 1 to clear this bit.
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Offset: 0x0038 Register Name: SMHC_RINTSTS
Bit Read/Write Default/Hex Description
CARD_INSERT
30 R/W1C 0x0 Card Inserted
Write 1 to clear this bit.
29:17 / / /
SDIOI_INT
16 R/W1C 0x0 SDIO Interrupt
Write 1 to clear this bit.
DEE
Data End-bit Error
When the bit is set during receiving data, it means that the host
15 R/W1C 0x0 controller does not receive the valid data end bit.
When the bit is set during transmitting data, it means that the
host controller does not receive the CRC status token.
Write 1 to clear this bit.
ACD
Auto Command Done
14 R/W1C 0x0 When set, it means that the auto-stop command (CMD12) is
completed.
Write 1 to clear this bit.
DSE_BC
Data Start Error/Busy Clear
When the bit is set during receiving data, it means that the host
13 R/W1C 0x0 controller found an error start bit.
When the bit is set during transmitting data, it means that the
busy signal is cleared after the last block.
Write 1 to clear this bit.
CB_IW
12 R/W1C 0x0 Command Busy and Illegal Write
Write 1 to clear this bit.
FU_FO
11 R/W1C 0x0 FIFO Underrun/Overflow
Write 1 to clear this bit.
DSTO_VSD
10 R/W1C 0x0 Data Starvation Timeout/V1.8 Switch Done
Write 1 to clear this bit.
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Offset: 0x0038 Register Name: SMHC_RINTSTS
Bit Read/Write Default/Hex Description
DTO_BDS
Data Timeout/Boot Data Start
9 R/W1C 0x0 When the bit is set during receiving data, it means that some of
the channel of DATA[3:0] lack of the start bit.
Write 1 to clear this bit.
RTO_BACK
8 R/W1C 0x0 Response Timeout/Boot ACK Received
Write 1 to clear this bit.
DCE
Data CRC Error
When the bit is set during receiving data, it means that the
7 R/W1C 0x0 received data have data CRC error.
When the bit is set during transmitting data, it means that the
received CRC status taken is negative.
Write 1 to clear this bit.
RCE
6 R/W1C 0x0 Response CRC Error
Write 1 to clear this bit.
DRR
Data Receive Request
5 R/W1C 0x0 When set, it means that there are enough data in FIFO during
receiving data.
Write 1 to clear this bit.
DTR
Data Transmit Request
4 R/W1C 0x0 When set, it means that there is enough space in FIFO during
transmitting data.
Write 1 to clear this bit.
DTC
Data Transfer Complete
3 R/W1C 0x0 When set, it means that the current command completes even
through error occurs.
Write 1 to clear this bit.
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Offset: 0x0038 Register Name: SMHC_RINTSTS
Bit Read/Write Default/Hex Description
CC
Command Complete
2 R/W1C 0x0 When set, it means that the current command completes even
through error occurs.
Write 1 to clear this bit.
RE
Response Error
1 R/W1C 0x0 When set, it means that the transmit bit error, end bit error, or
CMD index error may occur.
Write 1 to clear this bit.
0 / / /
7.2.6.16 0x003C SMHC Status Register (Default Value: 0x0000_0006)
Offset: 0x003C Register Name: SMHC_STATUS
Bit Read/Write Default/Hex Description
DMA_REQ
31 R 0x0 DMA Request
DMA request signal state
30:26 / / /
FIFO_LEVEL
25:17 R 0x0 FIFO Level
Number of filled locations in FIFO
RESP_IDX
Response Index
16:11 R 0x0
Index of previous response, including any auto-stop sent by the
controller.
FSM_BUSY
10 R 0x0 Data FSM Busy
Data transmit or receive state-machine is busy.
CARD_BUSY
Card Data Busy
9 R 0x0 Inverted version of DATA[0]
0: Card data is not busy.
1: Card data is busy.
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Offset: 0x003C Register Name: SMHC_STATUS
Bit Read/Write Default/Hex Description
CARD_PRESENT
Data[3] Status
8 R 0x0 The level of DATA[3], checks whether the card is present.
0: The card is not present.
1: The card is present.
FSM_STA
Command FSM States
0000: Idle
0001: Send init sequence
0010: TX CMD start bit
0011: TX CMD TX bit
0100: TX CMD index + argument
0101: TX CMD CRC7
0110: TX CMD end bit
7:4 R 0x0
0111: RX response start bit
1000: RX response IRQ response
1001: RX response TX bit
1010: RX response CMD index
1011: RX response data
1100: RX response CRC7
1101: RX response end bit
1110: CMD path wait NCC
1111: Wait; CMD-to-response turn around
FIFO_FULL
FIFO Full
3 R 0x0
0: FIFO is not full
1: FIFO is full
FIFO_EMPTY
FIFO Empty
2 R 0x1
0: FIFO is not empty
1: FIFO is empty
FIFO_TX_LEVEL
FIFO TX Water Level Flag
1 R 0x1
0: FIFO does not reach the transmit trigger level
1: FIFO reaches the transmit trigger level
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Offset: 0x003C Register Name: SMHC_STATUS
Bit Read/Write Default/Hex Description
FIFO_RX_LEVEL
FIFO RX Water Level Flag
0 R 0x0
0: FIFO does not reach the receive trigger level.
1: FIFO reaches the receive trigger level.
7.2.6.17 0x0040 SMHC FIFO Water Level Register (Default Value: 0x000F_0000)
Offset: 0x0040 Register Name: SMHC_FIFOTH
Bit Read/Write Default/Hex Description
31 / / /
BSIZE_OF_TRANS
Burst Size of Multiple Transaction
000: 1 transfers
001: 4
010: 8
011: 16
Others: Reserved
30:28 R/W 0x0 It should be programmed the same as the DMA controller
multiple transaction size. The units for the transfer are the
DWORD. A single transfer would be signaled based on this
value. The value should be sub-multiple of (RX_TL + 1) and
(FIFO_DEPTH - TX_TL)
Recommended:
FIFO_DEPTH = 256, FIFO_SIZE = 256 * 32 = 1K
MSize = 16, TX_TL = 240, RX_TL = 15
27:24 / / /
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Offset: 0x0040 Register Name: SMHC_FIFOTH
Bit Read/Write Default/Hex Description
RX_TL
RX Trigger Level
0x0 to 0xFE: The RX trigger level is from 0 to 254.
0xFF: Reserved
Indicates the FIFO threshold for the FIFO request host to receive
23:16 R/W 0xF data from the FIFO. When the FIFO data level is greater than
this value, the DMA request is raised if DMA enabled, or the RX
interrupt bit is set if interrupt enabled. At the end of the packet,
if the last transfer is less than this level, the value is ignored and
the relative request will be raised as usual.
Recommended: 15 (means greater than 15)
15:8 / / /
TX_TL
TX Trigger Level
0x1 to 0xFF: The TX trigger level is 1 to 255.
0x0: No trigger
Indicates the FIFO threshold for the FIFO request host to
7:0 R/W 0x0 transmit data to the FIFO. When the FIFO data level is less than
or equal to this value, the DMA TX request is raised if DMA
enabled, or TX request interrupt bit is set if interrupt enabled.
At the end of the packet, if the last transfer is less than this level,
the value is ignored and the relative request will be raised as
usual.
Recommended: 240 (means less than or equal to 240)
7.2.6.18 0x0044 SMHC Function Select Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: SMHC_FUNS
Bit Read/Write Default/Hex Description
31:3 / / /
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Offset: 0x0044 Register Name: SMHC_FUNS
Bit Read/Write Default/Hex Description
ABT_RDATA
Abort Read Data
0: Ignored
1: After the suspend command is issued during the read-
transfer, the software polls card to find when the suspend
2 R/W 0x0
happens. Once the suspend occurs, the software sets the bit to
reset the data state-machine, which is waiting for the next block
of data.
This bit is used in the SDIO card suspends sequence and is auto-
cleared once the controller resets to the idle state.
READ_WAIT
Read Wait
1 R/W 0x0
0: Clear SDIO read wait
1: Assert SDIO read wait
HOST_SEND_MMC_IRQRESQ
Host Send MMC IRQ Response
0: Ignored
1: Send auto IRQ response
0 R/W 0x0 When the host is waiting for the MMC card interrupt response,
setting this bit will make the controller cancel the waiting state
and return to the idle state, at which time, the controller will
receive the IRQ response sent by itself.
This bit is auto-cleared after the response is sent.
7.2.6.19 0x0048 SMHC Transferred Byte Count Register 0 (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: SMHC_TBC0
Bit Read/Write Default/Hex Description
TBC0
Transferred Count 0
The number of bytes transferred between the card and internal
31:0 R 0x0
FIFO.
The register should be accessed in full to avoid read-coherency
problems and read only after the data transfer completes.
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7.2.6.20 0x004C SMHC Transferred Byte Count Register 1 (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: SMHC_TBC1
Bit Read/Write Default/Hex Description
TBC1
Transferred Count 1
The number of bytes transferred between the Host/DMA
31:0 R 0x0
memory and internal FIFO.
The register should be accessed in full to avoid read-coherency
problems and read only after the data transfer completes.
7.2.6.21 0x0054 SMHC CRC Status Detect Control Register (Default Value: 0x0000_0003)
Offset: 0x0054 Register Name: SMHC_CSDC
Bit Read/Write Default/Hex Description
31:4 / / /
CRC_DET_PARA
110: HS400 speed mode
3:0 R/W 0x3
011: Other speed mode
Others: Reserved
7.2.6.22 0x0058 SMHC Auto Command 12 Argument Register (Default Value: 0x0000_FFFF)
Offset: 0x0058 Register Name: SMHC_A12A
Bit Read/Write Default/Hex Description
31:16 / / /
SD_A12A
Auto CMD12 Argument
15:0 R/W 0xffff
The argument of command 12 automatically sent by the
controller.
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7.2.6.23 0x005C SMHC New Timing Set Register (Default Value: 0x8171_0000)
Offset: 0x005C Register Name: SMHC_NTSR
Bit Read/Write Default/Hex Description
MODE_SELECT
31 R/W 0x1 0: Old mode of Sample/Output Timing
1: New mode of Sample/Output Timing
30:25 / / /
CMD_DAT_RX_PHASE_CLR
Clear the input phase of command lines and data lines during
24 R/W 0x1 the update clock operation.
0: Disabled
1: Enabled
23 / / /
DAT_CRC_STATUS_RX_PHASE_CLR
Clear the input phase of data lines before receiving the CRC
22 R/W 0x1 status.
0: Disabled
1: Enabled
DAT_TRANS_RX_PHASE_CLR
Clear the input phase of data lines before transferring the data.
21 R/W 0x1
0: Disabled
1: Enabled
DAT_RECV_RX_PHASE_CLR
Clear the input phase of data lines before receiving the data.
20 R/W 0x1
0: Disabled
1: Enabled
19:17 / / /
CMD_SEND_RX_PHASE_CLR
Clear command rx phase before sending the command.
16 R/W 0x1
0: Disabled
1: Enabled
15:10 / / /
DAT_SAMPLE_TIMING_PHASE
00: Sample timing phase offset 900
9:8 R/W 0x0 01: Sample timing phase offset 1800
10: Sample timing phase offset 2700
11: Sample timing phase offset 00 (only for SD2 hs400 mode)
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Offset: 0x005C Register Name: SMHC_NTSR
Bit Read/Write Default/Hex Description
7:6 / / /
CMD_SAMPLE_TIMING_PHASE
00: Sample timing phase offset 900
5:4 R/W 0x0 01: Sample timing phase offset 1800
10: Sample timing phase offset 2700
11: Ignore
3:1 / / /
HS400_NEW_SAMPLE_EN
0 R/W 0x0 0: Disable hs400 new sample method
1: Enable hs400 new sample method
7.2.6.24 0x0078 SMHC Hardware Reset Register (Default Value: 0x0000_0001)
Offset: 0x0078 Register Name: SMHC_HWRST
Bit Read/Write Default/Hex Description
31:1 / / /
HW_RST
1: Active mode
0 R/W 0x1 0: Reset
These bits cause the cards to enter the pre-idle state, which requires
them to be re-initialized.
7.2.6.25 0x0080 SMHC IDMAC Control Register (Default Value: 0x0000_0000)
Offset: 0x0080 Register Name: SMHC_IDMAC
Bit Read/Write Default/Hex Description
DES_LOAD_CTRL
When IDMAC fetches a descriptor, if the valid bit of a descriptor is
31 W 0x0 not set, IDMAC FSM will go to the suspend state. Setting this bit
will make the IDMAC refetch descriptor again and do the transfer
normally.
30:11 / / /
10:8 R 0x0 Reserved
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Offset: 0x0080 Register Name: SMHC_IDMAC
Bit Read/Write Default/Hex Description
IDMAC_ENB
7 R/W 0x0 IDMAC Enable
When set, the IDMAC is enabled.
6:2 R/W 0x0 Reserved
FIX_BUST_CTRL
Fixed Burst
Controls whether the AHB Master interface performs fixed burst
1 R/W 0x0
transfers or not. When set, the AHB will use only SINGLE, INCR4,
and INCR8 during the start of normal burst transfers. When reset,
the AHB will use SINGLE and INCR burst transfer operations.
IDMAC_RST
DMA Reset
0 R/W 0x0
When set, the DMA Controller resets all its internal registers. It is
automatically cleared after 1 clock cycle.
7.2.6.26 0x0084 SMHC Descriptor List Base Address Register (Default Value: 0x0000_0000)
Offset: 0x0084 Register Name: SMHC_DLBA_REG
Bit Read/Write Default/Hex Description
DES_BASE_ADDR
Start of Descriptor List
31:0 R/W 0x0
Contains the base address of the First Descriptor.
It is a word (4 Byte) address.
7.2.6.27 0x0088 SMHC IDMAC Status Register (Default Value: 0x0000_0000)
Offset: 0x0088 Register Name: SMHC_IDST_REG
Bit Read/Write Default/Hex Description
31:17 / / /
16:13 R 0x0 Reserved
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Offset: 0x0088 Register Name: SMHC_IDST_REG
Bit Read/Write Default/Hex Description
IDMAC_ERR_STA
Error Bits
Indicates the type of error that caused a Bus Error. Valid only with
Fatal Bus Error bit (IDST[2]) set. This field does not generate an
12:10 R 0x0
interrupt.
001: Host Abort received during the transmission.
010: Host Abort received during the reception.
Others: Reserved
ABN_INT_SUM (AIS)
Abnormal Interrupt Summary
Logical OR of the following:
IDST[2]: Fatal Bus Interrupt
9 R/W1C 0x0 IDST[4]: Descriptor Unavailable Bit Interrupt
IDST[5]: Card Error Summary Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding
bit that causes AIS to be set is cleared.
NOR_INT_SUM (NIS)
Normal Interrupt Summary
Logical OR of the following:
IDST[0]: Transmit Interrupt
8 R/W1C 0x0
IDST[1]: Receive Interrupt
Only unmasked bits affect this bit.
This is a sticky bit and must be cleared each time a corresponding
bit that causes NIS to be set is cleared.
7:6 / / /
ERR_FLAG_SUM
Card Error Summary
Indicates the status of the transaction to/from the card; also
present in RINTSTS. Indicates the logical OR of the following bits:
EBE: End Bit Error
RTO: Response Timeout
5 R/W1C 0x0
RCRC: Response CRC
SBE: Start Bit Error
DRTO: Data Read Timeout
DCRC: Data CRC for Receive
RE: Response Error
Writing 1 clears this bit.
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Offset: 0x0088 Register Name: SMHC_IDST_REG
Bit Read/Write Default/Hex Description
DES_UNAVL_INT
Descriptor Unavailable Interrupt
4 R/W1C 0x0 This bit is set when the descriptor is unavailable due to OWN bit =
0 (DES0[31] =0).
Writing 1 clears this bit.
3 / / /
FATAL_BERR_INT
Fatal Bus Error Interrupt
2 R/W1C 0x0 Indicates that a Bus Error occurred (IDST[12:10]). When this bit is
set, the DMA disables all its bus accesses.
Writing 1 clears this bit.
RX_INT
Receive Interrupt
1 R/W1C 0x0
Indicates the completion of data reception for a descriptor.
Writing 1 clears this bit.
TX_INT
Transmit Interrupt
0 R/W1C 0x0
Indicates that data transmission is finished for a descriptor.
Writing 1 clears this bit.
7.2.6.28 0x008C SMHC IDMAC Interrupt Enable Register (Default Value: 0x0000_0000)
Offset: 0x008C Register Name: SMHC_IDIE_REG
Bit Read/Write Default/Hex Description
31:6 / / /
ERR_SUM_INT_ENB
5 R/W 0x0 Card Error Summary Interrupt Enable.
When set, it enables the Card Interrupt Summary.
DES_UNAVL_INT_ENB
Descriptor Unavailable Interrupt.
4 R/W 0x0
When set along with Abnormal Interrupt Summary Enable, the
Descriptor Unavailable Interrupt is enabled.
3 / / /
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Offset: 0x008C Register Name: SMHC_IDIE_REG
Bit Read/Write Default/Hex Description
FERR_INT_ENB
Fatal Bus Error Enable
2 R/W 0x0 When set with Abnormal Interrupt Summary Enable, the Fatal Bus
Error Interrupt is enabled. When reset, the Fatal Bus Error Enable
Interrupt is disabled.
RX_INT_ENB
Receive Interrupt Enable.
1 R/W 0x0
When set with Normal Interrupt Summary Enable, Receive Interrupt
is enabled. When reset, the Receive Interrupt is disabled.
TX_INT_ENB
Transmit Interrupt Enable.
0 R/W 0x0
When set with Normal Interrupt Summary Enable, Transmit
Interrupt is enabled. When reset, the Transmit Interrupt is disabled.
7.2.6.29 0x0100 SMHC Card Threshold Control Register (Default Value: 0x0000_0000)
Offset: 0x0100 Register Name: SMHC_THLD
Bit Read/Write Default/Hex Description
31:28 / / /
CARD_WR_THLD
27:16 R/W 0x0
Card Read/Write Threshold Size
15:3 / / /
CARD_WR_THLD_ENB
Card Write Threshold Enable
0: Card write threshold disabled
2 R/W 0x0
1: Card write threshold enabled
Host controller initiates write transfer only if the card threshold
amount of data is available in transmit FIFO.
BCIG
Busy Clear Interrupt Generation
0: Busy clear interrupt disabled
1 R/W 0x0
1: Busy clear interrupt enabled
The application can disable this feature if it does not want to wait
for a Busy Clear Interrupt.
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Offset: 0x0100 Register Name: SMHC_THLD
Bit Read/Write Default/Hex Description
CARD_RD_THLD_ENB
Card Read Threshold Enable
0: Card read threshold disabled
0 R/W 0x0
1: Card read threshold enabled
Host controller initiates Read Transfer only if the CARD_RD_THLD
amount of space is available in receive FIFO.
7.2.6.30 0x0104 SMHC Sample FIFO Control Register (Default Value: 0x0000_0006)
Offset: 0x0104 Register Name: SMHC_SFC
Bit Read/Write Default/Hex Description
31:5 / / /
STOP_CLK_CTRL
Stop Clock Control
When receiving data, if CARD_RD_THLD_ENB is set and
CARD_RD_THLD is set the same with BLK_SZ, the device clock may
stop at the block gap during data receiving.
4:1 R/W 0x3 This field is used to control the position of the stopping clock.
The value can be changed between 0x0 and 0xF, but actually, the
available value and the position of the stopping clock must be
decided by the actual situation.
The value increases one in this field is linked to one cycle (two cycles
in DDR mode) that the position of the stopping clock moved up.
BYPASS_EN
0 R/W 0x0 Bypass enable
When set, sample FIFO will be bypassed.
7.2.6.31 0x0108 SMHC Auto Command 23 Argument Register (Default Value: 0x0000_0000)
Offset: 0x0108 Register Name: SMHC_A23A
Bit Read/Write Default/Hex Description
A23A
Auto CMD23 Argument
31:0 R/W 0x0
The argument of command 23 is automatically sent by controller
with this field.
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7.2.6.32 0x010C SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value: 0x0000_0000)
Offset: 0x010C Register Name: EMMC_DDR_SBIT_DET
Bit Read/Write Default/Hex Description
HS400_MD_EN
HS400 Mode Enable
0: Disabled
31 R/W 0x0
1: Enabled
It is required to set this bit to '1' before initiating any data
transfer CMD in HS400 mode.
30:1 / / /
HALF_START_BIT
Control for start bit detection mechanism inside mstorage based
on duration of start bit.
For eMMC 4.5, start bit can be:
0 R/W 0x0
0: Full cycle
1: Less than one full cycle
Set HALF_START_BIT = 1 for eMMC 4.5 and above; set to 0 for SD
applications.
7.2.6.33 0x0138 SMHC Extended Command Register (Default Value: 0x0000_0000)
Offset: 0x0138 Register Name: SMHC_EXT_CMD
Bit Read/Write Default/Hex Description
31:1 / / /
AUTO_CMD23_EN
Send CMD23 Automatically
0 R/W 0x0 When setting this bit, send CMD23 automatically before
sending the command specified in the SMHC_CMD register.
When SOFT_RST is set, this field will be cleared.
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7.2.6.34 0x013C SMHC Extended Response Register (Default Value: 0x0000_0000)
Offset: 0x013C Register Name: SMHC_EXT_RESP
Bit Read/Write Default/Hex Description
SMHC_EXT_RESP
31:0 R 0x0 When AUTO_CMD23_EN is set, this register stores the response
of CMD23.
7.2.6.35 0x0140 SMHC Drive Delay Control Register (Default Value: 0x0001_0000)
Offset: 0x0140 Register Name: SMHC_DRV_DL
Bit Read/Write Default/Hex Description
31:18 / / /
DAT_DRV_PH_SEL
Data Drive Phase Select
When 0x005C[31]=0:
0: Data drive phase offset is 90° at SDR mode, 45° at DDR8 mode,
and 90° at DDR4 mode.
1: Data drive phase offset is 180° at SDR mode, 90° at DDR8 mode,
17 R/W 0x0
and 0° at DDR4 mode.
When 0x005C[31]=1:
0: Data drive phase offset is 90° at SDR mode, and 45° at DDR
mode.
1: Data drive phase offset is 180° at SDR mode, and 90° at DDR
mode.
CMD_DRV_PH_SEL
Command Drive Phase Select
When 0x005C[31]=0:
0: Command drive phase offset is 90° at SDR mode, 45° at DDR8
mode, and 90° at DDR4 mode.
1: Command drive phase offset is 180° at SDR mode, 90° at DDR8
16 R/W 0x1
mode, and 180° at DDR4 mode.
When 0x005C[31]=1:
0: Command drive phase offset is 90° at SDR mode and 45° at DDR
mode.
1: Command drive phase offset is 180°at SDR mode and 90°at DDR
mode.
15:0 / / /
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7.2.6.36 0x0144 SMHC Sample Delay Control Register (Default Value: 0x0000_2000)
Offset: 0x0144 Register Name: SMHC_SAMP_DL
Bit Read/Write Default/Hex Description
31:16 / / /
SAMP_DL_CAL_START
15 R/W 0x0 Sample Delay Calibration Start
When set, it means that start sample delay chain calibration.
SAMP_DL_CAL_DONE
Sample Delay Calibration Done
14 R 0x0
When set, it means that sample delay chain calibration is done and
the result of calibration is shown in SAMP_DL.
SAMP_DL
Sample Delay
It indicates the number of delay cells corresponding to the current
card clock. The delay time generated by these delay cells is equal
13:8 R 0x20
to the cycle of the card clock nearly.
Generally, it is necessary to do drive delay calibration when the
card clock is changed.
This bit is valid only when SAMP_DL_CAL_DONE is set.
SAMP_DL_SW_EN
Sample Delay Software Enable
7 R/W 0x0
When set, it means that enable the sample delay specified at
SAMP_DL_SW.
6 / / /
SAMP_DL_SW
Sample Delay Software
The relative delay between the clock line and command line, data
5:0 R/W 0x0
line.
It can be determined according to the value of SAMP_DL, the cycle
of the card clock and the input timing requirement of the device.
7.2.6.37 0x0148 SMHC Data Strobe Delay Control Register (Default Value: 0x0000_2000)
Offset: 0x0148 Register Name: SMHC_DS_DL
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0148 Register Name: SMHC_DS_DL
Bit Read/Write Default/Hex Description
DS_DL_CAL_START
15 R/W 0x0 Data Strobe Delay Calibration Start
When set, it means that start sample delay chain calibration.
DS_DL_CAL_DONE
Data Strobe Delay Calibration Done
14 R 0x0
When set, it means that sample delay chain calibration is done and
the result of calibration is shown in DS_DL.
DS_DL
Data Strobe Delay
It indicates the number of delay cells corresponding to the current
13:8 R 0x20
card clock. The delay time generated by these delay cells is equal
to the cycle of SMHC’s clock nearly.
This bit is valid only when SAMP_DL_CAL_DONE is set.
DS_DL_SW_EN
7 R/W 0x0
Sample Delay Software Enable
6 / / /
DS_DL_SW
5:0 R/W 0x0
Data Strobe Delay Software
7.2.6.38 0x014C SMHC HS400 New Timing Delay Control Register (Default Value: 0x0000_8000)
Offset: 0x014C Register Name: SMHC_HS400_DL
Bit Read/Write Default/Hex Description
31:16 / / /
HS400_DL_CAL_START
15 R/W 0x0 HS400 Delay Calibration Start
When set, it means that start sample delay chain calibration.
HS400_DL_CAL_DONE
HS400 Delay Calibration Done
14 R 0x0
When set, it means that sample delay chain calibration is done and
the result of calibration is shown in HS400_DL.
13:12 / / /
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Offset: 0x014C Register Name: SMHC_HS400_DL
Bit Read/Write Default/Hex Description
HS400_DL
HS400 Delay
It indicates the number of delay cells corresponding to the current
11:8 R 0x8
card clock. The delay time generated by these delay cells is equal
to the cycle of the SMHC clock nearly.
This bit is valid only when HS400_DL_CAL_DONE is set.
HS400_DL_SW_EN
7 R/W 0x0
Sample Delay Software Enable
6 / / /
HS400_DL_SW
3:0 R/W 0x0
HS400 Delay Software
7.2.6.39 0x0200 SMHC FIFO Register (Default Value: 0x0000_0000)
Offset: 0x0200 Register Name: SMHC_FIFO
Bit Read/Write Default/Hex Description
TX/RX_FIFO
31:0 R/W 0x0
Data FIFO
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Contents
8 Audio ....................................................................................................................................................................... 615
8.1 I2S/PCM........................................................................................................................................................... 615
8.1.1 Overview ............................................................................................................................................. 615
8.1.2 Block Diagram ..................................................................................................................................... 615
8.1.3 Functional Description ........................................................................................................................ 617
8.1.4 Programming Guidelines..................................................................................................................... 623
8.1.5 Register List ......................................................................................................................................... 625
8.1.6 Register Description ............................................................................................................................ 627
8.2 DMIC................................................................................................................................................................ 675
8.2.1 Overview ............................................................................................................................................. 675
8.2.2 Block Diagram ..................................................................................................................................... 675
8.2.3 Functional Description ........................................................................................................................ 675
8.2.4 Register List ......................................................................................................................................... 678
8.2.5 Register Description ............................................................................................................................ 678
8.3 OWA ................................................................................................................................................................ 693
8.3.1 Overview ............................................................................................................................................. 693
8.3.2 Block Diagram ..................................................................................................................................... 694
8.3.3 Functional Description ........................................................................................................................ 695
8.3.4 Register List ......................................................................................................................................... 702
8.3.5 Register Description ............................................................................................................................ 703
8.4 Audio Codec .................................................................................................................................................... 726
8.4.1 Overview ............................................................................................................................................. 726
8.4.2 Block Diagram ..................................................................................................................................... 727
8.4.3 Functional Description ........................................................................................................................ 727
8.4.4 Programming Guidelines..................................................................................................................... 735
8.4.5 Register List ......................................................................................................................................... 736
8.4.6 Register Description ............................................................................................................................ 740
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Figures
Figure 8-1 I2S/PCM Interface System Block Diagram ....................................................................................................... 616
Figure 8-2 Typical Application of I2S/PCM Interface ........................................................................................................ 616
Figure 8-3 I2S Standard Mode Timing............................................................................................................................... 618
Figure 8-4 Left-Justified Mode Timing .............................................................................................................................. 618
Figure 8-5 Right-Justified Mode Timing ............................................................................................................................ 619
Figure 8-6 PCM Long Frame Mode Timing........................................................................................................................ 619
Figure 8-7 PCM Short Frame Mode Timing....................................................................................................................... 619
Figure 8-8 16-Channel Mapping Configuration................................................................................................................. 620
Figure 8-9 Timing Requirements for Inputs ...................................................................................................................... 621
Figure 8-10 Timing Requirements for Outputs ................................................................................................................. 621
Figure 8-11 I2S/PCM Operation Flow ............................................................................................................................... 622
Figure 8-12 DMIC Block Diagram ...................................................................................................................................... 675
Figure 8-13 DMIC Operation Mode................................................................................................................................... 677
Figure 8-14 OWA Block Diagram ....................................................................................................................................... 694
Figure 8-15 OWA Biphase-Mark Code .............................................................................................................................. 696
Figure 8-16 OWA Sub-Frame Format ................................................................................................................................ 697
Figure 8-17 OWA Frame/Block Format ............................................................................................................................. 698
Figure 8-18 Data-Burst Format ......................................................................................................................................... 699
Figure 8-19 Data-burst Preamble...................................................................................................................................... 699
Figure 8-20 Data-burst Preamble words ........................................................................................................................... 699
Figure 8-21 Fields of Burst-information ............................................................................................................................ 700
Figure 8-22 Length of the Burst-Payload Specified by Pd ................................................................................................. 700
Figure 8-23 OWA Operation Flow ..................................................................................................................................... 701
Figure 8-24 Audio Codec Block Diagram ........................................................................................................................... 727
Figure 8-25 Audio Codec Clock Diagram ........................................................................................................................... 728
Figure 8-26 Audio Codec Digital Part Reset System.......................................................................................................... 729
Figure 8-27 Audio Codec Analog Part Reset System ......................................................................................................... 729
Figure 8-28 Audio Codec Data Path Diagram.................................................................................................................... 730
Figure 8-29 Headphone Output Application ..................................................................................................................... 731
Figure 8-30 Audio Codec Interrupt System ....................................................................................................................... 731
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Figure 8-31 DAP Data Flow ............................................................................................................................................... 732
Figure 8-32 HPF Logic Structure ........................................................................................................................................ 732
Figure 8-33 DRC Block Diagram ........................................................................................................................................ 732
Figure 8-34 DRC Static Curve Parameters ......................................................................................................................... 733
Figure 8-35 Energy Filter Structure ................................................................................................................................... 733
Figure 8-36 Gain Smooth Filter ......................................................................................................................................... 735
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Tables
Table 8-1 I2S/PCM External Signals .................................................................................................................................. 617
Table 8-2 I2S/PCM Clock Sources...................................................................................................................................... 617
Table 8-3 DIN Slot ID and Encoder .................................................................................................................................... 620
Table 8-4 Proper MCLK Values with Different Fsin and Fsout .......................................................................................... 622
Table 8-5 DMIC External Signals ....................................................................................................................................... 676
Table 8-6 DMIC Clock Sources........................................................................................................................................... 676
Table 8-7 OWA Sub-blocks ................................................................................................................................................ 694
Table 8-8 OWA External Signals ........................................................................................................................................ 695
Table 8-9 OWA_TX Clock Sources ..................................................................................................................................... 695
Table 8-10 OWA_RX Clock Sources ................................................................................................................................... 695
Table 8-11 Biphase-Mark Encoder .................................................................................................................................... 696
Table 8-12 Preamble Codes .............................................................................................................................................. 697
Table 8-13 Bit Allocation of Data-Burst in IEC 60958 Subframes...................................................................................... 698
Table 8-14 The Corresponding Relation between Different System Clock and Sample Ratio .......................................... 701
Table 8-15 Audio Codec External Signals .......................................................................................................................... 727
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8 Audio
8.1 I2S/PCM
8.1.1 Overview
The I2S/PCM controller is designed to transfer streaming audio-data between the system memory and the
codec chip. The controller supports standard I2S format, Left-justified mode format, Right-justified mode
format, PCM mode format, and TDM mode format.
The I2S/PCM controller includes the following features:
Two I2S/PCM external interfaces (I2S1, I2S2) for connecting external power amplifier and MIC ADC
Compliant with standard Philips Inter-IC sound (I2S) bus specification
- Left-justified, Right-justified, PCM mode, and Time Division Multiplexing (TDM) format
- Programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)
Transmit and Receive data FIFOs
- Programmable FIFO thresholds
- 128 depth x 32-bit width TXFIFO and 64 depth x 32-bit width RXFIFO
Supports multiple function clock
- Clock up to 24.576 MHz Data Output of I2S/PCM in Master mode (Only if the IO PAD and Peripheral
I2S/PCM satisfy Timing Parameters)
- Clock up to 12.288 MHz Data Input of I2S/PCM in Master mode
Supports TX/RX DMA Slave interface
Supports multiple application scenarios
- Up to 16 channels (fs = 48 kHz) which has adjustable width from 8-bit to 32-bit
- Sample rate from 8 kHz to 384 kHz (CHAN = 2)
- 8-bit u-law and 8-bit A-law companded sample
Supports master/slave mode
8.1.2 Block Diagram
The following figure shows the functional block diagram of the I2S/PCM interface.
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Figure 8-1 I2S/PCM Interface System Block Diagram
PLL_AUDIO
Register
Clock
Divider
APB MCLK
I/F 128*32-bits ASRC I2S BCLK
TXFIFO Engine M
S
U LRCK
Y
X
N
DOUT
64*32-bits C PCM PCM
RXFIFO Codec Engine DIN
DMA & INT
PCM interface
The following figure shows the typical application of the I2S/PCM interface.
Figure 8-2 Typical Application of I2S/PCM Interface
I2S
sd_out
I2S_TX
BCLK_out
LRCK_out
External I2S
BCLK_in CMU
LRCK_in
sd_in
I2S_RX
The I2S/PCM interface system integrates one I2S_TX and one I2S_RX.
The I2S_TX is for playing music in I2S or PCM format.
The I2S_RX is for receiving data in I2S or PCM format.
When the I2S works in the master mode, the external I2S module provides BCLK_in and LRCK_in for the
clock management unit (CMU), and the I2S_TX and I2S_RX work with the two external clocks.
When the I2S works in the slave mode, the CMU provides clocks BCLK_out and LRCK_out for the external
I2S module, and the I2S_TX and I2S_RX work with the internal clocks.
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8.1.3 Functional Description
8.1.3.1 External Signals
The following table describes the external signals of the I2S/PCM interface.
LRCK and BCLK are bidirectional I/O. When the I2S/PCM interface works in the Master mode, LRCK and BCLK
are output pins. When the I2S/PCM interface works in the Slave mode, LRCK and BCLK are input pins.
MCLK is an output pin for external devices. DOUT are the serial data output pins and DIN are the serial data
input pins. For details about General Purpose I/O port, refer to section 9.7 “GPIO”.
Table 8-1 I2S/PCM External Signals
Signal Name Description Type
I2S1-MCLK I2S1 Master Clock O
I2S1-LRCK I2S1/PCM1 Sample Rate Clock/Sync I/O
I2S1-BCLK I2S1/PCM1 Bit Rate Clock I/O
I2S1-DOUT[1:0] I2S1/PCM1 Serial Data Output Channel [1:0] O
I2S1-DIN[1:0] I2S1/PCM1 Serial Data Input Channel [1:0] I
I2S2-MCLK I2S2 Master Clock O
I2S2-LRCK I2S2/PCM2 Sample Rate Clock/Sync I/O
I2S2-BCLK I2S2/PCM2 Bit Rate Clock I/O
I2S2-DOUT[2:0] I2S2/PCM2 Serial Data Output Channel [2:0] O
I2S2-DIN[2:0] I2S2/PCM2 Serial Data Input Channel [2:0] I
8.1.3.2 Clock Sources
The following table describes the clock sources for I2S/PCM. For clock setting, configurations, and gating
information, refer to section 3.3 “CCU”.
Table 8-2 I2S/PCM Clock Sources
Clock Name Description
PLL_AUDIO0(1X) By default, PLL_AUDIO0(1X) is 24.5714 MHz, and PLL_AUDIO0(4X) is 98.2856
PLL_AUDIO0(4X) MHz.
PLL_AUDIO1(DIV2) By default, PLL_AUDIO1 is 3072 MHz, PLL_AUDIO1(DIV2) is 1536 MHz, and
PLL_AUDIO1(DIV5) PLL_AUDIO1(DIV5) is 614.4 MHz (24.576 MHz*25).
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8.1.3.3 Timing Diagram
The I2S/PCM supports standard I2S mode, Left-justified I2S mode, Right-justified I2S mode, PCM mode, and
TDM mode. The software can select the modes by setting I2S/PCM_CTL. The following figures describe the
waveforms for SYNC, BCLK, DOUT, and DIN in different modes.
Each sampling period contains an LRCK. The low level of LRCK is the left channel corresponding to the even
slots, and the high level is the right channel corresponding to the odd slots. Each slot is the sampling point of a
mono channel. The sampling period can support the transmission of 2/4/8/16 slots. The BCLK corresponds to
the serial data bit.
Figure 8-3 I2S Standard Mode Timing
LRCK Left Channel Right Channel
BCLK
DOUT/DIN 16 Slots 0 2 4 12 14 1 3 5 13 15
DOUT/DIN 8 Slots 0 2 4 6 1 3 5 7
m Slot m = 0–15
DOUT/DIN 4 Slots 0 2 1 3
DOUT/DIN 2 Slots 0 n-1 n-2 … 1 0 1
MSB Sample LSB
Figure 8-4 Left-Justified Mode Timing
1 / fs
LRCK Left Channel Right Channel
BCLK
DOUT/DIN 16 Slots 0 2 4 12 14 1 3 5 13 15
DOUT/DIN 8 Slots 0 2 4 6 1 3 5 7
m Slot m = 0–15
DOUT/DIN 4 Slots 0 2 1 3
DOUT/DIN 2 Slots 0 n-1 n-2 … 1
MSB Sample LSB
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Figure 8-5 Right-Justified Mode Timing
LRCK Left Channel Right Channel
BCLK
DOUT/DIN 16 Slots 0 2 4 12 14 1 3 5 13 15
DOUT/DIN 8 Slots 0 2 4 6 1 3 5 7
DOUT/DIN 4 Slots m Slot m = 0–15 0 2 1 3
DOUT/DIN 2 Slots 0 1
n-1 n-2 …
MSB Sample LSB
Figure 8-6 PCM Long Frame Mode Timing
LRCK
(Long Frame)
BCLK
DOUT/DIN 16 Slots 0 1 2 3 4 5 6 7 14 15
DOUT/DIN 8 Slots 0 1 2 3 4 5 6 7
DOUT/DIN 4 Slots 0 1 2 3
m Slot m = 0–15
DOUT/DIN 2 Slots 0 1
n-1 n-2 … 1 0 Sample
DOUT/DIN 1 Slots 0 MSB LSB
Figure 8-7 PCM Short Frame Mode Timing
LRCK
(Short Frame)
BCLK
DOUT/DIN 16 Slots 0 1 2 3 4 5 6 7 14 15
DOUT/DIN 8 Slots 0 1 2 3 4 5 6 7
DOUT/DIN 4 Slots 0 1 2 3
m Slot m = 0–15
DOUT/DIN 2 Slots 0 1
n-1 n-2 … 1 0 Sample
MSB LSB
DOUT/DIN 1 Slots 0
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8.1.3.4 DIN Slot Mapping
The 4-wire DIN has 64 slots, each wire DIN has 16 slots. However, only 16 slots are valid and act as the RX
channels.
The following table shows the relationship between the slot id and encoder.
Table 8-3 DIN Slot ID and Encoder
DIN0 Slot ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN1 Slot ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN2 Slot ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN3 Slot ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
There are 16 channels mapping configuration, each wire selects four slots for RX. The following figure shows
the 16-channel mapping configuration.
Figure 8-8 16-Channel Mapping Configuration
LRCK
BCLK
DIN0 16 slot 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN1 16 slot 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN2 16 slot 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DIN3 16 slot 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RX Mapping 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
8.1.3.5 ASRC
The ASRC module supports sampling rate conversion between the up-sampling and down-sampling. The ASRC
also supports sampling rate conversion between dual-channel audio data, and the size of the sampling data is
up to 24 bits.
The ASRC module has the following features:
Typical THD + N: -130 dB (Range: -125 dB to -139 dB)
Supports sampling rate conversion between the up-sampling and down-sampling to implement the
sampling rate conversion for stereo data
- The up-sampling ratio ranges from 1 to 7.5x
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- The down-sampling ratio ranges from 8 to 1x
Supports sampling rate conversion between two identical frequencies
Sampling rate for both the input and output range is from 8 kHz to 192 kHz and can be decimal
Sampling rate can be configured manually or via adaptive generation
The ASRC input is connected to I2S RX_FIFO_WDATA [31:8], and the input data is 24-bit MSB big-endian.
For the input data that is less than 24 bits, use zeros to pad out the values at the low bits instead of high
bits
The ASRC needs some time to calculate the result. The output outsamplea/b will keep 0 during the
calculation, and then change to the valid value when the result comes out
Calculating the ASRC Latency
Calculate the ASRC up-sampling and down-sampling latency according to the following formulas.
UpsamplingLatency PhaseDelay FIFODelay 32 16 48InputSamplePeriods
ng Latency PhaseDelay FIFODelay (32* fsout/fsin) 16InputSamplePeriods
Downsampli
ASRC Timing
The MCLK samples the input clock CLKIN to generate pulse signals.
The following figure shows the timing requirements for the inputs.
Figure 8-9 Timing Requirements for Inputs
Tsu=0 Th=5*MCLK
Valid Data
Min= 5*MCLK
Min= 5*MCLK
The following figure shows the timing requirements for the outputs.
Figure 8-10 Timing Requirements for Outputs
Min= 5*MCLK
Min= 5*MCLK
3*MCLK 100*MCLK
Valid Data
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For the up-sampling, FMCLK Fsout*1350.
For the down-sampling, FMCLK Fsin* 0.30 Fsout* 295.
The following table provides the proper values of MCLK in MHz with different Fsin and Fsout in kHz.
Table 8-4 Proper MCLK Values with Different Fsin and Fsout
Fsout
32 44.1 48 88.2 96 144 192
Fsin
32 45 60 65 120 130 195 260
44.1 55 60 65 120 130 195 260
48 60 65 65 120 130 195 260
88.2 105 105 110 120 130 195 260
96 110 115 115 125 130 195 260
144 160 165 165 175 180 195 260
192 210 215 215 225 230 245 260
Note: The units for Fsin and Fsout are kHz and MCLK is MHz.
8.1.3.6 Operation Modes
The software operation of the I2S/PCM is divided into five steps: system setup, I2S/PCM initialization, the
channel setup, DMA setup, and Enable/Disable module.
The following figure shows the whole operation flow of I2S/PCM.
Figure 8-11 I2S/PCM Operation Flow
I2S/PCM System Setup I2S/PCM Initialization
System Setup
Pin Multiplex
Globe/TX/RX Disable
I2S/PCM Initialization
PLL_AUDIO Frequence and Enable
Channel Setup
Clear TXFIFO/RXFIFO
CLK Reset and Gating
DMA Setup
Enable/Disable Module Bus Reset and Gating Clear TXFIFO/RXFIFO Counter
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1. System Setup and I2S/PCM Initialization
The clock source for the I2S/PCM should be followed. Firstly, disable the PLL_AUDIO through PLL_AUDIOx
Control Register[PLL_ENABLE] in the CCU. Secondly, set up the frequency of the PLL_AUDIO in the
PLL_AUDIOx Control Register. After that, enable the I2S/PCM gating through the I2S/PCMx_CLK_REG
when you checkout that the PLL_AUDIOx Control Register[LOCK] becomes to 1. At last, reset and enable
the I2S/PCM bus gating by setting I2S/PCM_BGR_REG.
After the system setup, the register of I2S/PCM can be setup. Firstly, initialize the I2S/PCM. You should
close the Globe Enable bit (I2S/PCM_CTL[0]), Transmitter Block Enable bit (I2S/PCM_CTL[2]), and Receiver
Block Enable bit (I2S/PCM_CTL[1]) by writing 0. After that, clear the TX/RX FIFO by writing 0 to the
bit[25:24] of I2S/PCM_FCTL. At last, you can clear the TX FIFO and RX FIFO counter by writing 0 to
I2S/PCM_TXCNT and I2S/PCM_RXCNT.
2. Channel Setup and DMA Setup
First, you can set up the I2S/PCM of master and slave. The configuration can be referred to the protocol
of I2S/PCM. Then, you can set up the translation mode, the sample resolution, the wide of the slot, the
channel slot number, and the trigger level, and so on. The setup of the register can be found in the
specification.
The I2S/PCM supports two methods to transfer the data. The most common way is DMA, the setup of
DMA can be found in the “DMA”. In this module, you just enable the DRQ.
3. Enable and Disable I2S/PCM
To enable the function, you can enable TX/RX by writing I2S/PCM_CTL[TXEN]/I2S/PCM_CTL[RXEN]. After
that, enable I2S/PCM by writing 1 to I2S/PCM_CTL[Globe Enable]. Write 0 to the Globe Enable bit to
disable I2S/PCM.
8.1.4 Programming Guidelines
8.1.4.1 Application Example of Processing ASRC Input and Output Data
The following example shows a typical application of ASRC: the input data is 24-bit valid, and the output data
is a 32-bit data whose highest 24 bits are valid output and the lowest eight bits are padded out with zeros.
To implement the application, configure the sample resolution and slot width as 32 bits. Follow the steps below:
Step 1 For the input register: 0x04 [6:4] sample_res = 3`h7, 0x04 [2:0] slot_width = 3`h7.
The format of the input data: 32’hXXXXXXXX, where, bit[31] is the MSB and X is the valid data bit.
Step 2 For the output register: 0x04 [6:4] sample_res = 3`h7, 0x04 [2:0] slot_width = 3`h7
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The format of the output data: 32’hXXXXXX00, where, bit[31] is the MSB, X is the valid data bit, and
bit[7:0] are the padded zeros.
8.1.4.2 Converting the Sampling Rate with ASRC
Converting a 48 kHz sampling rate to 16 kHz is the most common scenario in actual applications. Follow the
steps below to convert the sampling rate from 48 kHz to 16 kHz for the 32-bit data.
1. Configure the PLL_AUDIO Register
a) Configure the PLL_AUDIO0_CTRL_REG[31:0] as 0x8814AB01. That is, PLL_AUDIO0 =
24*(171+1)/(1+1)/(1+0)/(1+20) = 98.286 MHz. According to the relationship among the Fsin, Fsout,
and MCLK, the MCLK should be greater than 60 MHz. In the simulation phase, the HOSC frequency is
25 MHz, so the output frequency of PLL_AUDIO0 should be 25*(171+1)/(1+1)/(1+0)/(1+20) = 102.381
MHz. In the IC test phase, configure the frequency of PLL_AUDIO0 according to its actual output
frequency.
b) It is suggested that you configure the ASRC MCLK as an equal-duty-cycle signal. You can specify an
odd number for bit[21:16] (PLL_POST_DIV_P) of PLL_AUDIO0_CTRL_REG to get an equal-duty-cycle
output clock of PLL_AUDIO0.
c) Configure bit[25:24] of I2S/PCM2_ASRC_CLK_REG as 0x00 to select the PLL_AUDIO0(4X).
2. Configure the I2S Registers
a) Configure bit[7:4] (BCLKDIV) of I2S/PCM_CLKD as 4`h9, that is, the frequency of BCLK will be 98.286
MHz/32 = 3.072 MHz.
b) Configure bit[17:8] (LRCK_PERIOD) of I2S/PCM_FMT0 as 10`h1F. That is, the LRCK_PERIOD width is
configured as 32 BLCKs and can generate the ASRC CLKIN with a 48 kHz sampling rate.
3.072MHz
( = 48kHz )
32* 2
c) Configure bit[6:4] (Sample Resolution bits) of I2S/PCM_FMT0 as 3`h7 to specify the sample
resolution as 32-bit.
d) Configure bit[2:0] (Slot Width bits) of I2S/PCM_FMT0 as 3`h7 to specify the slot width as 32-bit.
3. Configure the ASRC Registers
a) Configure bit[16] (clock gate) of MCLKCFG as 1`h1 to open the clock gating.
b) Configure bit[3:0] (division factor) of MCLKCFG as 1`h1 to specify the division factor as 1.
c) Configure bit[20] (clock gate ) of FSOUTCFG as 1`h1 to open the clock gating.
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d) Configure bit[19:16] (clock select) of FSOUTCFG as 4`h0 to select I2S0_ASRC_CLK as the clock source.
e) Configure bit[7:4] (the first division factor) of FSOUTCFG as 16`h13 to configure the first division factor
as 128.
f) Configure bit[3:0] (the second division factor) of FSOUTCFG as 16`h10 to configure the second division
factor as 48.
g) Configure the ASRC ratio.
To configure the ASRC ratio manually, configure bit[31] (Manual Configuration of ASRC Ratio Enable)
of ASRCMANCFG as 1`h1 to enable the manual configuration of ASRC ratio. Configure bit[25:0] of
ASRCMANCFG as 26`h155555 to specify the ratio value as 0x155555. The calculation formula for the
ratio value: Dec2Hex (Fsout/Fsin)*222). In this example, Fsout/Fsin = 16 kHz/48 kHz =1/3, then the
ratio is 0x155555.
To configure the ASRC ratio automatically, configure bit[31] (Manual Configuration of ASRC Ratio
Enable) of ASRCMANCFG as 1`h0 to enable the automatic configuration of ASRC ratio. Then the
system will automatically calculate the ratio value based on the MCLK, Fsout, and Fsin.
8.1.5 Register List
Module Name Base Address
I2S/PCM1 0x02033000
I2S/PCM2 0x02034000
Register Name Offset Description
I2S/PCM_CTL 0x0000 I2S/PCM Control Register
I2S/PCM_FMT0 0x0004 I2S/PCM Format Register 0
I2S/PCM_FMT1 0x0008 I2S/PCM Format Register 1
I2S/PCM_ISTA 0x000C I2S/PCM Interrupt Status Register
I2S/PCM_RXFIFO 0x0010 I2S/PCM RXFIFO Register
I2S/PCM_FCTL 0x0014 I2S/PCM FIFO Control Register
I2S/PCM_FSTA 0x0018 I2S/PCM FIFO Status Register
I2S/PCM_INT 0x001C I2S/PCM DMA & Interrupt Control Register
I2S/PCM_TXFIFO 0x0020 I2S/PCM TXFIFO Register
I2S/PCM_CLKD 0x0024 I2S/PCM Clock Divide Register
I2S/PCM_TXCNT 0x0028 I2S/PCM TX Sample Counter Register
I2S/PCM_RXCNT 0x002C I2S/PCM RX Sample Counter Register
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Register Name Offset Description
I2S/PCM_CHCFG 0x0030 I2S/PCM Channel Configuration Register
I2S/PCM_TX0CHSEL 0x0034 I2S/PCM TX0 Channel Select Register
I2S/PCM_TX1CHSEL 0x0038 I2S/PCM TX1 Channel Select Register
I2S/PCM_TX2CHSEL 0x003C I2S/PCM TX2 Channel Select Register
I2S/PCM_TX3CHSEL 0x0040 I2S/PCM TX3 Channel Select Register
I2S/PCM_TX0CHMAP0 0x0044 I2S/PCM TX0 Channel Mapping Register0
I2S/PCM_TX0CHMAP1 0x0048 I2S/PCM TX0 Channel Mapping Register1
I2S/PCM_TX1CHMAP0 0x004C I2S/PCM TX1 Channel Mapping Register0
I2S/PCM_TX1CHMAP1 0x0050 I2S/PCM TX1 Channel Mapping Register1
I2S/PCM_TX2CHMAP0 0x0054 I2S/PCM TX2 Channel Mapping Register0
I2S/PCM_TX2CHMAP1 0x0058 I2S/PCM TX2 Channel Mapping Register1
I2S/PCM_TX3CHMAP0 0x005C I2S/PCM TX3 Channel Mapping Register0
I2S/PCM_TX3CHMAP1 0x0060 I2S/PCM TX3 Channel Mapping Register1
I2S/PCM_RXCHSEL 0x0064 I2S/PCM RX Channel Select Register
I2S/PCM_RXCHMAP0 0x0068 I2S/PCM RX Channel Mapping Register0
I2S/PCM_RXCHMAP1 0x006C I2S/PCM RX Channel Mapping Register1
I2S/PCM_RXCHMAP2 0x0070 I2S/PCM RX Channel Mapping Register2
I2S/PCM_RXCHMAP3 0x0074 I2S/PCM RX Channel Mapping Register3
MCLKCFG 0x0080 ASRC MCLK Configuration Register
FsoutCFG 0x0084 ASRC Out Sample Rate Configuration Register
FsinEXTCFG 0x0088 ASRC Input Sample Pulse Extend Configuration Register
ASRCCFG 0x008C ASRC Enable Register
ASRCMANCFG 0x0090 ASRC Manual Ratio Configuration Register
ASRCRATIOSTAT 0x0094 ASRC Status Register
ASRCFIFOSTAT 0x0098 ASRC FIFO Level Status Register
ASRCMBISTCFG 0x009C ASRC MBIST Test Configuration Register
ASRCMBISTSTAT 0x00A0 ASRC MBIST Test Status Register
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8.1.6 Register Description
8.1.6.1 0x0000 I2S/PCM Control Register (Default Value: 0x0006_0000)
Offset: 0x0000 Register Name: I2S/PCM_CTL
Bit Read/Write Default/Hex Description
31:22 / / /
RX_SYNC_EN_START
The bit takes effect only when RX_SYNC_EN is set to 1.
21 R/W 0x0 I2S1/I2S2/OWA RX Synchronize Enable Start.
0: Disabled
1: Enabled
RX_SYNC_EN
I2S RX Synchronize Enable
20 R/W 0x0
0: Disabled
1: Enabled
19 / / /
BCLK_OUT
Bit Clock Direction Select
18 R/W 0x1
0: Input
1: Output
LRCK_OUT
LRCK Direction Select
17 R/W 0x1
0: Input
1: Output
16:12 / / /
DOUT3_EN
Data3 Output Enable
11 R/W 0x0
0: Disabled, Hi-Z State
1: Enabled
DOUT2_EN
Data2 Output Enable
10 R/W 0x0
0: Disabled, Hi-Z State
1: Enabled
DOUT1_EN
Data1 Output Enable
9 R/W 0x0
0: Disabled, Hi-Z State
1: Enabled
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Offset: 0x0000 Register Name: I2S/PCM_CTL
Bit Read/Write Default/Hex Description
DOUT0_EN
Data0 Output Enable
8 R/W 0x0
0: Disabled, Hi-Z State
1: Enabled
7 / / /
OUT_MUTE
Data Output Mute Enable
6 R/W 0x0
0: Normal Transfer
1: Force DOUT to output 0
MODE_SEL
Mode Selection
00: PCM Mode (offset 0: Long Frame; offset 1: Short Frame)
5:4 R/W 0x0
01: Left Mode (offset 0: LJ Mode; offset 1: I2S Mode)
10: Right-Justified Mode
11: Reserved
LOOP
Loopback Test
0: Normal Mode
3 R/W 0x0
1: Loopback Test
When set to ‘1’, the bit indicates that the DOUT is connected to
the DIN.
TXEN
Transmitter Block Enable
2 R/W 0x0
0: Disabled
1: Enabled
RXEN
Receiver Block Enable
1 R/W 0x0
0: Disabled
1: Enabled
GEN
Globe Enable
0 R/W 0x0
0: Disabled
1: Enabled
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8.1.6.2 0x0004 I2S/PCM Format Register 0 (Default Value: 0x0000_0033)
Offset: 0x0004 Register Name: I2S/PCM_FMT0
Bit Read/Write Default/Hex Description
31 / / /
LRCK_WIDTH
LRCK Width (only applies to the PCM mode)
30 R/W 0x0
0: LRCK = 1 BCLK Width (Short Frame)
1: LRCK = 2 BCLK Width (Long Frame)
29:20 / / /
LRCK_POLARITY
In I2S/Left-Justified/Right-Justified mode:
0: Left Channel when LRCK is low.
19 R/W 0x0 1: Left channel when LRCK is high.
In PCM mode:
0: PCM LRCK asserted at the negative edge.
1: PCM LRCK asserted at the positive edge.
18 / / /
LRCK_PERIOD
It is used to program the number of BCLKs per channel of the
sample frame. This value is interpreted as follows.
PCM mode: Number of BCLKs within (Left + Right) channel
width.
17:8 R/W 0x0 I2S/Left-Justified/Right-Justified mode: Number of BCLKs
within each channel width (Left or Right).
For example:
N = 7: 8 BCLKs width
…
N = 1023: 1024 BCLKs width
BCLK_POLARITY
7 R/W 0x0 0: Normal mode, DOUT drives data at negative edge
1: Invert mode, DOUT drives data at positive edge
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Offset: 0x0004 Register Name: I2S/PCM_FMT0
Bit Read/Write Default/Hex Description
SR
Sample Resolution
000: Reserved
001: 8-bit
010: 12-bit
6:4 R/W 0x3
011: 16-bit
100: 20-bit
101: 24-bit
110: 28-bit
111: 32-bit
EDGE_TRANSFER
Edge Transfer
0: DOUT drives data and DIN sample data at the different BCLK
edge
1: DOUT drives data and DIN sample data at the same BCLK
edge
BCLK_POLARITY = 0, EDGE_TRANSFER = 0, DIN sample data at
3 R/W 0x0
positive edge;
BCLK_POLARITY = 0, EDGE_TRANSFER = 1, DIN sample data at
negative edge;
BCLK_POLARITY = 1, EDGE_TRANSFER = 0, DIN sample data at
negative edge;
BCLK_POLARITY = 1, EDGE_TRANSFER = 1, DIN sample data at
positive edge.
SW
Slot Width Select
000: Reserved
001: 8-bit
010: 12-bit
2:0 R/W 0x3
011: 16-bit
100: 20-bit
101: 24-bit
110: 28-bit
111: 32-bit
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8.1.6.3 0x0008 I2S/PCM Format Register 1 (Default Value: 0x0000_0030)
Offset: 0x0008 Register Name: I2S/PCM_FMT1
Bit Read/Write Default/Hex Description
31:8 / / /
RX MLS
MSB/LSB First Select
7 R/W 0x0
0: MSB First
1: LSB First
TX MLS
MSB/LSB First Select
6 R/W 0x0
0: MSB First
1: LSB First
SEXT
Sign Extend in Slot [Sample Resolution < Slot Width]
00: Zeros or audio gain padding at LSB position
5:4 R/W 0x3
01: Sign extension at MSB position
10: Reserved
11: Transfer 0 after each sample in each Slot
RX_PDM
PCM Data Mode
00: Linear PCM
3:2 R/W 0x0
01: Reserved
10: 8-bit u-law
11: 8-bit A-law
TX_PDM
PCM Data Mode
00: Linear PCM
1:0 R/W 0x0
01: Reserved
10: 8-bit u-law
11: 8-bit A-law
8.1.6.4 0x000C I2S/PCM Interrupt Status Register (Default Value: 0x0000_0010)
Offset: 0x000C Register Name: I2S/PCM_ISTA
Bit Read/Write Default/Hex Description
31:7 / / /
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Offset: 0x000C Register Name: I2S/PCM_ISTA
Bit Read/Write Default/Hex Description
TXU_INT
TXFIFO Underrun Pending Interrupt
6 R/W1C 0x0 0: No pending interrupt
1: TXFIFO underrun pending interrupt
Write ‘1’ to clear this interrupt.
TXO_INT
TXFIFO Overrun Pending Interrupt
5 R/W1C 0x0 0: No pending interrupt
1: TXFIFO overrun pending interrupt
Write ‘1’ to clear this interrupt.
TXE_INT
TXFIFO Empty Pending Interrupt
4 R 0x1 0: No pending IRQ
1: TXFIFO empty pending interrupt when data in TXFIFO are less
than TX trigger level
3 / / /
RXU_INT
RXFIFO Underrun Pending Interrupt
2 R/W1C 0x0 0: No pending interrupt
1: RXFIFO underrun pending interrupt
Write ‘1’ to clear this interrupt.
RXO_INT
RXFIFO Overrun Pending Interrupt
1 R/W1C 0x0 0: No pending IRQ
1: RXFIFO overrun pending IRQ
Write ‘1’ to clear this interrupt.
RXA_INT
RXFIFO Data Available Pending Interrupt
0 R/W 0x0 0: No pending IRQ
1: Data available pending IRQ when data in RXFIFO are more
than RX trigger level
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8.1.6.5 0x0010 I2S/PCM RXFIFO Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: I2S/PCM_RXFIFO
Bit Read/Write Default/Hex Description
RX_DATA
RX Sample
31:0 R 0x0
The host can get one sample by reading this register. The left
channel sample data is first and then the right channel sample.
8.1.6.6 0x0014 I2S/PCM FIFO Control Register (Default Value: 0x0004_00F0)
Offset: 0x0014 Register Name: I2S/PCM_FCTL
Bit Read/Write Default/Hex Description
HUB_EN
Audio Hub Enable
The bit takes effect only when TXEN is set to 1.
31 R/W 0x0
I2S1/I2S2/OWA TXFIFO Hub Enable.
0: Disabled
1: Enabled
30:26 / / /
FTX
25 R/WAC 0x0
Write ‘1’ to flush TXFIFO, self clear to ‘0’.
FRX
24 R/WAC 0x0
Write ‘1’ to flush RXFIFO, self clear to ‘0’.
23:19 / / /
TXTL
TXFIFO Empty Trigger Level
18:12 R/W 0x40 Interrupt and DMA request trigger level for TXFIFO normal
condition.
Trigger Level = TXTL
11:10 / / /
RXTL
RXFIFO Trigger Level
9:4 R/W 0xF Interrupt and DMA request trigger level for RXFIFO normal
condition.
Trigger Level = RXTL + 1
3 / / /
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Offset: 0x0014 Register Name: I2S/PCM_FCTL
Bit Read/Write Default/Hex Description
TXIM
TXFIFO Input Mode (Mode 0, 1)
0: Valid data at the MSB of TXFIFO register
2 R/W 0x0 1: Valid data at the LSB of TXFIFO register
Example for 20-bit transmitted audio sample:
Mode 0: TXFIFO[31:0] = {APB_WDATA[31:12], 12’h0}
Mode 1: TXFIFO[31:0] = {APB_WDATA[19:0], 12’h0}
RXOM
RXFIFO Output Mode (Mode 0, 1, 2, 3)
00: Expanding ‘0’ at LSB of RXFIFO register
01: Expanding received sample sign bit at MSB of RXFIFO
register
10: Truncating received samples at high half-word of RXFIFO
register and low half-word of RXFIFO register is filled by ‘0’
1:0 R/W 0x0 11: Truncating received samples at low half-word of RXFIFO
register and high half-word of RXFIFO register is expanded by
its sign bit
Example for 20-bit received audio sample:
Mode 0: APB_RDATA[31:0] = {RXFIFO[31:12], 12’h0}
Mode 1: APB_RDATA[31:0] = {12{RXFIFO[31]}, RXFIFO[31:12]}
Mode 2: APB_RDATA [31:0] = {RXFIFO[31:16], 16’h0}
Mode 3: APB_RDATA[31:0] = {16{RXFIFO[31], RXFIFO[31:16]}
8.1.6.7 0x0018 I2S/PCM FIFO Status Register (Default Value: 0x1080_0080)
Offset: 0x0018 Register Name: I2S/PCM_FSTA
Bit Read/Write Default/Hex Description
31:29 / / /
TXE
TXFIFO Empty
28 R 0x1
0: No room for new sample in TXFIFO
1: More than one room for new sample in TXFIFO (>= 1 Word)
27:24 / / /
TXE_CNT
23:16 R 0x80
TXFIFO Empty Space Word Counter
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Offset: 0x0018 Register Name: I2S/PCM_FSTA
Bit Read/Write Default/Hex Description
15:9 / / /
RXA
RXFIFO Available
8 R 0x0
0: No available data in RXFIFO
1: More than one sample in RXFIFO (>= 1 Word)
PLACE_HOLDER
7 R 0x1
NO Meaning.
RXA_CNT
6:0 R 0x0
RXFIFO available sample word counter
8.1.6.8 0x001C I2S/PCM DMA & Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: I2S/PCM_INT
Bit Read/Write Default/Hex Description
31:8 / / /
TX_DRQ
TXFIFO Empty DRQ Enable
7 R/W 0x0
0: Disabled
1: Enabled
TXUI_EN
TXFIFO Underrun Interrupt Enable
6 R/W 0x0
0: Disabled
1: Enabled
TXOI_EN
TXFIFO Overrun Interrupt Enable
0: Disabled
5 R/W 0x0
1: Enabled
When set to ‘1’, an interrupt happens when writing new audio
data if TXFIFO is full.
TXEI_EN
TXFIFO Empty Interrupt Enable
4 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x001C Register Name: I2S/PCM_INT
Bit Read/Write Default/Hex Description
RX_DRQ
RXFIFO Data Available DRQ Enable
0: Disabled
3 R/W 0x0
1: Enabled
When set to ‘1’, RXFIFO DMA request line is asserted if data is
available in RXFIFO.
RXUI_EN
RXFIFO Underrun Interrupt Enable
2 R/W 0x0
0: Disabled
1: Enabled
RXOI_EN
RXFIFO Overrun Interrupt Enable
1 R/W 0x0
0: Disabled
1: Enabled
RXAI_EN
RXFIFO Data Available Interrupt Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.1.6.9 0x0020 I2S/PCM TXFIFO Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: I2S/PCM_TXFIFO
Bit Read/Write Default/Hex Description
TX_DATA
TX Sample
31:0 W 0x0 Transmitting left, right channel sample data should be written
to this register one by one. The left channel sample data is first
and then the right channel sample.
8.1.6.10 0x0024 I2S/PCM Clock Divide Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: I2S/PCM_CLKD
Bit Read/Write Default/Hex Description
31:9 / / /
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Offset: 0x0024 Register Name: I2S/PCM_CLKD
Bit Read/Write Default/Hex Description
MCLKO_EN
0: Disable MCLK Output
8 R/W 0x0 1: Enable MCLK Output
Note: Whether in slave or master mode, when this bit is set to
‘1’, MCLK should be output.
BCLKDIV
BCLK Divide Ratio from PLL_AUDIO
0000: Reserved
0001: Divide by 1
0010: Divide by 2
0011: Divide by 4
0100: Divide by 6
0101: Divide by 8
0110: Divide by 12
7:4 R/W 0x0
0111: Divide by 16
1000: Divide by 24
1001: Divide by 32
1010: Divide by 48
1011: Divide by 64
1100: Divide by 96
1101: Divide by 128
1110: Divide by 176
1111: Divide by 192
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Offset: 0x0024 Register Name: I2S/PCM_CLKD
Bit Read/Write Default/Hex Description
MCLKDIV
MCLK Divide Ratio from PLL_AUDIO
0000: Reserved
0001: Divide by 1
0010: Divide by 2
0011: Divide by 4
0100: Divide by 6
0101: Divide by 8
0110: Divide by 12
3:0 R/W 0x0
0111: Divide by 16
1000: Divide by 24
1001: Divide by 32
1010: Divide by 48
1011: Divide by 64
1100: Divide by 96
1101: Divide by 128
1110: Divide by 176
1111: Divide by 192
8.1.6.11 0x0028 I2S/PCM TX Sample Counter Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: I2S/PCM_TXCNT
Bit Read/Write Default/Hex Description
TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO. When one
sample is put into TXFIFO by DMA or by host IO, the TX sample
31:0 R/W 0x0
counter register increases by one. The TX sample counter
register can be set to any initial value at any time. After being
updated by the initial value, the counter register should count
on the base of this initial value.
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8.1.6.12 0x002C I2S/PCM RX Sample Counter Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: I2S/PCM_RXCNT
Bit Read/Write Default/Hex Description
RX_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO. When one
sample is written by Digital Audio Engine, the RX sample
31:0 R/W 0x0
counter register increases by one. The RX sample counter
register can be set to any initial value at any time. After being
updated by the initial value, the counter register should count
on the base of this initial value.
8.1.6.13 0x0030 I2S/PCM Channel Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: I2S/PCM_CHCFG
Bit Read/Write Default/Hex Description
31:10 / / /
TX_SLOT_HIZ
9 R/W 0x0 0: Normal mode for the last half-cycle of BCLK in the slot
1: Turn to Hi-Z state for the last half-cycle of BCLK in the slot
TX_STATE
8 R/W 0x0 0: Transfer level 0 in non-transferring slot
1: Turn to Hi-Z State (TDM) in non-transferring slot
RX_SLOT_NUM
RX Channel/Slot number between CPU/DMA and RXFIFO
0000: 1 channel or slot
...
7:4 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
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Offset: 0x0030 Register Name: I2S/PCM_CHCFG
Bit Read/Write Default/Hex Description
TX_SLOT_NUM
TX Channel/Slot number between CPU/DMA and TXFIFO
0000: 1 channel or slot
...
3:0 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111:16 channels or slots
8.1.6.14 0x0034 I2S/PCM TX0 Channel Select Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: I2S/PCM_TX0CHSEL
Bit Read/Write Default/Hex Description
31:22 / / /
TX0_OFFSET
TX0 Offset Tune (TX0 Data offset to LRCK)
21:20 R/W 0x0
0: No offset
n: Data is offset by n BCLKs to LRCK
TX0_CHSEL
TX0 Channel (Slot) Number Select for Each Output
0000: 1 channel or slot
...
19:16 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
TX0_CHEN
TX0 Channel (Slot) Enable
The bit[15:0] refer to Slot [15:0]. When one or more slots are
15:0 R/W 0x0
disabled, the affected slots are set to the disable state.
0: Disabled
1: Enabled
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8.1.6.15 0x0038 I2S/PCM TX1 Channel Select Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: I2S/PCM_TX1CHSEL
Bit Read/Write Default/Hex Description
31:22 / / /
TX1_OFFSET
TX1 Offset Tune (TX1 Data offset to LRCK)
21:20 R/W 0x0
0: No offset
n: Data is offset by n BCLKs to LRCK
TX1_CHSEL
TX1 Channel (Slot) Number Select for Each Output
0000: 1 channel or slot
...
19:16 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
TX1_CHEN
TX1 Channel (Slot) Enable
The bit[15:0] refers to Slot [15:0]. When one or more slots are
15:0 R/W 0x0
disabled, the affected slots are set to the disable state.
0: Disabled
1: Enabled
8.1.6.16 0x003C I2S/PCM TX2 Channel Select Register (Default Value: 0x0000_0000)
Offset: 0x003C Register Name: I2S/PCM_TX2CHSEL
Bit Read/Write Default/Hex Description
31:22 / / /
TX2_OFFSET
TX2 Offset Tune (TX2 Data offset to LRCK)
21:20 R/W 0x0
0: No offset
n: Data is offset by n BCLKs to LRCK
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Offset: 0x003C Register Name: I2S/PCM_TX2CHSEL
Bit Read/Write Default/Hex Description
TX2_CHSEL
TX2 Channel (Slot) Number Select for Each Output
0000: 1 channel or slot
...
19:16 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
TX2_CHEN
TX2 Channel (Slot) Enable
The bit[15:0] refers to Slot [15:0]. When one or more slots are
15:0 R/W 0x0
disabled, the affected slots are set to the disable state.
0: Disabled
1: Enabled
8.1.6.17 0x0040 I2S/PCM TX3 Channel Select Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: I2S/PCM_TX3CHSEL
Bit Read/Write Default/Hex Description
31:22 / / /
TX3_OFFSET
TX3 Offset Tune (TX3 Data offset to LRCK)
21:20 R/W 0x0
0: No offset
n: Data is offset by n BCLKs to LRCK
TX3_CHSEL
TX3 Channel (Slot) Number Select for Each Output
0000: 1 channel or slot
...
19:16 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
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Offset: 0x0040 Register Name: I2S/PCM_TX3CHSEL
Bit Read/Write Default/Hex Description
TX3_CHEN
TX3 Channel (Slot) Enable
The bit[15:0] refers to Slot [15:0]. When one or more slots are
15:0 R/W 0x0
disabled, the affected slots are set to the disable state.
0: Disabled
1: Enabled
8.1.6.18 0x0044 I2S/PCM TX0 Channel Mapping0 Register 0 (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: I2S/PCM_TX0CHMAP0
Bit Read/Write Default/Hex Description
TX0_CH15_MAP
TX0 Channel 15 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH14_MAP
TX0 Channel 14 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH13_MAP
TX0 Channel 13 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0044 Register Name: I2S/PCM_TX0CHMAP0
Bit Read/Write Default/Hex Description
TX0_CH12_MAP
TX0 Channel 12 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH11_MAP
TX0 Channel 11 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH10_MAP
TX0 Channel 10 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH9_MAP
TX0 Channel 9 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0044 Register Name: I2S/PCM_TX0CHMAP0
Bit Read/Write Default/Hex Description
TX0_CH8_MAP
TX0 Channel 8 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.19 0x0048 I2S/PCM TX0 Channel Mapping1 Register 1 (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: I2S/PCM_TX0CHMAP1
Bit Read/Write Default/Hex Description
TX0_CH7_MAP
TX0 Channel 7 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH6_MAP
TX0 Channel 6 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0048 Register Name: I2S/PCM_TX0CHMAP1
Bit Read/Write Default/Hex Description
TX0_CH5_MAP
TX0 Channel 5 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH4_MAP
TX0 Channel 4 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH3_MAP
TX0 Channel 3 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH2_MAP
TX0 Channel 2 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0048 Register Name: I2S/PCM_TX0CHMAP1
Bit Read/Write Default/Hex Description
TX0_CH1_MAP
TX0 Channel 1 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX0_CH0_MAP
TX0 Channel 0 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.20 0x004C I2S/PCM TX1 Channel Mapping0 Register 0 (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: I2S/PCM_TX1CHMAP0
Bit Read/Write Default/Hex Description
TX1_CH15_MAP
TX1 Channel 15 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x004C Register Name: I2S/PCM_TX1CHMAP0
Bit Read/Write Default/Hex Description
TX1_CH14_MAP
TX1 Channel 14 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH13_MAP
TX1 Channel 13 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH12_MAP
TX1 Channel 12 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH11_MAP
TX1 Channel 11 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x004C Register Name: I2S/PCM_TX1CHMAP0
Bit Read/Write Default/Hex Description
TX1_CH10_MAP
TX1 Channel 10 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH9_MAP
TX1 Channel 9 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH8_MAP
TX1 Channel 8 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.21 0x0050 I2S/PCM TX1 Channel Mapping1 Register 1 (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: I2S/PCM_TX1CHMAP1
Bit Read/Write Default/Hex Description
TX1_CH7_MAP
TX1 Channel 7 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH6_MAP
TX1 Channel 6 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH5_MAP
TX1 Channel 5 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH4_MAP
TX1 Channel 4 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0050 Register Name: I2S/PCM_TX1CHMAP1
Bit Read/Write Default/Hex Description
TX1_CH3_MAP
TX1 Channel 3 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH2_MAP
TX1 Channel 2 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH1_MAP
TX1 Channel 1 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX1_CH0_MAP
TX1 Channel 0 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.22 0x0054 I2S/PCM TX2 Channel Mapping0 Register 0 (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: I2S/PCM_TX2CHMAP0
Bit Read/Write Default/Hex Description
TX2_CH15_MAP
TX2 Channel 15 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH14_MAP
TX2 Channel 14 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH13_MAP
TX2 Channel 13 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH12_MAP
TX2 Channel 12 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0054 Register Name: I2S/PCM_TX2CHMAP0
Bit Read/Write Default/Hex Description
TX2_CH11_MAP
TX2 Channel 11 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH10_MAP
TX2 Channel 10 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH9_MAP
TX2 Channel 9 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH8_MAP
TX2 Channel 8 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.23 0x0058 I2S/PCM TX2 Channel Mapping1 Register 1 (Default Value: 0x0000_0000)
Offset: 0x0058 Register Name: I2S/PCM_TX2CHMAP1
Bit Read/Write Default/Hex Description
TX2_CH7_MAP
TX2 Channel 7 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH6_MAP
TX2 Channel 6 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH5_MAP
TX2 Channel 5 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH4_MAP
TX2 Channel 4 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0058 Register Name: I2S/PCM_TX2CHMAP1
Bit Read/Write Default/Hex Description
TX2_CH3_MAP
TX2 Channel 3 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH2_MAP
TX2 Channel 2 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH1_MAP
TX2 Channel 1 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX2_CH0_MAP
TX2 Channel 0 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.24 0x005C I2S/PCM TX3 Channel Mapping0 Register 0 (Default Value: 0x0000_0000)
Offset: 0x005C Register Name: I2S/PCM_TX3CHMAP0
Bit Read/Write Default/Hex Description
TX3_CH15_MAP
TX3 Channel 15 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH14_MAP
TX3 Channel 14 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH13_MAP
TX3 Channel 13 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH12_MAP
TX3 Channel 12 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x005C Register Name: I2S/PCM_TX3CHMAP0
Bit Read/Write Default/Hex Description
TX3_CH11_MAP
TX3 Channel 11 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH10_MAP
TX3 Channel 10 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH9_MAP
TX3 Channel 9 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH8_MAP
TX3 Channel 8 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.25 0x0060 I2S/PCM TX3 Channel Mapping1 Register 1 (Default Value: 0x0000_0000)
Offset: 0x0060 Register Name: I2S/PCM_TX3CHMAP1
Bit Read/Write Default/Hex Description
TX3_CH7_MAP
TX3 Channel 7 Mapping
0000: The first sample
…
31:28 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH6_MAP
TX3 Channel 6 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH5_MAP
TX3 Channel 5 Mapping
0000: The first sample
…
23:20 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH4_MAP
TX3 Channel 4 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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Offset: 0x0060 Register Name: I2S/PCM_TX3CHMAP1
Bit Read/Write Default/Hex Description
TX3_CH3_MAP
TX3 Channel 3 Mapping
0000: The first sample
…
15:12 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH2_MAP
TX3 Channel 2 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH1_MAP
TX3 Channel 1 Mapping
0000: The first sample
…
7:4 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
TX3_CH0_MAP
TX3 Channel 0 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
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8.1.6.26 0x0064 I2S/PCM RX Channel Select Register (Default Value: 0x0000_0000)
Offset: 0x0064 Register Name: I2S/PCM_RXCHSEL
Bit Read/Write Default/Hex Description
31:22 / / /
RX_OFFSET
RX Offset Tune (RX Data offset to LRCK)
21:20 R/W 0x0
0: No offset
n: Data is offset by n BCLKs to LRCK
RX_CHSEL
RX Channel (Slot) Number Select for Input
0000: 1 channel or slot
...
19:16 R/W 0x0
0111: 8 channels or slots
1000: 9 channels or slots
...
1111: 16 channels or slots
15:0 / / /
8.1.6.27 0x0068 I2S/PCM RX Channel Mapping Register0 (Default Value: 0x0000_0000)
Offset: 0x0068 Register Name: I2S/PCM_RXCHMAP0
Bit Read/Write Default/Hex Description
31:30 / / /
RX_CH15_SELECT
RX Channel 15 Select
00: SDI0
29:28 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0068 Register Name: I2S/PCM_RXCHMAP0
Bit Read/Write Default/Hex Description
RX_CH15_MAP
RX Channel 15 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
23:22 / / /
RX_CH14_SELECT
RX Channel 14 Select
00: SDI0
21:20 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH14_MAP
RX Channel 14 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
15:14 / / /
RX_CH13_SELECT
RX Channel 13 Select
00: SDI0
13:12 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0068 Register Name: I2S/PCM_RXCHMAP0
Bit Read/Write Default/Hex Description
RX_CH13_MAP
RX Channel 13 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
7:6 / / /
RX_CH12_SELECT
RX Channel 12 Select
00: SDI0
5:4 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH12_MAP
RX Channel 12 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.28 0x006C I2S/PCM RX Channel Mapping Register1 (Default Value: 0x0000_0000)
Offset: 0x006C Register Name: I2S/PCM_RXCHMAP1
Bit Read/Write Default/Hex Description
31:30 / / /
RX_CH11_SELECT
RX Channel 11 Select
00: SDI0
29:28 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x006C Register Name: I2S/PCM_RXCHMAP1
Bit Read/Write Default/Hex Description
RX_CH11_MAP
RX Channel 11 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
23:22 / / /
RX_CH10_SELECT
RX Channel 10 Select
00: SDI0
21:20 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH10_MAP
RX Channel 10 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
15:14 / / /
RX_CH9_SELECT
RX Channel 9 Select
00: SDI0
13:12 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x006C Register Name: I2S/PCM_RXCHMAP1
Bit Read/Write Default/Hex Description
RX_CH9_MAP
RX Channel 9 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
7:6 / / /
RX_CH8_SELECT
RX Channel 8 Select
00: SDI0
5:4 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH8_MAP
RX Channel 8 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.29 0x0070 I2S/PCM RX Channel Mapping Register2 (Default Value: 0x0000_0000)
Offset: 0x0070 Register Name: I2S/PCM_RXCHMAP2
Bit Read/Write Default/Hex Description
31:30 / / /
RX_CH7_SELECT
RX Channel 7 Select
00: SDI0
29:28 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0070 Register Name: I2S/PCM_RXCHMAP2
Bit Read/Write Default/Hex Description
RX_CH7_MAP
RX Channel 7 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
23:22 / / /
RX_CH6_SELECT
RX Channel 6 Select
00: SDI0
21:20 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH6_MAP
RX Channel 6 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
15:14 / / /
RX_CH5_SELECT
RX Channel 5 Select
00: SDI0
13:12 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0070 Register Name: I2S/PCM_RXCHMAP2
Bit Read/Write Default/Hex Description
RX_CH5_MAP
RX Channel 5 Mapping
0000: The first sample
…
11: 8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
7:6 / / /
RX_CH4_SELECT
RX Channel 4 Select
00: SDI0
5:4 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH4_MAP
RX Channel 4 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.30 0x0074 I2S/PCM RX Channel Mapping Register3 (Default Value: 0x0000_0000)
Offset: 0x0074 Register Name: I2S/PCM_RXCHMAP3
Bit Read/Write Default/Hex Description
31:30 / / /
RX_CH3_SELECT
RX Channel 3 Select
00: SDI0
29:28 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0074 Register Name: I2S/PCM_RXCHMAP3
Bit Read/Write Default/Hex Description
RX_CH3_MAP
RX Channel 3 Mapping
0000: The first sample
…
27:24 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
23:22 / / /
RX_CH2_SELECT
RX Channel 2 Select
00: SDI0
21:20 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH2_MAP
RX Channel 2 Mapping
0000: The first sample
…
19:16 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
15:14 / / /
RX_CH1_SELECT
RX Channel 1 Select
00: SDI0
13:12 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
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Offset: 0x0074 Register Name: I2S/PCM_RXCHMAP3
Bit Read/Write Default/Hex Description
RX_CH1_MAP
RX Channel 1 Mapping
0000: The first sample
…
11:8 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
7:6 / / /
RX_CH0_SELECT
RX Channel 0 Select
00: SDI0
5:4 R/W 0x0
01: SDI1
10: SDI2
11: SDI3
RX_CH0_MAP
RX Channel 0 Mapping
0000: The first sample
…
3:0 R/W 0x0
0111: The eighth sample
1000: The ninth sample
...
1111: The sixteenth sample
8.1.6.31 0x0080 I2S/PCM ASRC MCLK Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0080 Register Name: MCLKCFG
Bit Read/Write Default/Hex Description
31:17 R 0x0 /
ASRC_MCLK_GATE
ASRC Clock Gate Enable Control
16 R/W 0x0
0: Gated
1: Not gated
15:4 / / /
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Offset: 0x0080 Register Name: MCLKCFG
Bit Read/Write Default/Hex Description
ASRC_MCLK_FREQ_DIV_COE
Frequency Division Coefficient
4’d0 = Res (no output),
4’d1 = 1x,
4’d2 = 1/2x,
4’d3 = 1/4x,
4’d4 = 1/6x,
4’d5 = 1/8x,
4’d6 = 1/12x,
3:0 R/W 0x0 4’d7 = 1/16x,
4’d8 = 1/24x,
4’d9 = 1/32x,
4’d10 = 1/48,
4’d11 = 1/64x,
4’d12 = 1/96x,
4’d13 = 1/128x,
4’d14 = 1/176x,
4’d15 = 1/192x,
others = Res
8.1.6.32 0x0084 I2S/PCM ASRC OUT Sample Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0084 Register Name: FSOUTCFG
Bit Read/Write Default/Hex Description
31:21 R 0x0 /
FSOUT_GATE
fsout Clock Gate Enable Control
20 R/W 0x0
0: Gated
1: Not gated
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Offset: 0x0084 Register Name: FSOUTCFG
Bit Read/Write Default/Hex Description
FSOUT_CLK_SRC_SEL
fsout Clock Source Select
00: I2S0_ASRC_CLK
19:16 R/W 0x0 01: ACLK
10: ACLKM
11: BCLK
Others: Reserved
15:8 / / /
FSOUT_CLK_FREQ_DIV_COE1
fsout Frequency Division Coefficient 1
The First Division Factor
It has two levels of frequency division, the first level is bit[7:4],
the second level is bit[3:0], and the frequency division factors
are multiplied by the two division factors, the division
relationship of the two divisions are the same.
4’d0 = Res (no output),
4’d1 = 1x,
4’d2 = 1/2x,
4’d3 = 1/4x,
7:4 R/W 0x0 4’d4 = 1/6x,
4’d5 = 1/8x,
4’d6 = 1/12x,
4’d7 = 1/16x,
4’d8 = 1/24x,
4’d9 = 1/32x,
4’d10 = 1/48,
4’d11 = 1/64x,
4’d12 = 1/96x,
4’d13 = 1/128x,
4’d14 = 1/176x,
4’d15 = 1/192x
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Offset: 0x0084 Register Name: FSOUTCFG
Bit Read/Write Default/Hex Description
FSOUT_CLK_FREQ_DIV_COE2
fsout Frequency Division Coefficient 2
The Second Division Factor
4’d0 = Res (no output),
4’d1 = 1x,
4’d2 = 1/2x,
4’d3 = 1/4x,
4’d4 = 1/6x,
4’d5 = 1/8x,
3:0 R/W 0x0 4’d6 = 1/12x,
4’d7 = 1/16x,
4’d8 = 1/24x,
4’d9 = 1/32x,
4’d10 = 1/48,
4’d11 = 1/64x,
4’d12 = 1/96x,
4’d13 = 1/128x,
4’d14 = 1/176x,
4’d15 = 1/192x
8.1.6.33 0x0088 I2S/PCM IN Sample Pulse Extend Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0088 Register Name: FsinEXTCFG
Bit Read/Write Default/Hex Description
31:17 R 0x0 /
Extend Enable
0: Disabled
16 R/W 0x0
1: Enabled
Enable the bit when using ASRC.
The Cycle Number of Pulse Extend
15:0 R/W 0x0
The cycle is BCLK clock and is 1 at least.
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8.1.6.34 0x008C I2S/PCM ASRC Enable Register (Default Value: 0x0000_0000)
Offset: 0x008C Register Name: ASRCEN
Bit Read/Write Default/Hex Description
31:1 R 0x0 /
ASRC Function Enable
0 R/W 0x0 0: Disabled
1: Enabled
8.1.6.35 0x0090 I2S/PCM ASRC Manual Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0090 Register Name: ASRCMANCFG
Bit Read/Write Default/Hex Description
ASRC_RATIO_MANUAL_EN
Manual Configuration of ASRC Ratio Enable
31 R/W 0x0
0: Disabled
1: Enabled
30:26 R 0x0 /
ASRC_RATIO_VALUE_MANUAL_CFG
ASRC Ratio Value Manual Configure
25:0 R/W 0x0 The ratio value is an unsigned 26-bit number and uses 4.22 data
format, which means there are 4 bits to the left of the decimal
point and 22 bits to the right of the decimal point.
8.1.6.36 0x0094 I2S/PCM ASRC Ratio State Register (Default Value: 0x0040_0000)
Offset: 0x0094 Register Name: ASRCRATIOSTAT
Bit Read/Write Default/Hex Description
31:30 R 0x0 /
ASRC_BUF_OVERFLOW_STA
ASRC Receive Data Buffer Overflow State
29 R 0x0 It can control the mute with lock.
0: No overflow
1: Overflow
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Offset: 0x0094 Register Name: ASRCRATIOSTAT
Bit Read/Write Default/Hex Description
ADAPT_COMPUT_LOCK
Adaptive Ratio Computational Lock
28 R 0x0
0: Unlocked
1: Locked
27:26 R 0x0 /
ADAPT_COMPUT_VALUE
25:0 R 0x400000
Adaptive Ratio Computational Value
8.1.6.37 0x0098 I2S/PCM ASRC FIFO State Register (Default Value: 0x0000_0000)
Offset: 0x0098 Register Name: ASRCFIFOSTAT
Bit Read/Write Default/Hex Description
31:9 / / /
ASRC_RX_FIFO_FULL_LEVAL
8:0 R 0x0 ASRC RXFIFO Full Level
The manually-configured FIFO fill level for the ratio value of the
received data.
8.1.6.38 0x009C I2S/PCM MBIST Test Configuration Register (Default Value: 0x0000_0000)
Offset: 0x009C Register Name: ASRCMBISTCFG
Bit Read/Write Default/Hex Description
31:9 / / /
ASRC_RAM_BIST_EN
8 R/W 0x0 ASRC RAM BIST Enable
Enable the RAM BIST.
7:1 / / /
ASRC_ROM_BIST_EN
0 R/W 0x0 ASRC ROM BIST Enable
Enable the ROM BIST.
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8.1.6.39 0x00A0 I2S/PCM ASRC MBIST Test State Register (Default Value: 0x0000_0002)
Offset: 0x00A0 Register Name: ASRCMBISTSTA
Bit Read/Write Default/Hex Description
31:19 / / /
ROM_BIST_ERROR_XOR
18 R 0x0
ROM BIST error xor
ROM_BIST_ERROR_SUM
17 R 0x0
ROM BIST error sum
ROM_BUSY_STATUS
ROM BUSY STATUS
16 R 0x0
1: ROM busy
0: ROM idle
15:8 / / /
RAM_BIST_ERR_STATUS
RAM BIST error status
7 R 0x0
1: Error
0: No effect
RAM_BIST_ERROR_PATTERN.
6:4 R 0x0
RAM BIST error pattern
RAM_BIST_ERROR_CYCLE
3:2 R 0x0
RAM BIST error cycle
RAM_STOP_STATUS
RAM stop status
1 R 0x1
1: Stop
0: Running
RAM_BUSY_STATUS
RAM busy status
0 R 0x0
1: RAM busy
0: RAM idle
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8.2 DMIC
8.2.1 Overview
The DMIC controller supports one 8-channel digital microphone interface and can output 128 fs or 64 fs (fs =
ADC sample rate).
The DMIC controller includes the following features:
Supports up to 8 channels
Sample rate from 8 kHz to 48 kHz
8.2.2 Block Diagram
The following figure shows a block diagram of the DMIC.
Figure 8-12 DMIC Block Diagram
PLL_AUDIO
Clock
DMIC_CLK
Divider
APB RXFIFO
I/F
Receiver DMIC_DATA[3:0]
Registers FSM & Control
DMA & INT
8.2.3 Functional Description
8.2.3.1 External Signals
The following table describes the external signals of DMIC.
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Table 8-5 DMIC External Signals
Signal Description Type
DMIC-CLK Digital Microphone Clock Output O
DMIC-DATA0 Digital Microphone Data Input I
DMIC-DATA1 Digital Microphone Data Input I
DMIC-DATA2 Digital Microphone Data Input I
DMIC-DATA3 Digital Microphone Data Input I
8.2.3.2 Clock Sources
The following table describes the clock source for DMIC. For clock setting, configurations, and gating
information, refer to section 3.3 “CCU”.
Table 8-6 DMIC Clock Sources
Clock Sources Description
PLL_AUDIO0(1X) By default, PLL_AUDIO0(1X) is 24.5714 MHz.
PLL_AUDIO1(DIV2) By default, PLL_AUDIO1 is 3072 MHz, PLL_AUDIO1(DIV2) is 1536 MHz, and
PLL_AUDIO1(DIV5) PLL_AUDIO1(DIV5) is 614.4 MHz (24.576 MHz*25).
8.2.3.3 Operation Mode
The software operation of the DMIC is divided into five steps: system setup, DMIC initialization, channel setup,
DMA setup, and Enable/Disable module.
The following figure shows the flow chart of the whole operation, the system setup, and the DMIC initialization.
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Figure 8-13 DMIC Operation Mode
DMIC System Setup DMIC Initialization
System Setup
Pin Multiplex
Globe Disable
DMIC Initialization
PLL_AUDIO Frequence and Enable
Channel Setup
Flush RXFIFO
CLK Reset and Gating
DMA Setup
Enable/Disable Module Bus Reset and Gating Clear DATA/RXFIFO Counter
1. System Setup and DMIC Initialization
The first step in the system setup is properly programming the GPIO because the DMIC port is a multiplex
pin. For functions of the multiplex pins, refer to the pin multiplex specification.
Perform the following steps for the clock source. Firstly, disable the PLL_AUDIO through PLL_AUDIOx
Control Register[PLL_ENABLE]. Secondly, set up the frequency of the PLL_AUDIO in PLL_AUDIOx Control
Register. Then enable PLL_AUDIO. After that, enable the DMIC gating through DMIC_CLK_REG when you
checkout that the LOCK bit of PLL_AUDIOx Control Register becomes 1. At last, reset and enable the DMIC
bus gating by DMIC_BGR_REG.
After the system setup, the register of DMIC can be setup. Firstly, initialize the DMIC. You should close the
globe enable bit (DMIC_EN[8]), data channel enable bit (DMIC_EN[7:0]) by writing 0 to it. After that, flush
the RXFIFO by writing 1 to DMIC_RXFIFO_CTR[31]. At last, you can clear the Data/RXFIFO counter by
writing 1 to DMIC_RXFIFO_STA, DMIC_CNT.
2. Channel Setup and DMA Setup
You can set up the sample rate, the sample resolution, the over-sample rate, the channel number, the
RXFIFO output mode, the RXFIFO trigger level, and so on. The setup of the register can be found in the
specification.
The DMIC supports two methods to transfer the data. The most common way is DMA, the setup of DMA
can be found in section 3.9 “DMAC”. In this module, you just enable the DRQ.
3. Enable and Disable DMIC
To enable the function, you can enable the data channel enable bit (DMIC_EN[7:0]) by writing 1 to it. After
that, enable DMIC by writing 1 to the Globe Enable bit (DMIC_EN[8]). Write 0 to DMIC_EN[8] to disable
DMIC.
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8.2.4 Register List
Module Name Base Address
DMIC 0x02031000
Register Name Offset Description
DMIC_EN 0x0000 DMIC Enable Control Register
DMIC_SR 0x0004 DMIC Sample Rate Register
DMIC_CTR 0x0008 DMIC Control Register
DMIC_DATA 0x0010 DMIC Data Register
DMIC_INTC 0x0014 MIC Interrupt Control Register
DMIC_INTS 0x0018 DMIC Interrupt Status Register
DMIC_RXFIFO_CTR 0x001C DMIC RXFIFO Control Register
DMIC_RXFIFO_STA 0x0020 DMIC RXFIFO Status Register
DMIC_CH_NUM 0x0024 DMIC Channel Numbers Register
DMIC_CH_MAP 0x0028 DMIC Channel Mapping Register
DMIC_CNT 0x002C DMIC Counter Register
DATA0_DATA1_VOL_CTR 0x0030 Data0 and Data1 Volume Control Register
DATA2_DATA3_VOL_CTR 0x0034 Data2 And Data3 Volume Control Register
HPF_EN_CTR 0x0038 High Pass Filter Enable Control Register
HPF_COEF_REG 0x003C High Pass Filter Coefficient Register
HPF_GAIN_REG 0x0040 High Pass Filter Gain Register
8.2.5 Register Description
8.2.5.1 0x0000 DMIC Enable Control Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: DMIC_EN
Bit Read/Write Default/Hex Description
31:30 / / /
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Offset: 0x0000 Register Name: DMIC_EN
Bit Read/Write Default/Hex Description
RX_SYNC_EN_START
Audio Subsys RX Synchronize Enable Start
Includes Audio codec/I2S1/I2S2/DMIC/OWA RX.
29 R/W 0x0
The bit takes effect only when RX_SYNC_EN is set to 1.
0: Disabled
1: Enabled
RX_SYNC_EN
DMIC RX Synchronize Enable
28 R/W 0x0
0: Disabled
1: Enabled
27:9 / / /
GLOBE_EN
DMIC Globe Enable
8 R/W 0x0
0: Disabled
1: Enabled
DATA3_CHR_EN
DATA3 Right Channel Enable
7 R/W 0x0
0: Disabled
1: Enabled
DATA3_CHL_EN
DATA3 Left Channel Enable
6 R/W 0x0
0: Disabled
1: Enabled
DATA2_CHR_EN
DATA2 Right Channel Enable
5 R/W 0x0
0: Disabled
1: Enabled
DATA2_CHL_EN
DATA2 Left Channel Enable
4 R/W 0x0
0: Disabled
1: Enabled
DATA1_CHR_EN
DATA1 Right Channel Enable
3 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0000 Register Name: DMIC_EN
Bit Read/Write Default/Hex Description
DATA1_CHL_EN
DATA1 Left Channel Enable
2 R/W 0x0
0: Disabled
1: Enabled
DATA0_CHR_EN
DATA0 Right Channel Enable
1 R/W 0x0
0: Disabled
1: Enabled
DATA0_CHL_EN
DATA0 Left Channel Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.2.5.2 0x0004 DMIC Sample Rate Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: DMIC_SR
Bit Read/Write Default/Hex Description
31:3 / / /
DMIC_SR
Sample Rate of DMIC
000: 48 kHz
010: 24 kHz
100: 12 kHz
110: Reserved
2:0 R/W 0x0
001: 32 kHz
011: 16 kHz
101: 8 kHz
111: Reserved
44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL
Configure Bit.
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8.2.5.3 0x0008 DMIC Control Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: DMIC_CTR
Bit Read/Write Default/Hex Description
31:11 / / /
DMICFDT
DMIC RXFIFO Delay Time for Writing Data after GLOBE_EN
00: 5 ms
10:9 R/W 0x0
01: 10 ms
10: 20 ms
11: 30 ms
DMICDFEN
DMIC RXFIFO Delay Function for Writing Data after GLOBE_EN
8 R/W 0x0
0: Disabled
1: Enabled
DATA3 Left Data and Right Data Swap Enable
7 R/W 0x0 0: Disabled
1: Enabled
DATA2 Left Data and Right Data Swap Enable
6 R/W 0x0 0: Disabled
1: Enabled
DATA1 Left Data and Right Data Swap Enable
5 R/W 0x0 0: Disabled
1: Enabled
DATA0 Left Data and Right Data Swap Enable
4 R/W 0x0 0: Disabled
1: Enabled
3:1 / / /
DMIC Oversample Rate
0 R/W 0x0 0: 128 (Supports 8 kHz to 24 kHz)
1: 64 (Supports 16 kHz to 48 kHz)
8.2.5.4 0x0010 DMIC DATA Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: DMIC_DATA
Bit Read/Write Default/Hex Description
31:0 R 0x0 DMIC_DATA
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8.2.5.5 0x0014 DMIC Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: DMIC_INTC
Bit Read/Write Default/Hex Description
31:3 / / /
RXFIFO_DRQ_EN
DMIC RXFIFO Data Available DRQ Enable
2 R/W 0x0
0: Disabled
1: Enabled
RXFIFO_OVERRUN_IRQ_EN
DMIC RXFIFO Overrun IRQ Enable
1 R/W 0x0
0: Disabled
1: Enabled
DATA_IRQ_EN
DMIC RXFIFO Data Available IRQ Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.2.5.6 0x0018 DMIC Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: DMIC_INTS
Bit Read/Write Default/Hex Description
31:2 / / /
RXFIFO_OVERRUN_IRQ_PENDING
DMIC RXFIFO Overrun Pending Interrupt
0: No pending IRQ
1 R/W1C 0x0
1: RXFIFO overrun pending IRQ
Writing ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
RXFIFO_DATA_IRQ_PENDING
DMIC RXFIFO Data Available Pending Interrupt
0: No pending IRQ
0 R/ W1C 0x0
1: Data available pending IRQ
Writing ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
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8.2.5.7 0x001C DMIC RXFIFO Control Register (Default Value: 0x0000_0040)
Offset: 0x001C Register Name: DMIC_RXFIFO_CTR
Bit Read/Write Default/Hex Description
DMIC_RXFIFO_FLUSH
31 R/W1C 0x0 DMIC RXFIFO Flush
Writing ‘1’ to flush RXFIFO, self clear to ‘0’
30:10 / / /
RXFIFO_MODE
RXFIFO Output Mode (Mode 0, 1)
0: Expanding ‘0’ at LSB of RXFIFO register
1: Expanding received sample sign bit at MSB of RXFIFO register
For 24-bit received audio sample:
9 R/W 0x0
Mode 0: RXDATA[31:0] = {RXFIFO_O[20:0], 11’h0}
Mode 1: RXDATA[31:0] = {8{RXFIFO_O[20]}, RXFIFO_O[20:0], 3’h0}
For 16-bit received audio sample:
Mode 0: RXDATA[31:0] = {RXFIFO_O[20:5], 16’h0}
Mode 1: RXDATA[31:0] = {16{RXFIFO_O[20]}, RXFIFO_O[20:5]}
Sample_Resolution
8 R/W 0x0 0: 16-bit
1: 24- bit
RXFIFO_TRG_LEVEL
RXFIFO Trigger Level (TRLV[7:0])
Interrupt and DMA request trigger level for DMIC RXFIFO normal
7:0 R/W 0x40
condition IRQ/DRQ Generated when WLEVEL > TRLV[7:0])
WLEVEL represents the number of valid samples in the DMIC
RXFIFO
8.2.5.8 0x0020 DMIC RXFIFO Status Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: DMIC_RXFIFO_STA
Bit Read/Write Default/Hex Description
31:9 / / /
8 R 0x1 Reserved
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Offset: 0x0020 Register Name: DMIC_RXFIFO_STA
Bit Read/Write Default/Hex Description
DMIC_DATA_CNT
7:0 R/W 0x0
DMIC RXFIFO Available Sample Word Counter
8.2.5.9 0x0024 DMIC Channel Numbers Register (Default Value: 0x0000_0001)
Offset: 0x0024 Register Name: DMIC_CH_NUM
Bit Read/Write Default/Hex Description
31:3 / / /
DMIC_CH_NUM
2:0 R/W 0x1
DMIC enable channel numbers are (N + 1).
8.2.5.10 0x0028 DMIC Channel Mapping Register (Default Value: 0x7654_3210)
Offset: 0x0028 Register Name: DMIC_CH_MAP
Bit Read/Write Default/Hex Description
DMIC_CH7_MAP
DMIC Channel 7 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
31:28 R/W 0x7
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
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Offset: 0x0028 Register Name: DMIC_CH_MAP
Bit Read/Write Default/Hex Description
DMIC_CH6_MAP
DMIC Channel 6 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
27:24 R/W 0x6
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
DMIC_CH5_MAP
DMIC Channel 5 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
23:20 R/W 0x5
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
DMIC_CH4_MAP
DMIC Channel 4 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
19:16 R/W 0x4
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
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Offset: 0x0028 Register Name: DMIC_CH_MAP
Bit Read/Write Default/Hex Description
DMIC_CH3_MAP
DMIC Channel 3 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
15:12 R/W 0x3
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
DMIC_CH2_MAP
DMIC Channel 2 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
11:8 R/W 0x2
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
DMIC_CH1_MAP
DMIC Channel 1 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
7:4 R/W 0x1
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
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Offset: 0x0028 Register Name: DMIC_CH_MAP
Bit Read/Write Default/Hex Description
DMIC_CH0_MAP
DMIC Channel0 Mapping
0000: DATA0 Left Channel
0001: DATA0 Right Channel
0010: DATA1 Left Channel
3:0 R/W 0x0
0011: DATA1 Right Channel
0100: DATA2 Left Channel
0101: DATA2 Right Channel
0110: DATA3 Left Channel
0111: DATA3 Right Channel
8.2.5.11 0x002C DMIC Counter Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: DMIC_CNT
Bit Read/Write Default/Hex Description
DMIC_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO. When one
sample is read by Digital Audio Engine, the RX sample counter
31:0 R/W 0x0 register increases by one. The RX sample counter register can be
set to any initial valve at any time. After being updated by the
initial value, the counter register should count on the base of this
initial value.
Note: It is used for Audio/Video Synchronization.
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8.2.5.12 0x0030 DATA0 and DATA1 Volume Control Register (Default Value: 0xA0A0_A0A0)
Offset: 0x0030 Register Name: DATA0_DATA1_VOL_CTR
Bit Read/Write Default/Hex Description
DATA1L_VOL
Data1 Left Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
31:24 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
DATA1R_VOL
Data1 Right Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
23:16 R/W 0xA0
...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
DATA0L_VOL
Data0 Left Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
15:8 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
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Offset: 0x0030 Register Name: DATA0_DATA1_VOL_CTR
Bit Read/Write Default/Hex Description
DATA0R_VOL
Data0 Right Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
7:0 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
8.2.5.13 0x0034 DATA2 and DATA3 Volume Control Register (Default Value: 0xA0A0_A0A0)
Offset: 0x0034 Register Name: DATA2_DATA3_VOL_CTR
Bit Read/Write Default/Hex Description
DATA3L_VOL
Data3 Light Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
31:24 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
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Offset: 0x0034 Register Name: DATA2_DATA3_VOL_CTR
Bit Read/Write Default/Hex Description
DATA3R_VOL
Data3 Right Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
23:16 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
DATA2L_VOL
Data2 Light Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
15:8 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
DATA2R_VOL
Data2 Right Channel Volume Control
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
7:0 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
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8.2.5.14 0x0038 High Pass Filter Enable Control Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: HPF_EN_CTR
Bit Read/Write Default/Hex Description
31:8 / / /
HPF_DATA3_CHR_EN
High Pass Filter DATA3 Right Channel Enable
7 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA3_CHL_EN
High Pass Filter DATA3 Left Channel Enable
6 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA2_CHR_EN
High Pass Filter DATA2 Right Channel Enable
5 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA2_CHL_EN
High Pass Filter DATA2 Left Channel Enable
4 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA1_CHR_EN
High Pass Filter DATA1 Right Channel Enable
3 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA1_CHL_EN
High Pass Filter DATA1 Left Channel Enable
2 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA0_CHR_EN
High Pass Filter DATA0 Right Channel Enable
1 R/W 0x0
0: Disabled
1: Enabled
HPF_DATA0_CHL_EN
High Pass Filter DATA0 Left Channel Enable
0 R/W 0x0
0: Disabled
1: Enabled
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8.2.5.15 0x003C High Pass Filter Coefficient Register (Default Value: 0x00FF_AA45)
Offset: 0x003C Register Name: HPF_COEF_REG
Bit Read/Write Default/Hex Description
HPF_COE
31:0 R/W 0x00FFAA45
High Pass Filter Coefficient
8.2.5.16 0x0040 High Pass Filter Gain Register (Default Value: 0x00FF_D522)
Offset: 0x0040 Register Name: HPF_GAIN_REG
Bit Read/Write Default/Hex Description
HPF_GAIN
31:0 R/W 0x00FFD522
High Pass Filter Gain
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8.3 OWA
8.3.1 Overview
The One Wire Audio (OWA) provides a serial bus interface for audio data. This interface is widely used for
consumer audio.
The OWA includes the following features:
Compliance with S/PDIF Interface
Compatible with standard IEC-60958 and IEC-61937
- IEC-60958 supports 16-bit, 20-bit and 24-bit data formats
- IEC-61937 uses the IEC-60958 series for the conveying of non-linear PCM bit streams, each sub-
frame transmits 16-bit
TXFIFO and RXFIFO
- One 128×24bits TXFIFO and one 64×24bits RXFIFO for audio data transfer
- Programmable FIFO thresholds
Supports TX/RX DMA slave interface
Supports multiple function clock
- Separate clock for OWA TX and OWA RX
- The clock of TX function includes a series of 24.576 MHz and 22.579 MHz frequency
- The clock of RX function includes a series of 24.576*8 MHz frequency (RX function clock 24.576*8
MHz supports CDR of sample rate from 8 kHz to 192 kHz)
Supports hardware parity on TX/RX
- Hardware parity generation on the transmitter
- Hardware parity checking on the receiver
Supports channel status capture for the receiver
Supports channel sample rate capture on the receiver
Supports insertion detection for the receiver
Supports channel status insertion for the transmitter
Supports interrupts and DMA
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8.3.2 Block Diagram
The following figure shows the OWA block diagram.
Figure 8-14 OWA Block Diagram
PLL_AUDIO
Clock Divider
RXFIFO RXDET
Channel Status Receiver OWA_IN
Registers
APB
I/F
Registers FSM & Control
Channel status
& user data
Transmitter OWA_OUT
buffers
TXFIFO
Clock Divider
DMA & INT
PLL_AUDIO
OWA contains the following sub-blocks:
Table 8-7 OWA Sub-blocks
Sub-block Description
Registers Analyze the configuration parameter, DMA requests, and IRQ feedbacks.
Receiver Parses the frame header and receives the data.
Transmitter Sends the data
FSM Finite state machine
Clock Divider Clock divider circuit
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8.3.3 Functional Description
8.3.3.1 External Signals
The OWA is a Biphase-Mark Encoding Digital Audio Transfer protocol. In this protocol, the CLK signal and data
signal are transferred in the same line. The following figure describes the external signals of OWA. OWA-OUT
is the output pin for the output CLK and DATA, and OWA-IN is the input pin for the input CLK and DATA.
Table 8-8 OWA External Signals
Signal Name Description Type
OWA-OUT OWA output O
OWA-IN OWA input I
8.3.3.2 Clock Sources
The OWA has separate clock for OWA_TX and OWA_RX. The following tables describe the clock sources for
OWA_TX and OWA_RX. For clock setting, configurations and gating information, refer to section 3.3 “CCU”.
Table 8-9 OWA_TX Clock Sources
Clock Name Description
PLL_AUDIO0(1X) By default, PLL_AUDIO0(1X) is 24.5714 MHz, and PLL_AUDIO0(4X) is 98.2856
PLL_AUDIO0(4X) MHz.
PLL_AUDIO1(DIV2) By default, PLL_AUDIO1 is 3072 MHz, PLL_AUDIO1(DIV2) is 1536 MHz, and
PLL_AUDIO1(DIV5) PLL_AUDIO1(DIV5) is 614.4 MHz (24.576 MHz*25).
Table 8-10 OWA_RX Clock Sources
Clock Name Description
PLL_PERI(1X) The default frequency of PLL_PERI(1X) is 600 MHz.
PLL_AUDIO1(DIV2) By default, PLL_AUDIO1 is 3072 MHz, PLL_AUDIO1(DIV2) is 1536 MHz, and
PLL_AUDIO1(DIV5) PLL_AUDIO1(DIV5) is 614.4 MHz (24.576 MHz*25).
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8.3.3.3 Biphase-Mark Code (BMC)
In the OWA format, the digital signal is coded using the biphase-mark code (BMC). The clock, frame, and data
are embedded in only one signal—the data pin. In the BMC system, each data bit is encoded into two logical
states (00, 01, 10, or 11) at the pin. The following figure and table show how data is encoded to the BMC format.
The frequency of the clock is twice the data bit rate, as shown in the following figure. Also, the clock is always
programmed to 128 x fs, where fs is the sample rate. The device receiving in the OWA format can recover the
clock and frame information from the BMC signal.
Figure 8-15 OWA Biphase-Mark Code
Clock
128 × FS
Data
1 0 1 1 0 0 1 0 1 1 0
BMC
1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1
Table 8-11 Biphase-Mark Encoder
Data Previous State BMC
0 0 11
0 1 00
1 0 10
1 1 01
8.3.3.4 IEC60958 Transmit Format
The OWA supports digital audio data transfer and receive. It also supports full-duplex synchronous work mode.
The software can set the work mode by the OWA Control Register.
Every audio sample transmitted in a sub-frame consists of 32-bit, numbered from 0 to 31. The following figure
shows a sub-frame.
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Figure 8-16 OWA Sub-Frame Format
0 3 4 7 8 27 28 31
L M
Sync
Aux S Audio sample word S V U C P
preamble
B B
Validity flag
User data
Channel status
Parity bit
Bits 0-3 carry one of the four permitted preambles to signify the type of audio sample in the current sub-frame.
The preamble is not encoded in BMC format, and therefore the preamble code can contain more than two
consecutive 0 or 1 logical states in a row.
Bits 4-27 carry the audio sample word in linear 2s-complement representation. The most-significant bit (MSB)
is carried by bit 27. When a 24-bit coding range is used, the least-significant bit (LSB) is in bit 4. When a 20-bit
coding range is used, bit[8:27] carry the audio sample word with the LSB in bit 8. Bit[4:7] may be used for other
applications and are designated auxiliary sample bits.
If the source provides fewer bits than the interface allows (either 20 or 24), the unused LSBs are set to logical
0. For a nonlinear PCM audio application or a data application, the main data field may carry any other
information.
Bit 28 carries the validity bit (V) associated with the main data field in the sub-frame.
Bit 29 carries the user data channel (U) associated with the main data field in the sub-frame.
Bit 30 carries the channel status information (C) associated with the main data field in the sub-frame. The
channel status indicates if the data in the sub-frame is a digital audio or some other type of data.
Bit 31 carries a parity bit (P) such that bit 4-31 carry an even number of 1s and an even number of 0s (even
parity). As shown in the following table, the preambles (bit 0-3) are also defined with even parity.
Table 8-12 Preamble Codes
Preamble Code Previous Logical State Logical State Description
B (or Z) 0 1110 1000 Start of a block and sub-frame 1
M (or X) 0 1110 0010 Sub-frame 1
W (or Y) 0 1110 0100 Sub-frame 2
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Figure 8-17 OWA Frame/Block Format
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 Channel 2 M Channel 1 W Channel 2
Sub-frame Sub-frame
Frame 191 Frame 0 Frame 191
Block
8.3.3.5 IEC61937 Transmit Format
IEC 61937 applies to the digital audio interface by using the IEC 60958 series for the conveying of non-linear
PCM encoded audio bitstreams. The non-linear PCM encoded audio bitstream is transferred by using the basic
16-bit data area of the IEC 60958 subframes, i.e. in time-slots 12 to 27. Because the non-linear PCM encoded
audio bitstream to be transported is at a lower data rate than that supported by the IEC 60958 interface, the
audio bitstream is broken into a sequence of discrete data-bursts, and stuffing between the data-bursts is
necessary .
IEC 60958 Data Burst
The method of placing the data into the IEC 60958 bitstream is to format the data to be transmitted into data-
bursts and to send each data-burst in a continuous sequence of IEC 60958 frames.
Table 8-13 Bit Allocation of Data-Burst in IEC 60958 Subframes
Data Burst Format
Each data-burst contains a burst-preamble consisting of four 16-bit words (Pa, Pb, Pc and Pd) followed by the
burst-payload which contains data of an encoded audio frame.
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Figure 8-18 Data-Burst Format
(1) Burst-preamble
The burst-preamble consists of four mandatory fields. Pa and Pb represent a synchronization word. Pc gives
information about the type of data, and some information/control for the receiver. Pd gives the length of the
burst-payload, and is limited to 65535 bits in the case of Pd represent bits length, or is limited to 65535 bytes
in the case of Pd represent bytes length.
Figure 8-19 Data-burst Preamble
The four preamble words are contained in two sequential IEC 60958 frames. The frame beginning the data-
burst contains preamble word Pa in subframe 1, and Pb in subframe 2. The next frame contains Pc in subframe
1 and Pd in subframe 2. When placed into an IEC 60958 subframe, the MSB of a 16-bit burst-preamble word is
placed into time-slot 27 and the LSB is placed into time-slot 12.
Figure 8-20 Data-burst Preamble words
(2) Burst-information
The 16-bit burst-information contains information about the data which will be found in the data-burst.
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Figure 8-21 Fields of Burst-information
The 7-bit data-type is defined in bits 0-6 of the burst-preamble Pc, the bit 6 is the MSB. This data-type field
indicates the format of the burst-payload, which will be conveyed in the data-burst. Typical properties of a
data-type are the reference point and repetition period of the burst, which is the number of sampling periods
of the audio between the reference point of the current data-burst and the reference point of the next data-
burst. The reference point is inherently defined for each data-type.
The error-flag bit is available to indicate if the contents of the data-burst contain data errors.If a data-burst is
thought to be error-free, or if the data source does not know if the data contains errors, then the value of this
bit is set to a ‘0’. If the data source does know that a particular data-burst contains some errors this bit may be
set to a ’1’. The usage of this bit by receiver is optional.
The meaning of the 5-bit data-type-dependent info depends on the value of the data-type.
The 3-bit bitstream-number indicates to which bitstream the data-burst belongs. Eight codes (0-7) are available
so that up to eight independent bitstreams may be multiplexed in one bitstream in a time multiplex. Each
independent bitstream shall use a unique bit-streamnumber.
(3) Length-code
The length-code indicates the number of bits or bytes according to data-type within the databurst, from 0 to
65535. The size of the Pa, Pb, Pc and Pd is not counted in the value of the length-code. In other words, the
length-code indicates the number of bits of the burst-payload in bits, plus the conditional length of Pe and Pf,
or the number of bytes of the burst-payload in bytes, plus the conditional length of Pe and Pf if exists.
Figure 8-22 Length of the Burst-Payload Specified by Pd
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8.3.3.6 Audio Sample Ratio Detection
The sampling rate is calculated according to the data pulse back-stepping method. In the first phase lock of the
CDR, find 1 Frame period, count by using the high-speed sampling clock, and read the counting value of the
pulse, then the sampling rate can be calculated.
Table 8-14 The Corresponding Relation between Different System Clock and Sample Ratio
Sample Clock Cycles
TX Sample Rate (kHz) 196.608 MHz-SysClk 200 MHz-SysClk
22.05 8916(±5) 9070(±5)
24 8192(±5) 8333(±5)
32 6144(±5) 6250(±5)
44.1 4458(±5) 4535(±5)
48 4096(±5) 4166(±5)
96 2048(±5) 2083(±5)
176.4 1114(±5) 1133(±5)
192 1024(±5) 1041(±5)
8.3.3.7 Operation Modes
The software operation of the OWA is divided into five steps: system setup, OWA initialization, channel setup,
DMA setup and enable/disable module. The following sections describe these five steps.
Figure 8-23 OWA Operation Flow
OWA System Setup OWA Initialization
System Setup
Pin Multiplex
Globe/TX/RX Disable
OWA Initialization
PLL_AUDIO Frequence and Enable
Channel Setup
Clear TXFIFO/RXFIFO
CLK Reset and Gating
DMA Setup
Enable/Disable Module Bus Reset and Gating Clear TXFIFO/RXFIFO Counter
1. System Setup and OWA Initialization
The first step in the OWA initialization is properly programming the GPIO because the OWA port is a multiplex
pin. You can find the function in section 9.7 “GPIO”.
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The clock source for the OWA should be followed. Firstly, reset the audio PLL in PLL_AUDIOx Control Register.
Secondly, set up the frequency of the Audio PLL in the PLL_AUDIOx Control Register. After that, enable the
OWA gating. Lastly, enable the OWA bus gating.
After the system setup, the register of OWA can be set up. Firstly, reset the OWA by writing 1 to OWA_CTL[0]
and clear the TX/RX FIFO by writing 1 to OWA_FCTL[17:16]. After that, enable the globe enable bit by writing
1 to OWA_CTL[1] and clear the interrupt and TX/RX counter by setting OWA_ISTA and
OWA_TX_CNT/OWA_RX_CNT.
2. Channel Setup and DMA Setup
You can set up the audio type, clock divider ratio, the sample format, and the trigger level, and so on. The setup
of the register can be found in the specification.
The OWA supports two methods to transfer the data. The most common way is DMA, the configuration of
DMA can be found in section 3.9 “DMAC”. In this module, you just enable the DRQ in OWA_INT[7].
3. Enable and Disable OWA
To enable the function, you can enable TX/RX by writing OWA_TX_CFIG[31]/OWA_RX_CFIG[0]. After that,
enable OWA by writing 1 to OWA_CTL[1]. Writing 0 to OWA_CTL[1] to disable process.
8.3.4 Register List
Module Name Base Address
OWA 0x02036000
Register Name Offset Description
OWA_GEN_CTL 0x0000 OWA General Control Register
OWA_TX_CFIG 0x0004 OWA TX Configuration Register
OWA_RX_CFIG 0x0008 OWA RX Configuration Register
OWA_ISTA 0x000C OWA Interrupt Status Register
OWA_RXFIFO 0x0010 OWA RXFIFO Register
OWA_FCTL 0x0014 OWA FIFO Control Register
OWA_FSTA 0x0018 OWA FIFO Status Register
OWA_INT 0x001C OWA Interrupt Control Register
OWA_TX_FIFO 0x0020 OWA TX FIFO Register
OWA_TX_CNT 0x0024 OWA TX Counter Register
OWA_RX_CNT 0x0028 OWA RX Counter Register
OWA_TX_CHSTA0 0x002C OWA TX Channel Status Register0
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Register Name Offset Description
OWA_TX_CHSTA1 0x0030 OWA TX Channel Status Register1
OWA_RXCHSTA0 0x0034 OWA RX Channel Status Register0
OWA_RXCHSTA1 0x0038 OWA RX Channel Status Register1
OWA_EXP_CTL 0x0040 OWA Expand Control Register
OWA_EXP_ISTA 0x0044 OWA Expand Interrupt Status Register
OWA_EXP_INFO_0 0x0048 OWA Expand Infomation Register0
OWA_EXP_INFO_1 0x004C OWA Expand Infomation Register1
OWA_EXP_DBG_0 0x0050 OWA Expand Debug Register0
OWA_EXP_DBG_1 0x0054 OWA Expand Debug Register1
8.3.5 Register Description
8.3.5.1 0x0000 OWA General Control Register (Default Value: 0x0000_0080)
Offset: 0x0000 Register Name: OWA_CTL
Bit Read/Write Default/Hex Description
31:13 / / /
RST_RX
Reset RX
12 R/WAC 0x0 0: Normal
1: Reset
Self clear to ‘0’.
11:8 / / /
7 R 0x1 Reserved
6:3 / / /
LOOP
Loopback Test
2 R/W 0x0 0: Normal Mode
1: Loopback Test
When the bit is set to ‘1’, the DOUT and DIN need be connected.
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Offset: 0x0000 Register Name: OWA_CTL
Bit Read/Write Default/Hex Description
GEN
Global Enable
Disabling this bit overrides the operations of enabling and
1 R/W 0x0
flushing all FIFOs by any other blocks or channels.
0: Disabled
1: Enabled
RST_TX
Reset TX
0 R/W 0x0 0: Normal
1: Reset
Self clear to 0.
8.3.5.2 0x0004 OWA TX Configure Register (Default Value: 0x0000_00F0)
Offset: 0x0004 Register Name: OWA_TX_CFIG
Bit Read/Write Default/Hex Description
TX_SINGLE_MODE
Tx Single Channel Mode
31 R/W 0x0
0: Disabled
1: Enabled
30:18 / / /
ASS
Audio Sample Select when TX FIFO Underrun
17 R/W 0x0 0: Sending 0
1: Sending the last audio
Note: This bit is only valid in PCM mode.
TX_AUDIO
TX Data Type
16 R/W 0x0
0: Linear PCM (Valid bit of both sub-frame set to 0 )
1: Non-audio (Valid bit of both sub-frame set to 1)
15:9 / / /
TX_RATIO
TX Clock Divide Ratio
8:4 R/W 0xF
Clock divide ratio = TX_TATIO + 1
Fs = PLL_AUDIO/[(TX_TATIO + 1)*64*2]
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Offset: 0x0004 Register Name: OWA_TX_CFIG
Bit Read/Write Default/Hex Description
TX_SF
TX Sample Format
00: 16 bits
3:2 R/W 0x0
01: 20 bits
10: 24 bits
11: Reserved
TX_CHM
CHSTMODE
1 R/W 0x0
0: Channel status A and B set to 0
1: Channel status A and B generated from TX_CHSTA
TXEN
TX Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.3.5.3 0x0008 OWA RX Configure Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: OWA_RX_CFIG
Bit Read/Write Default/Hex Description
31:5 / / /
RX_LOCK_FLAG
RX Lock Flag
4 R 0x0
0: Unlocked
1: Locked
RX_CHST_SRC
RX Channel State Source Select
3 R/W 0x0
0: RX_CH_STA register holds status from Channel A
1: RX_CH_STA register holds status from Channel B
2 / / /
CHST_CP
Channel Status Capture
0: Idle or Capture End
1 R/W 0x0 1: Capture Channel Status Start
The field must be set to 1 at each operation (such as recording).
When set to ‘1’, the system starts to capture the channel
status. When finished, the bit will automatically turn to ‘0’.
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Offset: 0x0008 Register Name: OWA_RX_CFIG
Bit Read/Write Default/Hex Description
RXEN
0 R/W 0x0 0: Disabled
1: Enabled
8.3.5.4 0x000C OWA Interrupt Status Register (Default Value: 0x0000_0010)
Offset: 0x000C Register Name: OWA_ISTA
Bit Read/Write Default/Hex Description
31:19 / / /
RX_LOCK_INT
RX Lock Interrupt
0: No Pending IRQ
18 R/W1C 0x0
1: RX Lock Pending Interrupt (RX_LOCK_FLAG turns from 0 to
1)
Write ‘1’ to clear this interrupt.
RX_UNLOCK_INT
RX Unlock Pending Interrupt
0: No Pending IRQ
17 R/W1C 0x0
1: RX Unlock Pending Interrupt (RX_LOCK_FLAG turns from 0
to 1)
Write 1 to clear this interrupt.
RX_PARERRI_INT
RX Parity Error Pending Interrupt
16 R/W1C 0x0 0: No Pending IRQ
1: RX Parity Error Pending Interrupt
Write “1” to clear this interrupt.
15:7 / / /
TXU_INT
TX FIFO Underrun Pending Interrupt
6 R/W1C 0x0 0: No Pending IRQ
1: FIFO Underrun Pending Interrupt
Writing “1” to clear this interrupt.
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Offset: 0x000C Register Name: OWA_ISTA
Bit Read/Write Default/Hex Description
TXO_INT
TX FIFO Overrun Pending Interrupt
5 R/W1C 0x0 0: No Pending IRQ
1: FIFO Overrun Pending Interrupt
Writing “1” to clear this interrupt.
TXE_INT
TX FIFO Empty Pending Interrupt
0: No Pending IRQ
4 R/W1C 0x1
1: FIFO Empty Pending Interrupt
Writing “1” to clear this interrupt or automatically clear if the
interrupt condition fails.
3:2 / / /
RXO_INT
RXFIFO Overrun Pending Interrupt
1 R/W1C 0x0
0: RXFIFO Overrun Pending
Write ‘1’ to clear this interrupt.
RXA_INT
RXFIFO Available Pending Interrupt
0: No Pending IRQ
0 R/W1C 0x0
1: Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
8.3.5.5 0x0010 OWA RXFIFO Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: OWA_RXFIFO
Bit Read/Write Default/Hex Description
RX_DATA
31:0 R 0x0 The host can get one sample by reading this register, A channel
data is first, and then the B channel data.
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8.3.5.6 0x0014 OWA FIFO Control Register (Default Value: 0x0004_0200)
Offset: 0x0014 Register Name: OWA_FCTL
Bit Read/Write Default/Hex Description
HUB_EN
Audio Hub Enable
The bit takes effect only when the TXEN is set to 1.
31 R/W 0x0
Audio codec/I2S1/I2S2/OWA TXFIFO Hub Enable.
0: Disabled
1: Enabled
FTX
30 R/W1C 0x0
Write ‘1’ to flush TXFIFO, self clear to ‘0’.
FRX
29 R/W1C 0x0
Write ‘1’ to flush RXFIFO, self clear to ‘0’.
28:22 / / /
RX_SYNC_EN_START
The bit takes effect only when the RX_SYNC_EN is set to 1.
Audio Codec/I2S1/I2S2/DMIC/OWA RX Synchronize Enable
21 R/W 0x0
Start.
0: Disabled
1: Enabled
RX_SYNC_EN
OWA RX Synchronize Enable
20 R/W 0x0
0: Disabled
1: Enabled
TXTL
TX FIFO Empty Trigger Level
19:12 R/W 0x40 Interrupt and DMA request trigger level for TX FIFO normal
condition.
Trigger Level = TXTL
11 / / /
RXTL
RX FIFO Trigger Level
10:4 R/W 0x20 Interrupt and DMA request trigger level for RX FIFO normal
condition.
Trigger Level = RXTL + 1
3 / / /
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Offset: 0x0014 Register Name: OWA_FCTL
Bit Read/Write Default/Hex Description
TXIM
TXFIFO Input Mode (Mode0, 1)
0: Valid data at the MSB of TXFIFO Register
2 R/W 0x0 1: Valid data at the LSB of TXFIFO Register
Example for 20-bit transmitted audio sample:
Mode 0: TXFIFO[23:0] = {APB_WDATA[31:12], 4’h0}
Mode 1: TXFIFO[23:0] = {APB_WDATA[19:0], 4’h0}
RXOM
RXFIFO Output Mode(Mode 0,1,2,3)
00: Expanding ‘0’ at LSB of RXFIFO Register
01: Expanding received sample sign bit at MSB of RXFIFO
Register
10: Truncating received samples at high half-word of RXFIFO
Register and low half-word of RXFIFO Register is filled by ‘0’
1:0 R/W 0x0
11: Truncating received samples at low half-word of RXFIFO
Register and high half-word of RXFIFO Register is expanded by
its sigh bit
Mode 0: APB_RDATA[31:0] = {RXFIFO[23:0], 8’h0}
Mode 1: APB_RDATA[31:0] = {8’RXFIFO[23], RXFIFO[23:0]}
Mode 2: APB_RDATA[31:0] = {RXFIFO[23:8], 16’h0}
Mode 3: APB_RDATA[31:0] = {16’RXFIFO[23], RXFIFO[23:8]}
8.3.5.7 0x0018 OWA FIFO Status Register (Default Value: 0x8080_0000)
Offset: 0x0018 Register Name: OWA_FSTA
Bit Read/Write Default/Hex Description
TXE
TXFIFO Empty (indicate the TXFIFO is not full)
31 R 0x1
0: No room for new sample in TXFIFO
1: More than one room for new sample in TXFIFO ( >= 1 Word )
30:24 / / /
TXE_CNT
23:16 R 0x80
TXFIFO Empty Space Word Counter
RXA
RXFIFO Available
15 R 0x0
0: No available data in RXFIFO
1: More than one sample in RXFIFO ( >= 1 Word )
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Offset: 0x0018 Register Name: OWA_FSTA
Bit Read/Write Default/Hex Description
14:7 / / /
RXA_CNT
6:0 R 0x0
RXFIFO Available Sample Word Counter
8.3.5.8 0x001C OWA Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: OWA_INT
Bit Read/Write Default/Hex Description
31:19 / / /
RX_LOCKI_EN
RX LOCK Interrupt Enable
18 R/W 0x0
0: Disabled
1: Enabled
RX_UNLOCKI_EN
RX UNLOCK Interrupt Enable
17 R/W 0x0
0: Disabled
1: Enabled
RX_PARERRI_EN
RX PARITY ERORR Interrupt Enable
16 R/W 0x0
0: Disabled
1: Enabled
15:8 / / /
TX_DRQ
TXFIFO Empty DRQ Enable
7 R/W 0x0
0: Disabled
1: Enabled
TXUI_EN
TXFIFO Underrun Interrupt Enable
6 R/W 0x0
0: Disabled
1: Enabled
TXOI_EN
TXFIFO Overrun Interrupt Enable
5 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x001C Register Name: OWA_INT
Bit Read/Write Default/Hex Description
TXEI_EN
TXFIFO Empty Interrupt Enable
4 R/W 0x0
0: Disabled
1: Enabled
3 / / /
RX_DRQ
RXFIFO Data Available DRQ Enable
When set to ‘1’, RXFIFO DMA Request is asserted if data is
2 R/W 0x0
available in RXFIFO.
0: Disabled
1: Enabled
RXOI_EN
RXFIFO Overrun Interrupt Enable
1 R/W 0x0
0: Disabled
1: Enabled
RXAI_EN
RXFIFO Data Available Interrupt Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.3.5.9 0x0020 OWA TX FIFO Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: OWA_TXFIFO
Bit Read/Write Default/Hex Description
TX_DATA
31:0 W 0x0 Transmitting A, B channel data should be written this register
one by one. A channel data is first, and then the B channel data.
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8.3.5.10 0x0024 OWA TX Counter Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: OWA_TX_CNT
Bit Read/Write Default/Hex Description
TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO.
31:0 R/W 0x0 When one sample is put into TXFIFO by DMA or by host IO, the
TX sample counter register increases by one. The TX sample
counter register can be set to any initial value at any time. After
updated by the initial value, the counter register should count
on the base of this initial value.
8.3.5.11 0x0028 OWA RX Counter Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: OWA_RX_CNT
Bit Read/Write Default/Hex Description
RX_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO.
31:0 R/W 0x0 When one sample is written by Codec, the RX sample counter
register increases by one. The RX counter register can be set to
any initial value at any time. After being updated by the initial
value, the counter register should count on the base of this
value.
8.3.5.12 0x002C OWA TX Channel Status Register0 (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: OWA_TX_CHSTA0
Bit Read/Write Default/Hex Description
31: 30 / / /
CA
Clock Accuracy
00: Level 2
29:28 R/W 0x0
01: Level 1
10: Level 3
11: Not matched
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Offset: 0x002C Register Name: OWA_TX_CHSTA0
Bit Read/Write Default/Hex Description
FREQ
Sampling Frequency
0000: 44.1 kHz
0001: Not indicated
0010: 48 kHz
0011: 32 kHz
0100: 22.05 kHz
0101: Reserved
0110: 24 kHz
27:24 R/W 0x0
0111: Reserved
1000: Reserved
1001: 768 kHz
1010: 96 kHz
1011: Reserved
1100: 176.4 kHz
1101: Reserved
1110: 192 kHz
1111: Reserved
CN
23:20 R/W 0x0
Channel Number
SN
19:16 R/W 0x0
Source Number
CC
Category Code
15:8 R/W 0x0
Indicates the kind of equipment that generates the digital audio
interface signal.
MODE
Mode
7:6 R/W 0x0
00: Default Mode
01 to 11: Reserved
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Offset: 0x002C Register Name: OWA_TX_CHSTA0
Bit Read/Write Default/Hex Description
EMP
Emphasis
Additional format information
For bit 1 = “0”, Linear PCM audio mode:
000: 2 audio channels without pre-emphasis
001: 2 audio channels with 50 μs/15 μs pre-emphasis
5:3 R/W 0x0
010: Reserved (for 2 audio channels with pre-emphasis)
011: Reserved (for 2 audio channels with pre-emphasis)
100 to 111: Reserved
For bit 1 = “1”, other than Linear PCM applications:
000: Default state
001 to 111: Reserved
CP
Copyright
2 R/W 0x0
0: Copyright is asserted
1: No copyright is asserted
TYPE
Audio Data Type
1 R/W 0x0
0: Linear PCM samples
1: Non-linear PCM audio
PRO
Application Type
0 R/W 0x0 0: Consumer application
1: Professional application
This bit must be fixed to “0”.
8.3.5.13 0x0030 OWA TX Channel Status Register1 (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: OWA_TX_CHSTA1
Bit Read/Write Default/Hex Description
31:10 / / /
CGMS_A
00: Copying is permitted without restriction
9:8 R/W 0x0 01: One generation of copies may be made
10: Condition not be used
11: No copying is permitted
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Offset: 0x0030 Register Name: OWA_TX_CHSTA1
Bit Read/Write Default/Hex Description
ORIG_FREQ
Original Sampling Frequency
0000: Not indicated
0001: 192 kHz
0010: 12 kHz
0011: 176.4 kHz
0100: Reserved
0101: 96 kHz
0110: 8 kHz
7:4 R/W 0x0
0111: 88.2 kHz
1000: 16 kHz
1001: 24 kHz
1010: 11.025 kHz
1011: 22.05 kHz
1100: 32 kHz
1101: 48 kHz
1110: Reserved
1111: 44.1 kHz
WL
Sample Word Length
For bit 0 = “0”:
000: Not indicated
001: 16 bits
010: 18 bits
100: 19 bits
101: 20 bits
110: 17 bits
3:1 R/W 0x0
111: Reserved
For bit 0 = “1”:
000: Not indicated
001: 20 bits
010: 22 bits
100: 23 bits
101: 24 bits
110: 21 bits
111: Reserved
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Offset: 0x0030 Register Name: OWA_TX_CHSTA1
Bit Read/Write Default/Hex Description
MWL
Max Word Length
0 R/W 0x0
0: Maximum audio sample word length is 20 bits
1: Maximum audio sample word length is 24 bits
8.3.5.14 0x0034 OWA RX Channel Status Register0 (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: OWA_RX_CHSTA0
Bit Read/Write Default/Hex Description
31:30 / / /
CA
Clock Accuracy
00: Level 2
29:28 R/W 0x0
01: Level 1
10: Level 3
11: Not Matched
FREQ
Sampling Frequency
0000: 44.1 kHz
0001: Not Indicated
0010: 48 kHz
0011: 32 kHz
0100: 22.05 kHz
0101: Reserved
0110: 24 kHz
27:24 R/W 0x0
0111: Reserved
1000: Reserved
1001: 768 kHz
1010: 96 kHz
1011: Reserved
1100: 176.4 kHz
1101: Reserved
1110: 192 kHz
1111: Reserved
CN
23:20 R/W 0x0
Channel Number
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Offset: 0x0034 Register Name: OWA_RX_CHSTA0
Bit Read/Write Default/Hex Description
SN
19:16 R/W 0x0
Source Number
CC
Category Code
15:8 R/W 0x0
Indicates the Kind of Equipment that Generates the digital audio
interface Signal.
MODE
Mode
7:6 R/W 0x0
00: Default mode
01 to 11: Reserved
EMP
Emphasis
Additional Format Information
For bit 1 = ‘0’, Linear PCM Audio mode:
000: 2 Audio channels without pre-emphasis
001: 2 Audio channels with 50 μs/15 μs pre-emphasis
5:3 R/W 0x0
010: Reserved (For 2 Audio channels with pre-emphasis)
011: Reserved (For 2 Audio channels with pre-emphasis)
100 to 111: Reserved
For bit 1 = ‘1’, Other than Linear PCM applications:
000: Default state
001 to 111: Reserved
CP
Copyright
2 R/W 0x0
0: Copyright is asserted
1: No Copyright is asserted
TYPE
Audio Data Type
1 R/W 0x0
0: Linear PCM samples
1: Non-linear PCM audio
PRO
Application Type
0 R/W 0x0
0: Consumer application
1: Professional application
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8.3.5.15 0x0038 OWA RX Channel Status Register1 (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: OWA_RX_CHSTA1
Bit Read/Write Default/Hex Description
31:10 / / /
CGMS_A
00: Copying is permitted without restriction
9:8 R/W 0x0 01: One generation of copies may be made
10: Condition is not be used
11: No copying is permitted
ORIG_FREQ
Original Sampling Frequency
0000: Not indicated
0001: 192 kHz
0010: 12 kHz
0011: 176.4 kHz
0100: Reserved
0101: 96 kHz
0110: 8 kHz
7:4 R/W 0x0
0111: 88.2 kHz
1000: 16 kHz
1001: 24 kHz
1010: 11.025 kHz
1011: 22.05 kHz
1100: 32 kHz
1101: 48 kHz
1110: Reserved
1111: 44.1 kHz
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Offset: 0x0038 Register Name: OWA_RX_CHSTA1
Bit Read/Write Default/Hex Description
WL
Sample Word Length
For bit 0 = ‘0’:
000: Not indicated
001: 16 bits
010: 18 bits
100: 19 bits
101: 20 bits
110: 17 bits
3:1 R/W 0x0
111: Reserved
For bit 0 = ‘1’:
000: Not indicated
001: 20 bits
010: 22 bits
100: 23 bits
101: 24 bits
110: 21 bits
111: Reserved
MWL
Max Word Length
0 R/W 0x0
0: Maximum Audio sample word length is 20 bits
1: Maximum Audio sample word length is 24 bits
8.3.5.16 0x0040 OWA Expand Control Register (Default Value: 0x0000_000F)
Offset: 0x0040 Register Name: OWA_EXP_CTL
Bit Read/Write Default/Hex Description
31 / / /
BURST_DATAOUT_SELECT
Burst data output select
30 R/W 0x0
0: Burst preamble and payload
1: Burst payload
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Offset: 0x0040 Register Name: OWA_EXP_CTL
Bit Read/Write Default/Hex Description
REPEAT_PERIOD_OF_FR_NUM
The number for the repetition period of the burst frame
29:16 R/W 0x0 Configure this field according to RX data.
A mismatch between the configuration data and the received data
will result in an error interrupt.
UNIT_SELECT
Unit Select
15 R/W 0x0 Configure this field according to RX data type
0: In units of 16-bit
1: In units of 2-byte
OWA_RX_MODE_MAN
OWA RX Proteocol Select
14 R/W 0x0
0: IEC60958
1: IEC61937
OWA_RX_MODE
OWA RX Mode Select
13 R/W 0x0 0: Manual Ctrl. Configure by OWA_RX_MODE_MAN
1: Auto Ctrl. Configure by the channel status values resolved by
hardware
AUDIO_DATA_BITORDER_EN
Audio data bitorder enable
12 R/W 0x0 0: The audio data received by RX is stored directly into FIFO
1: The audio data received by RX is reversed high and low bits, then
stored into FIFO
DATA_LENGTH_BITORDER_EN
Data length bitorder enable
11 R/W 0x0 0: The received PD data is as the length of the valid audio data
1: The received PD data is reversed high and low bits, then as the
length of the valid audio data
DATA_TYPE_BITORDER_EN
Data type bitorder enable
10 R/W 0x0 0: The received PC data is as the data length of the valid audio
1: The received PC data is reversed high and low bits, then as the
length of the valid audio data
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Offset: 0x0040 Register Name: OWA_EXP_CTL
Bit Read/Write Default/Hex Description
SYNCW_BITORDER_EN
Syncw_bitorder_en
9 R/W 0x0
0: Pa/Pb is the sync code of audio data
1: Pa/Pb reversed high and low bits is the sync code of audio data
INSERT_DETECTION_ENABLE
Insert detection enable
8 R/W 0x0
0: Disable
1: Enable
INSERT_DETECTION_NUM
Insert detection number
7:0 R/W 0x0F
Configure how many jumping edges are detected to generate an
insertion interrupt
8.3.5.17 0x0044 OWA Expand Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: OWA_EXP_ISTA
Bit Read/Write Default/Hex Description
31:25 / / /
PD_CHANGE_INT_EN
PD_LENGTH_CHANGE Interrupt Enable
24 R/W 0x0
0: Disable
1: Enable
PC_PAUSE_STOP_INT
PC_PAUSE_BURSTS_STOP Interrupt Enable
23 R/W 0x0
0: Disable
1: Enable
PC_BITSTRM_CHANGE_INT_EN
PC_BITSTREAM_CHANGE Interrupt Enable
22 R/W 0x0
0: Disable
1: Enable
PC_ERR_FLAG_INT
PC_ERROR_FLAG Interrupt Enable
21 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0044 Register Name: OWA_EXP_ISTA
Bit Read/Write Default/Hex Description
PC_DTYPE_CHANGE_INT_EN
PC_DATATYPE_CHANGE Interrupt Enable
20 R/W 0x0
0: Disable
1: Enable
RPDB_ERR_INT_EN
RPDB_ERROR Interrupt Enable
19 R/W 0x0
0: Disable
1: Enable
PCPD_CAP_INT_EN
PCPD_CAP Interrupt Enable
18 R/W 0x0
0: Disable
1: Enable
PAPB_CAP_INT_EN
PAPB_CAP Interrupt Enable
17 R/W 0x0
0: Disable
1: Enable
INSERT_INT_EN
INSERT Interrupt Enable
16 R/W 0x0
0: Disable
1: Enable
15:9 / / /
PD_CHANGE_INT
PD CHANGE INT
0: No Pending IRQ
8 R/W1C 0x0
1: PD Data length information is change.
(except Pause/Null data burst type)
Write ‘1’ to clear this interrupt.
PC_PAUSE_STOP_INT
Audio bitstream is interrupted. When stopped, the interface
becomes idle.
0: No Pending IRQ
7 R/W1C 0x0
1: PC Pause burst Stop, frame sequence discontinued. Transmitters
may optionally use the STOP value to indicate that the transmission
of the current encoded
Write ‘1’ to clear this interrupt.
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Offset: 0x0044 Register Name: OWA_EXP_ISTA
Bit Read/Write Default/Hex Description
PC_BITSTRM_CHANGE_INT
PC BITSTRM CHANGE INT
0: No Pending IRQ
6 R/W1C 0x0 1: PC Bitstream Number is change. Bitstream Number indicates
which bitstream the data burst belongs. (except Pause/Null data
bursts type )
Write ‘1’ to clear this interrupt.
PC_ERR_FLAG_INT
PC ERR FLAG INT
0: No Pending IRQ
5 R/W1C 0x0 1: PC Error-flag is available to indicate if the contents of the data-
burst contain data errors (except Pause/Null data bursts type) . The
using of this bit by receivers is optional.
Write ‘1’ to clear this interrupt.
PC_DTYPE_CHANGE_INT
PC DTYPE CHANGE INT
4 R/W1C 0x0 0: No Pending IRQ
1: PC Datatype (except Pause/Null data type) information is change
Write ‘1’ to clear this interrupt.
RPDB_ERR_INT
RPDB ERR INT
0: No Pending IRQ
3 R/W1C 0x0
1: Hardware counts the repetition period of the burst frame is
different from register configuration number
Write ‘1’ to clear this interrupt.
PCPD_CAP_INT
PCPD CAP INT
2 R/W1C 0x0 0: No Pending IRQ
1: IEC61937 mode captures PC and PD
Write ‘1’ to clear this interrupt.
PAPB_CAP_INT
PAPB CAP INT
1 R/W1C 0x0 0: No Pending IRQ
1: IEC61937 mode captures PA and PB
Write ‘1’ to clear this interrupt.
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Offset: 0x0044 Register Name: OWA_EXP_ISTA
Bit Read/Write Default/Hex Description
INSERT_INT
INSERT INT
0 R/W1C 0x0 0: No Pending IRQ
1: OWA RX detects device insertion
Write ‘1’ to clear this interrupt.
8.3.5.18 0x0048 OWA Expand Information Register 0 (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: OWA_EXP_INFO_0
Bit Read/Write Default/Hex Description
PC_DATA
31:16 R 0x0
PC Data information
PD_DATA
15:0 R 0x0
PD Data information
8.3.5.19 0x004C OWA Expand Information Register 1 (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: OWA_EXP_INFO_1
Bit Read/Write Default/Hex Description
31:30 / / /
REPET_PERIOD_OF_FR_VALUE
Repetition period of the burst frame value
29:16 R 0x0
Check whether the repetition period of the burst frame calculated
by hardware is consistent with the configuration value.
SR_VALUE
15:0 R 0x0 Sample Rate Value
Read this value after RX_LOCK.
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8.3.5.20 0x0050 OWA Expand Debug Register 0 (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: OWA_EXP_DBG_0
Bit Read/Write Default/Hex Description
31:19 / / /
IEC61937_DATA_CAP_FSM
IEC61937 Data Captures State Machine
000: IDLE
001: SYNC_PA
18:16 R 0x0
010: SYNC_PB
011: DTYPE_PC
100: DLEN_PD
101: RX_ACTIVE
DATA_CAP_NUM
15:0 R 0x0 Remains Data Counter Value
See the value of the sampled valid data in real time.
8.3.5.21 0x0054 OWA Expand Debug Register 1 (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: OWA_EXP_DBG_1
Bit Read/Write Default/Hex Description
31:30 / / /
REPET_PERIOD_OF_FR_CNT
29:16 R 0x0 Repetition period of the burst frame counter
See the value of repetition period counter in real time.
SR_CNT
15:0 R 0x0 Sample Rate Counter
See the value of audio sample ratio in real time.
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8.4 Audio Codec
8.4.1 Overview
The Audio Codec is high-performance audio encoder and decoder module which supports DAC/ADC, dynamic
range controller (DRC) and dynamic voltage controller (DVC) functions.
The Audio Codec has the following features:
Two audio digital-to-analog converter (DAC) channels
- Supports the DAC sample rate from 8 kHz to 192 kHz
- 100 ± 2 dB SNR@A-weight, -85 ± 3 dB THD + N
- Supports 16-bit and 20-bit audio sample resolution
One audio output
- One stereo headphone output: HPOUTL/R
There audio analog-to-digital converter (ADC) channels
- Supports the ADC sample rate from 8 kHz to 48 kHz
- 95 ± 3 dB SNR@A-weight, -80 ± 3 dB THD + N
- Supports 16-bit and 20-bit audio sample resolution
Three audio inputs
- One differential microphone input: MICIN3P/3N, or one single-end microphone input: MICIN3P
- One stereo LINEIN input: LINEINL/R
- One stereo FMIN input: FMINL/R
Supports Dynamic Range Controller (DRC) adjusting the ADC recording and DAC playback
One 128x20-bit FIFO for DAC data transmit, one 128x20-bit FIFO for ADC data receive
Programmable FIFO thresholds
Supports interrupts and DMA
Internal HPLDO output for HPVCC
Internal ALDO output for AVCC
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8.4.2 Block Diagram
The following figure shows the block diagram of Audio Codec.
Figure 8-24 Audio Codec Block Diagram
AVCC HPVCC VDD_SYS
0.9 V Reference
VRA1
0.9 V Voltage
VRA2 APB BUS
AGND
1.8 V
AVCC
HP_DET HP_DET
Register
MIC_DET MIC_DET
RXFIFO TXFIFO
1.8 V
HPVCC
FMINL
Mixer ADC1
LINEINL
DACL HPOUTL
ADC DAC
Volume Volume HPOUTR
FMINR DAP Headphone HPOUTFB
Mixer ADC2 High High
LINEINR
Filter Filter DACR
MICIN3P
PGA ADC3
MICIN3N
8.4.3 Functional Description
8.4.3.1 External Signals
Table 8-15 Audio Codec External Signals
Signal Type Description
MICIN3P AI Positive Differential Input for MIC3
MICIN3N AI Negative Differential Input for MIC3
FMINL AI FMIN Left Input
FMINR AI FMIN Right Input
LINEINL AI LINEIN Left Single-End Input
LINEINR AI LINEIN Right Single-End Input
HPOUTL AO Headphone Light Output
HPOUTR AO Headphone Right Output
HPOUTFB AI Pseudo Differential Headphone Ground Reference
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Signal Type Description
VRA1 AO Internal Reference Voltage
VRA2 AO Internal Reference Voltage
HPVCC P Headphone Power
AVCC P Analog Power
AGND G Analog Ground
8.4.3.2 Clock Sources
The following figure describes the clock source of Audio Codec. For clock setting, configuration, and gating
information, refer to section 3.3 “CCU”.
Figure 8-25 Audio Codec Clock Diagram
APBCLK
Digital Control Register
ADDA_PR Control Register
ADCCLKSEL HPF&DRC
PLL_AUDIO0
24.576 MHz ADCCLK
ADC_DIGITAL
DACCLK
PLL_AUDIO1 DAC_DIGITAL
24.576 MHz/22.5792 MHz
DACCLKSEL
CLK32K
CLK32K_RTC VRA1_SPEEUP
Digital Part
CK_ADC
ADC_ANALOG
CK_DAC
DAC_ANALOG
Analog Part
The clock source for the digital part is the PLL_AUDIO0 and PLL_AUDIO1. For the ADC clock, configure
AUDIO_CODEC_ADC_CLK_REG[25:24] to select the clock source. For the DAC clock, configure
AUDIO_CODEC_DAC_CLK_REG[25:24] to select the clock source. The PK-PK jitter of PLL_AUDIO0 and
PLL_AUDIO1 should be less than 200 ps.
The clock source for the analog part is the CK_ADC and CK_DAC, both of which are divided from the digital part.
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8.4.3.3 Reset System
Digital Part Reset System
The following figure shows the reset system of the audio codec digital part.
Figure 8-26 Audio Codec Digital Part Reset System
SYS_RST REGISTER ADC/DAC
SOFT_RST DIGITAL PART
HPF&DRC
The SYS_RST comes from the VDD-SYS domain and is produced by the RTC domain. Each domain has the de-
bounce to confirm the reset system is strong. For the codec register part, MIX can be reset by the SYS_RST
when being powered on or the system soft is writing the reset control logic. The other parts can be reset by
the soft configuration through writing the register.
Analog Part Reset System
The following figure shows the reset system of the audio codec analog part.
Figure 8-27 Audio Codec Analog Part Reset System
SYS_ RST ADDA LOGIC
CORE
AVCC ANALOG
POWER ON LS RC
PART
When AVCC is powered on, it sends the AVCC_POR signal. The AVCC_POR signal passes the level shift and RC
filter part to the ADDA logic core.
8.4.3.4 Data Path Diagram
The following figure shows a data path of the Audio Codec.
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Figure 8-28 Audio Codec Data Path Diagram
FMINL
ADC1 Reg000[31]
LINEINL Reg310[15]
Reg300[31] Reg324[15]
Reg030[28]
Reg050[00] DACL G HPOUTL
F F
FMINR D D
ADC2 I APB APB I
A A
LINEINR F F Reg000[31]
P P Reg310[14]
Reg308[31] O O
Reg030[28] Reg324[15]
Reg050[01] DACR G HPOUTR
Reg308[30]
MICIN3P +
-G
ADC3
MICIN3N
Reg308[31]
Reg030[28]
Reg050[02]
8.4.3.5 Three ADCs
The three ADCs are used for recording stereo sound and a reference signal. The sample rates of the three ADCs
are independent of the DAC sample rate. The digital ADC part can be enabled or disabled by the bit[28] of the
AC_ADC_FIFOC register.
8.4.3.6 Stereo DAC
The stereo DAC sample rate can be configured by setting the register. To save power, the analog DACL can be
enabled or disabled by setting the bit[15] of the DAC_REG register, and the analog DACR can be enabled or
disabled by setting the bit[14] of the DAC_REG register. The digital DAC part can be enabled or disabled by the
bit[31] of the AC_DAC_DPC register.
8.4.3.7 Analog Audio Input Path
The Audio Codec supports 3 analog audio input paths:
MICIN3P/N
LINEINL/R
FMINL/R
LINEINL, FMINL provide differential input that can be mixed into the ADC1 record mixer. LINEINR, FMINR
provide differential input that can be mixed into the ADC2 record mixer. MICIN3P/N provides differential input.
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The MICIN is a high impedance, low capacitance input suitable for connecting to various differential
microphones of different dynamics and sensitivity. The gain for each pre-amplifier can be set independently.
8.4.3.8 Analog Audio Output Path
The Audio Codec has 1 analog output paths:
HPOUTL/R
The headphone PA is powered up or down by HP_REG[bit15] (HPPA_EN). HPOUTL/R can drive a 16R or 32R
headphone load without DC capacitors by using Charge Pump to generate the negative rails. HP-FB is the
ground loop noise rejection feedback.
Figure 8-29 Headphone Output Application
HBIAS
Headphone
Driver HPOUTL
HPOUTR
HP-FB
8.4.3.9 Interrupts
The Audio Codec has two interrupts. The following figure describes the Audio Codec interrupt system.
Figure 8-30 Audio Codec Interrupt System
ADC_IRQ_EN
ADC_IRQ_STATUS
ADC_IRQ
ADC_OVERRUN_IRQ_EN
ADC_OVERRUN_IRQ_STATUS
IRQ
DAC_IRQ_EN
DAC_IRQ_STATUS
DAC_OVERRUN_IRQ_EN DAC_IRQ
DAC_OVERRUN_IRQ_STATUS
DAC_UNDERRUN_IRQ_EN
DAC_UNDERRUN_IRQ_STATUS
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8.4.3.10 Digital Audio Processor (DAP)
The DAP module is used to remove the DC offset and automatically adjusts the volume to a flatten volume
level. It mainly consists of two HPF and one DRC.
The following figure shows the DAP data flow.
Figure 8-31 DAP Data Flow
M
U L
HPF X
DRC
Alpha Filter
M M
Compression Smooth U
U
X control Filter X
Alpha Filter
M
U R
HPF X
HPF Function
The DAP has individual channel high pass filter (HPF, -3 dB cutoff < 1 Hz) that can be enabled and disabled. The
filter cutoff frequency is less than 1 Hz that can be removed DC offset from ADC recording. The HPF can also
be bypassed.
Figure 8-32 HPF Logic Structure
DRC Function
The DRC scheme has three thresholds, three offsets, and four slopes (all programmable). There is one ganged
DRC for the left and right channels. The following figure shows the diagram of DRC input/output.
Figure 8-33 DRC Block Diagram
x(n) g(n)
Energy Compression Smooth
Filter control Filter
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Figure 8-34 DRC Static Curve Parameters
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
(Outpu t dB)
-10
-20
OPL
Kl -30
OPC Kc
-40
-50
Kn
-60
OPE
-70
-80
Ke
-90
-100
NT ET CT LT (Inpu t dB)
Professional-quality dynamic range compression automatically adjusts the volume to flatten volume level.
One DRC for left/right and one DRC for the subwoofer.
Each DRC has an adjustable threshold, offset, and compression levels, programmable energy, attack, and decay
time constants.
Transparent compression: Compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Configure the DRC parameters according to the following guidelines:
Number format
The Number format is N.M which means there are N bits to the left of the decimal point including the sign
bit and M bits to the right of the decimal point. For example, Numbers formatted 9.23 means that there
are 9 bits at the left of the decimal point and 23 bits at the right decimal point.
Energy Filter
The following figure shows the structure of the energy filter.
Figure 8-35 Energy Filter Structure
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The Energy Filter is to estimate the RMS value of the audio data stream into DRC and has two parameters,
which determine the time window over which RMS to be made. The parameter is computed by
1 e2.2Ts / ta .
For the Compression Control, there are ten parameters (ET, CT, LT, Ke, Kn, Kc, Kl, OPL, OPC, and OPE), which
are all programmable, and the computation will be explained as follows.
Threshold Parameter Computation (T parameter)
The threshold is the value that determines the signal to be compressed or not. When the RMS of the signal
is larger than the threshold, the signal will be compressed. The value of threshold input to the coefficient
TdB
register is computed by Tin .
6.0206
Where, TdB must less than zero, the positive value is illegal.
For example, it is desired to set CT = -40 dB, then the Tin require to set CT to -40 dB is CTin = - (-40
dB)/6.0206 = 6.644, CTin is entered as a 32-bit number in 8.24 format.
Therefore, CTin = 6.644 = 0000 0110.1010 0100 1101 0011 1100 0000 = 0x06A4 D3C0 in 8.24 format.
Slope Parameter Computation (K parameter)
The K is the slope within the compression region. For example, an n: 1 compression means that an output
1
increase of 1 dB is for n dB RMS input. The k input to the coefficient ram is computed by K
n
Where, n is from 1 to 50, and must be an integer.
For example, it is desired to set to 2:1, then the Kc requires to set to 2:1, is Kc = 1/2 = 0.5, Kc is entered as
a 32-bit number in 8.24 format.
Therefore, Kc = 0.5 = 0000 0000.1000 0000 0000 0000 0000 0000 = 0x0080 0000 in 8.24 format.
Gain Smooth Filter
The Gain Smooth Filter is to smooth the gain and control the ratio of gain increase and decrease. The
decay time and attack are shown in Figure 8-36. The structure of the Gain Smooth filter is also the Alpha
filter, so the rise time computation is the same as the Energy filter which is 1 e2.2Ts / ta .
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Figure 8-36 Gain Smooth Filter
Input
Signal
Output
Signal
Target Level
Gain
Attack Time Decay Time
8.4.4 Programming Guidelines
8.4.4.1 Record Process
In recording mode, the analog audio signals are recorded from the microphones at the specified sample rate,
processed by the ADC, and then transferred to the DRAM via the DMA.
Step 1 Codec initialization: configure AUDIO_CODEC_BGR_REG to open the audio codec bus clock gating
and de-assert bus reset; configure AUDIO_CODEC_ADC_CLK_REG and PLL_AUDIO0_CTRL_REG to
configure PLL_Audio0 frequency and enable PLL_Audio0. For details, refer to section 3.3 “CCU”.
Step 2 Configure the sample rate and data transfer format, then open the ADC.
Step 3 Configure the DMA and DMA request.
Step 4 Enable the ADC DRQ and DMA.
8.4.4.2 Playback Process
In playback mode, the audio data are transferred from the DRAM via DMA, processed by the DAC, and finally
output via the analog interface.
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Step 1 Codec initialization: configure AUDIO_CODEC_BGR_REG to open the audio codec bus clock gating
and de-assert bus reset; configure AUDIO_CODEC_DAC_CLK_REG and PLL_AUDIO1_CTRL_REG to
configure PLL_Audio1 frequency and enable PLL_Audio1. For details, refer to section 3.3 “CCU”.
Step 2 Configure the sample rate and data transfer format, then open the DAC.
Step 3 Configure the DMA and DMA request.
Step 4 Enable the DAC DRQ and DMA.
8.4.5 Register List
Module Name Base Address
Audio Codec 0x02030000
Register Name Offset Description
AC_DAC_DPC 0x0000 DAC Digital Part Control Register
DAC_VOL_CTRL 0x0004 DAC Volume Control Register
AC_DAC_FIFOC 0x0010 DAC FIFO Control Register
AC_DAC_FIFOS 0x0014 DAC FIFO Status Register
AC_DAC_TXDATA 0x0020 DAC TX DATA Register
AC_DAC_CNT 0x0024 DAC TX FIFO Counter Register
AC_DAC_DG 0x0028 DAC Debug Register
AC_ADC_FIFOC 0x0030 ADC FIFO Control Register
ADC_VOL_CTRL1 0x0034 ADC Volume Control1 Register
AC_ADC_FIFOS 0x0038 ADC FIFO Status Register
AC_ADC_RXDATA 0x0040 ADC RX Data Register
AC_ADC_CNT 0x0044 ADC RX Counter Register
AC_ADC_DG 0x004C ADC Debug Register
ADC_DIG_CTRL 0x0050 ADC Digtial Control Register
VRA1SPEEDUP_DOWN_CTRL 0x0054 VRA1 Speedup Down Control Register
AC_DAC_DAP_CTRL 0x00F0 DAC DAP Control Register
AC_ADC_DAP_CTR 0x00F8 ADC DAP Control Register
AC_DAC_DRC_HHPFC 0x0100 DAC DRC High HPF Coef Register
AC_DAC_DRC_LHPFC 0x0104 DAC DRC Low HPF Coef Register
AC_DAC_DRC_CTRL 0x0108 DAC DRC Control Register
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Register Name Offset Description
DAC DRC Left Peak Filter High Attack Time Coef
AC_DAC_DRC_LPFHAT 0x010C
Register
AC_DAC_DRC_LPFLAT 0x0110 DAC DRC Left Peak Filter Low Attack Time Coef Register
DAC DRC Right Peak Filter High Attack Time Coef
AC_DAC_DRC_RPFHAT 0x0114
Register
AC_DAC_DRC_RPFLAT 0x0118 DAC DRC Peak Filter Low Attack Time Coef Register
DAC DRC Left Peak Filter High Release Time Coef
AC_DAC_DRC_LPFHRT 0x011C
Register
DAC DRC Left Peak Filter Low Release Time Coef
AC_DAC_DRC_LPFLRT 0x0120
Register
DAC DRC Right Peak filter High Release Time Coef
AC_DAC_DRC_RPFHRT 0x0124
Register
DAC DRC Right Peak filter Low Release Time Coef
AC_DAC_DRC_RPFLRT 0x0128
Register
AC_DAC_DRC_LRMSHAT 0x012C DAC DRC Left RMS Filter High Coef Register
AC_DAC_DRC_LRMSLAT 0x0130 DAC DRC Left RMS Filter Low Coef Register
AC_DAC_DRC_RRMSHAT 0x0134 DAC DRC Right RMS Filter High Coef Register
AC_DAC_DRC_RRMSLAT 0x0138 DAC DRC Right RMS Filter Low Coef Register
AC_DAC_DRC_HCT 0x013C DAC DRC Compressor Threshold High Setting Register
AC_DAC_DRC_LCT 0x0140 DAC DRC Compressor Slope High Setting Register
AC_DAC_DRC_HKC 0x0144 DAC DRC Compressor Slope High Setting Register
AC_DAC_DRC_LKC 0x0148 DAC DRC Compressor Slope Low Setting Register
DAC DRC Compressor High Output at Compressor
AC_DAC_DRC_HOPC 0x014C
Threshold Register
DAC DRC Compressor Low Output at Compressor
AC_DAC_DRC_LOPC 0x0150
Threshold Register
AC_DAC_DRC_HLT 0x0154 DAC DRC Limiter Threshold High Setting Register
AC_DAC_DRC_LLT 0x0158 DAC DRC Limiter Threshold Low Setting Register
AC_DAC_DRC_HKl 0x015C DAC DRC Limiter Slope High Setting Register
AC_DAC_DRC_LKl 0x0160 DAC DRC Limiter Slope Low Setting Register
AC_DAC_DRC_HOPL 0x0164 DAC DRC Limiter High Output at Limiter Threshold
AC_DAC_DRC_LOPL 0x0168 DAC DRC Limiter Low Output at Limiter Threshold
AC_DAC_DRC_HET 0x016C DAC DRC Expander Threshold High Setting Register
AC_DAC_DRC_LET 0x0170 DAC DRC Expander Threshold Low Setting Register
AC_DAC_DRC_HKE 0x0174 DAC DRC Expander Slope High Setting Register
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Register Name Offset Description
AC_DAC_DRC_LKE 0x0178 DAC DRC Expander Slope Low Setting Register
AC_DAC_DRC_HOPE 0x017C DAC DRC Expander High Output at Expander Threshold
AC_DAC_DRC_LOPE 0x0180 DAC DRC Expander Low Output at Expander Threshold
AC_DAC_DRC_HKN 0x0184 DAC DRC Linear Slope High Setting Register
AC_DAC_DRC_LKN 0x0188 DAC DRC Linear Slope Low Setting Register
DAC DRC Smooth filter Gain High Attack Time Coef
AC_DAC_DRC_SFHAT 0x018C
Register
DAC DRC Smooth filter Gain Low Attack Time Coef
AC_DAC_DRC_SFLAT 0x0190
Register
DAC DRC Smooth filter Gain High Release Time Coef
AC_DAC_DRC_SFHRT 0x0194
Register
DAC DRC Smooth filter Gain Low Release Time Coef
AC_DAC_DRC_SFLRT 0x0198
Register
AC_DAC_DRC_MXGHS 0x019C DAC DRC MAX Gain High Setting Register
AC_DAC_DRC_MXGLS 0x01A0 DAC DRC MAX Gain Low Setting Register
AC_DAC_DRC_MNGHS 0x01A4 DAC DRC MIN Gain High Setting Register
AC_DAC_DRC_MNGLS 0x01A8 DAC DRC MIN Gain Low Setting Register
AC_DAC_DRC_EPSHC 0x01AC DAC DRC Expander Smooth Time High Coef Register
AC_DAC_DRC_EPSLC 0x01B0 DAC DRC Expander Smooth Time Low Coef Register
AC_DAC_DRC_HPFHGAIN 0x01B8 DAC DRC HPF Gain High Coef Register
AC_DAC_DRC_HPFLGAIN 0x01BC DAC DRC HPF Gain Low Coef Register
AC_ADC_DRC_HHPFC 0x0200 ADC DRC High HPF Coef Register
AC_ADC_DRC_LHPFC 0x0204 ADC DRC Low HPF Coef Register
AC_ADC_DRC_CTRL 0x0208 ADC DRC Control Register
ADC DRC Left Peak Filter High Attack Time Coef
AC_ADC_DRC_LPFHAT 0x020C
Register
AC_ADC_DRC_LPFLAT 0x0210 ADC DRC Left Peak Filter Low Attack Time Coef Register
ADC DRC Right Peak Filter High Attack Time Coef
AC_ADC_DRC_RPFHAT 0x0214
Register
ADC DRC Right Peak Filter Low Attack Time Coef
AC_ADC_DRC_RPFLAT 0x0218
Register
ADC DRC Left Peak Filter High Release Time Coef
AC_ADC_DRC_LPFHRT 0x021C
Register
ADC DRC Left Peak Filter Low Release Time Coef
AC_ADC_DRC_LPFLRT 0x0220
Register
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Register Name Offset Description
ADC DRC Right Peak Filter High Release Time Coef
AC_ADC_DRC_RPFHRT 0x0224 Register
ADC DRC Right Peak Filter Low Release Time Coef
AC_ADC_DRC_RPFLRT 0x0228 Register
AC_ADC_DRC_LRMSHAT 0x022C ADC DRC Left RMS Filter High Coef Register
AC_ADC_DRC_LRMSLAT 0x0230 ADC DRC Left RMS Filter Low Coef Register
AC_ADC_DRC_RRMSHAT 0x0234 ADC DRC Right RMS Filter High Coef Register
AC_ADC_DRC_RRMSLAT 0x0238 ADC DRC Right RMS Filter Low Coef Register
AC_ADC_DRC_HCT 0x023C ADC DRC Compressor Threshold High Setting Register
AC_ADC_DRC_LCT 0x0240 ADC DRC Compressor Slope High Setting Register
AC_ADC_DRC_HKC 0x0244 ADC DRC Compressor Slope High Setting Register
AC_ADC_DRC_LKC 0x0248 ADC DRC Compressor Slope Low Setting Register
ADC DRC Compressor High Output at Compressor
AC_ADC_DRC_HOPC 0x024C
Threshold Register
ADC DRC Compressor Low Output at Compressor
AC_ADC_DRC_LOPC 0x0250
Threshold Register
AC_ADC_DRC_HLT 0x0254 ADC DRC Limiter Threshold High Setting Register
AC_ADC_DRC_LLT 0x0258 ADC DRC Limiter Threshold Low Setting Register
AC_ADC_DRC_HKl 0x025C ADC DRC Limiter Slope High Setting Register
AC_ADC_DRC_LKl 0x0260 ADC DRC Limiter Slope Low Setting Register
AC_ADC_DRC_HOPL 0x0264 ADC DRC Limiter High Output at Limiter Threshold
AC_ADC_DRC_LOPL 0x0268 ADC DRC Limiter Low Output at Limiter Threshold
AC_ADC_DRC_HET 0x026C ADC DRC Expander Threshold High Setting Register
AC_ADC_DRC_LET 0x0270 ADC DRC Expander Threshold Low Setting Register
AC_ADC_DRC_HKE 0x0274 ADC DRC Expander Slope High Setting Register
AC_ADC_DRC_LKE 0x0278 ADC DRC Expander Slope Low Setting Register
AC_ADC_DRC_HOPE 0x027C ADC DRC Expander High Output at Expander Threshold
AC_ADC_DRC_LOPE 0x0280 ADC DRC Expander Low Output at Expander Threshold
AC_ADC_DRC_HKN 0x0284 ADC DRC Linear Slope High Setting Register
AC_ADC_DRC_LKN 0x0288 ADC DRC Linear Slope Low Setting Register
ADC DRC Smooth filter Gain High Attack Time Coef
AC_ADC_DRC_SFHAT 0x028C
Register
ADC DRC Smooth filter Gain Low Attack Time Coef
AC_ADC_DRC_SFLAT 0x0290
Register
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Register Name Offset Description
ADC DRC Smooth filter Gain High Release Time Coef
AC_ADC_DRC_SFHRT 0x0294
Register
ADC DRC Smooth filter Gain Low Release Time Coef
AC_ADC_DRC_SFLRT 0x0298
Register
AC_ADC_DRC_MXGHS 0x029C ADC DRC MAX Gain High Setting Register
AC_ADC_DRC_MXGLS 0x02A0 ADC DRC MAX Gain Low Setting Register
AC_ADC_DRC_MNGLS 0x02A4 ADC DRC MIN Gain High Setting Register
AC_ADC_DRC_MXGLS 0x02A8 ADC DRC MIN Gain Low Setting Register
AC_ADC_DRC_EPSHC 0x02AC ADC DRC Expander Smooth Time High Coef Register
AC_ADC_DRC_EPSLC 0x02B0 ADC DRC Expander Smooth Time Low Coef Register
AC_ADC_DRC_HPFHGAIN 0x02B8 ADC DRC HPF Gain High Coef Register
AC_ADC_DRC_HPFLGAIN 0x02BC ADC DRC HPF Gain Low Coef Register
Analog Domain Register
ADC1_REG 0x0300 ADC1 Analog Control Register
ADC2_REG 0x0304 ADC2 Analog Control Register
ADC3_REG 0x0308 ADC3 Analog Control Register
DAC_REG 0x0310 DAC Analog Control Register
MICBIAS_REG 0x0318 MICBIAS Analog Control Register
RAMP_REG 0x031C BIAS Analog Control Register
BIAS_REG 0x0320 BIAS Analog Control Register
ADC5_REG 0x0330 ADC5 Analog Control Register
8.4.6 Register Description
8.4.6.1 0x0000 DAC Digital Part Control Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: AC_DAC_DPC
Bit Read/Write Default/Hex Description
EN_DA
DAC Digital Part Enable
31 R/W 0x0
0: Disabled
1: Enabled
30:29 / / /
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Offset: 0x0000 Register Name: AC_DAC_DPC
Bit Read/Write Default/Hex Description
MODQU
Internal DAC Quantization Levels
28:25 R/W 0x0
Levels = [7*(21 + MODQU[3:0])]/128
Default levels = 7*21/128 = 1.15
DWA
DWA Function Disable
24 R/W 0x0
0: Enabled
1: Disabled
23:19 / / /
HPF_EN
High Pass Filter Enable
18 R/W 0x0
0: Disabled
1: Enabled
DVOL
17:12 R/W 0x0 Digital volume control: DVC, ATT = DVC[5:0]*(-1.16 dB)
64 steps, -1.16 dB/step
11:1 / / /
HUB_EN
Audio Hub Enable
The bit takes effect only when the EN_DA is set to 1.
0 R/W 0x0
System Domain: Audio Codec/I2S1/I2S2/OWA TXFIFO Hub Enable.
0: Disabled
1: Enabled
8.4.6.2 0x0004 DAC Volume Control Register (Default Value: 0x0000_A0A0)
Offset: 0x0004 Register Name: DAC_VOL_CTRL
Bit Read/Write Default/Hex Description
31:17 / / /
DAC_VOL_SEL
DAC Volume Control Selection Enable
16 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0004 Register Name: DAC_VOL_CTRL
Bit Read/Write Default/Hex Description
DAC_VOL_L
DAC left channel volume
(-119.25 dB to 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
15:8 R/W 0xA0 ...
0x9F = -0.75 dB
0xA0 = 0 dB
0xA1 = 0.75 dB
...
0xFF = 71.25 dB
DAC_VOL_R
DAC right channel volume
(-119.25 dB To 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
7:0 R/W 0xA0 ...
0x9F = -0.75 dB
0xA0 = 0 dB
0xA1 = 0.75 dB
...
0xFF = 71.25 dB
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8.4.6.3 0x0010 DAC FIFO Control Register (Default Value: 0x0000_4000)
Offset: 0x0010 Register Name: AC_DAC_FIFOC
Bit Read/Write Default/Hex Description
DAC_FS
Sample Rate of DAC
000: 48 kHz
010: 24 kHz
100: 12 kHz
110: 192 kHz
31:29 R/W 0x0
001: 32 kHz
011: 16 kHz
101: 8 kHz
111: 96 kHz
44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL
Configure Bit
FIR_VER
FIR Version
28 R/W 0x0
0: 64-Tap FIR
1: 32-Tap FIR
27 / / /
SEND_LASAT
Audio sample select when TX FIFO underrun
26 R/W 0x0
0: Sending zero
1: Sending the last audio sample
FIFO_MODE
For 20-bit transmitted audio sample:
00/10: FIFO_I[19:0] = {TXDATA[31:12]}
25:24 R/W 0x0 01/11: FIFO_I[19:0] = {TXDATA[19:0]}
For 16-bit transmitted audio sample:
00/10: FIFO_I[19:0] = {TXDATA[31:16], 4’b0}
01/11: FIFO_I[19:0] = {TXDATA[15:0], 4’b0}
23 / / /
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Offset: 0x0010 Register Name: AC_DAC_FIFOC
Bit Read/Write Default/Hex Description
DAC_DRQ_CLR_CNT
When TX FIFO available room is less than or equal N, the DRQ
request will be de-asserted. N is defined here:
22:21 R/W 0x0 00: IRQ/DRQ de-asserted when WLEVEL > TXTL
01: 4
10: 8
11: 16
20:15 / / /
TX_TRIG_LEVEL
TX FIFO Empty Trigger Level (TXTL[12:0])
Interrupt and DMA request trigger level for TX FIFO normal
14:8 R/W 0x40 condition.
IRQ/DRQ generated when WLEVEL ≤ TXTL
Note: WLEVEL represents the number of valid samples in the TX
FIFO. Only TXTL[6:0] valid when TXMODE = 0
7 / / /
DAC_MONO_EN
DAC Mono Enable
6 R/W 0x0 0: Stereo, 64 levels FIFO
1: Mono, 128 levels FIFO
When enabled, L & R channel send the same data.
TX_SAMPLE_BITS
Transmitting Audio Sample Resolution
5 R/W 0x0
0: 16 bits
1: 20 bits
DAC_DRQ_EN
DAC FIFO Empty DRQ Enable
4 R/W 0x0
0: Disabled
1: Enabled
DAC_IRQ_EN
DAC FIFO Empty IRQ Enable
3 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0010 Register Name: AC_DAC_FIFOC
Bit Read/Write Default/Hex Description
FIFO_UNDERRUN_IRQ_EN
DAC FIFO Underrun IRQ Enable
2 R/W 0x0
0: Disabled
1: Enabled
FIFO_OVERRUN_IRQ_EN
DAC FIFO Overrun IRQ Enable
1 R/W 0x0
0: Disabled
1: Enabled
FIFO_FLUSH
0 R/WC 0x0 DAC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’
8.4.6.4 0x0014 DAC FIFO Status Register (Default Value: 0x0080_8008)
Offset: 0x0014 Register Name: AC_DAC_FIFOS
Bit Read/Write Default/Hex Description
31:24 / / /
TX_EMPTY
TX FIFO Empty
23 R 0x1
0: No room for new sample in TX FIFO
1: More than one room for new sample in TX FIFO (>= 1 word)
TXE_CNT
22:8 R 0x80
TX FIFO Empty Space Word Counter
7:4 / / /
TXE_INT
TX FIFO Empty Pending Interrupt
0: No Pending IRQ
3 R/W1C 0x1
1: FIFO Empty Pending Interrupt
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
TXU_INT
TX FIFO Underrun Pending Interrupt
2 R/W1C 0x0 0: No Pending Interrupt
1: FIFO Underrun Pending Interrupt
Write ‘1’ to clear this interrupt
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Offset: 0x0014 Register Name: AC_DAC_FIFOS
Bit Read/Write Default/Hex Description
TXO_INT
TX FIFO Overrun Pending Interrupt
1 R/W1C 0x0 0: No Pending Interrupt
1: FIFO Overrun Pending Interrupt
Write ‘1’ to clear this interrupt
0 / / /
8.4.6.5 0x0020 DAC TX DATA Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: AC_DAC_TXDATA
Bit Read/Write Default/Hex Description
TX_DATA
Write the transmitting left and right channel sample data to this
31:0 W 0x0
register one by one. Write the left channel sample data first and
then the right channel sample.
8.4.6.6 0x0024 DAC TX Counter Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: AC_DAC_CNT
Bit Read/Write Default/Hex Description
TX_CNT
TX Sample Counter
The audio sample number of sending into TXFIFO.
When one sample is put into TXFIFO by DMA or by host IO, the TX
31:0 R/W 0x0 sample counter register increases by one. The TX sample counter
register can be set to any initial valve at any time. After being
updated by the initial value, the counter register should count from
this initial value.
Note: It is used for Audio/Video Synchronization.
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8.4.6.7 0x0028 DAC Debug Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: AC_DAC_DG
Bit Read/Write Default/Hex Description
31:12 / / /
DAC_MODU_SELECT
DAC Modulator Debug
11 R/W 0x0
0: DAC Modulator Normal Mode
1: DAC Modulator Debug Mode
DAC_PATTERN_SELECT
DAC Pattern Select
00: Normal (Audio sample from TX FIFO)
10:9 R/W 0x0
01: -6 dB Sin wave
10: -60 dB Sin wave
11: Silent wave
CODEC_CLK_SELECT
CODEC Clock Source Select
8 R/W 0x0
0: CODEC clock from PLL
1: CODEC clock from OSC (for Debug)
7 / / /
DA_SWP
DAC Output Channel Swap Enable
6 R/W 0x0
0: Disabled
1: Enabled
5:3 / / /
ADDA_LOOP_MODE
ADDA Loop Mode Select
000: Disabled
2:0 R/W 0x0
001: ADDA LOOP MODE DACL/DACR is connected to ADC1/ADC2
010: ADDA LOOP MODE DACL/DACR is connected to ADC3
Others: Reserved
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8.4.6.8 0x0030 ADC FIFO Control Register (Default Value: 0x0000_0400)
Offset: 0x0030 Register Name: AC_ADC_FIFOC
Bit Read/Write Default/Hex Description
ADFS
Sample Rate of ADC
000: 48 kHz
010: 24 kHz
100: 12 kHz
110: Reserved
31:29 R/W 0x0
001: 32 kHz
011: 16 kHz
101: 8 kHz
111: Reserved
44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL
Configure Bit.
EN_AD
ADC Digital Part Enable
28 R/W 0x0
0: Disabled
1: Enabled
ADCFDT
ADC FIFO delay time for writing data after EN_AD
00: 5 ms
27:26 R/W 0x0
01: 10 ms
10: 20 ms
11: 30 ms
ADCDFEN
ADC FIFO delay function for writing data after EN_AD
25 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0030 Register Name: AC_ADC_FIFOC
Bit Read/Write Default/Hex Description
RX_FIFO_MODE
RX FIFO Output Mode (Mode 0, 1)
0: Expanding ‘0’ at LSB of TX FIFO register
1: Expanding received sample sign bit at MSB of TX FIFO register
For 20-bit received audio sample:
24 R/W 0x0
Mode 0: RXDATA[31:0] = {FIFO_O[19:0], 12’h0}
Mode 1: RXDATA[31:0] = {12{FIFO_O[19]}, FIFO_O[19:0]}
For 16-bit received audio sample:
Mode 0: RXDATA[31:0] = {FIFO_O[19:4], 16’h0}
Mode 1: RXDATA[31:0] = {16{FIFO_O[19]}, FIFO_O[19:4]}
23:22 / / /
RX_SYNC_EN_START
The bit takes effect only when RX_SYNC_EN is set to 1.
System Domain: Audio codec/I2S1/I2S2/DMIC/OWA RX
21 R/W 0x0
Synchronize Enable Start.
0: Disabled
1: Enabled
RX_SYNC_EN
Audiocodec RX Synchronize Enable
20 R/W 0x0
0: Disabled
1: Enabled
19:17 / / /
RX_SAMPLE_BITS
Receiving Audio Sample Resolution
16 R/W 0x0
0: 16 bits
1: 20 bits
15:12 / / /
RX_FIFO_TRG_LEVEL
RX FIFO Trigger Level (RXTL[5:0])
Interrupt and DMA request trigger level for RX FIFO normal
11:4 R/W 0x40 condition
IRQ/DRQ generated when WLEVEL > RXTL[5:0]
Note: WLEVEL represents the number of valid samples in the RX
FIFO.
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Offset: 0x0030 Register Name: AC_ADC_FIFOC
Bit Read/Write Default/Hex Description
ADC_DRQ_EN
ADC FIFO Data Available DRQ Enable
3 R/W 0x0
0: Disabled
1: Enabled
ADC_IRQ_EN
ADC FIFO Data Available IRQ Enable
2 R/W 0x0
0: Disabled
1: Enabled
ADC_OVERRUN_IRQ_EN
ADC FIFO Overrun IRQ Enable
1 R/W 0x0
0: Disabled
1: Enabled
ADC_FIFO_FLUSH
0 R/WC 0x0 ADC FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’.
8.4.6.9 0x0034 ADC Volume Control1 Register (Default Value: 0xA0A0_A0A0)
Offset: 0x0034 Register Name: ADC_VOL_CTRL1
Bit Read/Write Default/Hex Description
31:24 R/W 0xA0 Reserved
ADC3_VOL
ADC3 channel volume
(-119.25 dB To 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
23:16 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
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Offset: 0x0034 Register Name: ADC_VOL_CTRL1
Bit Read/Write Default/Hex Description
ADC2_VOL
ADC2 channel volume
(-119.25 dB To 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
15:8 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
ADC1_VOL
ADC1 channel volume
(-119.25 dB To 71.25 dB, 0.75 dB/Step)
0x00: Mute
0x01: -119.25 dB
7:0 R/W 0xA0 ...
0x9F: -0.75 dB
0xA0: 0 dB
0xA1: 0.75 dB
...
0xFF: 71.25 dB
8.4.6.10 0x0038 ADC FIFO Status Register (Default Value: 0x0000_0001)
Offset: 0x0038 Register Name: AC_ADC_FIFOS
Bit Read/Write Default/Hex Description
31:24 / / /
RXA
RX FIFO Available
23 R 0x0
0: No available data in RX FIFO
1: More than one sample in RX FIFO (>= 1 word)
22:17 / / /
RXA_CNT
16:8 R 0x0
RX FIFO Available Sample Word Counter
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Offset: 0x0038 Register Name: AC_ADC_FIFOS
Bit Read/Write Default/Hex Description
7:4 / / /
RXA_INT
RX FIFO Data Available Pending Interrupt
0: No Pending IRQ
3 R/W1C 0x0
1: Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if the interrupt
condition fails.
2 / / /
RXO_INT
RX FIFO Overrun Pending Interrupt
1 R/W1C 0x0 0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt.
0 R 0x1 Reserved
8.4.6.11 0x0040 ADC RX DATA Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: AC_ADC_RXDATA
Bit Read/Write Default/Hex Description
RX_DATA
RX Sample
31:0 R 0x0
The host can get one sample by reading this register. The left
channel sample data comes first and then the right channel sample.
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8.4.6.12 0x0044 ADC RX Counter Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: AC_ADC_CNT
Bit Read/Write Default/Hex Description
RX_CNT
RX Sample Counter
The audio sample number of writing into RXFIFO. When one sample
is written by Digital Audio Engine, the RX sample counter register
31:0 R/W 0x0
increases by one. The RX sample counter register can be set to any
initial valve at any time. After being updated by the initial value, the
counter register should count from this initial value.
Note: It is used for Audio/Video Synchronization.
8.4.6.13 0x004C ADC Debug Register (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: AC_ADC_DG_REG
Bit Read/Write Default/Hex Description
31:26 / / /
AD_SWP2
ADC output channel swap enable (for digital filter)
25 R/W 0x0 0: Disabled
1: Enabled
Note: ADC3 and ADC4 swap data.
AD_SWP1
ADC output channel swap enable (for digital filter)
24 R/W 0x0 0: Disabled
1: Enabled
Note: ADC1 and ADC2 swap data.
23:0 / / /
8.4.6.14 0x0050 ADC Digtial Control Register (Default Value: 0x0000_0000)
Offset: 0x0050 Register Name: ADC_DIG_CTRL
Bit Read/Write Default/Hex Description
31:18 / / /
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Offset: 0x0050 Register Name: ADC_DIG_CTRL
Bit Read/Write Default/Hex Description
ADC3_VOL_EN
ADC3 Volume Control Enable
17 R/W 0x0
0: Disabled
1: Enabled
ADC1_2_VOL_EN
ADC1/2 Volume Control Enable
16 R/W 0x0
0: Disabled
1: Enabled
15:3 / / /
ADC_CHANNEL_EN
Bit 3: ADC4 enabled
2:0 R/W 0x0 Bit 2: ADC3 enabled
Bit 1: ADC2 enabled
Bit 0: ADC1 enabled
8.4.6.15 0x0054 VRA1 Speedup Down Control Register (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: VRA1SPEEDUP_DOWN_CTRL
Bit Read/Write Default/Hex Description
31:5 / / /
VRA1SPEEDUP_DOWN_STATE
Only if VAR1SPEEDUP_DOWN_Further_CTRL (0x310[22]) is set 0,
4 R 0x0 VAR1Speedup Down State is valid.
0: VAR1Speedup_Down does not work.
1: VAR1Speedup_Down works.
3:2 / / /
VRA1SPEEDUP_DOWN_CTRL
VAR1Speedup Down Manual Control Enable
1 R/W 0x0 0: Disabled. VAR1Speedup Down converts to 1 after the bus rst
releases 32 ms.
1: Enabled. VAR1Speedup Down converts to 1 immediately.
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Offset: 0x0054 Register Name: VRA1SPEEDUP_DOWN_CTRL
Bit Read/Write Default/Hex Description
VRA1SPEEDUP_DOWN_RST_CTRL
VAR1Speedup Down RST Manual Control Enable
0 R/W 0x0 0: Disabled. VAR1Speedup Down converts to 1 after the bus rst
releases 32 ms.
1: Enabled. VAR1Speedup Down reset 0 immediately.
8.4.6.16 0x00F0 DAC DAP Control Register (Default Value: 0x0000_0000)
Offset: 0x00F0 Register Name: AC_DAC_DAP_CTR
Bit Read/Write Default/Hex Description
DDAP_EN
DAP for DRC enable
31 R/W 0x0
0: Bypassed
1: Enabled
30 / / /
DDAP_DRC_EN
DRC enable control
29 R/W 0x0
0: Disabled
1: Enabled
DDAP_HPF_EN
HPF enable control
28 R/W 0x0
0: Disabled
1: Enabled
27:0 / / /
8.4.6.17 0x00F8 ADC DAP Control Register (Default Value: 0x0000_0000)
Offset: 0x00F8 Register Name: AC_ADC_DAP_CTR
Bit Read/Write Default/Hex Description
ADC_DAP0_EN (control the DAP of ADC1/2)
DAP for ADC enable
31 R/W 0x0
0: Bypassed
1: Enabled
30 / / /
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Offset: 0x00F8 Register Name: AC_ADC_DAP_CTR
Bit Read/Write Default/Hex Description
ADC_DRC0_EN
ADC DRC0 enable control
29 R/W 0x0
0: Disabled
1: Enabled
ADC_HPF0_EN
ADC HPF0 enable control
28 R/W 0x0
0: Disabled
1: Enabled
ADC_DAP1_EN (control the DAP of ADC3)
27 R/W 0x0
ADC DAP1 enable control
26 / / /
ADC_DRC1_EN
ADC DRC1 enable control
25 R/W 0x0
0: Disabled
1: Enabled
ADC_HPF1_EN
ADC HPF1 enable control
24 R/W 0x0
0: Disabled
1: Enabled
23:0 / / /
8.4.6.18 0x0100 DAC DRC High HPF Coef Register (Default Value: 0x0000_00FF)
Offset: 0x0100 Register Name: AC_DAC_DRC_HHPFC
Bit Read/Write Default/Hex Description
31:11 / / /
10:0 R/W 0xFF HPF coefficient setting and the data is 3.24 format.
8.4.6.19 0x0104 DAC DRC Low HPF Coef Register (Default Value: 0x0000_FAC1)
Offset: 0x0104 Register Name: AC_DAC_DRC_LHPFC
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0104 Register Name: AC_DAC_DRC_LHPFC
Bit Read/Write Default/Hex Description
15:0 R/W 0xFAC1 HPF coefficient setting and the data is 3.24 format.
8.4.6.20 0x0108 DAC DRC Control Register (Default Value: 0x0000_0080)
Offset: 0x0108 Register Name: AC_DAC_DRC_CTRL
Bit Read/Write Default/Hex Description
31:16 / / /
DRC delay buffer data output state when The DRC delay function
is enabled and the DRC function is disabled. After disabling the
DRC function and this bit goes to 0, write the DRC delay function
15 R 0x0
bit to 0.
0: Not completed
1: Completed
14:10 / / /
Signal delay time setting
6'h00: (8x1) fs
6'h01: (8x2) fs
6'h02: (8x3) fs
----------------------------------------
13:8 R/W 0x0 6'h2e: (8*47) fs
6'h2f: (8*48) fs
6'h30 -- 6'h3f: (8*48) fs
Delay time = 8*(n + 1) fs, n<6'h30;
When the delay function is disabled, the signal delay time is
unused.
DAC_DRC_DELAY_BUF_EN
The delay buffer use or not when the DRC is disabled and the
7 R/W 0x1 DRC buffer data output completely.
0: Do not use the buffer.
1: Use the buffer.
DAC_DRC_GAIN_MAX_LIMIT_EN
DRC gain max limit enable
6 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0108 Register Name: AC_DAC_DRC_CTRL
Bit Read/Write Default/Hex Description
DAC_DRC_GAIN_MIN_LIMIT_EN
DRC gain min limit enable
When this function is enabled, it will overwrite the noise detect
5 R/W 0x0
function.
0: Disabled
1: Enabled
DAC_DRC_DETECT_NOISE_EN
Control the DRC to detect noise when ET is enabled.
4 R/W 0x0
0: Disabled
1: Enabled
DAC_DRC_SIGNAL_FUNC_SEL
Signal function select
0: RMS filter
1: Peak filter
When the signal function selects the Peak filter, the RMS
3 R/W 0x0 parameter is unused. (AC_DRC_LRMSHAT, AC_DRC_LRMSLAT,
AC_DRC_LRMSHAT, AC_DRC_LRMSLAT)
When the signal function selects the RMS filter, the Peak filter
parameter is unused. (AC_DRC_LPFHAT, AC_DRC_LPFLAT,
AC_DRC_RPFHAT, AC_DRC_RPFLAT, AC_DRC_LPFHRT,
AC_DRC_LPFLRT, AC_DRC_RPFHRT, and AC_DRC_RPFLRT)
DAC_DRC_DELAY_FUNC_EN
Delay function enable
2 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, the signal delay time is unused.
DAC_DRC_LT_EN
DRC LT enable
1 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, Kl and OPL parameter is unused.
DAC_DRC_ET_EN
DRC ET enable
0 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, Ke and OPE parameter is unused.
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8.4.6.21 0x010C DAC DRC Left Peak Filter High Attack Time Coef Register (Default Value: 0x0000_000B)
Offset: 0x010C Register Name: AC_DAC_DRC_LPFHAT
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_LPFHAT
The left peak filter attack time parameter setting, which is
10:0 R/W 0x000B
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.22 0x0110 DAC DRC Left Peak Filter Low Attack Time Coef Register (Default Value: 0x0000_77BF)
Offset: 0x0110 Register Name: AC_DAC_DRC_LPFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LPFLAT
The left peak filter attack time parameter setting, which is
15:0 R/W 0x77BF
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.23 0x0114 DAC DRC Right Peak Filter High Attack Time Coef Register (Default Value: 0x0000_000B)
Offset: 0x0114 Register Name: AC_DAC_DRC_RPFHAT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_RPFHAT
The right peak filter attack time parameter setting, which is
15:0 R/W 0xB
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.24 0x0118 DAC DRC Left Peak Filter Low Attack Time Coef Register (Default Value: 0x0000_77BF)
Offset: 0x0118 Register Name: AC_DAC_DRC_RPFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0118 Register Name: AC_DAC_DRC_RPFLAT
Bit Read/Write Default/Hex Description
DAC_DRC_RPFLAT
The left peak filter attack time parameter setting, which is
15:0 R/W 0x77BF
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.25 0x011C DAC DRC Left Peak Filter High Release Time Coef Register (Default Value: 0x0000_00FF)
Offset: 0x011C Register Name: AC_DAC_DRC_LPFHRT
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_LPFHRT
The left peak filter release time parameter setting, which is
10:0 R/W 0x00FF
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.26 0x0120 DAC DRC Left Peak Filter Low Release Time Coef Register (Default Value: 0x0000_E1F8)
Offset: 0x0120 Register Name: AC_DAC_DRC_LPFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LPFLRT
The left peak filter release time parameter setting, which is
15:0 R/W 0xE1F8
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.27 0x0124 DAC DRC Right Peak Filter High Release Time Coef Register (Default Value: 0x0000_00FF)
Offset: 0x0124 Register Name: AC_DAC_DRC_RPFHRT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0124 Register Name: AC_DAC_DRC_RPFHRT
Bit Read/Write Default/Hex Description
DAC_DRC_RPFHRT
The right peak filter release time parameter setting, which is
15:0 R/W 0xFF
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.28 0x0128 DAC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000_E1F8)
Offset: 0x0128 Register Name: AC_DAC_DRC_RPFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_RPFLRT
The right peak filter release time parameter setting, which is
15:0 R/W 0xE1F8
determined by the equation that AT = exp(-2.2Ts/tr). The format is
3.24. (The default value is 100 ms)
8.4.6.29 0x012C DAC DRC Left RMS Filter High Coef Register (Default Value: 0x0000_0001)
Offset: 0x012C Register Name: AC_DAC_DRC_LRMSHAT
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_LRMSHAT
The left RMS filter average time parameter setting, which is
10:0 R/W 0x0001
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.30 0x0130 DAC DRC Left RMS Filter Low Coef Register (Default Value: 0x0000_2BAF)
Offset: 0x0130 Register Name: AC_DAC_DRC_LRMSLAT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0130 Register Name: AC_DAC_DRC_LRMSLAT
Bit Read/Write Default/Hex Description
DAC_DRC_LRMSLAT
The left RMS filter average time parameter setting, which is
15:0 R/W 0x2BAF
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.31 0x0134 DAC DRC Right RMS Filter High Coef Register (Default Value: 0x0000_0001)
Offset: 0x0134 Register Name: AC_DAC_DRC_RRMSHAT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_RRMSHAT
The right RMS filter average time parameter setting, which is
15:0 R/W 0x2BAF
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.32 0x0138 DAC DRC Right RMS Filter Low Coef Register (Default Value: 0x0000_2BAF)
Offset: 0x0138 Register Name: AC_DAC_DRC_RRMSLAT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_RRMSLAT
The right RMS filter average time parameter setting, which is
15:0 R/W 0x2BAF
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.33 0x013C DAC DRC Compressor Theshold High Setting Register (Default Value: 0x0000_06A4)
Offset: 0x013C Register Name: AC_DAC_DRC_HCT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x013C Register Name: AC_DAC_DRC_HCT
Bit Read/Write Default/Hex Description
DAC_DRC_HCT
The compressor threshold setting, which is set by the equation
15:0 R/W 0x06A4
that CTin = -CT/6.0206. The format is 8.24. (The default value is -
40 dB)
8.4.6.34 0x0140 DAC DRC Compressor Slope High Setting Register (Default Value: 0x0000_D3C0)
Offset: 0x0140 Register Name: AC_DAC_DRC_LCT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LCT
The compressor threshold setting, which is set by the equation
15:0 R/W 0xD3C0
that CTin = -CT/6.0206. The format is 8.24. (The default value is -
40 dB)
8.4.6.35 0x0144 DAC DRC Compressor Slope High Setting Register (Default Value: 0x0000_0080)
Offset: 0x0144 Register Name: AC_DAC_DRC_HKC
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HKC
The slope of the compressor, which is determined by the equation
15:0 R/W 0x0080
that Kc = 1/R. R is the ratio of the compressor, which is always an
integer. The format is 8.24. (The default value is 2:1)
8.4.6.36 0x0148 DAC DRC Compressor Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0148 Register Name: AC_DAC_DRC_LKC
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0148 Register Name: AC_DAC_DRC_LKC
Bit Read/Write Default/Hex Description
DAC_DRC_LKC
The slope of the compressor, which is determined by the equation
15:0 R/W 0x0000
that Kc = 1/R. R is the ratio of the compressor, which is always an
integer. The format is 8.24. (The default value is 2:1)
8.4.6.37 0x014C DAC DRC Compressor High Output at Compressor Threshold Register (Default Value: 0x0000_F95B)
Offset: 0x014C Register Name: AC_DAC_DRC_HOPC
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HOPC
The output of the compressor, which is determined by the
15:0 R/W 0xF95B
equation -OPC/6.0206. The format is 8.24 (The default value is -40
dB)
8.4.6.38 0x0150 DAC DRC Compressor Low Output at Compressor Threshold Register (Default Value: 0x0000_2C3F)
Offset: 0x0150 Register Name: AC_DAC_DRC_LOPC
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LOPC
The output of the compressor, which is determined by the
15:0 R/W 0x2C3F
equation OPC/6.0206. The format is 8.24. (The default value is -40
dB)
8.4.6.39 0x0154 DAC DRC Limiter Theshold High Setting Register (Default Value: 0x0000_01A9)
Offset: 0x0154 Register Name: AC_DAC_DRC_HLT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HLT
15:0 R/W 0x01A9 The limiter threshold setting, which is set by the equation that LTin
= -LT/6.0206, The format is 8.24. (The default value is -10 dB)
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8.4.6.40 0x0158 DAC DRC Limiter Theshold Low Setting Register (Default Value: 0x0000_34F0)
Offset: 0x0158 Register Name: AC_DAC_DRC_LLT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LLT
15:0 R/W 0x34F0 The limiter threshold setting, which is set by the equation that LTin
= -LT/6.0206. The format is 8.24. (The default value is -10 dB)
8.4.6.41 0x015C DAC DRC Limiter Slope High Setting Register (Default Value: 0x0000_0005)
Offset: 0x015C Register Name: AC_DAC_DRC_HKl
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HKl
The slope of the limiter which is determined by the equation that
15:0 R/W 0x0005
Kl = 1/R. R is the ratio of the limiter, which is always an integer. The
format is 8.24. (The default value is <50:1>)
8.4.6.42 0x0160 DAC DRC Limiter Slope Low Setting Register (Default Value: 0x0000_1EB8)
Offset: 0x0160 Register Name: AC_DAC_DRC_LKl
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LKl
The slope of the limiter, which is determined by the equation that
15:0 R/W 0x1EB8
Kl = 1/R. R is the ratio of the limiter, which is always an integer. The
format is 8.24. (The default value is <50:1>)
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8.4.6.43 0x0164 DAC DRC Limiter High Output at Limiter Threshold Register (Default Value: 0x0000_FBD8)
Offset: 0x0164 Register Name: AC_DAC_DRC_HOPL
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HOPL
15:0 R/W 0xFBD8 The output of the limiter, which is determined by equation
OPT/6.0206. The format is 8.24. (The default value is -25 dB)
8.4.6.44 0x0168 DAC DRC Limiter Low Output at Limiter Threshold Register (Default Value: 0x0000_FBA7)
Offset: 0x0168 Register Name: AC_DAC_DRC_LOPL
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LOPL
15:0 R/W 0xFBA7 The output of the limiter, which is determined by equation
OPT/6.0206. The format is 8.24. (The default value is -25 dB)
8.4.6.45 0x016C DAC DRC Expander Theshold High Setting Register (Default Value: 0x0000_0BA0)
Offset: 0x016C Register Name: AC_DAC_DRC_HET
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HET
15:0 R/W 0x0BA0 The expander threshold setting, which is set by the equation that
ETin = -ET/6.0206. The format is 8.24. (The default value is -70 dB)
8.4.6.46 0x0170 DAC DRC Expander Theshold Low Setting Register (Default Value: 0x0000_7291)
Offset: 0x0170 Register Name: AC_DAC_DRC_LET
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LET
15:0 R/W 0x7291 The expander threshold setting, which is set by the equation that
ETin = -ET/6.0206. The format is 8.24. (The default value is -70 dB)
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8.4.6.47 0x0174 DAC DRC Expander Slope High Setting Register (Default Value: 0x0000_0500)
Offset: 0x0174 Register Name: AC_DAC_DRC_HKE
Bit Read/Write Default/Hex Description
31:14 / / /
DAC_DRC_HKE
The slope of the expander, which is determined by the equation
13:0 R/W 0x0500 that Ke = 1/R. R is the ratio of the expander, which is always an
integer and the ke must larger than 50. The format is 8.24. (The
default value is <1:5>)
8.4.6.48 0x0178 DAC DRC Expander Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0178 Register Name: AC_DAC_DRC_LKE
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LKE
The slope of the expander, which is determined by the equation
15:0 R/W 0x0000 that Ke = 1/R. R is the ratio of the expander, which is always an
integer and the ke must larger than 50. The format is 8.24. (The
default value is <1:5>)
8.4.6.49 0x017C DAC DRC Expander High Output at Expander Threshold Register (Default Value: 0x0000_F45F)
Offset: 0x017C Register Name: AC_DAC_DRC_HOPE
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HOPE
15:0 R/W 0xF45F The output of the expander, which is determined by equation
OPE/6.0206. The format is 8.24. (The default value is -70 dB)
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8.4.6.50 0x0180 DAC DRC Expander Low Output at Expander Threshold Register (Default Value: 0x0000_8D6E)
Offset: 0x0180 Register Name: AC_DAC_DRC_LOPE
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LOPE
15:0 R/W 0x8D6E The output of the expander which is determined by equation
OPE/6.0206. The format is 8.24. (The default value is -70 dB)
8.4.6.51 0x0184 DAC DRC Linear Slope High Setting Register (Default Value: 0x0000_0100)
Offset: 0x0184 Register Name: AC_DAC_DRC_HKN
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HKN
The slope of the linear, which is determined by the equation that
15:0 R/W 0x0100
Kn = 1/R. R is the ratio of the linear, which is always an integer. The
format is 8.24. (The default value is <1:1>)
8.4.6.52 0x0188 DAC DRC Linear Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0188 Register Name: AC_DAC_DRC_LKN
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_LKN
The slope of the linear, which is determined by the equation that
15:0 R/W 0x0000
Kn = 1/R. R is the ratio of the linear, which is always an integer. The
format is 8.24. (The default value is <1:1>)
8.4.6.53 0x018C DAC DRC Smooth Filter Gain High Attack Time Coef Register (Default Value: 0x0000_0002)
Offset: 0x018C Register Name: AC_DAC_DRC_SFHAT
Bit Read/Write Default/Hex Description
31:11 / / /
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Offset: 0x018C Register Name: AC_DAC_DRC_SFHAT
Bit Read/Write Default/Hex Description
DAC_DRC_SFHAT
The smooth filter attack time parameter setting, which is
10:0 R/W 0x0002
determined by the equation that AT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 5 ms)
8.4.6.54 0x0190 DAC DRC Smooth Filter Gain Low Attack Time Coef Register (Default Value: 0x0000_5600)
Offset: 0x0190 Register Name: AC_DAC_DRC_SFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_SFLAT
The smooth filter attack time parameter setting, which is
15:0 R/W 0x5600
determined by the equation that AT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 5 ms)
8.4.6.55 0x0194 DAC DRC Smooth Filter Gain High Release Time Coef Register (Default Value: 0x0000_0000)
Offset: 0x0194 Register Name: AC_DAC_DRC_SFHRT
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_SFHRT
The gain smooth filter release time parameter setting, which is
10:0 R/W 0x0000
determined by the equation that RT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 200 ms)
8.4.6.56 0x0198 DAC DRC Smooth Filter Gain Low Release Time Coef Register (Default Value: 0x0000_0F04)
Offset: 0x0198 Register Name: AC_DAC_DRC_SFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0198 Register Name: AC_DAC_DRC_SFLRT
Bit Read/Write Default/Hex Description
DAC_DRC_SFLRT
The gain smooth filter release time parameter setting, which is
15:0 R/W 0x0F04
determined by the equation that RT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 200 ms)
8.4.6.57 0x019C DAC DRC MAX Gain High Setting Register (Default Value: 0x0000_FE56)
Offset: 0x019C Register Name: AC_DAC_DRC_MXGHS
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_MXGHS
The max gain setting, which is determined by equation
15:0 R/W 0xFE56
MXGin=MXG/6.0206. The format is 8.24 and must -20 dB < MXG <
30 dB (The default value is -10 dB)
8.4.6.58 0x01A0 DAC DRC MAX Gain Low Setting Register (Default Value: 0x0000_CB0F)
Offset: 0x01A0 Register Name: AC_DAC_DRC_MXGLS
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_MXGLS
The max gain setting, which is determined by equation
15:0 R/W 0xCB0F
MXGin=MXG/6.0206. The format is 8.24 and must -20 dB < MXG <
30 dB (The default value is -10 dB)
8.4.6.59 0x01A4 DAC DRC MIN Gain High Setting Register (Default Value: 0x0000_F95B)
Offset: 0x01A4 Register Name: AC_DAC_DRC_MNGHS
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x01A4 Register Name: AC_DAC_DRC_MNGHS
Bit Read/Write Default/Hex Description
DAC_DRC_MNGHS
The min gain setting, which is determined by equation
15:0 R/W 0xF95B
MXGin=MXG/6.0206. The format is 8.24 and must -60 dB ≤ MNG ≤
-40 dB (The default value is -40 dB)
8.4.6.60 0x01A8 DAC DRC MIN Gain Low Setting Register (Default Value: 0x0000_2C3F)
Offset: 0x01A8 Register Name: AC_DAC_DRC_MNGLS
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_MNGLS
The min gain setting, which is determined by equation
15:0 R/W 0x2C3F
MXGin=MNG/6.0206. The format is 8.24 and must -60 dB ≤ MNG ≤
-40 dB (The default value is -40 dB)
8.4.6.61 0x01AC DAC DRC Expander Smooth Time High Coef Register (Default Value: 0x0000_0000)
Offset: 0x01AC Register Name: AC_DAC_DRC_EPSHC
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_EPSHC
The gain smooth filter release and attack time parameter setting
10:0 R/W 0x0000
in expander region, which are determined by the equation that RT
= 1-exp (-2.2Ts/tr). The format is 3.24. (The default value is 30 ms)
8.4.6.62 0x01B0 DAC DRC Expander Smooth Time Low Coef Register (Default Value: 0x0000_640C)
Offset: 0x01B0 Register Name: AC_DAC_DRC_EPSLC
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x01B0 Register Name: AC_DAC_DRC_EPSLC
Bit Read/Write Default/Hex Description
DAC_DRC_EPSLC
The gain smooth filter release and attack time parameter setting
15:0 R/W 0x640C
in expander region, which are determined by the equation that RT
= 1-exp (-2.2Ts/tr). The format is 3.24. (The default value is 30 ms)
8.4.6.63 0x01B8 DAC DRC HPF Gain High Coef Register (Default Value: 0x0000_0100)
Offset: 0x01B8 Register Name: AC_DAC_DRC_HPFHGAIN
Bit Read/Write Default/Hex Description
31:11 / / /
DAC_DRC_HPFHGAIN
10:0 R/W 0x100
The gain of HPF coefficient. The format is 3.24. (gain = 1)
8.4.6.64 0x01BC DAC DRC HPF Gain Low Coef Register (Default Value: 0x0000_0000)
Offset: 0x01BC Register Name: AC_DAC_DRC_HPFLGAIN
Bit Read/Write Default/Hex Description
31:16 / / /
DAC_DRC_HPFLGAIN
15:0 R/W 0x0000
The gain of HPF coefficient. The format is 3.24. (gain = 1)
8.4.6.65 0x0200 ADC DRC High HPF Coef Register (Default Value: 0x0000_00FF)
Offset: 0x0200 Register Name: AC_ADC_DRC_HHPFC
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_HHPFC
10:0 R/W 0xFF
HPF coefficient setting and the data is 3.24 format.
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8.4.6.66 0x0204 ADC DRC Low HPF Coef Register (Default Value: 0x0000_FAC1)
Offset: 0x0204 Register Name: AC_ADC_DRC_LHPFC
Bit Read/Write Default/Hex Description
31:16 / / /
15:0 R/W 0xFAC1 HPF coefficient setting and the data is 3.24 format.
8.4.6.67 0x0208 ADC DRC Control Register (Default Value: 0x0000_0080)
Offset: 0x0208 Register Name: AC_ADC_DRC_CTRL
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_DELAY_BUF_OUTPUT_STATE
DRC delay buffer data output state when The DRC delay function
is enabled and the DRC function is disabled. After disabled DRC
15 R 0x0 function and this bit goes to 0, the user should write the DRC delay
function bit to 0.
0: Not completed
1: Completed
14:10 / / /
ADC_DRC_SIGNAL_DELAY_TIME_SET
Signal delay time setting
6'h00: (8x1) fs
6'h01: (8x2) fs
6'h02: (8x3) fs
----------------------------------------
13:8 R/W 0x0
6'h2e: (8*47) fs
6'h2f: (8*48) fs
6'h30 -- 6'h3f: (8*48) fs
Delay time = 8*(n + 1) fs, n < 6'h30;
When the delay function is disabled, the signal delay time is
unused.
ADC_DRC_DELAY_BUF_EN
The delay buffer use or not when the DRC is disabled and the DRC
7 R/W 0x1 buffer data output completely.
0: Do not use the buffer
1: Use the buffer
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Offset: 0x0208 Register Name: AC_ADC_DRC_CTRL
Bit Read/Write Default/Hex Description
ADC_DRC_GAIN_MAX_LIMIT_EN
DRC gain max limit enable
6 R/W 0x0
0: Disabled
1: Enabled
ADC_DRC_GAIN_MIN_LIMIT_EN
DRC gain min limit enable
When this fuction is enabled, it will overwrite the noise detect
5 R/W 0x0
function.
0: Disabled
1: Enabled
ADC_DRC_DETECT_NOISE_EN
Control the DRC to detect noise when ET is enabled
4 R/W 0x0
0: Disabled
1: Enabled
ADC_DRC_SIGNAL_FUNC_SEL
Signal function select
0: RMS filter
1: Peak filter
When the signal function selects the Peak filter, the RMS
3 R/W 0x0 parameter is unused. (AC_DRC_LRMSHAT, AC_DRC_LRMSLAT,
AC_DRC_LRMSHAT, and AC_DRC_LRMSLAT)
When the signal function selects the RMS filter, the Peak filter
parameter is unused. (AC_DRC_LPFHAT, AC_DRC_LPFLAT,
AC_DRC_RPFHAT, AC_DRC_RPFLAT, AC_DRC_LPFHRT,
AC_DRC_LPFLRT, AC_DRC_RPFHRT, and AC_DRC_RPFLRT)
ADC_DRC_DELAY_FUNC_EN
Delay function enable
2 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, the signal delay time is unused.
ADC_DRC_LT_EN
DRC LT enable
1 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, Kl and OPL parameter is unused.
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Offset: 0x0208 Register Name: AC_ADC_DRC_CTRL
Bit Read/Write Default/Hex Description
ADC_DRC_ET_EN
DRC ET enable
0 R/W 0x0 0: Disabled
1: Enabled
When the bit is disabled, Ke and OPE parameter is unused.
8.4.6.68 0x020C ADC DRC Left Peak Filter High Attack Time Coef Register (Default Value: 0x0000_000B)
Offset: 0x020C Register Name: AC_ADC_DRC_LPFHAT
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_LPFHAT
The left peak filter attack time parameter setting, which is
10:0 R/W 0x000B
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.69 0x0210 ADC DRC Left Peak Filter Low Attack Time Coef Register (Default Value: 0x0000_77BF)
Offset: 0x0210 Register Name: AC_ADC_DRC_LPFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LPFLAT
The left peak filter attack time parameter setting, which is
15:0 R/W 0x77BF
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.70 0x0214 ADC DRC Right Peak Filter High Attack Time Coef Register (Default Value: 0x0000_000B)
Offset: 0x0214 Register Name: AC_ADC_DRC_RPFHAT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0214 Register Name: AC_ADC_DRC_RPFHAT
Bit Read/Write Default/Hex Description
ADC_DRC_RPFHAT
The right peak filter attack time parameter setting, which is
15:0 R/W 0x000B
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.71 0x0218 ADC DRC Right Peak Filter Low Attack Time Coef Register (Default Value: 0x0000_77BF)
Offset: 0x0218 Register Name: AC_ADC_DRC_RPFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_RPFLAT
The right peak filter attack time parameter setting, which is
15:0 R/W 0x77BF
determined by the equation that AT = 1-exp (-2.2Ts/ta). The format
is 3.24. (The default value is 1 ms)
8.4.6.72 0x021C ADC DRC Left Peak Filter High Release Time Coef Register (Default Value: 0x0000_00FF)
Offset: 0x021C Register Name: AC_ADC_DRC_LPFHRT
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_LPFHRT
The left peak filter release time parameter setting, which is
10:0 R/W 0x00FF
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.73 0x0220 ADC DRC Left Peak Filter Low Release Time Coef Register (Default Value: 0x0000_E1F8)
Offset: 0x0220 Register Name: AC_ADC_DRC_LPFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0220 Register Name: AC_ADC_DRC_LPFLRT
Bit Read/Write Default/Hex Description
ADC_DRC_LPFLRT
The left peak filter release time parameter setting, which is
15:0 R/W 0xE1F8
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.74 0x0224 ADC DRC Right Peak Filter High Release Time Coef Register (Default Value: 0x0000_00FF)
Offset: 0x0224 Register Name: AC_ADC_DRC_RPFHRT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_RPFHRT
The right peak filter release time parameter setting, which is
15:0 R/W 0x00FF
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.75 0x0228 ADC DRC Right Peak Filter Low Release Time Coef Register (Default Value: 0x0000_E1F8)
Offset: 0x0228 Register Name: AC_ADC_DRC_RPFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_RPFLRT
The right peak filter release time parameter setting, which is
15:0 R/W 0xE1F8
determined by the equation that RT = exp (-2.2Ts/tr). The format
is 3.24. (The default value is 100 ms)
8.4.6.76 0x022C ADC DRC Left RMS Filter High Coef Register (Default Value: 0x0000_0001)
Offset: 0x022C Register Name: AC_ADC_DRC_LRMSHAT
Bit Read/Write Default/Hex Description
31:11 / / /
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Offset: 0x022C Register Name: AC_ADC_DRC_LRMSHAT
Bit Read/Write Default/Hex Description
ADC_DRC_LRMSHAT
The left RMS filter average time parameter setting, which is
10:0 R/W 0x0001
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.77 0x0230 ADC DRC Left RMS Filter Low Coef Register (Default Value: 0x0000_2BAF)
Offset: 0x0230 Register Name: AC_ADC_DRC_LRMSLAT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LRMSLAT
The left RMS filter average time parameter setting, which is
15:0 R/W 0x2BAF
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.78 0x0234 ADC DRC Right RMS Filter High Coef Register (Default Value: 0x0000_0001)
Offset: 0x0234 Register Name: AC_ADC_DRC_RRMSHAT
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_RRMSHAT
The right RMS filter average time parameter setting, which is
10:0 R/W 0x0001
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.79 0x0238 ADC DRC Right RMS Filter Low Coef Register (Default Value: 0x0000_2BAF)
Offset: 0x0238 Register Name: AC_ADC_DRC_RRMSLAT
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0238 Register Name: AC_ADC_DRC_RRMSLAT
Bit Read/Write Default/Hex Description
ADC_DRC_RRMSLAT
The right RMS filter average time parameter setting, which is
15:0 R/W 0x2BAF
determined by the equation that AT = 1-exp (-2.2Ts/tav). The
format is 3.24. (The default value is 10 ms)
8.4.6.80 0x023C ADC DRC Compressor Theshold High Setting Register (Default Value: 0x0000_06A4)
Offset: 0x023C Register Name: AC_ADC_DRC_HCT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HCT
The compressor threshold setting, which is set by the equation
15:0 R/W 0x06A4
that CTin = -CT/6.0206. The format is 8.24. (The default value is -
40 dB)
8.4.6.81 0x0240 ADC DRC Compressor Slope High Setting Register (Default Value: 0x0000_D3C0)
Offset: 0x0240 Register Name: AC_ADC_DRC_LCT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LCT
The compressor threshold setting, which is set by the equation
15:0 R/W 0xD3C0
that CTin = -CT/6.0206. The format is 8.24. (The default value is -
40 dB)
8.4.6.82 0x0244 ADC DRC Compressor Slope High Setting Register (Default Value: 0x0000_0080)
Offset: 0x0244 Register Name: AC_ADC_DRC_HKC
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0244 Register Name: AC_ADC_DRC_HKC
Bit Read/Write Default/Hex Description
ADC_DRC_HKC
The slope of the compressor which is determined by the equation
15:0 R/W 0x0080
that Kc = 1/R. R is the ratio of the compressor, which is always an
integer. The format is 8.24. (The default value is <2:1>)
8.4.6.83 0x0248 ADC DRC Compressor Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0248 Register Name: AC_ADC_DRC_LKC
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LKC
The slope of the compressor, which is determined by the equation
15:0 R/W 0x0000
that Kc = 1/R. R is the ratio of the compressor, which is always an
integer. The format is 8.24. (The default value is <2:1>)
8.4.6.84 0x024C ADC DRC Compressor High Output at Compressor Threshold Register (Default Value: 0x0000_F95B)
Offset: 0x024C Register Name: AC_ADC_DRC_HOPC
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HOPC
The output of the compressor, which is determined by the
15:0 R/W 0xF95B
equation -OPC/6.0206. The format is 8.24. (The default value is -40
dB)
8.4.6.85 0x0250 ADC DRC Compressor Low Output at Compressor Threshold Register (Default Value: 0x0000_2C3F)
Offset: 0x0250 Register Name: AC_ADC_DRC_LOPC
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0250 Register Name: AC_ADC_DRC_LOPC
Bit Read/Write Default/Hex Description
ADC_DRC_LOPC
The output of the compressor, which is determined by the
15:0 R/W 0x2C3F
equation OPC/6.0206. The format is 8.24. (The default value is -40
dB)
8.4.6.86 0x0254 ADC DRC Limiter Theshold High Setting Register (Default Value: 0x0000_01A9)
Offset: 0x0254 Register Name: AC_ADC_DRC_HLT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HLT
15:0 R/W 0x01A9 The limiter threshold setting, which is set by the equation that LTin
= -LT/6.0206. The format is 8.24. (The default value is -10 dB)
8.4.6.87 0x0258 ADC DRC Limiter Theshold Low Setting Register (Default Value: 0x0000_34F0)
Offset: 0x0258 Register Name: AC_ADC_DRC_LLT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LLT
15:0 R/W 0x34F0 The limiter threshold setting, which is set by the equation that LTin
= -LT/6.0206. The format is 8.24. (The default value is -10 dB)
8.4.6.88 0x025C ADC DRC Limiter Slope High Setting Register (Default Value: 0x0000_0005)
Offset: 0x025C Register Name: AC_ADC_DRC_HKl
Bit Read/Write Default/Hex Description
31:14 / / /
ADC_DRC_HKl
The slope of the limiter, which is determined by the equation that
13:0 R/W 0x0005
Kl = 1/R. R is the ratio of the limiter, which is always an integer. The
format is 8.24. (The default value is <50:1>)
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8.4.6.89 0x0260 ADC DRC Limiter Slope Low Setting Register (Default Value: 0x0000_1EB8)
Offset: 0x0260 Register Name: AC_ADC_DRC_LKl
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LKl
The slope of the limiter, which is determined by the equation that
15:0 R/W 0x1EB8
Kl = 1/R. R is the ratio of the limiter, which is always an integer. The
format is 8.24. (The default value is <50:1>)
8.4.6.90 0x0264 ADC DRC Limiter High Output at Limiter Threshold Register (Default Value: 0x0000_FBD8)
Offset: 0x0264 Register Name: AC_ADC_DRC_HOPL
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HOPL
15:0 R/W 0xFBD8 The output of the limiter, which is determined by equation
OPT/6.0206. The format is 8.24. (The default value is -25 dB)
8.4.6.91 0x0268 ADC DRC Limiter Low Output at Limiter Threshold Register (Default Value: 0x0000_FBA7)
Offset: 0x0268 Register Name: AC_ADC_DRC_LOPL
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LOPL
15:0 R/W 0xFBA7 The output of the limiter which is determined by equation
OPT/6.0206. The format is 8.24. (The default value is -25 dB)
8.4.6.92 0x026C ADC DRC Expander Theshold High Setting Register (Default Value: 0x0000_0BA0)
Offset: 0x026C Register Name: AC_ADC_DRC_HET
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x026C Register Name: AC_ADC_DRC_HET
Bit Read/Write Default/Hex Description
ADC_DRC_HET
15:0 R/W 0x0BA0 The expander threshold setting, which is set by the equation that
ETin = -ET/6.0206, The format is 8.24. (The default value is -70 dB)
8.4.6.93 0x0270 ADC DRC Expander Theshold Low Setting Register (Default Value: 0x0000_7291)
Offset: 0x0270 Register Name: AC_ADC_DRC_LET
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LET
15:0 R/W 0x7291 The expander threshold setting, which is set by the equation that
ETin = -ET/6.0206, The format is 8.24. (The default value is -70 dB)
8.4.6.94 0x0274 ADC DRC Expander Slope High Setting Register (Default Value: 0x0000_0500)
Offset: 0x0274 Register Name: AC_ADC_DRC_HKE
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HKE
The slope of the expander, which is determined by the equation
15:0 R/W 0x0500 that Ke = 1/R. R is the ratio of the expander, which is always an
integer and the ke must larger than 50. The format is 8.24. (The
default value is <1:5>)
8.4.6.95 0x0278 ADC DRC Expander Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0278 Register Name: AC_ADC_DRC_LKE
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x0278 Register Name: AC_ADC_DRC_LKE
Bit Read/Write Default/Hex Description
ADC_DRC_LKE
The slope of the expander, which is determined by the equation
15:0 R/W 0x0000 that Ke = 1/R. R is the ratio of the expander, which is always an
integer and the ke must be larger than 50. The format is 8.24. (The
default value is <1:5>)
8.4.6.96 0x027C ADC DRC Expander High Output at Expander Threshold Register (Default Value: 0x0000_F45F)
Offset: 0x027C Register Name: AC_ADC_DRC_HOPE
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HOPE
15:0 R/W 0xF45F The output of the expander, which is determined by equation
OPE/6.0206. The format is 8.24. (The default value is -70 dB)
8.4.6.97 0x0280 ADC DRC Expander Low Output at Expander Threshold Register (Default Value: 0x0000_8D6E)
Offset: 0x0280 Register Name: AC_ADC_DRC_LOPE
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LOPE
15:0 R/W 0x8D6E The output of the expander, which is determined by equation
OPE/6.0206. The format is 8.24. (The default value is -70 dB)
8.4.6.98 0x0284 ADC DRC Linear Slope High Setting Register (Default Value: 0x0000_0100)
Offset: 0x0284 Register Name: AC_ADC_DRC_HKN
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HKN
The slope of the linear, which is determined by the equation that
15:0 R/W 0x0100
Kn = 1/R. R is the ratio of the linear, which is always an integer. The
format is 8.24. (The default value is <1:1>)
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8.4.6.99 0x0288 ADC DRC Linear Slope Low Setting Register (Default Value: 0x0000_0000)
Offset: 0x0288 Register Name: AC_ADC_DRC_LKN
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_LKN
The slope of the linear, which is determined by the equation that
15:0 R/W 0x0000
Kn = 1/R. R is the ratio of the linear, which is always an integer. The
format is 8.24. (The default value is <1:1>)
8.4.6.100 0x028C ADC DRC Smooth Filter Gain High Attack Time Coef Register (Default Value: 0x0000_0002)
Offset: 0x028C Register Name: AC_ADC_DRC_SFHAT
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_SFHAT
The smooth filter attack time parameter setting, which is
10:0 R/W 0x0002
determined by the equation that AT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 5 ms)
8.4.6.101 0x0290 ADC DRC Smooth Filter Gain Low Attack Time Coef Register (Default Value: 0x0000_5600)
Offset: 0x0290 Register Name: AC_ADC_DRC_SFLAT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_SFLAT
The smooth filter attack time parameter setting, which is
15:0 R/W 0x5600
determined by the equation that AT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 5 ms)
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8.4.6.102 0x0294 ADC DRC Smooth Filter Gain High Release Time Coef Register (Default Value: 0x0000_0000)
Offset: 0x0294 Register Name: AC_ADC_DRC_SFHRT
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_SFHRT
The gain smooth filter release time parameter setting, which is
10:0 R/W 0x0000
determined by the equation that RT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 200 ms)
8.4.6.103 0x0298 ADC DRC Smooth Filter Gain Low Release Time Coef Register (Default Value: 0x0000_0F04)
Offset: 0x0298 Register Name: AC_ADC_DRC_SFLRT
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_SFLRT
The gain smooth filter release time parameter setting, which is
15:0 R/W 0x0F04
determined by the equation that RT = 1-exp (-2.2Ts/tr). The format
is 3.24. (The default value is 200 ms)
8.4.6.104 0x029C ADC DRC MAX Gain High Setting Register (Default Value: 0x0000_FE56)
Offset: 0x029C Register Name: AC_ADC_DRC_MXGHS
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_MXGHS
The max gain setting, which is determined by equation
15:0 R/W 0xFE56
MXGin=MXG/6.0206. The format is 8.24 and must -20 dB < MXG <
30 dB (The default value is -10 dB)
8.4.6.105 0x02A0 ADC DRC MAX Gain Low Setting Register (Default Value: 0x0000_CB0F)
Offset: 0x02A0 Register Name: AC_ADC_DRC_MXGLS
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset: 0x02A0 Register Name: AC_ADC_DRC_MXGLS
Bit Read/Write Default/Hex Description
ADC_DRC_MXGLS
The max gain setting, which is determined by equation
15:0 R/W 0xCB0F
MXGin=MXG/6.0206. The format is 8.24 and must -20 dB < MXG <
30 dB (The default value is -10 dB)
8.4.6.106 0x02A4 ADC DRC MIN Gain High Setting Register (Default Value: 0x0000_F95B)
Offset: 0x02A4 Register Name: AC_ADC_DRC_MNGHS
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_MNGHS
The min gain setting, which is determined by equation
15:0 R/W 0xF95B
MXGin=MXG/6.0206. The format is 8.24 and must -60 dB ≤ MNG ≤
-40 dB (The default value is -40 dB)
8.4.6.107 0x02A8 ADC DRC MIN Gain Low Setting Register (Default Value: 0x0000_2C3F)
Offset: 0x02A8 Register Name: AC_ADC_DRC_MNGLS
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_MNGLS
The min gain setting, which is determined by equation
15:0 R/W 0x2C3F
MXGin=MNG/6.0206. The format is 8.24 and must -60 dB ≤ MNG ≤
-40 dB (The default value is -40 dB)
8.4.6.108 0x02AC ADC DAP Expander Smooth Time High Coef Register (Default Value: 0x0000_0000)
Offset: 0x02AC Register Name: AC_ADC_DRC_EPSHC
Bit Read/Write Default/Hex Description
31:11 / / /
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Offset: 0x02AC Register Name: AC_ADC_DRC_EPSHC
Bit Read/Write Default/Hex Description
ADC_DRC_EPSHC
The gain smooth filter release and attack time parameter setting
10:0 R/W 0x0000
in expander region, which is determined by the equation that RT =
1-exp (-2.2Ts/tr). The format is 3.24. (The default value is 30 ms)
8.4.6.109 0x02B0 ADC DRC Expander Smooth Time Low Coef Register (Default Value: 0x0000_640C)
Offset: 0x02B0 Register Name: AC_ADC_DRC_EPSLC
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_EPSLC
The gain smooth filter release and attack time parameter setting
15:0 R/W 0x640C
in expander region, which is determined by the equation that RT =
1-exp (-2.2Ts/tr). The format is 3.24. (The default value is 30 ms)
8.4.6.110 0x02B8 ADC DRC HPF Gain High Coef Register (Default Value: 0x0000_0100)
Offset: 0x02B8 Register Name: AC_ADC_DRC_HPFHGAIN
Bit Read/Write Default/Hex Description
31:11 / / /
ADC_DRC_HPFHGAIN
10:0 R/W 0x100
The gain of HPF coefficient setting, which format is 3.24. (gain = 1)
8.4.6.111 0x02BC ADC DRC HPF Gain Low Coef Register (Default Value: 0x0000_0000)
Offset: 0x02BC Register Name: AC_ADC_DRC_HPFLGAIN
Bit Read/Write Default/Hex Description
31:16 / / /
ADC_DRC_HPFLGAIN
15:0 R/W 0x0000
The gain of HPF coefficient setting, which format is 3.24. (gain = 1)
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8.4.6.112 0x0300 ADC1 Analog Control Register (Default Value: 0x001C_C055)
Offset: 0x0300 Register Name: ADC1_REG
Bit Read/Write Default/Hex Description
ADC1_EN
ADC1 Channel Enable
31 R/W 0x0
0: Disabled
1: Enabled
30 R/W 0x0 Reserved
ADC1 Dither Control
29 R/W 0x0 0: New Dither Off
1: New Dither On
28 R/W 0x0 Reserved
FMINLEN
FMINL Enable
27 R/W 0x0
0: Disable
1: Enable
FMINLG
FMINL Gain Control
26 R/W 0x0
0: 0 dB
1: 6 dB
DSM_DITHER_LVL
Dither Level Control (Dither level is positive ralated to the ctrl bits)
00: No Level
25:24 R/W 0x0
01: Min Level
10: Middle Level
11: Max Level
LINEINLEN
LINEINL Enable
23 R/W 0x0
0: Disable
1: Enable
LINEINLG
LINEINL Gain Control
22 R/W 0x0
0: 0 dB
1: 6 dB
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Offset: 0x0300 Register Name: ADC1_REG
Bit Read/Write Default/Hex Description
IOPBUFFER
PGA Vcm Buffer OP Bias Current Select
00: 6 uA
21:20 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
ADC1_PGA_CTRL_RCM
ADC1 PGA Common Mode Input Impedance Control for MICIN
00: 100 kΩ
19:18 R/W 0x3
01: 75 kΩ
10: 50 kΩ
11: 25 kΩ
ADC1_PGA_IN_VCM_CTRL
ADC1 PGA Common-Mode Voltage Control
00: 900 mV
17:16 R/W 0x0
01: 800 mV
10: 750 mV
11: 700 mV
IOPADC
ADC1-ADC3 Bias Current Select
00: 1 uA
15:14 R/W 0x3
01: 2 uA
10: 3 uA
11: 4 uA
13 / / /
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Offset: 0x0300 Register Name: ADC1_REG
Bit Read/Write Default/Hex Description
ADC1_PGA_GAIN_CTRL
ADC1 PGA gain settings:
0x0: 0 dB 0x10: 21 dB
0x1: 6 dB 0x11: 22 dB
0x2: 6 dB 0x12: 23 dB
0x3: 6 dB 0x13: 24 dB
0x4: 9 dB 0x14: 25 dB
0x5: 10 dB 0x15: 26 dB
0x6: 11 dB 0x16: 27 dB
12:8 R/W 0x0
0x7: 12 dB 0x17: 28 dB
0x8: 13 dB 0x18: 29 dB
0x9: 14 dB 0x19: 30 dB
0xA: 15 dB 0x1A: 31 dB
0xB: 16 dB 0x1B: 32 dB
0xC: 17 dB 0x1C: 33 dB
0xD: 18 dB 0x1D: 34 dB
0xE: 19 dB 0x1E: 35 dB
0xF: 20 dB 0x1F: 36 dB
ADC1_IOPAAF
ADC1 OP AAF Bias Current Select
00: 1.50*IOPADC
01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
7:6 R/W 0x1 IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
For example:
ADC1_REG<15:14> = 11, IOPADC = 4 uA
00: 1.50*4 uA = 6 uA
01: 1.75*4 uA = 7 uA
10: 2.00*4 uA = 8 uA
11: 2.25*4 uA = 9 uA
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Offset: 0x0300 Register Name: ADC1_REG
Bit Read/Write Default/Hex Description
ADC1_IOPSDM1
ADC1 OP SDM Bias Current Select 1
00: 1.50*IOPADC
5:4 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC1_IOPSDM2
ADC1 OP SDM Bias Current Select 2
00: 1.50*IOPADC
3:2 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC1_IOPMIC
ADC1 OP MIC Bias Current Select
00: 1.50*IOPADC
1:0 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
8.4.6.113 0x0304 ADC2 Analog Control Register (Default Value: 0x001C_0055)
Offset: 0x0304 Register Name: ADC2_REG
Bit Read/Write Default/Hex Description
ADC2_EN
ADC2 Channel Enable
31 R/W 0x0
0: Disabled
1: Enabled
30 R/W 0x0 Reserved
ADC2 Dither Control
29 R/W 0x0 0: New Dither Off
1: New Dither On
28 R/W 0x0 Reserved
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Offset: 0x0304 Register Name: ADC2_REG
Bit Read/Write Default/Hex Description
FMINREN
FMINR Enable
27 R/W 0x0
0: Disable
1: Enable
FMINRG
FMINR Gain Control
26 R/W 0x0
0: 0 dB
1: 6 dB
DSM_DITHER_LVL
Dither Level Control (Dither level is positive ralated to the ctrl bits)
00: No Level
25:24 R/W 0x0
01: Min Level
10: Middle Level
11: Max Level
LINEINREN
LINEINR Enable
23 R/W 0x0
0: Disable
1: Enable
LINEINRG
LINEINR Gain Control
22 R/W 0x0
0: 0 dB
1: 6 dB
IOPBUFFER
PGA Vcm Buffer OP Bias Current Select
00: 6 uA
21:20 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
ADC2_PGA_CTRL_RCM
ADC2 PGA Common Mode Input Impedance Control for MICIN
00: 100 kΩ
19:18 R/W 0x3
01: 75 kΩ
10: 50 kΩ
11: 25 kΩ
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Offset: 0x0304 Register Name: ADC2_REG
Bit Read/Write Default/Hex Description
ADC2_PGA_IN_VCM_CTRL
ADC2 PGA Common-Mode Voltage Control
00: 900 mV
17:16 R/W 0x0
01: 800 mV
10: 750 mV
11: 700 mV
15:13 / / /
ADC2_PGA_GAIN_CTRL
ADC2 PGA Gain Settings
0x0: 0 dB 0x10: 21 dB
0x1: 6 dB 0x11: 22 dB
0x2: 6 dB 0x12: 23 dB
0x3: 6 dB 0x13: 24 dB
0x4: 9 dB 0x14: 25 dB
0x5: 10 dB 0x15: 26 dB
0x6: 11 dB 0x16: 27 dB
12:8 R/W 0x0
0x7: 12 dB 0x17: 28 dB
0x8: 13 dB 0x18: 29 dB
0x9: 14 dB 0x19: 30 dB
0xA: 15 dB 0x1A: 31 dB
0xB: 16 dB 0x1B: 32 dB
0xC: 17 dB 0x1C: 33 dB
0xD: 18 dB 0x1D: 34 dB
0xE: 19 dB 0x1E: 35 dB
0xF: 20 dB 0x1F: 36 dB
ADC2_IOPAAF
ADC2 OP AAF Bias Current Select
00: 1.50*IOPADC
7:6 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
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Offset: 0x0304 Register Name: ADC2_REG
Bit Read/Write Default/Hex Description
ADC2_IOPSDM1
ADC2 OP SDM Bias Current Select 1
00: 1.50*IOPADC
5:4 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC2_IOPSDM2
ADC2 OP SDM Bias Current Select 2
00: 1.50*IOPADC
3:2 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC2_IOPMIC
ADC2 OP MIC Bias Current Select
00: 1.50*IOPADC
1:0 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
8.4.6.114 0x0308 ADC3 Analog Control Register (Default Value: 0x001C_0055)
Offset: 0x0308 Register Name: ADC3_REG
Bit Read/Write Default/Hex Description
ADC3_EN
ADC3 Channel Enable
31 R/W 0x0
0: Disabled
1: Enabled
MIC3_PGA_EN
MIC3 PGA Enable
30 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0308 Register Name: ADC3_REG
Bit Read/Write Default/Hex Description
ADC3 Dither Control
29 R/W 0x0 0: New Dither Off
1: New Dither On
MIC3_SIN_EN
MIC3 Single Input Enable
28 R/W 0x0
0: Disabled
1: Enabled
27:26 / / /
DSM_DITHER_LVL
Dither Level Control (Dither level is positive ralated to the ctrl bits)
00: No Level
25:24 R/W 0x0
01: Min Level
10: Middle Level
11: Max Level
23:22 / / /
IOPBUFFER
PGA Vcm Buffer OP Bias Current Select
00: 6 uA
21:20 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
ADC3_PGA_CTRL_RCM
ADC3 PGA Common Mode Input Impedance Control for MICIN
00: 100 kΩ
19:18 R/W 0x3
01: 75 kΩ
10: 50 kΩ
11: 25 kΩ
ADC3_PGA_IN_VCM_CTRL
ADC3 PGA Common-Mode Voltage Control
00: 900 mV
17:16 R/W 0x0
01: 800 mV
10: 750 mV
11: 700 mV
15:13 / / /
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Offset: 0x0308 Register Name: ADC3_REG
Bit Read/Write Default/Hex Description
ADC3_PGA_GAIN_CTRL
ADC3 PGA Gain Settings
0x0: 0 dB 0x10: 21 dB
0x1: 6 dB 0x11: 22 dB
0x2: 6 dB 0x12: 23 dB
0x3: 6 dB 0x13: 24 dB
0x4: 9 dB 0x14: 25 dB
0x5: 10 dB 0x15: 26 dB
0x6: 11 dB 0x16: 27 dB
12:8 R/W 0x0
0x7: 12 dB 0x17: 28 dB
0x8: 13 dB 0x18: 29 dB
0x9: 14 dB 0x19: 30 dB
0xA: 15 dB 0x1A: 31 dB
0xB: 16 dB 0x1B: 32 dB
0xC: 17 dB 0x1C: 33 dB
0xD: 18 dB 0x1D: 34 dB
0xE: 19 dB 0x1E: 35 dB
0xF: 20 dB 0x1F: 36 dB
ADC3_IOPAAF
ADC3 OP AAF Bias Current Select
00: 1.50*IOPADC
7:6 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC3_IOPSDM1
ADC3 OP SDM Bias Current Select 1
00: 1.50*IOPADC
5:4 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
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Offset: 0x0308 Register Name: ADC3_REG
Bit Read/Write Default/Hex Description
ADC3_IOPSDM2
ADC3 OP SDM Bias Current Select 2
00: 1.50*IOPADC
3:2 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC3_IOPMIC
ADC3 OP MIC Bias Current Select
00: 1.50*IOPADC
1:0 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
8.4.6.115 0x0310 DAC Analog Control Register (Default Value: 0x0015_0000)
Offset: 0x0310 Register Name: DAC_REG
Bit Read/Write Default/Hex Description
31:24 / / /
CURRENT_TEST_SELECT
Internal Current Sink Test Enable (from MICIN3P pin)
23 R/W 0x0
0: Normal
1: For Debug
22 / / /
IOPVRS
VRA2 Buffer OP and Headphone Feedback Buffer OP Bias Current
Select
21:20 R/W 0x1 00: 6 uA
01: 7 uA
10: 8 uA
11: 9 uA
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Offset: 0x0310 Register Name: DAC_REG
Bit Read/Write Default/Hex Description
ILINEOUTAMPS
LINEOUTLL/R AMP Bias Current Select
00: 6 uA
19:18 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
IOPDACS
OPDACL/R Bias Current Select
00: 6 uA
17:16 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
DACL_EN
DACL Enable
15 R/W 0x0
0: Disabled
1: Enabled
DACR_EN
DACR Enable
14 R/W 0x0
0: Disabled
1: Enabled
LINEOUTLEN
Left Channel LINEOUT Enable
13 R/W 0x0
0: Disable
1: Enable
LMUTE
DACL to Left Channel LINEOUT Mute Control
12 R/W 0x0
0: Mute
1: Not mute
LINEOUTREN
Right Channel LINEOUT Enable
11 R/W 0x0
0: Disable
1: Enable
RMUTE
DACR to Right Channel LINEOUT Mute Control
10 R/W 0x0
0: Mute
1: Not mute
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Offset: 0x0310 Register Name: DAC_REG
Bit Read/Write Default/Hex Description
9:7 / / /
LINEOUTL_DIFFEN
Left Channel LINEOUT Output Control
6 R/W 0x0
0: Single-End
1: Differential
LINEOUTR_DIFFEN
Right Channel LINEOUT Output Control
5 R/W 0x0
0: Single-End
1: Differential
LINEOUT_VOL_CTRL
4:0 R/W 0x0 LINEOUT Volume Control. Total 30 level from 0x1F to 0x02 with the
volume 0 dB to -43.5 dB, -1.5 dB/step, mute when 00000 & 00001.
8.4.6.116 0x0318 MICBIAS Analog Control Register (Default Value: 0x4000_3030)
Offset: 0x0318 Register Name: MICBIAS_REG
Bit Read/Write Default/Hex Description
31 / / /
SELDETADCFS
Select sample interval of the ADC sample
000: 2 ms
30:28 R/W 0x4 …
100: 32 ms
…
111: 256 ms
SELDETADCDB
Select debounce time when jack removal
00: 128 ms
27:26 R/W 0x0
01: 256 ms
10: 512 ms
11: 1024 ms
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Offset: 0x0318 Register Name: MICBIAS_REG
Bit Read/Write Default/Hex Description
SELDETADCBF
Select the time to enable HBIAS before MICADC work
00: 2 ms
25:24 R/W 0x0
01: 4 ms
10: 8 ms
11: 16 ms
JACKDETEN
Jack detect enable
23 R/W 0x0
0: Disable
1: Enable
SELDETADCDY
Select the delay time to pull low the micdet when jack removal
00: 0.5 ms
22:21 R/W 0x0
01: 1 ms
10: 1.5 ms
11: 2 ms
MICADCEN
Microphone detect ADC enable
20 R/W 0x0
0: Disabled
1: Enabled
POPFREE
19 R/W 0x0
When this bit is 0, HBIAS MICADC is controlled by registor
DET_MODE
MIC Detect Mode
18 R/W 0x0
0: Jack in pull low
1: Jack in pull high
AUTOPLEN
Enable the function to auto pull low MICDET when jack removal
17 R/W 0x0
0: Disabled
1: Enabled
MICDETPL
16 R/W 0x0 When this bit is 1and AUTOPLEN is 0, the MICDET is pulled down
to GND.
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Offset: 0x0318 Register Name: MICBIAS_REG
Bit Read/Write Default/Hex Description
HMICBIASEN
Headphone Microphone Bias Enable
15 R/W 0x0
0: Disabled
1: Enabled
HBIASSEL
HMICBIAS Voltage Level Select
00: 1.88 V
14:13 R/W 0x1
01: 2.09 V
10: 2.33 V
11: 2.55 V
HMIC_BIAS_CHOPPER_EN
HMIC BIAS Chopper Enable
12 R/W 0x1
0: Disabled
1: Enabled
HMIC_BIAS_CHOPPER_CLK_SEL
HMIC BIAS Chopper Clock Select
00: 250 kHz
11:10 R/W 0x0
01: 500 kHz
10: 1 MHz
11: 2 MHz
9:8 / / /
MMICBIASEN
Master Microphone Bias Enable
7 R/W 0x0
0: Disabled
1: Enabled
MBIASSEL
MMICBIAS Voltage Level Select
00: 1.88 V
6:5 R/W 0x1
01: 2.09 V
10: 2.33 V
11: 2.50 V
MMIC_BIAS_CHOPPER_EN
MMIC BIAS Chopper Enable
4 R/W 0x1
0: Disabled
1: Enabled
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Offset: 0x0318 Register Name: MICBIAS_REG
Bit Read/Write Default/Hex Description
MMIC_BIAS_CHOPPER_CLK_SEL
MMIC BIAS Chopper Clock Select
00: 250 kHz
3:2 R/W 0x0
01: 500 kHz
10: 1 MHz
11: 2 MHz
1:0 / / /
8.4.6.117 0x031C Ramp Control Register (Default Value: 0x0018_0000)
Offset: 0x031C Register Name: RAMP_REG
Bit Read/Write Default/Hex Description
RAMP_RISE_INT_EN
RAMP Rise Interrupt Enable
31 R/W 0x0
0: Enabled
1: Disabled
RAMP_RISE_INT
RK Increase Upward Finish and Rampen Pull Down Instruction
30 R/W1C 0x0 0: No Pending IRQ
1: Ramp Rise Finish Pending Interrupt
Write ‘1’ to clear this interrupt.
RAMP_FALL_INT_EN
RAMP Fall Int Enable
29 R/W 0x0
0: Enabled
1: Disabled
RAMP_FALL_INT
RK Downward Decrease Finish and Rampen Pull Down
Instruction
28 R/W1C 0x0
0: No Pending IRQ
1: Ramp Fall Finish Pending Interrupt
Write ‘1’ to clear this interrupt.
27:25 / / /
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Offset: 0x031C Register Name: RAMP_REG
Bit Read/Write Default/Hex Description
RAMP_SRST
Ramp Soft Reset
24 R/W 0x0
0: Disabled
1: Enabled
23:21 / / /
RAMP_CLK_DIV_M
Analog Ramp Clk Div Freq Value : M (from 0 to 31, Default: 24).
20:16 R/W 0x18
Ana_Ramp_Clk= 24MHz/(M+1)
Default Ramp Clk Freq: 24MHz/(24+1)=960 kHz
HP_PULL_OUT_EN
Heanphone Pullout Enable
15 R/W 0x0
0: Disabled
1: Enabled
RAMP_HOLD_STEP
RAMP HOLD STEP
000: 9600
001: 19200
010: 38400
011: 76800
100: 96000
101: 115200
110: 153600
111: 192000
14:12 R/W 0x0
Ramp Hold Time = Ramp Hold Step/Ramp Clk Freq
When Ramp Clk Freq is equal to 960 kHz, the corresponding
Ramp Hold time of each gear is:
000: 9600/960 kHz=10 ms
001: 19200/960 kHz=20 ms
010: 38400/960 kHz=40 ms
011: 76800/960 kHz=80 ms
100: 96000/960 kHz=100 ms
101: 115200/960 kHz=120 ms
110: 153600/960 kHz=160 ms
111: 192000/960 kHz=200 ms
11:10 / / /
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Offset: 0x031C Register Name: RAMP_REG
Bit Read/Write Default/Hex Description
GAP_STEP
Gap Step
00: ramp step
9:8 R/W 0x0
01: ramp step*2
10: ramp step*3
11: ramp step*4
7 / / /
RAMP_STEP
RK Frequency Gear, Control Ramp Rise/Fall Total Time
000: 20
001: 30
010: 40
011: 60
100: 80
101: 120
110: 160
111: 240
6:4 R/W 0x0
Ramp Rise/Fall Total Time =(Ramp Step/Ramp Clk Freq)*4096
When Default Ramp Clk Freq is equal to 960 kHz, the
corresponding time of each gear is:
000: (20/960kHz)*4096=85.3 ms
001: (30/960kHz)*4096=128 ms
010: (40/960kHz)*4096=170.6 ms
011: (60/960kHz)*4096=256 ms
100: (80/960kHz)*4096=341.3 ms
101: (120/960kHz)*4096=512 ms
110: (160/960kHz)*4096=682.6 ms
111: (240/960kHz)*4096=1024 ms
RMD_EN
Ramp Manual Down Enable
3 R/W 0x0
0: Disabled
1: Enabled
RMU_EN
Ramp Manual Up Enable
2 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x031C Register Name: RAMP_REG
Bit Read/Write Default/Hex Description
RMC_EN
Ramp Manual Control Enable
1 R/W 0x0
0: Disabled
1: Enabled
RD_EN
Ramp Digital Enable
0 R/W 0x0
0: Disabled
1: Enabled
8.4.6.118 0x0320 BIAS Analog Control Register (Default Value: 0x0000_0080)
The register is not controlled by the clock and reset of Audio Codec, only controlled by the clock and reset of
system bus.
Offset: 0x0320 Register Name: BIAS_REG
Bit Read/Write Default/Hex Description
31:8 / / /
BIASDATA
7:0 R/W 0x80
Bias Current Register Setting Data
8.4.6.119 0x0328 HMIC Control Register (Default Value: 0x0000_0008)
Offset: 0x0328 Register Name: HMIC_CTRL
Bit Read/Write Default/Hex Description
31:23 / / /
HMIC_SAMPLE_SELECT
Down Sample Setting Select
00: Down by 1, 128 Hz
22:21 R/W 0x0
01: Down by 2, 64 Hz
10: Down by 4, 32 Hz
11: Down by 8, 16 Hz
MDATA_THRESHOLD
20:16 R/W 0x0
MIC DET EN Threshold Value
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Offset: 0x0328 Register Name: HMIC_CTRL
Bit Read/Write Default/Hex Description
HMIC_SF
HMIC Smooth Filter setting
00: by pass
15:14 R/W 0x0
01: (x1+x2)/2
10: (x1+x2+x3+x4)/4
11: (x1+x2+x3+x4+ x5+x6+x7+x8)/8
HMIC_M
Debounce when the MIC Key down or up.
0000 :1 samlpe data
13:10 R/W 0x0
0001 :2 samlpe data
...
1111 :16 samlpe data
HMIC_N
Debounce when earphone plug in or pull out
125 ms to 2 s
9:6 R/W 0X0 0000:125 ms
0001:250 ms
…
1111:2 s
MDATA_THRESHOLD_DEBOUNCE
MDATA Threshold Debounce
000: 0
001: 1
010: 2
5:3 R/W 0x1
011: 3
100: 4
101: 5
110: 6
111: 7
JACK_OUT_IRQ_EN
MIC Detect Interrupt Set
2 R/W 0x0
0: Disabled
1: Enabled
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Offset: 0x0328 Register Name: HMIC_CTRL
Bit Read/Write Default/Hex Description
JACK_IN_IRQ_EN
MIC Detect Interrupt Set
1 R/W 0x0
0: Disabled
1: Enabled
MIC_DET_IRQ_EN
MIC Detect Interrupt Set
0 R/W 0x0
0: Disabled
1: Enabled
8.4.6.120 0x032C HMIC Status Register (Default Value: 0x0000_6000)
Offset: 0x032C Register Name: HMIC_STS
Bit Read/Write Default/Hex Description
31:15 / / /
MDATA_DISCARD
After MIC DATA data is received, the first N-data will be discarded.
N defined as follows:
14:13 R/W 0x3 00: None discarded
01: 1-data discarded
10: 2-data discarded
11: 4-data discarded
HMIC_DATA
12:8 R 0x0
HMIC Average Data
7:5 / / /
JACK_DET_OIRQ
Jack output detect pending interrupt
4 R/W1C 0x0 0: No Pending IRQ
1: Pending IRQ
Writing 1 clear pending.
JACK_DET_IIRQ
Jack input detect pending interrupt
3 R/W1C 0x0 0: No Pending IRQ
1: Pending IRQ
Writing 1 clear pending.
2:1 / / /
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Offset: 0x032C Register Name: HMIC_STS
Bit Read/Write Default/Hex Description
MIC_DET_ST
MIC detect pending interrupt
0 R/W1C 0x0 0: No pending IRQ
1: Pending IRQ
Writing 1 clear pending.
8.4.6.121 0x0340 Headphone2 Analog Control Register (Default Value: 0x0640_4000)
Offset: 0x0340 Register Name: HP2_REG
Bit Read/Write Default/Hex Description
HPFB_BUF_EN
Headphone Feedback Buffer OP Enable
31 R/W 0x0
0: Disable
1: Enable
HEADPHONE_GAIN
HeadPhone Gain
000: 0 dB
001: -6 dB
010: -12 dB
30:28 R/W 0x0
011: -18 dB
100: -24 dB
101: -30 dB
110: -36 dB
111: -42 dB
HPFB_RES
Headphone Feedback Big Resistor Control
00: 0.88 MΩ
27:26 R/W 0x1
01: 1.00 MΩ
10: 1.08 MΩ
11: 1.20 MΩ
OPDRV_CUR
Headphone OP Output Stage Current Setting
25:24 R/W 0x2
00: Min
11: Max
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Offset: 0x0340 Register Name: HP2_REG
Bit Read/Write Default/Hex Description
IOPHP
Headphone L/R OP Bias Current Select
00: 6 uA
23:22 R/W 0x1
01: 7 uA
10: 8 uA
11: 9 uA
HP_DRVEN
Headphone Driver Enable
21 R/W 0x0
0: Disable
1: Enable
HP_DRVOUTEN
Headphone Driver Output Enable
20 R/W 0x0
0: Disabled
1: Enabled
RSWITCH
RSwitch
19 R/W 0x0
0: HPOUT OUTPUT VCM of RAMP_DAC
1: VRA1
RAMPEN
Ramp DAC Enable
18 R/W 0x0
0: Disabled
1: Enabled
HPFB_IN_EN
Headphone Feedback PAD IN Switch Enable
17 R/W 0x0
0: Disabled
1: Enabled
RAMP_FINAL_CONTROL
Headphone Ramp Final Step Control
16 R/W 0x0
0: Ramp Output Select Ramp
1: Ramp Output Select HPFB buffer Output
RAMP_OUT_EN
Ramp Output Switch Enable
15 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0340 Register Name: HP2_REG
Bit Read/Write Default/Hex Description
RAMP_FINAL_STATE_RES
Ramp Final State Resistor
00: 2.5k
14:13 R/W 0x2
01: 5.0k
10: 10k
11: 20k
HPFB_BUF_OUTPUT_CURRENT
Headphone Feedback Buffer Output Current Select
00: 35I
9:8 R/W 0x0 01: 28I
10: 45I
11: 38I
I=7 uA
7:0 / / /
8.4.6.122 0x0348 POWER Analog Control Register (Default Value: 0x8000_3325)
The register is not controlled by the clock and reset of Audio Codec, only controlled by the clock and reset of
system bus.
Offset: 0x0348 Register Name: POWER_REG
Bit Read/Write Default/Hex Description
ALDO_EN
ALDO Enable
31 R/W 0x1
0: Disabled
1: Enabled
HPLDO_EN
HPLDO Enable
30 R/W 0x0
0: Disabled
1: Enabled
VAR1SPEEDUP_DOWN_Further_CTRL
VAR1 Speedup Down Further Control In Adda Analog
0: The digital logic signal input by the digital-analog interface pin
29 R/W 0x0 controls the var1_speedup_down function (that is, the var1 signal
is rapidly pulled up/down)
1: Writing 1 can finish the var1_speedup_down function (ignore
the control of the digital-analog interface pin)
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Offset: 0x0348 Register Name: POWER_REG
Bit Read/Write Default/Hex Description
28:17 / / /
AVCCPOR
16 R 0x0
Avccpor Monitor
15 / / /
ALDO_OUTPUT_VOLTAGE
ALDO Output Voltage Control
000: 2.03 V
001: 1.95 V
010: 1.87 V
14:12 R/W 0x3 011: 1.80 V
100: 1.73 V
101: 1.67 V
110: 1.61 V
111: 1.56 V
11 / / /
HPLDO_OUTPUT_VOLTAGE
HPLDO Output Voltage Control
000: 2.03 V
001: 1.95 V
010: 1.87 V
10:8 R/W 0x3 011: 1.80 V
100: 1.73 V
101: 1.67 V
110: 1.61 V
111: 1.56 V
BG_TRIM
BG Output Voltage Trimming
7:0 R/W 0x25
Only low 6-bit is used. The BG output voltage range is from 0.7 V
to 1.208 V.
8.4.6.123 0x034C ADC Current Analog Control Register (Default Value: 0x0015_1515)
Offset: 0x034C Register Name: ADC_CUR_REG
Bit Read/Write Default/Hex Description
31:22 / / /
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Offset: 0x034C Register Name: ADC_CUR_REG
Bit Read/Write Default/Hex Description
ADC3_IOPMIC2
ADC3 OP MIC2 Bias Current Select
00: 1.50*IOPADC
21:20 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA
ADC3_OUTPUT_CURRENT
ADC3 OP MIC1 Output Current Select
00: 15I
19:18 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
ADC3_OUTPUT_CURRENT
ADC3 OP MIC2 Output Current Select
00: 15I
17:16 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
15:14 / / /
ADC2_IOPMIC2
ADC2 OP MIC2 Bias Current Select
00: 1.50*IOPADC
13:12 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC2_OUTPUT_CURRENT
ADC2 OP MIC1 Output Current Select
00: 15I
11:10 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
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Offset: 0x034C Register Name: ADC_CUR_REG
Bit Read/Write Default/Hex Description
ADC2_OUTPUT_CURRENT
ADC2 OP MIC2 Output Current Select
00: 15I
9:8 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
7:6 / / /
ADC1_IOPMIC2
ADC1 OP MIC2 Bias Current Select
00: 1.50*IOPADC
5:4 R/W 0x1 01: 1.75*IOPADC
10: 2.00*IOPADC
11: 2.25*IOPADC
IOPADC is defined by ADC1_REG<15:14> from 1 uA to 4 uA.
ADC1_OUTPUT_CURRENT
ADC1 OP MIC1 Output Current Select
00: 15I
3:2 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
ADC1_OUTPUT_CURRENT
ADC1 OP MIC2 Output Current Select
00: 15I
1:0 R/W 0x1 01: 20I
10: 35I
11: 40I
I=7 uA
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Contents
9 Interfaces ................................................................................................................................................................ 824
9.1 TWI .................................................................................................................................................................. 824
9.1.1 Overview ............................................................................................................................................. 824
9.1.2 Block Diagram ..................................................................................................................................... 824
9.1.3 Functional Description ........................................................................................................................ 826
9.1.4 Programming Guidelines..................................................................................................................... 831
9.1.5 Register List ......................................................................................................................................... 834
9.1.6 Register Description ............................................................................................................................ 835
9.2 UART................................................................................................................................................................ 850
9.2.1 Overview ............................................................................................................................................. 850
9.2.2 Block Diagram ..................................................................................................................................... 850
9.2.3 Functional Description ........................................................................................................................ 851
9.2.4 Programming Guidelines..................................................................................................................... 857
9.2.5 Register List ......................................................................................................................................... 860
9.2.6 Register Description ............................................................................................................................ 862
9.3 SPI.................................................................................................................................................................... 891
9.3.1 Overview ............................................................................................................................................. 891
9.3.2 Block Diagram ..................................................................................................................................... 891
9.3.3 Functional Description ........................................................................................................................ 893
9.3.4 Programming Guidelines..................................................................................................................... 901
9.3.5 Register List ......................................................................................................................................... 904
9.3.6 Register Description ............................................................................................................................ 905
9.4 SPI_DBI ............................................................................................................................................................ 926
9.4.1 Overview ............................................................................................................................................. 926
9.4.2 Block Diagram ..................................................................................................................................... 926
9.4.3 Functional Description ........................................................................................................................ 928
9.4.4 Programming Guidelines..................................................................................................................... 948
9.4.5 Register List ......................................................................................................................................... 956
9.4.6 Register Description ............................................................................................................................ 957
9.5 USB2.0 DRD ..................................................................................................................................................... 989
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9.5.1 Overview ............................................................................................................................................. 989
9.5.2 Block Diagram ..................................................................................................................................... 990
9.5.3 Functional Description ........................................................................................................................ 990
9.6 USB2.0 HOST ................................................................................................................................................... 992
9.6.1 Overview ............................................................................................................................................. 992
9.6.2 Block Diagram ..................................................................................................................................... 992
9.6.3 Functional Description ........................................................................................................................ 993
9.6.4 Register List ......................................................................................................................................... 993
9.6.5 EHCI Register Description.................................................................................................................... 995
9.6.6 OHCI Register Description ................................................................................................................. 1012
9.7 GPIO .............................................................................................................................................................. 1034
9.7.1 Overview ........................................................................................................................................... 1034
9.7.2 Block Diagram ................................................................................................................................... 1034
9.7.3 Functional Description ...................................................................................................................... 1035
9.7.4 Register List ....................................................................................................................................... 1043
9.7.5 Register Description .......................................................................................................................... 1045
9.8 GPADC ........................................................................................................................................................... 1136
9.8.1 Overview ........................................................................................................................................... 1136
9.8.2 Block Diagram ................................................................................................................................... 1136
9.8.3 Functional Description ??.................................................................................................................. 1137
9.8.4 Programming Guidelines................................................................................................................... 1138
9.8.5 Register List ....................................................................................................................................... 1140
9.8.6 Register Description .......................................................................................................................... 1141
9.9 TPADC............................................................................................................................................................ 1149
9.9.1 Overview ........................................................................................................................................... 1149
9.9.2 Functional Description ...................................................................................................................... 1149
9.9.3 Register List ....................................................................................................................................... 1155
9.9.4 Register Description .......................................................................................................................... 1156
9.10 PWM ............................................................................................................................................................. 1164
9.10.1 Overview ........................................................................................................................................... 1164
9.10.2 Block Diagram ................................................................................................................................... 1164
9.10.3 Functional Description ...................................................................................................................... 1165
9.10.4 Programming Guidelines................................................................................................................... 1175
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9.10.5 Register List ....................................................................................................................................... 1176
9.10.6 Register Description .......................................................................................................................... 1178
9.11 LEDC .............................................................................................................................................................. 1205
9.11.1 Overview ........................................................................................................................................... 1205
9.11.2 Block Diagram ................................................................................................................................... 1205
9.11.3 Functional Description ...................................................................................................................... 1206
9.11.4 Programming Guidelines................................................................................................................... 1210
9.11.5 Register List ....................................................................................................................................... 1215
9.11.6 Register Description .......................................................................................................................... 1215
9.12 EMAC ............................................................................................................................................................. 1226
9.12.1 Overview ........................................................................................................................................... 1226
9.12.2 Block Diagram ................................................................................................................................... 1226
9.12.3 Functional Description ...................................................................................................................... 1227
9.12.4 Programming Guidelines................................................................................................................... 1234
9.12.5 Register List ....................................................................................................................................... 1235
9.12.6 Register Description .......................................................................................................................... 1236
9.13 CIR Receiver .................................................................................................................................................. 1254
9.13.1 Overview ........................................................................................................................................... 1254
9.13.2 Block Diagram ................................................................................................................................... 1254
9.13.3 Functional Description ...................................................................................................................... 1255
9.13.4 Programming Guidelines................................................................................................................... 1259
9.13.5 Register List ....................................................................................................................................... 1260
9.13.6 Register Description .......................................................................................................................... 1260
9.14 CIR Transmitter ............................................................................................................................................. 1266
9.14.1 Overview ........................................................................................................................................... 1266
9.14.2 Block Diagram ................................................................................................................................... 1266
9.14.3 Functional Description ...................................................................................................................... 1267
9.14.4 Programming Guidelines................................................................................................................... 1269
9.14.5 Register List ....................................................................................................................................... 1270
9.14.6 Register Description .......................................................................................................................... 1270
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Figures
Figure 9-1 TWI Block Diagram ........................................................................................................................................... 825
Figure 9-2 Write Timing in 7-bit Standard Addressing Mode ........................................................................................... 827
Figure 9-3 Read Timing in 7-bit Standard Addressing Mode ............................................................................................ 827
Figure 9-4 Write Timing in 10-bit Extended Addressing Mode......................................................................................... 827
Figure 9-5 Read Timing in 10-bit Extended Addressing Mode.......................................................................................... 828
Figure 9-6 TWI Driver Write Packet Transmission ............................................................................................................ 828
Figure 9-7 TWI Driver Read Packet Transmission ............................................................................................................. 829
Figure 9-8 TWI Programming State Diagram .................................................................................................................... 831
Figure 9-9 UART Block Diagram ........................................................................................................................................ 851
Figure 9-10 UART Serial Data Format ............................................................................................................................... 852
Figure 9-11 Application Diagram for RTS/CTS Autoflow Control ...................................................................................... 853
Figure 9-12 RTS/CTS Autoflow Control Data Format ........................................................................................................ 853
Figure 9-13 Application Diagram for IrDA Transceiver ..................................................................................................... 853
Figure 9-14 Serial IrDA Data Format ................................................................................................................................. 854
Figure 9-15 Application Diagram for RS-485 Transceiver ................................................................................................. 854
Figure 9-16 RS-485 Data Format ....................................................................................................................................... 854
Figure 9-17 UART Mode Baud and Error Rates ................................................................................................................. 855
Figure 9-18 IrDA Mode Baud and Error Rates................................................................................................................... 856
Figure 9-19 RS485 Mode Baud and Error Rates ................................................................................................................ 856
Figure 9-20 SPI Block Diagram .......................................................................................................................................... 892
Figure 9-21 SPI Application Block Diagram ....................................................................................................................... 894
Figure 9-22 SPI Phase 0 Timing Diagram........................................................................................................................... 895
Figure 9-23 SPI Phase 1 Timing Diagram........................................................................................................................... 895
Figure 9-24 SPI 3-Wire Mode ............................................................................................................................................ 896
Figure 9-25 SPI Dual-Input/Dual-Output Mode ................................................................................................................ 897
Figure 9-26 SPI Dual I/O Mode.......................................................................................................................................... 897
Figure 9-27 SPI Quad-Input/Quad-Output Mode ............................................................................................................. 898
Figure 9-28 SPI Write/Read Data in CPU Mode ................................................................................................................ 902
Figure 9-29 SPI Write/Read Data in DMA Mode ............................................................................................................... 903
Figure 9-30 SPI_DBI Block Diagram ................................................................................................................................... 927
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Figure 9-31 SPI Application Block Diagram ....................................................................................................................... 930
Figure 9-32 DBI Application Block Diagram ...................................................................................................................... 930
Figure 9-33 SPI Phase 0 Timing Diagram........................................................................................................................... 931
Figure 9-34 SPI Phase 1 Timing Diagram........................................................................................................................... 931
Figure 9-35 SPI 3-Wire Mode ............................................................................................................................................ 932
Figure 9-36 SPI Dual-Input/Dual-Output Mode ................................................................................................................ 933
Figure 9-37 SPI Dual I/O Mode.......................................................................................................................................... 933
Figure 9-38 SPI Quad-Input/Quad-Output Mode ............................................................................................................. 934
Figure 9-39 DBI 3-Line Display Bus Serial Interface Writing Operation Format ............................................................... 936
Figure 9-40 DBI 3-Line Display Bus Serial Interface 8-bit Reading Operation Format ...................................................... 937
Figure 9-41 DBI 3-Line Display Bus Serial Interface 24-bit Reading Operation Format .................................................... 937
Figure 9-42 DBI 3-Line Display Bus Serial Interface 32-bit Reading Operation Format .................................................... 938
Figure 9-43 DBI 4-Line Display Bus Serial Interface Writing Operation Format ............................................................... 939
Figure 9-44 DBI 4-Line Display Bus Serial Interface 8-bit Reading Operation Format ...................................................... 939
Figure 9-45 DBI 4-Line Display Bus Serial Interface 24-bit Reading Operation Format .................................................... 940
Figure 9-46 DBI 4-Line Display Bus Serial Interface 32-bit Reading Operation Format .................................................... 940
Figure 9-47 RGB111 3-Line Interface Transmit Video Format .......................................................................................... 941
Figure 9-48 RGB444 3-Line Interface Transmit Video Format .......................................................................................... 941
Figure 9-49 RGB565 3-Line Interface Transmit Video Format .......................................................................................... 942
Figure 9-50 RGB666 3-Line Interface Transmit Video Format .......................................................................................... 942
Figure 9-51 RGB111 4-Line Interface Transmit Video Format .......................................................................................... 943
Figure 9-52 RGB444 4-Line Interface Transmit Video Format .......................................................................................... 943
Figure 9-53 RGB565 4-Line Interface Transmit Video Format .......................................................................................... 944
Figure 9-54 RGB666 4-Line Interface Transmit Video Format .......................................................................................... 944
Figure 9-55 RGB444 2 Data Lane Interface Transmit Video Format ................................................................................. 945
Figure 9-56 RGB565 2 Data Lane Interface Transmit Video Format ................................................................................. 946
Figure 9-57 RGB666 2 Data Lane Interface Transmit Video Format 0 .............................................................................. 947
Figure 9-58 RGB666 2 Data Lane Interface Transmit Video Format 1 (ilitek) ................................................................... 947
Figure 9-59 RGB666 2 Data Lane Interface Transmit Video Format 2 (New vision) ......................................................... 947
Figure 9-60 RGB888 2 Data Lane Interface Transmit Video Format ................................................................................. 948
Figure 9-61 SPI Write/Read Data in CPU Mode ................................................................................................................ 949
Figure 9-62 SPI Write/Read Data in DMA Mode ............................................................................................................... 950
Figure 9-63 USB2.0 DRD Controller Block Diagram .......................................................................................................... 990
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Figure 9-64 USB2.0 DRD Controller and PHY Connection Diagram .................................................................................. 991
Figure 9-65 USB2.0 Host Controller Block Diagram .......................................................................................................... 992
Figure 9-66 USB2.0 Host Controller and PHY Connection Diagram .................................................................................. 993
Figure 9-67 GPIO Block Diagram ..................................................................................................................................... 1035
Figure 9-68 Pull up/down Logic ...................................................................................................................................... 1040
Figure 9-69 IO Buffer Strength Diagram ......................................................................................................................... 1041
Figure 9-70 GPADC Block Diagram .................................................................................................................................. 1136
Figure 9-71 GPADC Clock and Timing Requirement ....................................................................................................... 1138
Figure 9-72 GPADC Initial Process ................................................................................................................................... 1139
Figure 9-73 TPADC Single-Ended Mode for AUX ADC ..................................................................................................... 1150
Figure 9-74 TPADC Differential Mode for Touch Panel................................................................................................... 1151
Figure 9-75 Single Touch X-Coordinate Measurement for Touch Panel ......................................................................... 1151
Figure 9-76 Dual Touch Detection for Touch Panel ........................................................................................................ 1152
Figure 9-77 Touch Pressure Measurement for Touch Panel .......................................................................................... 1153
Figure 9-78 Pen Down Detection for Touch Panel .......................................................................................................... 1154
Figure 9-79 Median and Averaging Filter Size ................................................................................................................ 1154
Figure 9-80 Median and Averaging Filter Example ......................................................................................................... 1155
Figure 9-81 PWM Block Diagram .................................................................................................................................... 1165
Figure 9-82 PWM01 Clock Controller Diagram ............................................................................................................... 1166
Figure 9-83 PWM01 Output Logic Module Diagram....................................................................................................... 1167
Figure 9-84 PWM0 High Level Active State..................................................................................................................... 1168
Figure 9-85 PWM0 Low Level Active State ..................................................................................................................... 1169
Figure 9-86 Phase of PWM0 High Level Active State ...................................................................................................... 1169
Figure 9-87 PWM0 Output Waveform in Pulse Mode and Cycle Mode ......................................................................... 1170
Figure 9-88 PWM01 Complementary Pair Output.......................................................................................................... 1171
Figure 9-89 Dead-time Output Waveform ...................................................................................................................... 1172
Figure 9-90 Group 0–3 PWM Signal Output ................................................................................................................... 1173
Figure 9-91 PWM01 Capture Logic Module Diagram ..................................................................................................... 1173
Figure 9-92 PWM0 Channel Capture Timing................................................................................................................... 1174
Figure 9-93 LEDC Block Diagram ..................................................................................................................................... 1205
Figure 9-94 LEDC Package Output Timing Diagram ........................................................................................................ 1206
Figure 9-95 LEDC 1-frame Output Timing Diagram......................................................................................................... 1207
Figure 9-96 LEDC Input Data Structure ........................................................................................................................... 1207
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Figure 9-97 LEDC Typical Circuit...................................................................................................................................... 1207
Figure 9-98 LEDC Data Input Code .................................................................................................................................. 1208
Figure 9-99 LEDC Data Transfer Mode ............................................................................................................................ 1208
Figure 9-100 LEDC Normal Configuration Process .......................................................................................................... 1211
Figure 9-101 LEDC Timeout Abnormal Processing Flow ................................................................................................. 1213
Figure 9-102 FIFO Overflow Abnormal Processing Flow ................................................................................................. 1214
Figure 9-103 EMAC Block Diagram ................................................................................................................................. 1227
Figure 9-104 EMAC Typical Application .......................................................................................................................... 1229
Figure 9-105 EMAC RX/TX Descriptor List ....................................................................................................................... 1230
Figure 9-106 CIR_RX Block Diagram ................................................................................................................................ 1254
Figure 9-107 CIR_RX Clock System .................................................................................................................................. 1255
Figure 9-108 CIR_RX Application Diagram ...................................................................................................................... 1255
Figure 9-109 NEC Protocol .............................................................................................................................................. 1256
Figure 9-110 Logical ‘0’ and Logical ‘1’ of NEC Protocol ................................................................................................. 1256
Figure 9-111 ATHR Definition ......................................................................................................................................... 1257
Figure 9-112 ITHR Definition ........................................................................................................................................... 1257
Figure 9-113 NTHR Definition ......................................................................................................................................... 1257
Figure 9-114 APAM Definition ........................................................................................................................................ 1258
Figure 9-115 CIR Receiver Process .................................................................................................................................. 1259
Figure 9-116 CIR_TX Block Diagram ................................................................................................................................ 1266
Figure 9-117 CIR_TX Clock System .................................................................................................................................. 1267
Figure 9-118 Definitions of Logical “1” and Logical “0” .................................................................................................. 1268
Figure 9-119 CIR Message Timing Diagram..................................................................................................................... 1268
Figure 9-120 CIR Transmitter Process ............................................................................................................................. 1269
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Tables
Table 9-1 TWI Sub-blocks .................................................................................................................................................. 825
Table 9-2 TWI External Signals .......................................................................................................................................... 826
Table 9-3 TWI Clock Sources ............................................................................................................................................. 826
Table 9-4 UART External Signals ....................................................................................................................................... 851
Table 9-5 UART Clock Sources........................................................................................................................................... 852
Table 9-6 SPI Sub-blocks ................................................................................................................................................... 892
Table 9-7 SPI External Signals ........................................................................................................................................... 893
Table 9-8 SPI Clock Sources............................................................................................................................................... 893
Table 9-9 SPI Transmit Format .......................................................................................................................................... 894
Table 9-10 SPI Old Sample Mode and Run Clock .............................................................................................................. 899
Table 9-11 SPI New Sample Mode .................................................................................................................................... 899
Table 9-12 SPI_DBI Sub-blocks .......................................................................................................................................... 927
Table 9-13 SPI_DBI External Signals .................................................................................................................................. 928
Table 9-14 SPI_DBI Clock Sources ..................................................................................................................................... 929
Table 9-15 SPI Transmit Format ........................................................................................................................................ 931
Table 9-16 SPI Old Sample Mode and Run Clock .............................................................................................................. 935
Table 9-17 SPI New Sample Mode .................................................................................................................................... 935
Table 9-18 USB2.0 DRD External Signals ........................................................................................................................... 990
Table 9-19 USB2.0 Host External Signals .......................................................................................................................... 993
Table 9-20 Multi-function Port ....................................................................................................................................... 1035
Table 9-21 PB Multiplex Function ................................................................................................................................... 1037
Table 9-22 PC Multiplex Function ................................................................................................................................... 1037
Table 9-23 PD Multiplex Function ................................................................................................................................... 1037
Table 9-24 PE Multiplex Function ................................................................................................................................... 1038
Table 9-25 PF Multiplex Function ................................................................................................................................... 1038
Table 9-26 PG Multiplex Function ................................................................................................................................... 1039
Table 9-27 Port Function................................................................................................................................................. 1040
Table 9-28 GPADC External Signals ................................................................................................................................. 1137
Table 9-29 GPADC Clock Sources .................................................................................................................................... 1137
Table 9-30 TPADC External Signals.................................................................................................................................. 1149
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Table 9-31 PWM External Signals ................................................................................................................................... 1165
Table 9-32 LEDC Sub-blocks ............................................................................................................................................ 1205
Table 9-33 LEDC External Signals .................................................................................................................................... 1206
Table 9-34 LEDC Clock Sources ....................................................................................................................................... 1206
Table 9-35 EMAC Pin Mapping........................................................................................................................................ 1227
Table 9-36 EMAC RGMII Pin List ..................................................................................................................................... 1228
Table 9-37 EMAC RMII Pin List ........................................................................................................................................ 1228
Table 9-38 EMAC Clock Characteristics........................................................................................................................... 1229
Table 9-39 EMAC_EPHY_CLK_REG0 Configuration Value ............................................................................................... 1234
Table 9-40 CIR_RX External Signals ................................................................................................................................. 1255
Table 9-41 CIR_TX External Signals ................................................................................................................................. 1267
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9 Interfaces
9.1 TWI
9.1.1 Overview
The Two Wire Interface (TWI) provides an interface between a CPU and any TWI-bus-compatible device that
connects via the TWI bus. The TWI is designed to be compatible with the standard I2C bus protocol. The
communication of the TWI is carried out by a byte-wise mode based on interrupt polled handshaking. Each
device on the TWI bus is recognized by a unique address and can operate as either transmitter or receiver, a
device connected to the TWI bus can be considered as master or slave when performing data transfers. Note
that a master device is a device that initiates a data transfer on the bus and generates the clock signals to
permit the transfer. During this transfer, any device addressed by this master is considered a slave.
The TWI has the following features:
Compliant with I2C bus standard
Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s)
Supports 7-bit and 10-bit device addressing modes
Supports master mode or slave mode
Master mode features:
- Supports the bus arbitration in the case of multiple master devices
- Supports clock synchronization and bit and byte waiting
- Supports packet transmission and DMA
Slave mode features:
- Interrupt on address detection
The TWI controller includes one TWI engine and one TWI driver. And the TWI driver supports packet
transmission and DMA mode when TWI works in master mode
9.1.2 Block Diagram
Figure 9-1 shows the block diagram of TWI.
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Figure 9-1 TWI Block Diagram
INT TWI_TOP
RESET
DRV_EN TWI_ENGINE
APB
0
TWI_DRIVER
CFG_REG CCU
CFG_REG
1
dma_tx_req SEND_FIFO
TWI_SCK
dma_rx_req RECV_FIFO PE
TWI_SDA
TWI contains the following sub-blocks:
Table 9-1 TWI Sub-blocks
Sub-block Description
RESET Module reset signal
INT Module output interrupt signal
CFG_REG Module configuration register in TWI
PE Packet encoding/decoding
CCU Module clock controller unit
The register address bytes and the written data bytes are buffered in
SEND_FIFO
SEND_FIFO
RECV_FIFO The read data bytes are buffered in RECV_FIFO
The controller includes TWI engine and TWI driver. Each time the TWI engine sends a START signal, a STOP
signal, or a BYTE data, or a corresponding ACK, the TWI engine will generate an interrupt, and wait for the CPU
to process and clear the interrupt before the next START, STOP, or BYTE, ACK transmission can be performed.
Therefore, when a device communication is completed, many interrupts will be generated, and the CPU needs
to wait for the previous interrupt before it can configure the next one. The TWI driver defines each
communication with the device as a packet transmission. The CPU can directly configure the slave address,
register address and data transmission for one or more package transmissions without waiting for interruption,
then start the TWI driver, and the TWI driver can control the TWI engine to complete a pre-configured
communication, and report an interrupt to the CPU after completion.
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9.1.3 Functional Description
9.1.3.1 External Signals
The TWI controller has 4 TWI modules called TWI0, TWI1, TWI2, and TWI3. The following table describes the
external signals of the TWI. The TWIn-SCK and TWIn-SDA are bidirectional I/O, when the TWI is configured as
a master device, the TWIn-SCK is an output pin; when the TWI is configurable as a slave device, the TWIn-SCK
is an input pin. When using TWI, the corresponding PADs are selected as TWI function via section 9.7 “GPIO”.
Table 9-2 TWI External Signals
Signal Description Type
TWI0-SCK TWI0 Clock Signal I/O, OD
TWI0-SDA TWI0 Serial Data I/O, OD
TWI1-SCK TWI1 Clock Signal I/O, OD
TWI1-SDA TWI1 Serial Data I/O, OD
TWI2-SCK TWI2 Clock Signal I/O, OD
TWI2-SDA TWI2 Serial Data I/O, OD
TWI3-SCK TWI3 Clock Signal I/O, OD
TWI3-SDA TWI3 Serial Data I/O, OD
9.1.3.2 Clock Sources
Each TWI controller has an input clock source. The following table describes the clock sources for TWI. After
selecting a proper clock, users must open the gating of TWI and release the corresponding reset bit.
For more details on the clock setting, configuration, and gating information, see section 3.3 “CCU”.
Table 9-3 TWI Clock Sources
Clock Sources Description
APB1 Bus TWI clock source. Refer to CCU for details on APB1.
9.1.3.3 Write/Read Timing in Standard and Extended Addressing Mode
This section is the 7-bit/10-bit addressing mode of the entire TWI protocol to read and write device registers.
It can be achieved by directly using the TWI engine or using the TWI driver to control the TWI engine.
Figure 9-2 describes the write timing in 7-bit standard addressing mode.
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Figure 9-2 Write Timing in 7-bit Standard Addressing Mode
Slave addr = 7-bit , register addr = 8-bit, data = 8-bit
Slave Address Register Address DATA
S [7:1] W A [7:0] A [7:0] A P
Slave addr = 7-bit , register addr = 8-bit, data = n-byte
Slave Address Register Address DATA DATA
S [7:1] W A [7:0] A [7:0] A …
[7:0] A P
data transferred(n-byte + acknowledge)
from master to slave S：START condition A：acknowledge(SDA LOW)
from slave to master P：STOP condition `A：not acknowledge(SDA HIGH)
Figure 9-3 describes the read timing in 7-bit standard address mode.
Figure 9-3 Read Timing in 7-bit Standard Addressing Mode
Slave addr = 7-bit , register addr = 8-bit, data = 8-bit
Slave Address Register Address Slave Address DATA
S [7:1] W A [7:0] A Sr [7:1] R A [7:0] `A P
Slave addr = 7-bit , register addr = 8-bit, data = n-byte
Slave Address Register Address Slave Address DATA DATA
S [7:1] W A [7:0] A Sr [7:1] R A [7:0] A …
[7:0] `A P
data transferred(n-byte + acknowledge)
from master to slave S：START condition A：acknowledge(SDA LOW)
Sr：RE-START condition
from slave to master P：STOP condition `A：not acknowledge(SDA HIGH)
Figure 9-4 describes the write timing in 10-bit extended address mode.
Figure 9-4 Write Timing in 10-bit Extended Addressing Mode
Slave addr = 10-bit , register addr = 8-bit, data = 8-bit
b11110+Slave Slave Address Register Address DATA
S Address[9:8] W A [7:0] A [7:0] A [7:0] A P
Slave addr = 10-bit , register addr = 8-bit, data = n-byte
b11110+Slave Slave Address Register Address DATA DATA
S Address[9:8] W A [7:0] A [7:0] A [7:0] A …
[7:0] A P
data transferred(n-byte + acknowledge)
from master to slave S：START condition A：acknowledge(SDA LOW)
from slave to master P：STOP condition `A：not acknowledge(SDA HIGH)
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Figure 9-5 describes the read timing in 10-bit extended address mode.
Figure 9-5 Read Timing in 10-bit Extended Addressing Mode
Slave addr = 10-bit , register addr = 8-bit, data = 8-bit
b11110+Slave Slave Address Register Address b11110+Slave DATA
S Address[9:8] W A [7:0] A [7:0] A Sr Address[9:8] R A [7:0] `A P
Slave addr = 10-bit , register addr = 8-bit, data = n-byte
b11110+Slave Slave Address Register Address b11110+Slave DATA DATA
S Address[9:8] W A [7:0] A [7:0] A Sr Address[9:8] R A [7:0] A …
[7:0] `A P
data transferred(n-byte + acknowledge)
from master to slave S：START condition A：acknowledge(SDA LOW)
Sr：RE-START condition
from slave to master P：STOP condition `A：not acknowledge(SDA HIGH)
9.1.3.4 Write/Read Packet Transmission of TWI Driver
The TWI driver is only supported for master mode. When the TWI works in master mode, the TWI driver drives
the TWI engine for one or more packet transmission instead of the CPU host. Packet transmission is defined in
the following figures. The register address bytes and the written data bytes are buffered in SEND_FIFO, the
read data bytes are buffered in RECV_FIFO.
Figure 9-6 TWI Driver Write Packet Transmission
Write Packet Transmission Start
(START_TRAN=1,CMD=0)
Start
Slave_id+W Slave_id_x
Packet 0 Reg(0)_Addr_byte(0) …… Reg(0)_Addr_byte(M-1) Wdata(0)_byte(0) …… Wdata(0)_byte(N-1)
Stop
Packet Interval Time
Start
Slave_id+W Slave_id_x
Packet 1 Reg(1)_Addr_byte(0) …… Reg(1)_Addr_byte(M-1) Wdata(1)_byte(0) …… Wdata(1)_byte(N-1)
Stop
Master to Slave T =1,2,3… as Packet_CNT
……
Slave to Master M=0,1,2… as ADDR_BYTE
Start Optional operation N=1,2,3… as DATA_BYTE
Slave_id+W Slave_id_x
Reg(T-1)_Addr_byte(0) …… Reg(T-1)_Addr_byte(M-1) Wdata(T-1)_byte(0) …… Wdata(T-1)_byte(N-1)
Packet T-1 Stop
Write Packet Transmission Complete
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Figure 9-7 TWI Driver Read Packet Transmission
Read Packet Transmission Start
(START_TRAN=1,CMD=1)
Start
Slave_id+W Slave_id_x
Packet 0 Reg(0)_Addr_byte(0) …… Reg(0)_Addr_byte(M-1)
Stop Start
Slave_id+R
Rdat a(0)_byte(0) …… Rdat a(0)_byte(N-1)
Stop
Packet Interval Time
Start
Slave_id+W Slave_id_x
Packet 1 Reg(1)_Addr_byte(0) …… Reg(1)_Addr_byte(M-1)
Stop Start
Slave_id+R
Rdat a(1)_byte(0) …… Rdat a(1)_byte(N-1)
Stop
Master to Slave T =1,2,3… as Packet_CNT
…… Slave to Master M=0,1,2… as ADDR_BYTE
Optional operation N=1,2,3… as DATA_BYTE
Start
Slave_id+W Slave_id_x
Reg(T-1)_Addr_byte(0) …… Reg(T-1)_Addr_byte(M-1)
Packet T-1 Stop Start
Slave_id+R
Rdat a(T-1)_byte(0) …… Rdat a(T-1)_byte(N-1)
Stop
Read Packet Transmission Complete
9.1.3.5 Master and Slave Mode of TWI Engine
In Master mode, the CPU host controls the TWI engine by writing command and data to its registers. The TWI
engine transmits an interrupt to CPU when each time a byte transfer is done or a START/STOP command is
detected. The CPU host can poll the status register if the interrupt mechanism is not disabled by the CPU host.
When the CPU host wants to start a bus transfer, it initiates a bus START to enter the master mode by setting
TWI_CNTR[M_STA] to high. The TWI engine will assert the INT line and TWI_CNTR[INT_FLAG] to indicate a
completion for the START command and each consequent byte transfer. At each interrupt, the CPU host needs
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to check the current state by the TWI_STAT register. A transfer must conclude with the STOP command by
setting TWI_CNTR[M_STP] to high.
In Slave mode, the TWI engine also constantly samples the bus and look for its own slave address during
addressing cycles. Once a match is found, it is addressed, and the TWI engine interrupts the CPU host with the
corresponding status. Upon request, the CPU host should read the status, read/write the TWI_DATA register,
and set the TWI_CNTR register. After each byte transfer, a slave device always stops the operation of the
remote master by holding the next low pulse on the SCL line until the CPU host responds to the status of the
previous byte transfer or START command.
9.1.3.6 Generation of Repeated Start
After the data transfer, if the master still requires the bus, it can signal another Start followed by another slave
address without signaling a Stop.
9.1.3.7 Programming State Diagram
Figure 9-8 shows the TWI programming state diagram. For the value between two states, see the TWI_STAT
register in section 9.1.6.5.
M_SEND_S: master sends START signal;
M_SEND_ADDR: master sends slave address;
M_SEND_XADD: master sends slave extended address;
M_SEND_SR: master repeated start;
M_SEND_DATA: master sends data;
M_SEND_P: master sends STOP signal;
M_RECV_DATA: master receives data;
ARB_LOST: Arbitration lost;
C_IDLE: Idle.
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Figure 9-8 TWI Programming State Diagram
ARB_LOST
arb_lost
M_SEND_S
M_SEND_ADDR
C_IDLE
M_SEND_XADD
M_RECV_DATA
M_SEND_SR
M_SEND_DATA
M_SEND_P
9.1.4 Programming Guidelines
The TWI controller operates in an 8-bit data format. The data on the TWI_SDA line is always 8 bits long. At first,
the TWI controller sends a start condition. When in the addressing formats of 7-bit, the TWI sends out an 8-bit
message which includes 7 MSB slave address and 1 LSB read/write flag. The least significant of the salve address
indicates the direction of transmission. When the TWI works in 10-bit slave address mode, the operation will
be divided into two steps, for details on the operation, refer to register description in Section 9.1.6.1 and 9.1.6.2.
The following takes the TWI module in the CPUX domain as an example.
9.1.4.1 Initialization for TWI Engine
To initialize the TWI engine, perform the following steps:
Step 1 Configure corresponding GPIO multiplex function as TWI mode.
Step 2 For TWIn, set TWI_BGR_REG[TWIn_GATING] in CCU module to 0 to close TWIn clock.
Step 3 For TWIn, set TWI_BGR_REG[TWIn_RST] in CCU module to 0, then set to 1 to reset TWIn.
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Step 4 For TWIn, set TWI_BGR_REG[TWIn_GATING] in CCU module to 1 to open TWIn clock.
Step 5 Configure TWI_CCR[CLK_M] and TWI_CCR[CLK_N] to get the needed rate (The clock source of TWI is
from APB1).
Step 6 Configure TWI_CNTR[BUS_EN] and TWI_CNTR[A_ACK], when using interrupt mode, set
TWI_CNTR[INT_EN] to 1, and register the system interrupt through PLIC module. In slave mode,
configure TWI_ADDR and TWI_XADDR registers to finish TWI initialization configuration.
9.1.4.2 Writing Data Operation for TWI Engine
To write data to the device, perform the following steps:
Step 1 Clear TWI_EFR register, and configure TWI_CNTR[M_STA] to 1 to transmit the START signal.
Step 2 After the START signal is transmitted, the first interrupt is triggered, then write device ID to TWI_DATA
(For a 10-bit device ID, firstly write the first byte ID, secondly write the second byte ID in the next
interrupt).
Step 3 The Interrupt is triggered again after device ID transmission completes, write device data address to
be read to TWI_DATA (For a 16-bit address, firstly write the first-byte address, secondly write the
second-byte address).
Step 4 Interrupt is triggered after data address transmission completes, write data to be transmitted to
TWI_DATA (For consecutive write data operation, every byte transmission completion triggers
interrupt, during interrupt write the next byte data to TWI_DATA).
Step 5 After transmission completes, write TWI_CNTR[M_STP] to 1 to transmit the STOP signal and end this
write-operation.
9.1.4.3 Reading Data Operation for TWI Engine
To read data from the device, perform the following steps:
Step 1 Clear TWI_EFR register, and set TWI_CNTR[A_ACK] to 1, and configure TWI_CNTR[M_STA] to 1 to
transmit the START signal.
Step 2 After the START signal is transmitted, the first interrupt is triggered, then write device ID to TWI_DATA
(For a 10-bit device ID, firstly write the first-byte ID, secondly write the second-byte ID in the next
interrupt).
Step 3 The Interrupt is triggered again after device ID transmission completes, write device data address to
be read to TWI_DATA (For a 16-bit address, firstly write the first-byte address, secondly write the
second-byte address).
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Step 4 The Interrupt is triggered after data address transmission completes, write TWI_CNTR[M_STA] to 1 to
transmit new START signal, and after interrupt triggers, write device ID to TWI_DATA to start read-
operation.
Step 5 After device address transmission completes, each receive completion will trigger an interrupt, in turn,
read TWI_DATA to get data, when receiving the previous interrupt of the last byte data, clear [A_ACK]
to stop acknowledge signal of the last byte.
Step 6 Write TWI_CNTR[M_STP] to 1 to transmit the STOP signal and end this read-operation.
9.1.4.4 Initialization for TWI Driver
To initialize the TWI driver, perform the following steps:
Step 1 Configure corresponding GPIO multiplex function as TWI mode.
Step 2 For TWIn, set TWI_BGR_REG[TWIn_GATING] in CCU module to 0 to close TWIn clock.
Step 3 For TWIn, set TWI_BGR_REG[TWIn_RST] in CCU module to 0, then set to 1 to reset TWIn.
Step 4 For TWIn, set TWI_BGR_REG[TWIn_GATING] in CCU module to 1 to open TWIn clock.
Step 5 Set TWI_DRV_CTRL[TWI_DRV_EN] to 1 to enable the TWI driver.
Step 6 Configure TWI_DRV_BUS_CTRL[CLK_M] and TWI_DRV_BUS_CTRL[CLK_N] to get the needed rate (The
clock source of TWI is from APB1).
Step 7 Set TWI_DRV_CTRL[RESTART_MODE] to 0 and [READ_TRAN_MODE] to 1, set
TWI_DRV_INT_CTRL[TRAN_COM_INT_EN] to 1.
Step 8 When using DMA for data transmission, set TWI_DRV_DMA_CFG[DMA_RX_EN] and
TWI_DRV_DMA_CFG[DMA_TX_EN] to 1, and configure TWI_DRV_DMA_CFG[RX_TRIG] and
TWI_DRV_DMA_CFG[TX_TRIG] to set the thresholds of RXFIFO and TXFIFO.
9.1.4.5 Writing Packet Transmission for TWI Driver
To write package to the device, perform the following steps:
Step 1 Configure TWI_DRV_SLV[SLV_ID] to set the device ID, and configure TWI_DRV_SLV[CMD] to 0 to set
the write operation.
Step 2 Configure TWI_DRV_FMT[ADDR_BYTE] according to the address width of the device register, and
TWI_DRV_FMT[DATA_BYTE] according to the written data count in a packet.
Step 3 Configure TWI_DRV_CFG[PACKET_CNT] to set the written packet number.
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Step 4 Configure DMA channel, including TWI TXFIFO, device register address, and the written data.
Step 5 Set [START_TRAN] to 1 to start TWI Driver transmission.
Step 6 When TWI driver transmission completes, the interrupt is triggered, it indicates that the write packet
transmission ends.
9.1.4.6 Reading Packet Transmission for TWI Driver
To read package from the device, perform the following steps:
Step 1 Configure TWI_DRV_SLV[SLV_ID] to set the device ID, and configure TWI_DRV_SLV[CMD] to 1 to set
the read operation.
Step 2 Configure TWI_DRV_FMT[ADDR_BYTE] according to the address width of the device register, and
TWI_DRV_FMT[DATA_BYTE] according to the read data count in a packet.
Step 3 Configure TWI_DRV_CFG[PACKET_CNT] to set the read packet number.
Step 4 Configure DMA channel, including TWI TXFIFO, TWI RXFIFO, device register address and the read data.
Step 5 Set [START_TRAN] to 1 to start TWI Driver transmission.
Step 6 When TWI driver transmission completes, the interrupt is triggered, it indicates that the read packet
transmission ends.
9.1.5 Register List
Module Name Base Address
TWI0 0x02502000
TWI1 0x02502400
TWI2 0x02502800
TWI3 0x02502C00
Register Name Offset Description
TWI_ADDR 0x0000 TWI Slave Address Register
TWI_XADDR 0x0004 TWI Extended Slave Address Register
TWI_DATA 0x0008 TWI Data Byte Register
TWI_CNTR 0x000C TWI Control Register
TWI_STAT 0x0010 TWI Status Register
TWI_CCR 0x0014 TWI Clock Control Register
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Register Name Offset Description
TWI_SRST 0x0018 TWI Software Reset Register
TWI_EFR 0x001C TWI Enhance Feature Register
TWI_LCR 0x0020 TWI Line Control Register
TWI_DRV_CTRL 0x0200 TWI_DRV Control Register
TWI_DRV_CFG 0x0204 TWI_DRV Transmission Configuration Register
TWI_DRV_SLV 0x0208 TWI_DRV Slave ID Register
TWI_DRV_FMT 0x020C TWI_DRV Packet Format Register
TWI_DRV_BUS_CTRL 0x0210 TWI_DRV Bus Control Register
TWI_DRV_INT_CTRL 0x0214 TWI_DRV Interrupt Control Register
TWI_DRV_DMA_CFG 0x0218 TWI_DRV DMA Configure Register
TWI_DRV_FIFO_CON 0x021C TWI_DRV FIFO Content Register
TWI_DRV_SEND_FIFO_ACC 0x0300 TWI_DRV Send Data FIFO Access Register
TWI_DRV_RECV_FIFO_ACC 0x0304 TWI_DRV Receive Data FIFO Access Register
9.1.6 Register Description
9.1.6.1 0x0000 TWI Slave Address Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: TWI_ADDR
Bit Read/Write Default/Hex Description
31:8 / / /
SLA
Slave Address
For 7-bit addressing, the bit[7:1] indicates:
7:1 R/W 0x0
SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA0
For 10-bit addressing, the bit[7:1] indicates:
1, 1, 1, 1, 0, SLAX[9:8]
GCE
General Call Address Enable
0 R/W 0x0
0: Disable
1: Enable
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NOTE
For 7-bit addressing:
SLA6 – SLA0 is the 7-bit address of the TWI in slave mode. When the TWI receives this address after a START
condition, it will generate an interrupt and enter slave mode. (SLA6 corresponds to the first bit received
from the TWI bus.) If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).
For 10-bit addressing:
When the address received starts with b’11110, the TWI recognizes b’11110 as the first part of a 10-bit
address and if the next two bits match ADDR[2:1] (For example, SLAX9 and SLAX8 for the extended address
of the device), it sends an ACK. (The device does not generate an interrupt at this point.) If the next byte of
the address matches the XADDR register (SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave
mode.
9.1.6.2 0x0004 TWI Extend Address Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: TWI_XADDR
Bit Read/Write Default/Hex Description
31:8 / / /
SLAX
7:0 R/W 0x0 Extend Slave Address
SLAX[7:0]
9.1.6.3 0x0008 TWI Data Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: TWI_DATA
Bit Read/Write Default/Hex Description
31:8 / / /
TWI_DATA
7:0 R/W 0x0
Data byte transmitted or received
9.1.6.4 0x000C TWI Control Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: TWI_CNTR
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x000C Register Name: TWI_CNTR
Bit Read/Write Default/Hex Description
INT_EN
Interrupt Enable
7 R/W 0x0
0: The interrupt line always low
1: The interrupt line will go high when INT_FLAG is set.
BUS_EN
TWI Bus Enable
0: The TWI bus SDA/SCL is ignored and the TWI controller will not
6 R/W 0x0 respond to any address on the bus.
1: The TWI will respond to call to its slave address – and to the
general call address if the GCE bit in the ADDR register is set.
Note: In master operation mode, this bit should be set to ‘1’.
M_STA
Master Mode Start
When the M_STA is set to ‘1’, the TWI controller enters master
mode and will transmit a START condition on the bus when the bus
is free. If the M_STA bit is set to ‘1’ when the TWI controller is
already in master mode and one or more bytes have been
5 R/WAC 0x0
transmitted, then a repeated START condition will be sent. If the
M_STA bit is set to ‘1’ when the TWI is accessed in slave mode, the
TWI will complete the data transfer in slave mode then enter
master mode when the bus has been released.
The M_STA bit is cleared automatically after a START condition has
been sent. Writing a ‘0’ to this bit has no effect.
M_STP
Master Mode Stop
If the M_STP is set to ‘1’ in master mode, a STOP condition is
transmitted on the TWI bus. If the M_STP bit is set to ‘1’ in slave
mode, the TWI will indicate if a STOP condition has been received,
4 R/W1C 0x0
but no STOP condition will be transmitted on the TWI bus. If both
M_STA and M_STP bits are set, the TWI will first transmit the STOP
condition (if in master mode), then transmit the START condition.
The M_STP bit is cleared automatically. Writing a ‘0’ to this bit has
no effect.
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Offset: 0x000C Register Name: TWI_CNTR
Bit Read/Write Default/Hex Description
INT_FLAG
Interrupt Flag
The INT_FLAG is automatically set to ‘1’ when any of the 28 (out
of the possible 29) states is entered (see ‘STAT Register’ below).
The state that does not set INT_FLAG is state F8h. If the INT_EN bit
3 R/W1C 0x0
is set, the interrupt line goes high when INT_FLAG is set to ‘1’. If
the TWI is operating in slave mode, the data transfer is suspended
when INT_FLAG is set and the low period of the TWI bus clock line
(SCL) is stretched until ‘1’ is written to INT_FLAG. The TWI clock
line is then released and the interrupt line goes low.
A_ACK
Assert Acknowledge
When A_ACK is set to ‘1’, an Acknowledge (low level on SDA) will
be sent during the acknowledge clock pulse on the TWI bus if:
(1). Either the whole of a matching 7-bit slave address or the first
or the second byte of a matching 10-bit slave address has been
received.
(2). The general call address has been received and the GCE bit in
2 R/W 0x0 the ADDR register is set to ‘1’.
(3). A data byte has been received in master or slave mode.
When A_ACK is ‘0’, a Not Acknowledge (high level on SDA) will be
sent when a data byte is received in master or slave mode.
If A_ACK is cleared to ‘0’ in slave transmitter mode, the byte in the
DATA register is assumed to be the ‘last byte’. After this byte has
been transmitted, the TWI will enter state C8h then return to the
idle state (status code F8h) when INT_FLAG is cleared.
The TWI will not respond as a slave unless A_ACK is set.
1 / / /
CLK_COUNT_MODE
0 R/W 0x0 0: scl clock high period count on oscl
1: scl clock high period count on iscl
9.1.6.5 0x0010 TWI Status Register (Default Value: 0x0000_00F8)
Offset: 0x0010 Register Name: TWI_STAT
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x0010 Register Name: TWI_STAT
Bit Read/Write Default/Hex Description
STA
Status Information Byte
Code Status
0x00: Bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
0x28: Data byte transmitted in master mode, ACK received
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK transmitted
0x58: Data byte received in master mode, not ACK transmitted
0x60: Slave address + Write bit received, ACK transmitted
0x68: Arbitration lost in the address as master, slave address +
Write bit received, ACK transmitted
7:0 R 0xF8 0x70: General Call address received, ACK transmitted
0x78: Arbitration lost in the address as master, General Call
address received, ACK transmitted
0x80: Data byte received after slave address received, ACK
transmitted
0x88: Data byte received after slave address received, not ACK
transmitted
0x90: Data byte received after General Call received, ACK
transmitted
0x98: Data byte received after General Call received, not ACK
transmitted
0xA0: STOP or repeated START condition received in slave mode
0xA8: Slave address + Read bit received, ACK transmitted
0xB0: Arbitration lost in the address as master, slave address +
Read bit received, ACK transmitted
0xB8: Data byte transmitted in slave mode, ACK received
0xC0: Data byte transmitted in slave mode, ACK not received
0xC8: The Last byte transmitted in slave mode, ACK received
0xD0: Second Address byte + Write bit transmitted, ACK received
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Offset: 0x0010 Register Name: TWI_STAT
Bit Read/Write Default/Hex Description
0xD8: Second Address byte + Write bit transmitted, ACK not
received
0xF8: No relevant status information, INT_FLAG=0
Others: Reserved
9.1.6.6 0x0014 TWI Clock Register (Default Value: 0x0000_0080)
Offset: 0x0014 Register Name: TWI_CCR
Bit Read/Write Default/Hex Description
31:8 / / /
CLK_DUTY
Setting duty cycle of clock as master
7 R/W 0x1
0: 50%
1: 40%
CLK_M
The TWI SCL output frequency, in master mode, is F1/10:
F1 = F0/(CLK_M + 1)
6:3 R/W 0x0
Fscl = F1/10 = Fin/(2^CLK_N * (CLK_M + 1)*10)
Specially, Fscl = F1/11 when CLK_M=0 and CLK_DUTY=40% due to
the delay of SCL sample debounce.
CLK_N
The TWI bus is sampled by the TWI at the frequency defined by F0:
Fsamp = F0 = Fin/2^CLK_N
The TWI SCL output frequency, in master mode, is F1/10:
F1 = F0/(CLK_M + 1)
Fscl = F1/10 = Fin/(2^CLK_N * (CLK_M + 1)*10)
Specially, Fscl = F1/11 when CLK_M=0 and CLK_DUTY=40% due to
2:0 R/W 0x0
the delay of SCL sample debounce.
For Example:
Fin = 24 MHz (APB clock input)
For 400 kHz full speed 2-wire, CLK_N = 1, CLK_M = 2
F0 = 24 MHz/2^1 = 12 MHz, F1 = F0/(10*(2+1)) = 0.4 MHz
For 100 kHz standard speed 2-wire, CLK_N = 1, CLK_M = 11
F0 = 24 MHz/2^1 = 12 MHz, F1 = F0/(10*(11+1)) = 0.1 MHz
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9.1.6.7 0x0018 TWI Soft Reset Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: TWI_SRST
Bit Read/Write Default/Hex Description
31:1 / / /
SOFT_RST
Soft Reset
0 R/WAC 0x0
Write ‘1’ to this bit to reset the TWI and clear to ‘0’ when
completing Soft Reset operation.
9.1.6.8 0x001C TWI Enhance Feature Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: TWI_EFR
Bit Read/Write Default/Hex Description
31:2 / / /
DBN
Data Byte Number Follow Read Command Control
00: No data byte can be written after the read command
1:0 R/W 0x0
01: Only 1-byte data can be written after the read command
10: 2-bytes data can be written after the read command
11: 3-bytes data can be written after the read command
9.1.6.9 0x0020 TWI Line Control Register (Default Value: 0x0000_003A)
Offset: 0x0020 Register Name: TWI_LCR
Bit Read/Write Default/Hex Description
31:6 / / /
SCL_STATE
Current State of TWI_SCL
5 R 0x1
0: Low
1: High
SDA_STATE
Current State of TWI_SDA
4 R 0x1
0: Low
1: High
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Offset: 0x0020 Register Name: TWI_LCR
Bit Read/Write Default/Hex Description
SCL_CTL
TWI_SCL Line State Control Bit
When the line control mode is enabled (bit[2] is set), this bit
3 R/W 0x1
decides the output level of TWI_SCL.
0: Output low level
1: Output high level
SCL_CTL_EN
TWI_SCL Line State Control Enable
When this bit is set, the state of TWI_SCL is controlled by the value
2 R/W 0x0
of bit[3].
0: Disable TWI_SCL line control mode
1: Enable TWI_SCL line control mode
SDA_CTL
TWI_SDA Line State Control Bit
When the line control mode is enabled (bit[0] is set), this bit
1 R/W 0x1
decides the output level of TWI_SDA.
0: Output low level
1: Output high level
SDA_CTL_EN
TWI_SDA Line State Control Enable
When this bit is set, the state of TWI_SDA is controlled by the value
0 R/W 0x0
of bit[1].
0: Disable TWI_SDA line control mode
1: Enable TWI_SDA line control mode
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9.1.6.10 0x0200 TWI_DRV Control Register (Default Value: 0x00F8_1000)
Offset: 0x0200 Register Name: TWI_DRV_CTRL
Bit Read/Write Default/Hex Description
START_TRAN
Start transmission
0: Transmission idle
1: Start transmission
31 R/WAC 0x0 Automatically cleared to ‘0’ when finished. If the slave is not
responding for the expected status over the time defined by
TIMEOUT, the current transmission will stop. All setting formats
and data will be loaded from registers and FIFO when the
transmission starts.
30 / / /
RESTART_MODE
Restart mode
29 R/W 0x0 0: RESTART
1: STOP+START
Define the TWI_DRV action after sending the register address.
READ_TRAN_MODE
Read transition mode
0: Send slave_id+W
28 R/W 0x0
1: Not send slave_id+W
Setting this bit to 1 if reading from a slave in which the register
width is equal to 0.
TRAN_RESULT
Transition result
27:24 R 0x0 000: OK
001: FAIL
Other: Reserved
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Offset: 0x0200 Register Name: TWI_DRV_CTRL
Bit Read/Write Default/Hex Description
TWI_STA
TWI status
0x00: bus error
0x08: START condition transmitted
0x10: Repeated START condition transmitted
0x18: Address + Write bit transmitted, ACK received
0x20: Address + Write bit transmitted, ACK not received
0x28: Data byte transmitted in master mode, ACK received
23:16 R 0xf8
0x30: Data byte transmitted in master mode, ACK not received
0x38: Arbitration lost in address or data byte
0x40: Address + Read bit transmitted, ACK received
0x48: Address + Read bit transmitted, ACK not received
0x50: Data byte received in master mode, ACK received
0x58: Data byte received in master mode, ACK not received
0x01: Timeout when sending the 9th SCL clock
Other: Reserved
TIMEOUT_N
Timeout number
15:8 R/W 0x10 When sending the 9th clock, assert fail signal when the slave device
does not respond after N*FSCL cycles. And the software must do a
reset to the TWI_DRV module and send a stop condition to slave.
7:2 / / /
SOFT_RESET
Software reset
1 R/W 0x0
0: Normal
1: Reset
TWI_DRV_EN
TWI driver enable
0 R/W 0x0
0: Module disable
1: Module enable (only use in TWI Master Mode)
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9.1.6.11 0x0204 TWI_DRV Transmission Configuration Register (Default Value: 0x0000_0001)
Offset: 0x0204 Register Name: TWI_DRV_CFG
Bit Read/Write Default/Hex Description
PKT_INTERVAL
31:16 R/W 0x0 Define the interval between each packet for PKT_INTERVAL FSCL
cycles.
PACKET_CNT
15:0 R/W 0x1 The FIFO data is transmitted as PACKET_CNT packets in current
format.
9.1.6.12 0x0208 TWI_DRV Slave ID Register (Default Value: 0x0000_0000)
Offset: 0x0208 Register Name: TWI_DRV_SLV
Bit Read/Write Default/Hex Description
31:16 / / /
SLV_ID
Slave device ID
For 7-bit addressing, the bit[7:1] indicates:
15:9 R/W 0x0
SLA6, SLA5, SLA4, SLA3, SLA2, SLA1, SLA0
For 10-bit addressing, the bit[7:1] indicates:
1, 1, 1, 1, 0, SLAX[9:8]
CMD
R/W operation to slave device
8 R/W 0x0
0: Write
1: Read
SLV_ID_X
7:0 R/W 0x0 SLAX[7:0]
The low 8 bits for slave device ID with 10-bit addressing.
9.1.6.13 0x020C TWI_DRV Packet Format Register (Default Value: 0x0001_0001)
Offset: 0x020C Register Name: TWI_DRV_FMT
Bit Read/Write Default/Hex Description
31:24 / / /
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Offset: 0x020C Register Name: TWI_DRV_FMT
Bit Read/Write Default/Hex Description
ADDR_BYTE
23:16 R/W 0x1 How many bytes be sent as slave device reg address
0~255
DATA_BYTE
15:0 R/W 0x1 How many bytes be sent/received as data
1~65535
9.1.6.14 0x0210 TWI_DRV Bus Control Register (Default Value: 0x0000_80C0)
Offset: 0x0210 Register Name: TWI_DRV_BUS_CTRL
Bit Read/Write Default/Hex Description
31:17 / / /
CLK_COUNT_MODE
Clock count mode
16 W 0x0
0: scl clock high period count on oscl
1: scl clock high period count on iscl
CLK_DUTY
Setting duty cycle of clock as Master
15 R/W 0x1
0: 50%
1: 40%
CLK_N
14:12 R/W 0x0
TWI_DRV bus sampling clock F0=24MHz/2^CLK_N
CLK_M
TWI_DRV output SCL frequency is FSCL=F1/10=(F0/(CLK_M+1))/10
11:8 R/W 0x0
Specially, Foscl = F1/11 when CLK_M=0 and CLK_DUTY=40% due
to the delay of SCL sample debounce.
SCL_STA
7 R 0x1
SCL current status
SDA_STA
6 R 0x1
SDA current status
5:4 / / /
SCL_MOV
3 R/W 0x0
SCL manual output value
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Offset: 0x0210 Register Name: TWI_DRV_BUS_CTRL
Bit Read/Write Default/Hex Description
SDA_MOV
2 R/W 0x0
SDA manual output value
SCL_MOE
1 R/W 0x0
SCL manual output enable
SDA_MOE
0 R/W 0x0
SDA manual output enable
9.1.6.15 0x0214 TWI_DRV Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0214 Register Name: TWI_DRV_INT_CTRL
Bit Read/Write Default/Hex Description
31:18 / / /
RX_REQ_INT_EN
19 R/W 0x0
If set, an interrupt is sent when RX_REQ_PD sets.
TX_REQ_INT_EN
18 R/W 0x0
If set, an interrupt is sent when TX_REQ_PD sets.
TRAN_ERR_INT_EN
17 R/W 0x0
If set, an interrupt is sent when TRAN_ERR_PD sets.
TRAN_COM_INT_EN
16 R/W 0x0
If set, an interrupt is sent when TRAN_COM_PD sets.
15:4 / / /
RX_REQ_PD
3 R/W1C 0x0
Set when the data byte number in RECV_FIFO reaches RX_TRIG.
TX_REQ_PD
2 R/W1C 0x0 Set when there is no less than DMA_TX_TRIG empty byte number
in SEND_FIFO.
TRAN_ERR_PD
1 R/W1C 0x0
Packet transmission failure pending
TRAN_COM_PD
0 R/W1C 0x0
Packet transmission completion pending
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9.1.6.16 0x0218 TWI_DRV DMA Configure Register (Default Value: 0x0010_0010)
Offset: 0x0218 Register Name: TWI_DRV_DMA_CFG
Bit Read/Write Default/Hex Description
31:25 / / /
DMA_RX_EN
24 R/W 0x0
DMA RX Enable
23:22 / / /
RX_TRIG
RX trigger
When DMA_RX_EN is set, send DMA RX Req when the data byte
21:16 R/W 0x10
number in RECV_FIFO reaches RX_TRIG, or the read transmission
is completed, the data of RECV_FIFO does not reach RX_TRIG but
as long as the RECV_FIFO is not empty.
15:9 / / /
DMA_TX_EN
8 R/W 0x0
DMA TX Enable
7:6 / / /
TX_TRIG
TX trigger
5:0 R/W 0x10
When DMA_TX_EN is set, send DMA TX Req when the space of
SEND_FIFO (FIFO Level – data volume) reaches TX_TRIG.
9.1.6.17 0x021C TWI_DRV FIFO Content Register (Default Value: 0x0000_0000)
Offset: 0x021C Register Name: TWI_DRV_FIFO_CON
Bit Read/Write Default/Hex Description
31:23 / / /
RECV_FIFO_CLEAR
22 R/WAC 0x0 Set this bit to clear RECV_FIFO pointer, and this bit is cleared
automatically.
RECV_FIFO_CONTENT
21:16 R 0x0
The number of data in RECV_FIFO
15:7 / / /
SEND_FIFO_CLEAR
6 R/WAC 0x0 Set this bit to clear SEND_FIFO pointer, and this bit is cleared
automatically.
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Offset: 0x021C Register Name: TWI_DRV_FIFO_CON
Bit Read/Write Default/Hex Description
SEND_FIFO_CONTENT
5:0 R 0x0
The number of data in SEND_FIFO
9.1.6.18 0x0300 TWI_DRV Send Data FIFO Access Register (Default Value: 0x0000_0000)
Offset: 0x0300 Register Name: TWI_DRV_SEND_FIFO_ACC
Bit Read/Write Default/Hex Description
31:8 / / /
SEND_DATA_FIFO
7:0 W 0x0 Address of a 32x8 SEND_FIFO, which stores reg address and data
sending to the slave device.
9.1.6.19 0x0304 TWI_DRV Receive Data FIFO Access Register (Default Value: 0x0000_0000)
Offset: 0x0304 Register Name: TWI_DRV_RECV_FIFO_ACC
Bit Read/Write Default/Hex Description
31:8 / / /
RECV_DATA_FIFO
7:0 R 0x0 Address of a 32x8 RECV_FIFO, which stores data received from the
slave device.
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9.2 UART
9.2.1 Overview
The universal asynchronous receiver transmitter (UART) provides an asynchronous serial communication with
external devices, modem (data carrier equipment, DCE). It performs serial-to-parallel conversion on the data
received from peripherals and transmits the converted data to the internal bus. It also performs parallel-to-
serial conversion on the data that is transmitted to peripherals.
The UART has the following features:
Compatible with industry-standard 16450/16550 UARTs
Supports IrDA-compatible slow infrared (SIR) format
Two separate FIFOs: one is RX FIFO, and the other is TX FIFO
- Each of them is 64 bytes (For UART0)
- Each of them is 256 bytes (For UART1, UART2, UART3, UART4, and UART5)
The working reference clock is from the APB bus clock
- Speed up to 4 Mbit/s with 64 MHz APB clock
- Speed up to 1.5 Mbit/s with 24 MHz APB clock
5 to 8 data bits for RS-232 characters, or 9 bits RS-485 format
1, 1.5 or 2 stop bits
Programmable parity (even, odd, or no parity)
Supports TX/RX DMA slave controller interface
Supports software/hardware flow control
Supports RX DMA Master interface (Only for UART1)
Supports auto-flow by using CTS & RTS (Only for UART1/2/3)
9.2.2 Block Diagram
Figure 9-9 shows a block diagram of the UART.
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Figure 9-9 UART Block Diagram
SGR
FIFO Modem
MC_SYNC Ctrl
TX_FIFO
(SYNC) TX sout
Regfile
RX_FIFO TO_DET
(ASYNC) RX sin
RXDMA
AHB
APB
9.2.3 Functional Description
9.2.3.1 External Signals
The following table describes the external signals of UART.
Table 9-4 UART External Signals
Signal Description Type
UART0-TX UART0 Data Transmit O
UART0-RX UART0 Data Receive I
UART1-TX UART1 Data Transmit O
UART1-RX UART1 Data Receive I
UART1-CTS UART1 Data Clear to Send I
UART1-RTS UART1 Data Request to Send O
UART2-TX UART2 Data Transmit O
UART2-RX UART2 Data Receive I
UART2-CTS UART2 Data Clear to Send I
UART2-RTS UART2 Data Request to Send O
UART3-TX UART3 Data Transmit O
UART3-RX UART3 Data Receive I
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Signal Description Type
UART3-CTS UART3 Data Clear to Send I
UART3-RTS UART3 Data Request to Send O
UART4-TX UART4 Data Transmit O
UART4-RX UART4 Data Receive I
UART5-TX UART5 Data Transmit O
UART5-RX UART5 Data Receive I
9.2.3.2 Clock Sources
The following table describes the clock sources of UART.
Table 9-5 UART Clock Sources
Clock Sources Description
APB1 Bus UART clock source. Refer to CCU for details on APB1.
9.2.3.3 Typical Applications and Timing Diagram
UART Serial Data Format
The following figure shows the UART serial data format. The start bit, data bit, parity bit, and stop bit can be
configured.
Figure 9-10 UART Serial Data Format
One Character
One Bit
TX/RX Start Data Bits5-8 Parity Stop
Using UART for RTS/CTS Autoflow Control
Figure 9-11 shows the typical application diagram for RTS/CTS autoflow control. Figure 9-12 shows the data
format of the RTS/CTS autoflow control.
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Figure 9-11 Application Diagram for RTS/CTS Autoflow Control
SoC
UART-TX
TX
UART-RX External
RX
UART1/2/3 UART-RTS UART
RTS Device
UART-CTS CTS
Figure 9-12 RTS/CTS Autoflow Control Data Format
TX Start Data Stop Start Data Stop Start Data Stop
CTS-
RX Start Data N Stop Start Data N+1 Stop Start Data N+2 Stop
RTS-
Using UART for Serial IrDA
Figure 9-13 shows the application diagram for the IrDA transceiver. Figure 9-14 shows the data format of the
serial IrDA.
Figure 9-13 Application Diagram for IrDA Transceiver
SoC
UART-TX
SIR_IN
UART-RX
SIR_OUT
UART1/2/3 UART-RTS
SD/MODE
UART-CTS
IrDA Transceiver
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Figure 9-14 Serial IrDA Data Format
Data Bits
Bit Time
SIN/SOUT S Stop
3/16 Bit Time 3/16 Bit Time
SIR_OUT
3/16 Bit Time
SIR_IN
Using UART for RS-485
Figure 9-15 shows the application diagram for the RS-485 transceiver. Figure 9-16 shows the data format of
the RS-485.
Figure 9-15 Application Diagram for RS-485 Transceiver
SoC
UART-TX
DIN
UART-RX RS-485
DOUT
UART1/2/3 UART-RTS Transceiver
TXEN
UART-CTS RXEN
Figure 9-16 RS-485 Data Format
TX Start Data P Stop
RTS Drive Enable
9.2.3.4 UART Operating Mode
Data Frame Format
The UART_LCR register can set the basic parameter of a data frame: data width (5 to 8 bits), stop bit number
(1/1.5/2), parity type.
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A frame transfer of the UART includes the start signal, data signal, parity bit, and stop signal. The LSB is
transmitted first.
Start signal (start bit): It is the start flag of a data frame. According to the UART protocol, the low level of
the TXD signal indicates the start of a data frame. When the UART transmits data, the level needs to hold
high.
Data signal (data bit): The data bit width can be configured as 5-bit, 6-bit, 7-bit, and 8-bit through different
applications.
Parity bit: It is a 1-bit error correction signal. Parity bit includes odd parity, even parity. The UART can
enable and disable the parity bit by setting the UART_LCR register.
Stop Signal (stop bit): It is the stop bit of a data frame. The stop bit can be set to 1-bit, 1.5-bit, and 2-bit
by the UART_LCR register. The high level of the TXD signal indicates the end of a data frame.
Baud and Error Rates
The baud rate is calculated as follows: Baud rate = SCLK/(16 * divisor).
The SCLK is usually APB1 and can be set in section 3.3 “CCU”.
The divisor is frequency divider of UART. The frequency divider has 16-bit, the low 8-bit is in the UART_DLL
register, the high 8-bit is in the UART_DLH register.
The relationship between the different UART mode and the error rate is as follows.
Figure 9-17 UART Mode Baud and Error Rates
Clock source Divisor Baud rate Over sampling Error (%)
24000000 5000 300 16 0
24000000 2500 600 16 0
24000000 1250 1200 16 0
24000000 625 2400 16 0
24000000 313 4800 16 -0.16
24000000 156 9600 16 0.16
24000000 78 19200 16 0.16
24000000 39 38400 16 0.16
24000000 26 57600 16 0.16
24000000 13 115200 16 0.16
48000000 13 230400 16 0.16
64000000 7 576000 16 -0.794
75000000 5 921600 16 1.725
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Clock source Divisor Baud rate Over sampling Error (%)
48000000 3 1000000 16 0
24000000 1 1500000 16 0
48000000 1 3000000 16 0
64000000 1 4000000 16 0
Figure 9-18 IrDA Mode Baud and Error Rates
Clock source Divisor Baud rate Encoding Error (%)
24000000 5000 300 3/16 0
24000000 2500 600 3/16 0
24000000 1250 1200 3/16 0
24000000 625 2400 3/16 0
24000000 313 4800 3/16 -0.16
24000000 156 9600 3/16 0.16
24000000 78 19200 3/16 0.16
24000000 39 38400 3/16 0.16
24000000 26 57600 3/16 0.16
24000000 13 115200 3/16 0.16
Figure 9-19 RS485 Mode Baud and Error Rates
Clock source Divisor Baud rate Encoding Error (%)
24000000 5000 300 16 0
24000000 2500 600 16 0
24000000 1250 1200 16 0
24000000 625 2400 16 0
24000000 313 4800 16 -0.16
24000000 156 9600 16 0.16
24000000 78 19200 16 0.16
24000000 39 38400 16 0.16
24000000 26 57600 16 0.16
24000000 13 115200 16 0.16
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DLAB Definition
The DLAB control bit (UART_LCR[7]) is the access control bit of the divisor Latch register.
If DLAB is 0, then the 0x00 offset address is the UART_RBR/UART_THR (RX/TX FIFO) register, and the 0x04
offset address is the UART_IER register.
If DLAB is 1, then the 0x00 offset address is the UART_DLL register, and the 0x04 offset address is the
UART_DLH register.
When the UART initials, the divisor needs to be set. That is, writing 1 to DLAB can access the UART_DLL and
UART_DLH register, after finished the configuration, writing 0 to DLAB can access the UART_RBR/UART_THR
register.
CHCFG_AT_BUSY Definition
The function of the CHCFG_AT_BUSY (UART_HALT[1]) and CHANGE_UPDATE (UART_HALT[2]) are as follows.
CHCFG_AT_BUSY: Enable the bit, the software can also set the UART controller when UART is busy, such as the
UART_LCR, UART_DLH, UART_DLL register.
CHANGE_UPDATE: If CHCFG_AT_BUSY is enabled, and CHANGE_UPDATE is written to 1, the configuration of
the UART controller can be updated. After completed the update, the bit is cleared to 0 automatically.
Setting divisor performs the following steps:
Step 1 Write 1 to CHCFG_AT_BUSY to enable “configure at busy”.
Step 2 Write 1 to DLAB (UART_LCR[7]) and set the UART_DLH and UART_DLL registers.
Step 3 Write 1 to CHANGE_UPDATE to update the configuration. The bit is cleared to 0 automatically after
completing the update.
UART Busy Flag
The UART_USR[0] is a busy flag of the UART controller.
When the TX transmits data, or the RX receives data, or the TX FIFO is not empty, or the RX FIFO is not empty,
then the busy flag bit can be set to 1 by hardware, which indicates the UART controller is busy.
9.2.4 Programming Guidelines
The following takes the UART module in the CPUX domain as an example.
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9.2.4.1 Initialization
Step 1 System Initialization
Configure APB1_CFG_REG in the CCU module to set the APB1 bus clock (The clock is 24MHz by
default).
Set UART_BGR_REG[UARTx_GATING] to 1 to enable the module clock, and set
UART_BGR_REG[UARTx_RST] to 1 to de-assert the module.
Step 2 UART Controller Initialization
IO configuration: Configure GPIO multiplex as UART function, and set UART pins to internal pull-
up mode (For detail, see the description in section 9.7 “GPIO”).
Baud-rate configuration:
Set UART baud-rate (refer to section 9.2.3.4);
Write UART_FCR[FIFOE] to 1 to enable TX/RX FIFO;
Write UART_HALT[HALT_TX] to 1 to disable TX transfer;
Set UART_LCR[DLAB] to 1, remain default configuration for other bits; set 0x00 offset
address to the UART_DLL register, set 0x04 offset address to the UART_DLH register;
Write the high 8-bit of divisor to the UART_DLH register, and write the low 8-bit of divisor
to the UART_DLL register;
Set UART_LCR[DLAB] to 0, remain default configuration for other bits; set 0x00 offset
address to the UART_RBR/UART_THR register, set 0x04 offset address to the UART_IER
register;
Set UART_HALT[HALT_TX] to 0 to enable TX transfer.
Step 3 Controller Parameter Configuration
Set data width, stop bits, and even/odd parity type by writing the UART_LCR register.
Reset, enable FIFO and set FIFO trigger condition by writing the UART_FCR register.
Set the flow control parameter by writing the UART_MCR register.
Step 4 Interrupt Configuration
Configure UART interrupt vector number to request UART interrupt (Refer to section 3.8 “PLIC”
module for interrupt vector number).
In DMA mode, write UART_IER to 0 to disable interrupt; write UART_HSK[Handshake
configuration] to 0xE5 to set DMA handshake mode; write UART_FCR[DMAM] to 1 to set DMA
transmission/reception mode; set DMA parameter and request DMA interrupt according to
DMA configuration process.
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In Interrupt mode, configure UART_IER to enable the corresponding interrupt according to
requirements: such as transmit (TX) interrupt, receive (RX) interrupt, receive line status
interrupt, RS48 interrupt, etc. (Here TX/RX interrupt is usually used).
9.2.4.2 Transferring/Receiving Data in Query Mode
Data transfer
Step 1 Write data to UART_THR to start data transfer.
Step 2 Check TX_FIFO status by reading UART_USR[TFNF]. If the bit is 1, data can continue to be written; if
the bit is 0, wait for data transfer, and data cannot continue to write until FIFO is not full.
Data receive
Step 1 Check RX_FIFO status by reading UART_USR[RFNE].
Step 2 Read data from UART_RBR if RX_FIFO is not empty.
Step 3 If UART_USR[RFNE] is 0, data is received completely.
9.2.4.3 Transferring/Receiving Data in Interrupt Mode
Data transfer
Step 1 Set UART_IER[ETBEI] to 1 to enable the UART transmission interrupt.
Step 2 Write the data to be transmitted to UART_THR.
Step 3 When the data of TX_FIFO meets trigger condition (such as FIFO/2, FIFO/4), the UART transfer
interrupt is generated.
Step 4 Check UART_USR[TFE] and determine whether TX_FIFO is empty. If UART_USR[TFE] is 1, it indicates
that the data in TX_FIFO is transmitted completely.
Step 5 Clear UART_IER[ETBEI] to 0 to disable transfer interrupt.
Data receive
Step 1 Set UART_IER[ERBFI] to 1 to enable the UART reception interrupt.
Step 2 When the received data from RX_FIFO meets trigger condition (such as FIFO/2, FIFO/4), the UART
receive interrupt is generated.
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Step 3 Read data from UART_RBR.
Step 4 Check RX_FIFO status by reading UART_USR[RFNE] and determine whether to read data. If the bit is
1, continue to read data from UART_RBR until UART_USR[RFNE] is cleared to 0, which indicates data
is received completely.
9.2.4.4 Transferring/Receiving Data in DMA Mode
Data transfer
Step 1 Configure the UART DMA interrupt according to the initialization process.
Step 2 Configure DMA data channel, including the transfer source address, the transfer destination address,
the number of data to be transferred, and the transfer type, and so on. (For details, see section 3.9
“DMAC”).
Step 3 Enable the DMA transfer function of the UART by setting the register of the DMA module.
Step 4 Determine whether UART data is transferred completely based on the DMA status. If all data is
transferred completely, disable the DMA transfer function of the UART.
Data receive
Step 1 Configure DMA data channel, including the transfer source address, the transfer destination address,
the number of data to be transferred, and the transfer type, and so on. (For details, see section 3.9
“DMAC”).
Step 2 Enable the DMA receive function of the UART by setting the register of the DMA module.
Step 3 Determine whether UART data is received completely based on the DMA status. If all data is received
completely, disable the DMA receive function of the UART.
9.2.5 Register List
Module Name Base Address
UART0 0x02500000
UART1 0x02500400
UART2 0x02500800
UART3 0x02500C00
UART4 0x02501000
UART5 0x02501400
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Register Name Offset Description
UART_RBR 0x0000 UART Receive Buffer Register
UART_THR 0x0000 UART Transmit Holding Register
UART_DLL 0x0000 UART Divisor Latch Low Register
UART_DLH 0x0004 UART Divisor Latch High Register
UART_IER 0x0004 UART Interrupt Enable Register
UART_IIR 0x0008 UART Interrupt Identity Register
UART_FCR 0x0008 UART FIFO Control Register
UART_LCR 0x000C UART Line Control Register
UART_MCR 0x0010 UART Modem Control Register
UART_LSR 0x0014 UART Line Status Register
UART_MSR 0x0018 UART Modem Status Register
UART_SCH 0x001C UART Scratch Register
UART_USR 0x007C UART Status Register
UART_TFL 0x0080 UART Transmit FIFO Level Register
UART_RFL 0x0084 UART Receive FIFO Level Register
UART_HSK 0x0088 UART DMA Handshake Configuration Register
UART_DMA_REQ_EN 0x008C UART DMA Request Enable Register
UART_HALT 0x00A4 UART Halt TX Register
UART_DBG_DLL 0x00B0 UART Debug DLL Register
UART_DBG_DLH 0x00B4 UART Debug DLH Register
UART_A_FCC 0x00F0 UART FIFO Clock Control Register
UART_A_RXDMA_CTRL 0x0100 UART RXDMA Control Register
UART_A_RXDMA_STR 0x0104 UART RXDMA Start Register
UART_A_RXDMA_STA 0x0108 UART RXDMA Status Register
UART_A_RXDMA_LMT 0x010C UART RXDMA Limit Register
UART_A_RXDMA_SADDRL 0x0110 UART RXDMA Buffer Start Address Low Register
UART_A_RXDMA_SADDRH 0x0114 UART RXDMA Buffer Start Address High Register
UART_A_RXDMA_BL 0x0118 UART RXDMA Buffer Length Register
UART_A_RXDMA_IE 0x0120 UART RXDMA Interrupt Enable Register
UART_A_RXDMA_IS 0x0124 UART RXDMA Interrupt Status Register
UART_A_RXDMA_WADDRL 0x0128 UART RXDMA Write Address Low Register
UART_A_RXDMA_WADDRH 0x012C UART RXDMA Write Address high Register
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Register Name Offset Description
UART_A_RXDMA_RADDRL 0x0130 UART RXDMA Read Address Low Register
UART_A_RXDMA_RADDRH 0x0134 UART RXDMA Read Address high Register
UART_A_RXDMA_DCNT 0x0138 UART RADMA Data Count Register
9.2.6 Register Description
9.2.6.1 0x0000 UART Receiver Buffer Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: UART_RBR
Bit Read/Write Default/Hex Description
31:8 / / /
RBR
Receiver Buffer Register
Data byte received on the serial input port (sin) in UART mode, or
the serial infrared input (sir_in) in infrared mode. The data in this
register is valid only if the Data Ready (DR) bit in UART_LCR is set.
7:0 R 0x0 If in FIFO mode and FIFOs are enabled (The UART_FCR[0] is set to
1), this register accesses the head of the receive FIFO. If the
receive FIFO is full and this register can not read before the next
data character arrives, then the data already in the FIFO are
preserved, but any incoming data are lost and an overrun error
occurs.
9.2.6.2 0x0000 UART Transmit Holding Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: UART_THR
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x0000 Register Name: UART_THR
Bit Read/Write Default/Hex Description
THR
Transmit Holding Register
Data is transmitted on the serial output port (SOUT) in UART
mode or the serial infrared output (sir_out_n) in infrared mode.
Data should only be written to the UART_THR when the THRE bit
7:0 W 0x0
(UART_LSR[5]) is set.
If in FIFO mode and FIFOs are enabled (UART_FCR[0] = 1) and
THRE is set, the 16 number of characters data may be written to
the UART_THR before the FIFO is full. When the FIFO is full, any
written data results in the written data being lost.
9.2.6.3 0x0000 UART Divisor Latch Low Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: UART_DLL
Bit Read/Write Default/Hex Description
31:8 / / /
DLL
Divisor Latch Low
Lower 8 bits of 16 bits, read/write, Divisor Latch Register contains
the baud rate divisor for the UART. This register may only be
accessed when the DLAB bit (UART_LCR[7]) is set and the UART is
not busy (UART_USR[0] is 0).
The output baud rate is equal to the serial clock (SCLK) frequency
7:0 R/W 0x0
divided by sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq)/(16 * divisor).
Note that when the Divisor Latch Registers (UART_DLL and
UART_DLH) are set to 0, the baud clock is disabled and no serial
communications occur. Also, once the DLL is set, at least 8 clock
cycles of the slowest UART clock should be allowed to pass before
transmitting or receiving data.
9.2.6.4 0x0004 UART Divisor Latch High Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: UART_DLH
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x0004 Register Name: UART_DLH
Bit Read/Write Default/Hex Description
DLH
Divisor Latch High
Upper 8 bits of 16 bits, read/write, Divisor Latch Register contains
the baud rate divisor for the UART. This register may only be
accessed when the DLAB bit (UART_LCR[7]) is set and the UART is
not busy (UART_USR[0] is 0).
The output baud rate is equal to the serial clock (SCLK) frequency
7:0 R/W 0x0
divided by sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq)/(16 * divisor).
Note that when the Divisor Latch Registers (UART_DLL and
UART_DLH) is set to 0, the baud clock is disabled and no serial
communications occur. Also, once the DLH is set, at least 8 clock
cycles of the slowest UART clock should be allowed to pass before
transmitting or receiving data.
9.2.6.5 0x0004 UART Interrupt Enable Register (Default Value: 0x0000_0000)
Offset: 0x0004 Register Name: UART_IER
Bit Read/Write Default/Hex Description
31:8 / / /
PTIME
Programmable THRE Interrupt Mode Enable
7 R/W 0x0 This is used to enable/disable the generation of THRE Interrupt.
0: Disable
1: Enable
6:5 / / /
RS485_INT_EN
RS485 Interrupt Enable
4 R/W 0x0
0: Disable
1: Enable
EDSSI
Enable Modem Status Interrupt
This is used to enable/disable the generation of Modem Status
3 R/W 0x0
Interrupt. This is the fourth highest priority interrupt.
0: Disable
1: Enable
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Offset: 0x0004 Register Name: UART_IER
Bit Read/Write Default/Hex Description
ELSI
Enable Receiver Line Status Interrupt
This is used to enable/disable the generation of Receiver Line
2 R/W 0x0
Status Interrupt. This is the highest priority interrupt.
0: Disable
1: Enable
ETBEI
Enable Transmit Holding Register Empty Interrupt
This is used to enable/disable the generation of Transmitter
1 R/W 0x0 Holding Register Empty Interrupt. This is the third-highest priority
interrupt.
0: Disable
1: Enable
ERBFI
Enable Received Data Available Interrupt
This is used to enable/disable the generation of Received Data
Available Interrupt and the Character Timeout Interrupt (if in FIFO
0 R/W 0x0
mode and FIFOs enabled). These are the second-highest priority
interrupt.
0: Disable
1: Enable
9.2.6.6 0x0008 UART Interrupt Identity Register (Default Value: 0x0000_0001)
Offset: 0x0008 Register Name: UART_IIR
Bit Read/Write Default/Hex Description
31:8 / / /
FEFLAG
FIFOs Enable Flag
7:6 R 0x0 This is used to indicate whether the FIFOs are enabled or disabled.
00: Disable
11: Enable
5:4 / / /
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Offset: 0x0008 Register Name: UART_IIR
Bit Read/Write Default/Hex Description
IID
Interrupt ID
This indicates the highest priority pending interrupt which can be
one of the following types.
0000: modem status
0001: no interrupt pending
0010: THR empty
3:0 R 0x1 0011: RS485 Interrupt
0100: received data available
0110: receiver line status
0111: busy detect
1100: character timeout
The bit 3 indicates an interrupt can only occur when the FIFOs are
enabled and used to distinguish a Character Timeout condition
interrupt.
Interrupt Priority Interrupt
Interrupt Source Interrupt Reset
ID Level Type
0001 - None None -
Receiver
Overrun/parity/framing
0110 Highest line Reading the line status register
errors or break interrupt
status
In RS485 mode, receives
RS485
0011 Second address data and match Writes 1 to addr flag to reset
Interrupt
setting address
Receiver data available (non- Reading the receiver buffer
Received FIFO mode or FIFOs disabled) register (non-FIFO mode or FIFOs
0100 Third data or RCVR FIFO trigger level disabled) or the FIFO drops below
available reached (FIFO mode and the trigger level (FIFO mode and
FIFOs enabled) FIFOs enabled)
No characters in or out of the
RCVR FIFO during the last 4
Character
character times and there is Reading the receiver buffer
1100 Fourth timeout
at least 1character in it register
indication
during
This time
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Interrupt Priority Interrupt
Interrupt Source Interrupt Reset
ID Level Type
Reading the IIR register (if the
Transmitter holding register
Transmit source of interrupt); or, writing
empty (Program THRE mode
holding into THR (FIFOs or THRE mode not
0010 Fifth disabled) or XMIT FIFO at or
register selected or disabled) or XMIT FIFO
below threshold (Program
empty above threshold (FIFOs and THRE
THRE mode enabled)
mode selected and enabled).
Clear to send or data set
ready or ring indicator or
data carrier detect. Note that
Modem Reading the Modem status
0000 Sixth if the autoflow control mode
status register
is enabled, a change in CTS
(that is, DCTS set) does not
cause an interrupt.
UART_16550_COMPATIBLE =
Busy NO and master has tried to
0111 Seventh detect write to the Line Control Reading the UART status register
indication Register while the UART is
busy (USR[0] is set to one).
9.2.6.7 0x0008 UART FIFO Control Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: UART_FCR
Bit Read/Write Default/Hex Description
31:8 / / /
RT
RCVR Trigger
This is used to select the trigger level in the receiver FIFO when
the Received Data Available Interrupt is generated. In the
autoflow control mode, it is used to determine when the rts_n
7:6 W 0x0 signal is de-asserted. It also determines when the dma_rx_req_n
signal is asserted in certain modes of operation.
00: 1 character in the FIFO
01: FIFO ¼ full
10: FIFO ½ full
11: FIFO-2 less than full
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Offset: 0x0008 Register Name: UART_FCR
Bit Read/Write Default/Hex Description
TFT
TX Empty Trigger
This is used to select the empty threshold level when the THRE
Interrupts are generated and the mode is active. It also
determines when the dma_tx_req_n signal is asserted in certain
5:4 W 0x0
modes of operation.
00: FIFO empty
01: 2 characters in the FIFO
10: FIFO ¼ full
11: FIFO ½ full
DMAM
DMA Mode
0: Mode 0
In this mode, when the PTE in UART_HALT is high and TX FIFO is
enabled, the TX DMA request will be set when the TFL in
UART_TFL is less than or equal to FIFO Trigger Level (otherwise it
will be cleared). When the PTE is high and TX FIFO is disabled, the
TX DMA request will be set only if the THR in UART_THR is empty.
If the PTE is low, the TX DMA request will be set only if the TX FIFO
(TX FIFO enabled) or THR (TX FIFO disabled) is empty.
When the DMA_PTE_RX in UART_HALT is high and RX FIFO is
enabled, the RX DRQ will be set only if the RFL in UART_RFL is
3 W 0x0
equal to or more than FIFO Trigger Level, otherwise, it will be
cleared.
1: Mode 1
In this mode, TX FIFO should be enabled. If the PTE in UART_HALT
is high, the TX DMA request will be set when the TFL in UART_TFL
is less than or equal to FIFO Trigger Level; If the PTE is low, the TX
DMA request will be set when TX FIFO is empty. Once the request
is set, it is cleared only when TX FIFO is full.
If the RFL in UART_RFL is equal to or more than FIFO Trigger Level
or there is a character timeout, the RX DRQ will be set; Once the
RX DRQ is set, it is cleared only when RX FIFO (RX FIFO enabled)
or RBR (RX FIFO disabled) is empty.
XFIFOR
XMIT FIFO Reset
2 W 0x0 The bit resets the control part of the transfer FIFO and treats the
FIFO as empty. This also de-asserts the DMA TX request.
It is 'self-cleared'. It is not necessary to clear this bit.
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Offset: 0x0008 Register Name: UART_FCR
Bit Read/Write Default/Hex Description
RFIFOR
RCVR FIFO Reset
1 W 0x0 The bit resets the control part of the receive FIFO and treats the
FIFO as empty. This also de-asserts the DMA RX request.
It is 'self-cleared'. It is not necessary to clear this bit.
FIFOE
Enable FIFOs
0 W 0x0 The bit enables/disables the transmitting (XMIT) and receiving
(RCVR) FIFOs. Whenever the value of this bit is changed, both the
XMIT and RCVR controller part of FIFOs is reset.
9.2.6.8 0x000C UART Line Control Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: UART_LCR
Bit Read/Write Default/Hex Description
31:8 / / /
DLAB
Divisor Latch Access Bit
It is writable only when UART is not busy (UART_USR[0] is 0) and
always readable. This bit is used to enable the reading and writing
of the Divisor Latch register (UART_DLL and UART_DLH) to set the
7 R/W 0x0 baud rate of the UART. This bit must be cleared after the initial
baud rate setup in order to access other registers.
0: Select RX Buffer Register (UART_RBR)/TX Holding Register
(UART_THR) and Interrupt Enable Register (UART_IER)
1: Select Divisor Latch LS Register (UART_DLL) and Divisor Latch
MS Register (UART_DLM)
BC
Break Control Bit
This is used to cause a break condition to be transmitted to the
receiving device. If set to 0, the serial output is forced to the
spacing (logic 0) state. When not in Loopback mode, as
6 R/W 0x0
determined by UART_MCR[4], the SOUT line is forced low until
the Break bit is cleared. If SIR_MODE is enabled and active
(UART_MCR[6] is set to 1), the sir_out_n line is continuously
pulsed. When in Loopback mode, the break condition is internally
looped back to the receiver and the sir_out_n line is forced low.
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Offset: 0x000C Register Name: UART_LCR
Bit Read/Write Default/Hex Description
EPS
Even Parity Select
It is writable only when UART is not busy (UART_USR[0] is 0). This
is used to select the even and odd parity when the PEN is enabled
(the UART_LCR[3] is set to 1). Setting the UART_LCR[5] is unset to
reverse the LCR[4].
00: Odd Parity
5:4 R/W 0x0
01: Even Parity
1X: Reverse LCR[4]
In RS485 mode, it is the 9th bit--address bit.
11: 9th bit = 0, indicates that this is a data byte.
10: 9th bit = 1, indicates that this is an address byte.
Note: When using this function, the PEN(UART_LCR[3]) must set
to 1.
PEN
Parity Enable
It is writable only when UART is not busy (UART_USR[0] is 0) and
always readable. This bit is used to enable and disable parity
3 R/W 0x0
generation and detection in transmitted and received serial
characters respectively.
0: Parity disabled
1: Parity enabled
STOP
Number of stop bits
It is writable only when UART is not busy (UART_USR[0] is 0) and
always readable. This is used to select the number of stop bits per
character that the peripheral transmits and receives. If set to 0,
one stop bit is transmitted in the serial data. If set to 1 and the
2 R/W 0x0
data bits are set to 5 (UART_LCR[1:0] is 0), one and a half stop bit
is transmitted. Otherwise, two stop bits are transmitted. Note
that regardless of the number of stop bits selected, the receiver
checks only the first stop bit.
0: 1 stop bit
1: 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
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Offset: 0x000C Register Name: UART_LCR
Bit Read/Write Default/Hex Description
DLS
Data Length Select
It is writable only when UART is not busy (UART_USR[0] is 0) and
always readable. This is used to select the count of bits in a
1:0 R/W 0x0 transmitted or received frame.
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
9.2.6.9 0x0010 UART Modem Control Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: UART_MCR
Bit Read/Write Default/Hex Description
31:8 / / /
UART_FUNCTION
Select IrDA or RS485
00: UART Mode
7:6 R/W 0x0
01: IrDA SIR Mode
10: RS485 Mode
11: Reserved
AFCE
Auto Flow Control Enable
When FIFOs are enabled and the AFCE bit is set, the AutoFlow
5 R/W 0x0
Control is enabled.
0: Auto Flow Control mode disabled
1: Auto Flow Control mode enabled
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Offset: 0x0010 Register Name: UART_MCR
Bit Read/Write Default/Hex Description
LOOP
Loop Back Mode
0: Normal Mode
1: Loop Back Mode
This is used to put the UART into a diagnostic mode for test
purposes. If operating in UART mode (SIR_MODE != Enabled or
not active, UART_MCR[6] is set to 0), the data on the SOUT line is
4 R/W 0x0 held high, while serial data output is looped back to the sin line,
internally. In this mode, all the interrupts are fully functional. Also,
in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n,
dcd_n) are disconnected and the modem control outputs (dtr_n,
rts_n, out1_n, out2_n) are looped back to the inputs, internally. If
operating in infrared mode (SIR_MODE == Enabled AND active,
UART_MCR[6] is set to 1), the data on the sir_out_n line is held
low, while serial data output is inverted and looped back to the
sir_in line.
3:2 / / /
RTS
Request to Send
This is used to directly control the Request to Send (rts_n) output.
The RTS (rts_n) output is used to inform the modem or data set
that the UART is ready to exchange data. When Auto RTS Flow
Control is not enabled (UART_MCR[5] is set to 0), the rts_n signal
is set low by programming UART_MCR[1] (RTS) to a high. In Auto
Flow Control, AFCE_MODE == Enabled and active (UART_MCR[5]
is set to 1) and FIFOs enable (UART_FCR[0] is set to 1), the rts_n
1 R/W 0x0
output is controlled in the same way, but is also gated with the
receiver FIFO threshold trigger (rts_n is inactive high when above
the threshold). The rts_n signal is de-asserted when
UART_MCR[1] is set low.
0: rts_n de-asserted (logic 1)
1: rts_n asserted (logic 0)
Note that in Loopback mode (UART_MCR[4] is set to 1), the rts_n
output is held inactive high while the value of this location is
internally looped back to an input.
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Offset: 0x0010 Register Name: UART_MCR
Bit Read/Write Default/Hex Description
DTR
Data Terminal Ready
This is used to directly control the Data Terminal Ready (dtr_n)
output. The value written to this location is inverted and driven
out on dtr_n.
0: dtr_n de-asserted (logic 1)
0 R/W 0x0
1: dtr_n asserted (logic 0)
The DTR output is used to inform the modem or data set that the
UART is ready to establish communications.
Note that in Loopback mode (UART_MCR[4] is set to 1), the dtr_n
output is held inactive high while the value of this location is
internally looped back to an input.
9.2.6.10 0x0014 UART Line Status Register (Default Value: 0x0000_0060)
Offset:0x0014 Register Name: UART_LSR
Bit Read/Write Default/Hex Description
31:8 / / /
FIFOERR
RX Data Error in FIFO
When FIFOs are disabled, this bit is always 0. When FIFOs are
7 R 0x0
enabled, this bit is set to “1” when there is at least one PE, FE, or
BI in the RX FIFO. It is cleared by reading from the UART_LSR
register, there are no subsequent errors in the FIFO.
TEMT
Transmitter Empty
If the FIFOs are disabled, this bit is set to "1" whenever the TX
6 R 0x1 Holding Register (UART_THR) and the TX Shift Register are empty.
If the FIFOs are enabled, this bit is set whenever the TX FIFO and
the TX Shift Register are empty. In both cases, this bit is cleared
when a byte is written to the TX data channel.
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Offset:0x0014 Register Name: UART_LSR
Bit Read/Write Default/Hex Description
THRE
TX Holding Register Empty
If the FIFOs are disabled, this bit is set to "1" when the TX Holding
Register (UART_THR) is empty and ready to accept new data and
5 R 0x1
it is cleared when the CPU writes to the TX Holding Register.
If the FIFOs are enabled, this bit is set to "1" whenever the TX FIFO
is empty and it is cleared when at least one byte is written to the
TX FIFO.
BI
Break Interrupt
This is used to indicate the detection of a break sequence on the
serial input data.
If in UART mode (SIR_MODE == Disabled), it is set when the serial
input, sir_in, is held in a logic '0' state for longer than the sum of
start time + data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set when the
4 R 0x0 serial input, sir_in, is continuously pulsed to logic '0' for longer
than the sum of start time + data bits + parity + stop bits. A break
condition on serial input causes one and only one character,
consisting of all zeros, to be received by the UART.
In the FIFO mode, the character associated with the break
condition is carried through the FIFO and is revealed when the
character is at the top of the FIFO. Reading the UART_LSR clears
the BI bit. In the non-FIFO mode, the BI indication occurs
immediately and persists until the UART_LSR is read.
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Offset:0x0014 Register Name: UART_LSR
Bit Read/Write Default/Hex Description
FE
Framing Error
This is used to indicate the occurrence of a framing error in the
receiver. A framing error occurs when the receiver does not
detect a valid STOP bit in the received data.
In the FIFO mode, since the framing error is associated with a
character received, it is revealed when the character with the
framing error is at the top of the FIFO. When a framing error
3 RC 0x0 occurs, the UART tries to resynchronize. It does this by assuming
that the error was due to the start bit of the next character and
then continues receiving the other bit i.e. data, and/or parity and
stop. It should be noted that the Framing Error (FE) bit
(UART_LSR[3]) is set if a break interrupt has occurred, as indicated
by Break Interrupt (BI) bit (UART_LSR[4]).
0: no framing error
1: framing error
Reading the UART_LSR clears the FE bit.
PE
Parity Error
This is used to indicate the occurrence of a parity error in the
receiver if the Parity Enable (PEN) bit (UART_LCR[3]) is set. In the
FIFO mode, since the parity error is associated with a character
received, it is revealed when the character with the parity error
2 RC 0x0
arrives at the top of the FIFO. It should be noted that the Parity
Error (PE) bit (UART_LSR[2]) is set if a break interrupt has
occurred, as indicated by Break Interrupt (BI) bit (UART_LSR[4]).
0: no parity error
1: parity error
Reading the UART_LSR clears the PE bit.
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Offset:0x0014 Register Name: UART_LSR
Bit Read/Write Default/Hex Description
OE
Overrun Error
This occurs if a new data character was received before the
previous data was read. In the non-FIFO mode, the OE bit is set
when a new character arrives in the receiver before the previous
character was read from the UART_RBR. When this happens, the
1 RC 0x0 data in the UART_RBR is overwritten. In the FIFO mode, an
overrun error occurs when the FIFO is full and a new character
arrives at the receiver. The data in the FIFO is retained and the
data in the receive shift register is lost.
0: no overrun error
1: overrun error
Reading the UART_LSR clears the OE bit.
DR
Data Ready
This is used to indicate that the receiver contains at least one
character in the UART_RBR or the receiver FIFO.
0: no data ready
0 R 0x0
1: data ready
This bit is cleared when the UART_RBR is read in non-FIFO mode,
or when the receiver FIFO is empty, in FIFO mode.
Note: Not use when the RXDMA master is enabled
(rxdma_ctrl[0] is set to 1).
9.2.6.11 0x0018 UART Modem Status Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: UART_MSR
Bit Read/Write Default/Hex Description
31:8 / / /
DCD
Line State of Data Carrier Detect
This is used to indicate the current state of the modem control
line dcd_n. This bit is the complement of dcd_n. When the Data
7 R 0x0
Carrier Detect input (dcd_n) is asserted it is an indication that the
carrier has been detected by the modem or data set.
0: dcd_n input is de-asserted (logic 1)
1: dcd_n input is asserted (logic 0)
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Offset: 0x0018 Register Name: UART_MSR
Bit Read/Write Default/Hex Description
RI
Line State of Ring Indicator
This is used to indicate the current state of the modem control
line ri_n. This bit is the complement of ri_n. When the Ring
6 R 0x0
Indicator input (ri_n) is asserted it is an indication that a telephone
ringing signal has been received by setting the modem or data.
0: ri_n input is de-asserted (logic 1)
1: ri_n input is asserted (logic 0)
DSR
Line State of Data Set Ready
This is used to indicate the current state of the modem control
line dsr_n. This bit is the complement of the dsr_n. When the Data
Set Ready input (dsr_n) is asserted, it is an indication that the
5 R 0x0 modem or data set is ready to establish communication with
UART.
0: dsr_n input is de-asserted (logic 1)
1: dsr_n input is asserted (logic 0)
In Loopback Mode (UART_MCR[4] is set to 1), the DSR is the same
as the DTR (UART_MCR[0]).
CTS
Line State of Clear To Send
This is used to indicate the current state of the modem control
line cts_n. This bit is the complement of cts_n. When the Clear to
Send input (cts_n) is asserted, it is an indication that the modem
4 R 0x0
or data set is ready to exchange data with UART.
0: cts_n input is de-asserted (logic 1)
1: cts_n input is asserted (logic 0)
In Loopback Mode (UART_MCR[4] = 1), the CTS is the same as the
RTS (UART_MCR[1]).
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Offset: 0x0018 Register Name: UART_MSR
Bit Read/Write Default/Hex Description
DDCD
Delta Data Carrier Detect
This is used to indicate that the modem control line dcd_n has
changed since the last time the UART_MSR was read.
0: no change on dcd_n since the last read of UART_MSR
3 RC 0x0
1: change on dcd_n since the last read of UART_MSR
Reading the UART_MSR clears the DDCD bit.
Note: If the DDCD bit is not set and the dcd_n signal is asserted
(low) and a reset occurs, then the DDCD bit is set when the reset
is removed if the dcd_n signal remains asserted.
TERI
Trailing Edge Ring Indicator
This is used to indicate that a change in the input ri_n (from an
active-low to an inactive-high state) has occurred since the last
2 RC 0x0
time the UART_MSR was read.
0: no change on ri_n since the last read of UART_MSR
1: change on ri_n since the last read of UART_MSR
Reading the UART_MSR clears the TERI bit.
DDSR
Delta Data Set Ready
This is used to indicate that the modem control line dsr_n has
changed since the last time the UART_MSR was read.
0: no change on dsr_n since the last read of UART_MSR
1: change on dsr_n since the last read of UART_MSR
1 RC 0x0
Reading the UART_MSR clears the DDSR bit. In Loopback Mode
(UART_MCR[4] = 1), the DDSR reflects changes on the DTR
(UART_MCR[0]).
Note: If the DDSR bit is not set and the dsr_n signal is asserted
(low) and a reset occurs, then the DDSR bit is set when the reset
is removed if the dsr_n signal remains asserted.
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Offset: 0x0018 Register Name: UART_MSR
Bit Read/Write Default/Hex Description
DCTS
Delta Clear to Send
This is used to indicate that the modem control line cts_n has
changed since the last time the UART_MSR was read.
0: no change on ctsdsr_n since the last read of UART_MSR
1: change on ctsdsr_n since the last read of UART_MSR
0 RC 0x0
Reading the UART_MSR clears the DCTS bit. In Loopback Mode
(UART_MCR[4] = 1), the DCTS reflects changes on the RTS
(UART_MCR[1]).
Note: If the DCTS bit is not set and the cts_n signal is asserted
(low) and a reset occurs, then the DCTS bit is set when the reset
is removed if the cts_n signal remains asserted.
9.2.6.12 0x001C UART Scratch Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: UART_SCH
Bit Read/Write Default/Hex Description
31:8 / / /
SCRATCH_REG
Scratch Register
7:0 R/W 0x0
This register is for programmers to use as a temporary storage
space. It has no defined purpose in the UART.
9.2.6.13 0x007C UART Status Register (Default Value: 0x0000_0006)
Offset: 0x007C Register Name: UART_USR
Bit Read/Write Default/Hex Description
31:5 / / /
RFF
RX FIFO Full
This is used to indicate that the RX FIFO is completely full.
4 R 0x0
0: RX FIFO not full
1: RX FIFO Full
This bit is cleared when the RX FIFO is no longer full.
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Offset: 0x007C Register Name: UART_USR
Bit Read/Write Default/Hex Description
RFNE
RX FIFO Not Empty
This is used to indicate that the RX FIFO contains one or more
3 R 0x0 entries.
0: RX FIFO is empty
1: RX FIFO is not empty
This bit is cleared when the RX FIFO is empty.
TFE
TX FIFO Empty
This is used to indicate that the TX FIFO is completely empty.
2 R 0x1
0: TX FIFO is not empty
1: TX FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.
TFNF
TX FIFO Not Full
This is used to indicate that the TX FIFO is not full.
1 R 0x1
0: TX FIFO is full
1: TX FIFO is not full
This bit is cleared when the TX FIFO is full.
BUSY
UART Busy Bit
0 R 0x0
0: Idle or inactive
1: Busy
9.2.6.14 0x0080 UART Transmit FIFO Level Register (Default Value: 0x0000_0000)
Offset: 0x0080 Register Name: UART_TFL
Bit Read/Write Default/Hex Description
31:9 / / /
TFL
8:0 R 0x0 TX FIFO Level
The bit indicates the number of data entries in the TX FIFO.
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9.2.6.15 0x0084 UART Receive FIFO Level Register (Default Value: 0x0000_0000)
Offset: 0x0084 Register Name: UART_RFL
Bit Read/Write Default/Hex Description
31:9 / / /
RFL
RX FIFO Level
8:0 R 0x0 The bit indicates the number of data entries in the RX FIFO.
Note: Not use when the RXDMA master is enabled
(UART_RXDMA_CTRL[0] is set to 1).
9.2.6.16 0x0088 UART DMA Handshake Configuration Register (Default Value: 0x0000_00A5)
Offset: 0x0088 Register Name: UART_HSK
Bit Read/Write Default/Hex Description
31:8 / / /
Handshake configuration
7:0 R/W 0xA5 0xA5: DMA wait cycle mode
0xE5: DMA handshake mode
9.2.6.17 0x008C UART DMA Request Enable Register(Default Value: 0x0000_0003)
Offset: 0x008C Register Name: UART_DMA_REQ_EN
Bit Read/Write Default/Hex Description
31:3 / / /
DMA Timeout Enable
2 R/W 0x0 0: Disable
1: Enable
DMA TX REQ Enable
1 R/W 0x1 0: Disable
1: Enable
DMA RX REQ Enable
0 R/W 0x1 0: Disable
1: Enable
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9.2.6.18 0x00A4 UART Halt TX Register (Default Value: 0x0000_0000)
Offset: 0x00A4 Register Name: UART_HALT
Bit Read/Write Default/Hex Description
31:8 / / /
PTE
The sending of TX_REQ
In DMA1 mode (FIFO on), if the PTE is set to 1 when the TFL in
UART_TFL is less than or equal to the trigger value, the controller
sends the DMA request. If the PTE is set to 0, when FIFO is empty,
the controller sends the DMA request. The DMA request will stop
when FIFO is full.
7 R/W 0x0
In DMA0 mode, if the PTE is set to 1 and FIFO is on, when the TFL
in UART_TFL is less than or equal to the trigger value, the
controller sends DMA request. If the PTE is set to 1 and FIFO off,
when the THR in UART_THR is empty, the controller sends DMA
request. If the PTE is set to 0, when FIFO(FIFO Enable) or THR(FIFO
Enable) is empty, the controller sends DMA request. Otherwise,
the DMA request is cleared.
DMA_PTE_RX
The Transmission of RX_DRQ
In DMA1 mode, when RFL is more than or equal to the trigger
value, or a receive timeout has occurred, the controller sends
6 R/W 0x0 DRQ.
In DMA0 mode, when DMA_PTE_RX = 1 and FIFO is on, if RFL is
more than or equal to trig, the controller sends DRQ, else DRQ is
cleared. In other cases, once the received data is valid, the
controller sends DRQ.
SIR_RX_INVERT
SIR RX Pulse Polarity Invert
5 R/W 0x0
0: Not invert receiver signal
1: Invert receiver signal
SIR_TX_INVERT
SIR TX Pulse Polarity Invert
4 R/W 0x0
0: Not invert transmit pulse
1: Invert transmit pulse
3 / / /
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Offset: 0x00A4 Register Name: UART_HALT
Bit Read/Write Default/Hex Description
CHANGE_UPDATE
After the user uses UART_HALT[1] to change the baud rate or LCR
configuration, write 1 to update the configuration and wait this
2 R/WAC 0x0
bit to self-clear to 0 to finish update process. Writing 0 to this bit
has no effect.
1: Update trigger, self-clear to 0 when finish update.
CHCFG_AT_BUSY
This is an enable bit for the user to change LCR register
1 R/W 0x0 configuration and baud rate register (UART_DLH and UART_DLL)
when the UART is busy.
1: Enable change when busy
HALT_TX
Halt TX
This register is used to halt transmissions for testing, so that the
transmit FIFO can be filled by the master when FIFOs are
0 R/W 0x0 implemented and enabled.
0 : Halt TX disabled
1 : Halt TX enabled
Note: If FIFOs are not enabled, the setting has no effect on
operation.
9.2.6.19 0x00B0 UART DBG DLL Register (Default Value: 0x0000_0000)
Offset: 0x00B0 Register Name: UART_DBG_DLL
Bit Read/Write Default/Hex Description
31:8 / / /
7:0 R 0x0 DEBUG DLL
9.2.6.20 0x00B4 UART DBG DLH Register (Default Value: 0x0000_0000)
Offset: 0x00B4 Register Name: UART_DBG_DLH
Bit Read/Write Default/Hex Description
31:8 / / /
7:0 R 0x0 DEBUG DLH
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9.2.6.21 0x00F0 UART FIFO Clock Control Register (Default Value: 0x0000_0003)
Offset: 0x00F0 Register Name: UART_FCC
Bit Read/Write Default/Hex Description
FIFO Depth
31:8 R 0x0
Indicates the depth of TX/RX FIFO
7:3 / / /
RXFIFO Clock Mode
0: Sync mode, writing/reading clocks use apb clock
2 R/W 0x0
1: Sync mode, writing clock uses apb clock, reading clock uses ahb
clock
TX FIFO Clock Enable
1 R/W 0x1 0: Clock disable
1: Clock enable
RX FIFO Clock Enable
0 R/W 0x1 0: Clock disable
1: Clock enable
9.2.6.22 0x0100 UART RXDMA Control Register (Default Value: 0x0000_0000)
Offset: 0x0100 Register Name: UART_RXDMA_CTRL
Bit Read/Write Default/Hex Description
31:24 / / /
RXDMA Timeout Threshold
23:8 R/W 0x0 Unit is 1 UART bit time
Note that this field is only configurable when RXDMA Busy is 0.
7 / / /
RXDMA Timeout Enable
Once enable, the DMA starts a transfer even the data entries in
6 R/W 0x0
RX FIFO do not reach BLK_SIZE.
Note that this field is only configurable when RXDMA Busy is 0.
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Offset: 0x0100 Register Name: UART_RXDMA_CTRL
Bit Read/Write Default/Hex Description
RXDMA AHB Burst Mode
Set for AHB port burst supported
INCR8 is recommended, while INCR16 may be unsupported due
to the system bus.
5:4 R/W 0x0 00: SIGNLE
01: INCR4
10: INCR8
11: INCR16
Note that this field is only configurable while RXDMA Busy is 0.
RXDMA BLK SIZE
Every time when data entries in RX FIFO reach BLK_SIZE, start a
DMA block transfer. It is recommended that the block size no
more than RX FIFO Depth.
3:2 R/W 0x0 00: 8 bytes
01: 16 bytes
10: 32 bytes
11: 64 bytes
Note that this field is only configurable while RXDMA Busy is 0.
RXDMA Mode
0: Continous
1: Limited
1 R/W 0x0 When data transferred reaches the limited count set in RXDMA
LIMIT, the DMA stops and the RXDMA Start bit is cleared
automatically.
Note that this field is only configurable while RXDMA Busy is 0.
RXDMA Enable
0: RXDMA Disable
1: RXDMA Enable
0 R/W 0x0
Note that if the software turns off this bit, the RXDMA will stop
after the current block transfer completes, then the software
should do a reset to the RX FIFO before re-enable.
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9.2.6.23 0x0104 UART RXDMA Start Register (Default Value: 0x0000_0000)
Offset: 0x0104 Register Name: UART_RXDMA_STR
Bit Read/Write Default/Hex Description
31:2 / / /
RXDMA Start
0 R/WAC 0x0 Only valid when RXDMA mode is set to 1, it is auto cleared when
data transferred reaches the RXDMA Limit Size.
9.2.6.24 0x0108 UART RXDMA Status Register (Default Value: 0x0000_0000)
Offset: 0x0108 Register Name: UART_RXDMA_STA
Bit Read/Write Default/Hex Description
31:1 / / /
Buffer Read Address Updating
0: Buffer Read Address Register is ready for updating
1 R 0x0 1: Buffer Read Address Register is busy for updating
The software should not update Buffer Read Address Register
until this bit is 0.
RXDMA BUSY
0 R 0x0 0: RXDMA is idle
1: RXDMA is busy
9.2.6.25 0x010C UART RXDMA Limit Register (Default Value: 0x0000_0000)
Offset: 0x010C Register Name: UART_RXDMA_LMT
Bit Read/Write Default/Hex Description
31:16 / / /
RXDMA Limit Size
15:0 R/W 0x0 Only valid when RXDMA Mode is set to 1, and the unit is byte.
Note that this field is only configurable while RXDMA Busy is 0.
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9.2.6.26 0x0110 UART RXDMA Buffer Start Address Low Register (Default Value: 0x0000_0000)
Offset: 0x0110 Register Name: UART_RXDMA_SADDRL
Bit Read/Write Default/Hex Description
RXDMA Buffer Start Address [31:0]
31:0 R/W 0x0 Byte address
Note that this field is only configurable while RXDMA Busy is 0.
9.2.6.27 0x0114 UART RXDMA Buffer Start Address High Register (Default Value: 0x0000_0000)
Offset: 0x0114 Register Name: UART_RXDMA_SADDRH
Bit Read/Write Default/Hex Description
31:2 / / /
RXDMA Buffer Start Address [33:32]
1:0 R/W 0x0 Byte address
Note that this field is only configurable while RXDMA Busy is 0.
9.2.6.28 0x0118 UART RXDMA Buffer Length Register (Default Value: 0x0000_0000)
Offset: 0x0118 Register Name: UART_RXDMA_BL
Bit Read/Write Default/Hex Description
31:16 / / /
RXDMA Buffer Length
15:0 R/W 0x0 Unit is byte
Note that this field is only configurable while RXDMA Busy is 0.
9.2.6.29 0x0120 UART RXDMA Interrupt Enable Register (Default Value: 0x0000_0000)
Offset: 0x0120 Register Name: UART_RXDMA_IE
Bit Read/Write Default/Hex Description
31:4 / / /
RXDMA Buffer Overrun
3 R/W 0x0
RXDMA Buffer Overrun Interrupt Enable
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Offset: 0x0120 Register Name: UART_RXDMA_IE
Bit Read/Write Default/Hex Description
RXDMA Timeout Done
2 R/W 0x0
RXDMA Timeout Done Interrupt Enable
RXDMA BLK Done
1 R/W 0x0
RXDMA BLK Done Interrupt Enable
RXDMA Limit Done
0 R/W 0x0
RXDMA Limit Done Interrupt Enable
9.2.6.30 0x0124 UART RXDMA Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0124 Register Name: UART_RXDMA_IS
Bit Read/Write Default/Hex Description
31:4 / / /
RXDMA Buffer Overrun
3 R/W1C 0x0
Asserted when the RXDMA buffer is overflow.
RXDMA Timeout Done
2 R/W1C 0x0
Asserted when a DMA transfer caused by timeout is done.
RXDMA BLK Done
1 R/W1C 0x0
Asserted when a DMA block transfer is done.
RXDMA Limit Done
0 R/W1C 0x0 Asserted when data transferred reaches limit size in RXDMA Limit
Mode.
9.2.6.31 0x0128 UART RXDMA Write Address Low Register (Default Value: 0x0000_0000)
Offset: 0x0128 Register Name: UART_RXDMA_WADDRL
Bit Read/Write Default/Hex Description
RXDMA Current Write Address[31:0]
31:0 R 0x0 Updated when every DMA transfer is done
It is byte address.
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9.2.6.32 0x012C UART RXDMA Write Address High Register (Default Value: 0x0000_0000)
Offset: 0x012C Register Name: UART_RXDMA_WADDRH
Bit Read/Write Default/Hex Description
31:2 / / /
RXDMA Current Write Address[33:32]
1:0 R 0x0 Updated when every DMA transfer is done
It is byte address.
9.2.6.33 0x0130 UART RXDMA Read Address Low Register (Default Value: 0x0000_0000)
Offset: 0x0130 Register Name: UART_RXDMA_RADDRL
Bit Read/Write Default/Hex Description
RXDMA Current Read Address[31:0]
Software should update this register after reading data in RXDMA
Buffer in time
It is byte address.
31:0 R/W 0x0
The software should not update Buffer Read Address Register
until UART_RXDMA_STA[1] is 0. The software should update Read
Address High Register first, and then Read Address Low Register,
even there is no change on Read Address High Register.
9.2.6.34 0x0134 UART RXDMA Read Address High Register (Default Value: 0x0000_0000)
Offset: 0x0134 Register Name: UART_RXDMA_RADDRH
Bit Read/Write Default/Hex Description
31:2 / / /
RXDMA Current Read Address[33:32]
Software should update this register after reading data in RXDMA
Buffer in time.
It is byte address.
1:0 R/W 0x0
The software should not update Buffer Read Address Register
until until UART_RXDMA_STA[1] is 0. The software should update
Read Address High Register first and then Read Address Low
Register , even there is no change on Read Address High Register.
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9.2.6.35 0x0138 UART RXDMA Data Count Register (Default Value: 0x0000_0000)
Offset: 0x0138 Register Name: UART_RXDMA_DCNT
Bit Read/Write Default/Hex Description
31:16 / / /
RXDMA Data Count
Only valid while RXDMA Mode is set to 1, it is used for counting
15:0 R 0x0 the data transferred by RXDMA, and is cleared when reaches
RXDMA Limit Size.
Its unit is byte.
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9.3 SPI
9.3.1 Overview
The Serial Peripheral Interface (SPI) is a full-duplex, synchronous, four-wire serial communication interface
between a CPU and SPI-compliant external devices. The SPI controller contains a 64 x 8 bits receiver buffer
(RXFIFO) and a 64 x 8 bits transmit buffer (TXFIFO). It can work in master mode and slave mode.
The SPI has the following features:
Full-duplex synchronous serial interface
Master/slave configurable
8-bit wide by 64-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable
Supports interrupts and DMA
Supports mode0, mode1, mode2, and mode3
Supports 3-wire/4-wire SPI
Supports programmable serial data frame length: 1 bit to 32 bits
Supports standard SPI, dual-output/dual-input SPI, dual I/O SPI, quad-output/quad-input SPI
Supports maximum IO rate of the mass production: 100 MHz
9.3.2 Block Diagram
Figure 9-20 shows a block diagram of the SPI.
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Figure 9-20 SPI Block Diagram
spi_top
spi_mosi_oen
spi_mosi_out
tbuf txfifo spi_tx
spi_miso_oen
spi_miso_out
AHB sckt
spi_ss_oen
spi_ss_out
spi_ss_in
TX DMA spi_rf spi_cmu spi_sck_oen
spi_sck_out
spi_sck_in
RX DMA
sckr
spi_mosi_in
rbuf rxfifo spi_rx
INTC spi_miso_in
hclk sclk
domain domain
SPI contains the following sub-blocks:
Table 9-6 SPI Sub-blocks
Sub-block Description
Responsible for implementing the internal register, interrupt, and DMA
spi_rf
Request.
The data length transmitted from AHB to TXFIFO is converted into 8 bits,
spi_tbuf
then the data is written into the RXFIFO.
The block is used to convert the RXFIFO data into the reading data length
spi_rbuf
of AHB.
The data transmitted from the SPI to the external serial device is written
txfifo, rxfifo into the TXFIFO; the data received from the external serial device into SPI
is pushed into the RXFIFO.
Responsible for implementing SPI bus clock, chip select, internal sample,
spi_cmu
and the generation of transfer clock.
Responsible for implementing SPI data transfer, the interface of the
spi_tx
internal TXFIFO, and status register.
Responsible for implementing SPI data receive, the interface of the
spi_rx
internal RXFIFO, and status register.
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9.3.3 Functional Description
9.3.3.1 External Signals
The following table describes the external signals of SPI. The MOSI and MISO are bidirectional I/O, when SPI is
as a master device, the CLK and CS are the output pin; when SPI is as a slave device, the CLK and CS are the
input pin. When using SPI, the corresponding PADs are selected as SPI function via section 9.7 “GPIO”.
Table 9-7 SPI External Signals
Signal Description Type
SPI0 chip select signal, low active
SPI0-CS When the device is not selected, data will not be accepted via the SI I/O
pin, and the SO pin will stop transmission.
SPI0 clock signal
SPI0-CLK This pin is used to provide a clock to the device and is used to control I/O
the flow of data to and from the device.
SPI0-MOSI SPI0 master data out, slave data in I/O
SPI0-MISO SPI0 master data in, slave data out I/O
Write protection and low active
SPI0-WP It also can be used for serial data input and output for SPI Quad Input I/O
or Quad Output mode.
When the device is selected and a serial sequence is underway, the
HOLD pin can be used to temporarily pause the serial
communication with the master device without deselecting or
resetting the serial sequence. While the HOLD pin is asserted, the SO
SPI0-HOLD I/O
pin is at high impedance, and all transitions on the SCK pin and data
on the SI pin are ignored.
It also can be used for serial data input and output for SPI Quad Input
or Quad Output mode.
9.3.3.2 Clock Sources
The SPI controller gets 5 different clock sources, users can select one of them to make SPI clock source. The
following table describes the clock sources for SPI. For more details on the clock setting, configuration, and
gating information, see section 3.3 “CCU”.
Table 9-8 SPI Clock Sources
Clock Sources Description
HOSC 24 MHz Crystal
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Clock Sources Description
PLL_PERI(1X) Peripheral Clock, default value is 600 MHz
PLL_PERI(2X) Peripheral Clock, default value is 1200 MHz
PLL_AUDIO0(DIV2) Audio Clock, the default value is 1536 MHz
PLL_AUDIO0(DIV5) Audio Clock, the default value is 614.4 MHz
9.3.3.3 Typical Application
Figure 9-21 shows the application block diagram when the SPI master device is connected to a slave device.
Figure 9-21 SPI Application Block Diagram
SoC
SPI-CLK
SCK
SPI-CS
CS# SPI-
SPI-MISO
SO/IO1 compliant
SPI SPI-MOSI SI/IO0 External
SPI-WP Device
WP#/IO2
SPI-HOLD
HOLD#/IO3
9.3.3.4 SPI Transmit Format
The SPI supports 4 different formats for data transfer. The software can select one of the four modes in which
the SPI works by setting the bit1 (Polarity) and bit0 (Phase) of SPI_TCR. The SPI controller master uses the
SPI_SCLK signal to transfer data in and out of the shift register. Data is clocked using any one of four
programmable clock phase and polarity combinations.
The CPOL (SPI_TCR[1]) defines the polarity of the clock signal (SPI_SCLK). The SPI_SCLK is a high level when
CPOL is ‘1’ and it is a low level when CPOL is ‘0’. The CPHA (SPI_TCR[0]) decides whether the leading edge of
SPI_SCLK is used to setup or sample data. The leading edge is used to setup data when CPHA is ‘1’, and sample
data when CPHA is ‘0’. The following table lists the four modes.
Table 9-9 SPI Transmit Format
Mode Polarity (CPOL) Phase (CPHA) Leading Edge Trailing Edge
Mode0 0 0 Sample on the rising edge Setup on the falling edge
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Mode Polarity (CPOL) Phase (CPHA) Leading Edge Trailing Edge
Mode1 0 1 Setup on the rising edge Sample on the falling edge
Mode2 1 0 Sample on the falling edge Setup on the rising edge
Mode3 1 1 Setup on the falling edge Sample on the rising edge
Figure 9-22 and Figure 9-23 describe four waveforms for SPI_SCLK.
Figure 9-22 SPI Phase 0 Timing Diagram
Figure 9-23 SPI Phase 1 Timing Diagram
9.3.3.5 SPI Master and Slave Mode
The SPI controller can be configured to a master or slave device. The master mode is selected by setting the
MODE bit (SPI_GCR[1]); the slave mode is selected by clearing the MODE bit.
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In master mode, the SPI_CLK is generated and transmitted to the external device, and the data from the TX
FIFO is transmitted on the MOSI pin, the data from the slave device is received on the MISO pin and sent to RX
FIFO. The Chip Select (SPI_SS) is an active low signal, and it must be set low before the data are transmitted or
received. The SPI_SS can be selected the auto control mode or software manual control mode. When using the
auto control, the SS_OWNER (SPI_TCR[6]) must be cleared (default value is 0); when using the manual control,
the SS_OWNER must be set. And the level of SPI_SS is controlled by SS_LEVEL (SPI_TCR[7]).
In slave mode, after the software selects the MODE bit (SPI_GCR[1]) to '0', it waits for master initiate a
transaction. When the master asserts SPI_SS, then SPI_CLK is transmitted to the slave device, the slave data is
transmitted from TX FIFO on the MISO pin and the data from the MOSI pin is received in RX FIFO.
9.3.3.6 SPI 3-Wire Mode
The SPI 3-wire mode is only valid when the SPI controller work in master mode, and is selected when the Work
Mode Select bit (SPI_BATC[1:0]) is equal to 0x2. And in the 3-wire mode, the input data and the output data
use the same single data line. The following figure describes the 3-wire mode.
Figure 9-24 SPI 3-Wire Mode
9.3.3.7 SPI Dual-Input/Dual-Output and Dual I/O Mode
The dual read mode (SPI x2) is selected when the DRM is set in SPI_BCC[28]. Using the dual mode allows data
to be transferred to or from the device at double the rate of standard single mode, the data can be read at fast
speed using two data bits (MOSI and MISO) at a time. The following figure describes the dual-input/dual-output
SPI (Figure 9-25) and the dual I/O SPI (Figure 9-26).
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Figure 9-25 SPI Dual-Input/Dual-Output Mode
In the dual-input/dual-output SPI mode, the command, address, and the dummy bytes output in a unit of a
single bit in serial mode through the SPI_MOSI line, only the data bytes are output (write) and input (read) in
a unit of dual bits through the SPI_MOSI and SPI_MISO.
Figure 9-26 SPI Dual I/O Mode
In the dual I/O SPI mode, only the command bytes output in a unit of a single bit in serial mode through the
SPI_MOSI line. The address bytes and the dummy bytes output in a unit of dual bits through the SPI_MOSI and
SPI_MISO. And the data bytes output (write) and input (read) in a unit of dual bits through the SPI_MOSI and
SPI_MISO.
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9.3.3.8 SPI Quad-Input/Quad-Output Mode
The quad read mode (SPI x4) is selected when the Quad_EN is set in SPI_BCC[29]. Using the quad mode allows
data to be transferred to or from the device at 4 times the rate of standard single mode, the data can be read
at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 (HOLD#)) at the same time. The following
figure describes the quad-input/quad-output SPI.
Figure 9-27 SPI Quad-Input/Quad-Output Mode
In the quad-input/quad-output SPI mode, the command, address, and the dummy bytes output in a unit of a
single bit in serial mode through SPI_MOSI line. Only the data bytes output (write) and input (read) in a unit of
quad bits through the SPI_MOSI, SPI_MISO, SPI_WP#, and SPI_HOLD#.
9.3.3.9 Transmission/Reception Bursts in Master Mode
In SPI master mode, the transmission and reception bursts (byte in unit) are configured before the SPI transfers
the serial data between the processor and external device. The transmission bursts are written in MWTC
(bit[23:0]) of the SPI Master Transmit Counter Register. The transmission bursts in single mode before
automatically sending dummy bursts are written in STC (bit[23:0]) of the SPI Master Transmit Counter Register.
For dummy data, the SPI controller can automatically send before receiving by writing DBC (bit[27:24]) in the
SPI Master Transmit Counter Register. If users do not use the SPI controller to send dummy data automatically,
then the dummy bursts are used as the transmission counters to write together in MWTC (bit[23:0]) of the SPI
Master Transmit Counter Register. In master mode, the total burst numbers are written in MBC (bit[23:0]) of
the SPI Master Transmit Counter Register. When all transmission and reception bursts are transferred, the SPI
controller will send a completed interrupt, at the same time, the SPI controller will clear DBC, MWTC, and MBC.
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9.3.3.10 SPI Sample Mode and Run Clock Configuration
The SPI controller runs at 3 kHz–100 MHz at its interface to external SPI devices. The internal SPI clock should
run at the same frequency as the outgoing clock in the master mode. The SPI clock is selected from different
clock sources, the SPI must configure different work mode. There are three work modes: normal sample mode,
delay half-cycle sample mode, delay one-cycle sample mode. The Delay half-cycle sample mode is the default
mode of the SPI controller. When the SPI runs at 40 MHz or below 40 MHz, the SPI can work at normal sample
mode or delay half-cycle sample mode. When the SPI runs over 80 MHz, setting the SDC bit in the SPI Transfer
Control Register to ‘1’ makes the internal read sample point with a half-cycle delay of SPI_CLK, which is used in
high speed read operation to reduce the error caused by the time delay of SPI_CLK between master and slave.
Table 9-10 and Table 9-11 show the different configurations of the SPI sample mode.
Table 9-10 SPI Old Sample Mode and Run Clock
SPI Sample Mode SDM(bit13) SDC(bit11) Run Clock
normal sample 1 0 <=24 MHz
delay half cycle sample 0 0 <=40 MHz
delay one cycle sample 0 1 >=80 MHz
CAUTION
The remaining spectrum is not recommended. Because when the output delay of SPI flash (refer to the
datasheet of the manufactures for the specific delay time) is the same with the half-cycle time of SPI working
clock, the variable edge of the output data for the device bumps into the clock sampling edge of the controller,
so setting 1 cycle of sampling delay would cause stability problem.
Table 9-11 SPI New Sample Mode
SPI Sample Mode SDM (bit13) SDC (bit11) SDC1 (bit15)
normal sample 1 0 0
delay half cycle sample 0 0 0
delay one cycle sample 0 1 0
delay 1.5 cycle sample 1 1 0
delay 2 cycle sample 1 0 1
delay 2.5 cycle sample 0 0 1
delay 3 cycle sample 0 1 1
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9.3.3.11 SPI Error Conditions
If any error conditions occur, the hardware will set the corresponding status bits in the SPI Interrupt Status
Register and stop the transfer. For the SPI controller, the following error scenarios can happen.
1. TX_FIFO Underrun
The TX_FIFO underrun happens when the CPU/DMA reads data from TX FIFO when it is empty. In the case,
the SPI controller will end the transaction and flag the error bit along with the TF_UDF bit in the SPI
Interrupt Status Register. The SPI controller will generate an interrupt if interrupts are enabled. The
software has to clear the error bit and the TF_UDF bit. To start a new transaction, the software has to reset
the FIFO by writing to the SRST (soft reset) bit in the SPI Global Control Register.
2. TX_FIFO Overflow
The TX_FIFO overflow happens when the CPU/DMA writes data into the TX FIFO when it is full. In the case,
the SPI controller will end the transaction and flag the error bit along with the TF_OVF bit in the SPI
Interrupt Status Register. The SPI controller will generate an interrupt if interrupts are enabled. The
software has to clear the error bit and the TF_OVF bit. To start a new transaction, the software has to reset
the FIFO by writing to the SRST (soft reset) bit in the SPI Global Control Register.
3. RX_FIFO Underrun
The RX_FIFO underrun happens when the CPU/DMA reads data from RX FIFO when it is empty. In the case,
the SPI controller will end the transaction and flag the error bit along with the RF_UDF bit in the SPI
Interrupt Status Register. The SPI controller will generate an interrupt if interrupts are enabled. The
software has to clear the error bit and the RF_UDF bit. To start a new transaction, the software has to reset
the fifo by writing to the SRST (soft reset) bit in the SPI Global Control Register.
4. RX_FIFO Overflow
The RX_FIFO overflow happens when the CPU/DMA writes data into the RX FIFO when it is full. In the case,
the SPI controller will end the transaction and flag the error bit along with the RF_OVF bit in the SPI
Interrupt Status Register. The SPI controller will generate an interrupt if interrupts are enabled. The
software has to clear the error bit and the RF_OVF bit. To start a new transaction, the software has to reset
the FIFO by writing to the SRST (soft reset) bit in the SPI Global Control Register.
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9.3.4 Programming Guidelines
9.3.4.1 Writing/Reading Data Process
The SPI transfers serial data between the processor and the external device. The CPU mode and DMA mode
are the two main operational modes for SPI. For each SPI, the data is simultaneously transmitted (shifted out
serially) and received (shifted in serially). The SPI has 2 channels, including the TX channel and RX channel. The
TX channel has the path from TX FIFO to the external device. The RX channel has the path from the external
device to RX FIFO.
Write Data: The CPU or DMA must write data on the SPI_TXD register, the data on the register are
automatically moved to TX FIFO.
Read Data: To read data from RX FIFO, the CPU or DMA must access the SPI_RXD register and the data are
automatically sent to the SPI_RXD register.
In CPU or DMA mode, the SPI sends a completed interrupt (SPI_ISR[TC]) to the processor after each
transmission is complete.
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CPU Mode
Figure 9-28 SPI Write/Read Data in CPU Mode
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DMA Mode
Figure 9-29 SPI Write/Read Data in DMA Mode
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9.3.4.2 Calibrate Delay Chain
The SPI has one delay chain which is used to generate delay to make proper timing between the internal SPI
clock signal and data signals. Delay chain is made up of 64 delay cells. The delay time of one delay cell can be
estimated through delay chain calibration.
The steps to calibrate delay chain are as follows:
Step 1 Enable SPI. To calibrate the delay chain by the operation registers in SPI, the SPI must be enabled
through AHB reset and AHB clock gating control registers.
Step 2 Configure a proper clock for SPI. The calibration delay chain is based on the clock for SPI from CCU.
Step 3 Set proper initial delay value. Write 0xA0 to the SPI Sample Delay Control Register to set initial delay
value 0x20 to delay chain. Then write 0x0 to the SPI Sample Delay Control Register to clear this value.
Step 4 Write 0x8000 to the SPI Sample Delay Control Register to start to calibrate the delay chain.
Step 5 Wait until the flag (bit14 in the SPI Sample Delay Control Register) of calibration done is set. The
number of delay cells is shown at the bit[13:8] of the SPI Sample Delay Control Register. The delay
time generated by these delay cells is equal to the cycle of the SPI clock nearly. This value is the result
of calibration.
Step 6 Calculate the delay time of one delay cell according to the cycle of the SPI clock and the result of
calibration.
9.3.5 Register List
Module Name Base Address
SPI0 0x04025000
Register Name Offset Description
SPI_GCR 0x0004 SPI Global Control Register
SPI_TCR 0x0008 SPI Transfer Control Register
SPI_IER 0x0010 SPI Interrupt Control Register
SPI_ISR 0x0014 SPI Interrupt Status Register
SPI_FCR 0x0018 SPI FIFO Control Register
SPI_FSR 0x001C SPI FIFO Status Register
SPI_WCR 0x0020 SPI Wait Clock Register
SPI_SAMP_DL 0x0028 SPI Sample Delay Control Register
SPI_MBC 0x0030 SPI Master Burst Counter Register
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Register Name Offset Description
SPI_MTC 0x0034 SPI Master Transmit Counter Register
SPI_BCC 0x0038 SPI Master Burst Control Register
SPI_BATCR 0x0040 SPI Bit-Aligned Transfer Configure Register
SPI_BA_CCR 0x0044 SPI Bit-Aligned Clock Configuration Register
SPI_TBR 0x0048 SPI TX Bit Register
SPI_RBR 0x004C SPI RX Bit Register
SPI_NDMA_MODE_CTL 0x0088 SPI Normal DMA Mode Control Register
SPI_TXD 0x0200 SPI TX Data Register
SPI_RXD 0x0300 SPI RX Data Register
9.3.6 Register Description
9.3.6.1 0x0004 SPI Global Control Register (Default Value: 0x0000_0080)
Offset:0x0004 Register Name: SPI_GCR
Bit Read/Write Default/Hex Description
SRST
Soft reset
31 R/WAC 0x0 Writing ‘1’ to this bit will clear the SPI controller, and auto clear to
‘0’ when reset operation completes.
Writing ‘0’ to this bit has no effect.
30:8 / / /
TP_EN
Transmit Pause Enable
In master mode, it is used to control the transmit state machine to
7 R/W 0x1 stop smart burst sending when RX FIFO is full.
0: Normal operation, ignore RXFIFO status
1: Stop transmit data when RXFIFO full
Cannot be written when XCH=1.
6:3 / / /
MODE_SELEC
Sample Timing Mode Select
2 R/W 0x0 0: Old mode of Sample Timing
1: New mode of Sample Timing
Cannot be written when XCH=1.
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Offset:0x0004 Register Name: SPI_GCR
Bit Read/Write Default/Hex Description
MODE
SPI Function Mode Select
1 R/W 0x0 0: Slave mode
1: Master mode
Cannot be written when XCH=1.
EN
SPI Module Enable Control
0: Disable
0 R/W 0x0
1: Enable
After transforming from bit_mode to byte_mode, it must enable
the SPI module again.
9.3.6.2 0x0008 SPI Transfer Control Register (Default Value: 0x0000_0087)
Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
XCH
Exchange Burst
In master mode, it is used to start SPI burst.
0: Idle
1: Initiates exchange.
31 R/WAC 0x0
Writing “1” to this bit will start the SPI burst, and will auto-clear
after finishing the bursts transfer specified by SPI_MBC. Writing
“1” to SRST (SPI_GCR[31]) will also clear this bit. Writing ‘0’ to this
bit has no effect.
Cannot be written when XCH=1.
30:16 / / /
SDC1
Master Sample Data Control register1
Set this bit to ‘1’ to make the internal read sample point with a
delay of half-cycle of SPI_CLK. It is used in high speed read
15 R/W 0x0 operation to reduce the error caused by the time delay of SPI_CLK
between master and slave.
0: normal operation, do not delay the internal read sample point
1: delay the internal read sample point
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
SDDM
Sending Data Delay Mode
0: Normal sending
14 R/W 0x0 1: Delay sending
Set the bit to "1" to make the data that should be sent with a delay
of half-cycle for SPI_CLK in dual IO mode of SPI mode0.
Cannot be written when XCH=1.
SDM
Master Sample Data Mode
0: Delay sample mode
1: Normal sample mode
In normal sample mode, the SPI master samples the data at the
13 R/W 0x0
correct edge for each SPI mode;
In delay sample mode, the SPI master samples data at the edge
that is half cycle delayed by the correct edge defined in respective
SPI mode.
Cannot be written when XCH=1.
FBS
First Transmit Bit Select
12 R/W 0x0 0: MSB first
1: LSB first
Cannot be written when XCH=1.
SDC
Master Sample Data Control
Set this bit to ‘1’ to make the internal read sample point with a
delay of half-cycle for SPI_CLK. It is used in high speed read
11 R/W 0x0 operation to reduce the error caused by the time delay of SPI_CLK
between master and slave.
0: Normal operation, do not delay the internal read sample point
1: Delay the internal read sample point
Cannot be written when XCH=1.
RPSM
Rapids Mode Select
Select rapid mode for high speed write.
10 R/W 0x0
0: Normal write mode
1: Rapid write mode
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
DDB
Dummy Burst Type
9 R/W 0x0 0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
Cannot be written when XCH=1.
DHB
Discard Hash Burst
In master mode, it controls whether discarding unused SPI bursts
8 R/W 0x0 0: Receiving all SPI bursts in the BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during
the dummy burst period. The burst number is specified by TC.
Cannot be written when XCH=1.
SS_LEVEL
When control SS signal manually (SS_OWNER (SPI_TCR[6])==1), set
this bit to ‘1’ or ‘0’ to control the level of SS signal.
7 R/W 0x1
0: Set SS to low
1: Set SS to high
Cannot be written when XCH=1.
SS_OWNER
SS Output Owner Select
Usually, the controller sends the SS signal automatically with data
together. When this bit is set to 1, the software must manually
6 R/W 0x0 write SS_LEVEL (SPI_TCR[7]) to 1 or 0 to control the level of the SS
signal.
0: SPI controller
1: Software
Cannot be written when XCH=1.
SS_SEL
SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
5:4 R/W 0x0
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
SSCTL
In master mode, this bit selects the output waveform for the
SPI_SSx signal. Only valid when SS_OWNER (SPI_TCR[6])= 0.
3 R/W 0x0
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
Cannot be written when XCH=1.
SPOL
SPI Chip Select Signal Polarity Control
2 R/W 0x1 0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.
CPOL
SPI Clock Polarity Control
1 R/W 0x1 0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.
CPHA
SPI Clock/Data Phase Control
0 R/W 0x1 0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
Cannot be written when XCH=1.
9.3.6.3 0x0010 SPI Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: SPI_IER
Bit Read/Write Default/Hex Description
31:14 / / /
SS_INT_EN
SSI Interrupt Enable
13 R/W 0x0 Chip select signal (SSx) from the valid state to the invalid state
0: Disable
1: Enable
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Offset: 0x0010 Register Name: SPI_IER
Bit Read/Write Default/Hex Description
TC_INT_EN
Transfer Completed Interrupt Enable
12 R/W 0x0
0: Disable
1: Enable
TF_UDR_INT_EN
TXFIFO Underrun Interrupt Enable
11 R/W 0x0
0: Disable
1: Enable
TF_OVF_INT_EN
TX FIFO Overflow Interrupt Enable
10 R/W 0x0
0: Disable
1: Enable
RF_UDR_INT_EN
RXFIFO Underrun Interrupt Enable
9 R/W 0x0
0: Disable
1: Enable
RF_OVF_INT_EN
RX FIFO Overflow Interrupt Enable
8 R/W 0x0
0: Disable
1: Enable
7 / / /
TF_FUL_INT_EN
TX FIFO Full Interrupt Enable
6 R/W 0x0
0: Disable
1: Enable
TX_EMP_INT_EN
TX FIFO Empty Interrupt Enable
5 R/W 0x0
0: Disable
1: Enable
TX_ERQ_INT_EN
TX FIFO Empty Request Interrupt Enable
4 R/W 0x0
0: Disable
1: Enable
3 / / /
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Offset: 0x0010 Register Name: SPI_IER
Bit Read/Write Default/Hex Description
RF_FUL_INT_EN
RX FIFO Full Interrupt Enable
2 R/W 0x0
0: Disable
1: Enable
RX_EMP_INT_EN
RX FIFO Empty Interrupt Enable
1 R/W 0x0
0: Disable
1: Enable
RF_RDY_INT_EN
RX FIFO Ready Request Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
9.3.6.4 0x0014 SPI Interrupt Status Register (Default Value: 0x0000_0032)
Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
31:14 / / /
SSI
SS Invalid Interrupt
13 R/W1C 0x0
When SSI is 1, it indicates that SPI_SS has changed from valid state
to invalid state. Writing 1 to this bit clears it.
TC
Transfer Completed
In master mode, it indicates that all bursts specified by SPI_MBC
have been exchanged. In other conditions, when setting, this bit
12 R/W1C 0x0 indicates that all the data in TXFIFO has been loaded in the Shift
register, and the Shift register has shifted out all the bits. Writing
1 to this bit clears it.
0: Busy
1: Transfer completed
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Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
TF_UDF
TXFIFO Underrun
This bit is set when the TXFIFO is underrun. Writing 1 to this bit
11 R/W1C 0x0
clears it.
0: TXFIFO is not underrun
1: TXFIFO is underrun
TF_OVF
TXFIFO Overflow
This bit is set when the TXFIFO is overflowed. Writing 1 to this bit
10 R/W1C 0x0
clears it.
0: TXFIFO is not overflowed
1: TXFIFO is overflowed
RX_UDF
RXFIFO Underrun
When set, this bit indicates that RXFIFO is underrun. Writing 1 to
9 R/W1C 0x0
this bit clears it.
0: RXFIFO is not underrun
1: RXFIFO is underrun
RX_OVF
RXFIFO Overflow
When set, this bit indicates that RXFIFO has overflowed. Writing 1
8 R/W1C 0x0
to this bit clears it.
0: RXFIFO is not overflowed
1: RXFIFO is overflowed
7 / / /
TX_FULL
TXFIFO Full
6 R/W1C 0x0 This bit is set when the TXFIFO is full. Writing 1 to this bit clears it.
0: TXFIFO is not Full
1: TXFIFO is Full
TX_EMP
TXFIFO Empty
This bit is set when the TXFIFO is empty. Writing 1 to this bit clears
5 R/W1C 0x1
it.
0: TXFIFO contains one or more words
1: TXFIFO is empty
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Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
TX_READY
TXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
4 R/W1C 0x1 1: TX_WL <= TX_TRIG_LEVEL
This bit will be immediately set to 1 if TX_WL <= TX_TRIG_LEVEL.
Writing “1” to this bit clears it. The TX_WL is the water level of
TXFIFO.
3 / / /
RX_FULL
RXFIFO Full
2 R/W1C 0x0 This bit is set when the RXFIFO is full. Writing 1 to this bit clears it.
0: Not Full
1: Full
RX_EMP
RXFIFO Empty
This bit is set when the RXFIFO is empty. Writing 1 to this bit clears
1 R/W1C 0x1
it.
0: Not empty
1: empty
RX_RDY
RXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
0 R/W1C 0x0 1: RX_WL >= RX_TRIG_LEVEL
This bit is will be immediately set to 1 if RX_WL >= RX_TRIG_LEVEL.
Writing “1” to this bit clears it. The RX_WL is the water level of
RXFIFO.
9.3.6.5 0x0018 SPI FIFO Control Register (Default Value: 0x0040_0001)
Offset: 0x0018 Register Name: SPI_FCR
Bit Read/Write Default/Hex Description
TX_FIFO_RST
TX FIFO Reset
31 R/WAC 0x0 Writing ‘1’ to this bit will reset the control portion of the TX FIFO
and auto clear to ‘0’ when completing reset operation, writing to
‘0’ has no effect.
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Offset: 0x0018 Register Name: SPI_FCR
Bit Read/Write Default/Hex Description
TF_TEST_ENB
TX Test Mode Enable
0: Disable
1: Enable
30 R/W 0x0 In normal mode, the TXFIFO can only be read by the SPI controller,
writing ‘1’ to this bit will switch the read and write function of the
TXFIFO to AHB bus. This bit is used to test the TXFIFO, do not set in
normal operation, and do not set RF_TEST and TF_TEST at the
same time.
29:25 / / /
TF_DRQ_EN
TXFIFO DMA Request Enable
24 R/W 0x0
0: Disable
1: Enable
TX_TRIG_LEVEL
23:16 R/W 0x40
TXFIFO Empty Request Trigger Level
RF_RST
RXFIFO Reset
15 R/WAC 0x0 Writing ‘1’ to this bit will reset the control portion of the receiver
FIFO, and auto clear to ‘0’ when completing reset operation,
writing ‘0’ to this bit has no effect.
RF_TEST
RX Test Mode Enable
0: Disable
1: Enable
14 R/W 0x0 In normal mode, the RXFIFO can only be written by the SPI
controller, writing ‘1’ to this bit will switch the read and write
function of RXFIFO to AHB bus. This bit is used to test the RXFIFO,
do not set in normal operation, and do not set RF_TEST and
TF_TEST at the same time.
13:9 / / /
RF_DRQ_EN
RX FIFO DMA Request Enable
8 R/W 0x0
0: Disable
1: Enable
RX_TRIG_LEVEL
7:0 R/W 0x1
RX FIFO Ready Request Trigger Level
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9.3.6.6 0x001C SPI FIFO Status Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: SPI_FSR
Bit Read/Write Default/Hex Description
TB_WR
31 R 0x0
TX FIFO Write Buffer Write Enable
TB_CNT
30:28 R 0x0 TX FIFO Write Buffer Counter
These bits indicate the number of words in TX FIFO Write Buffer
27:24 / / /
TF_CNT
TX FIFO Counter
These bits indicate the number of words in TX FIFO
0: 0 byte in TX FIFO
23:16 R 0x0
1: 1 byte in TX FIFO
…
64: 64 bytes in TX FIFO
other: Reserved
RB_WR
15 R 0x0
RX FIFO Read Buffer Write Enable
RB_CNT
14:12 R 0x0 RX FIFO Read Buffer Counter
These bits indicate the number of words in RX FIFO Read Buffer
11:8 / / /
RF_CNT
RX FIFO Counter
These bits indicate the number of words in RX FIFO
0: 0 byte in RX FIFO
7:0 R 0x0
1: 1 byte in RX FIFO
…
64: 64 bytes in RX FIFO
other: Reserved
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9.3.6.7 0x0020 SPI Wait Clock Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: SPI_WCR
Bit Read/Write Default/Hex Description
31:20 / / /
SWC
Dual mode direction switch wait clock counter (for master mode
only).
These bits control the number of wait states to be inserted before
19:16 R/W 0x0 starting dual data transfer in dual SPI mode. The SPI module counts
SPI_SCLK by SWC for delaying the next word data transfer.
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Cannot be written when XCH=1.
WCC
Wait Clock Counter (In master mode)
These bits control the number of wait states to be inserted in data
transfers. The SPI module counts SPI_SCLK by WCC for delaying the
15:0 R/W 0x0
next word data transfer.
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Cannot be written when XCH=1.
9.3.6.8 0x0028 SPI Sample Delay Control Register (Default Value: 0x0000_2000)
Offset: 0x0028 Register Name: SPI_SAMP_DL
Bit Read/Write Default/Hex Description
31:16 / / /
SAMP_DL_CAL_START
Sample Delay Calibration Start
15 R/W 0x0
When set, the sample delay chain calibration is started.
Cannot be written when XCH=1.
SAMP_DL_CAL_DONE
Sample Delay Calibration Done
14 R 0x0 When set, it means that sample delay chain calibration is done and
the result of calibration is shown in SAMP_DL.
Cannot be written when XCH=1.
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Offset: 0x0028 Register Name: SPI_SAMP_DL
Bit Read/Write Default/Hex Description
SAMP_DL
Sample Delay
It indicates the number of delay cells corresponding to the current
card clock. The delay time generated by these delay cells is equal
13:8 R 0x20 to the cycle of the card clock nearly.
Generally, it is necessary to do drive delay calibration when the
card clock is changed.
This bit is valid only when SAMP_DL_CAL_DONE is set.
Cannot be written when XCH=1.
SAMP_DL_SW_EN
Sample Delay Software Enable
7 R/W 0x0 When set, it indicates that enable sample delay specified at
SAMP_DL_SW.
Cannot be written when XCH=1.
6 / / /
SAMP_DL_SW
Sample Delay Software
The relative delay between the clock line and command line, data
5:0 R/W 0x0 lines.
It can be determined according to the value of SAMP_DL, the cycle
of the card clock, and the input timing requirement of the device.
Cannot be written when XCH=1.
9.3.6.9 0x0030 SPI Master Burst Counter Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: SPI_MBC
Bit Read/Write Default/Hex Description
31:24 / / /
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Offset: 0x0030 Register Name: SPI_MBC
Bit Read/Write Default/Hex Description
MBC
Master Burst Counter
In master mode, this field specifies the total burst number. The
total transfer data include the TXD, RXD, and dummy burst.
23:0 R/W 0x0 0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
9.3.6.10 0x0034 SPI Master Transmit Counter Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: SPI_MTC
Bit Read/Write Default/Hex Description
31:24 / / /
MWTC
Master Write Transmit Counter
In master mode, this field specifies the burst number that should
be sent to TXFIFO before automatically sending dummy bursts. For
saving bus bandwidth, the dummy bursts (all zero bits or all one
23:0 R/W 0x0 bits) are sent by SPI Controller automatically.
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
9.3.6.11 0x0038 SPI Master Burst Control Counter Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: SPI_BCC
Bit Read/Write Default/Hex Description
31:30 / / /
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Offset: 0x0038 Register Name: SPI_BCC
Bit Read/Write Default/Hex Description
Quad_EN
Quad Mode Enable
The quad mode includes Quad-Input and Quad-Output.
29 R/W 0x0
0: Quad mode disable
1: Quad mode enable
Cannot be written when XCH=1.
DRM
Master Dual Mode RX Enable
It is only valid when Quad_Mode_EN=0.
28 R/W 0x0
0: RX uses the single-bit mode
1: RX uses the dual-bit mode
Cannot be written when XCH=1.
DBC
Master Dummy Burst Counter
In master mode, this field specifies the burst number that should
be sent before receiving in dual SPI mode. The data does not care
by the device.
27:24 R/W 0x0
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
STC
Master Single Mode Transmit Counter
In master mode, this field specifies the burst number that should
be sent in the single mode before automatically sending dummy
bursts. This is the first transmit counter in all bursts.
23:0 R/W 0x0
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
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9.3.6.12 0x0040 SPI Bit-Aligned Transfer Configure Register (Default Value: 0x0000_00A0)
Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
TCE
Transfer Control Enable
In master mode, it is used to start to transfer the serial bit frame,
it is only valid when Work Mode Select==0x10/0x11.
0: Idle
31 R/WAC 0x0
1: Initiates transfer
Writing “1” to this bit will start to transfer serial bit frame (the
value comes from the SPI TX Bit Register or SPI RX Bit Register), and
will auto-clear after the bursts transfer completely. Writing ‘0’ to
this bit has no effect.
MSMS
Master Sample Standard
0: Delay Sample Mode
1: Standard Sample Mode
30 R/W 0x0 In Standard Sample Mode, the SPI master samples the data at the
standard rising edge of SCLK for each SPI mode;
In Delay Sample Mode, the SPI master samples data at the edge
that is half cycle delayed by the standard rising edge of SCLK
defined in respective SPI mode.
29:26 / / /
TBC
Transfer Bits Completed
When set, this bit indicates that the last bit of the serial data frame
in SPI TX Bit Register (or SPI RX Bit Register) has been transferred
25 R/W1C 0x0
completely. Writing 1 to this bit clears it.
0: Busy
1: Transfer Completed
It is only valid when Work Mode Select==0x10/0x11.
TBC_INT_EN
Transfer Bits Completed Interrupt Enable
24 R/W 0x0 0: Disable
1: Enable
It is only valid when Work Mode Select==0x10/0x11.
23:22 / / /
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Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
Configure the length of serial data frame (burst) of RX
000000: 0 bit
000001: 1 bit
…
21:16 R/W 0x00
100000: 32 bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot
be written when TCE (bit31) is 1.
15:14 / / /
TX_FRM_LEN
Configure the length of serial data frame (burst) of TX
000000: 0 bit
000001: 1 bit
13:8 R/W 0x00 …
100000: 32 bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot
be written when TCE (bit31) is 1.
SS_LEVEL
When control the SS signal manually, set this bit to ‘1’ or ‘0’ to
control the level of SS signal.
7 R/W 0x1 0: Set SS to low
1: Set SS to high
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE (bit31) is 1.
SS_OWNER
SS Output Owner Select
Usually, the controller sends the SS signal automatically with data
together. When this bit is set to 1, the software must manually
6 R/W 0x0 write SS_LEVEL to 1 or 0 to control the level of the SS signal.
0: SPI controller
1: Software
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE (bit31) is 1.
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Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
SPOL
SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
5 R/W 0x1
1: Active low polarity (1 = Idle)
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE (bit31) is 1.
4 / / /
SS_SEL
SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
3:2 R/W 0x0 01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
It is only valid when Work Mode Select= =0x10/0x11, and only
work in Mode0, cannot be written when TCE (bit31) is 1.
Work Mode Select
00: Data frame is byte aligned in standard SPI, dual-output/dual
input SPI, dual IO SPI, and quad-output/quad-input SPI
1:0 R/W 0x0
01: Reserved
10: Data frame is bit aligned in 3-wire SPI
11: Data frame is bit aligned in standard SPI
9.3.6.13 0x0044 SPI Bit-Aligned CLOCK Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: SPI_BA_CCR
Bit Read/Write Default/Hex Description
31:8 / / /
CDR_N
Clock Divide Rate (Master Mode Only)
7:0 R/W 0x0 The SPI_SCLK is determined according to the following equation:
SPI_CLK = Source_CLK / (2*(CDR_N + 1)).
This register is only valid when Work Mode Select==0x10/0x11.
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9.3.6.14 0x0048 SPI TX Bit Register (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: SPI_TBR
Bit Read/Write Default/Hex Description
VTB
The Value of the Transmit Bits
This register is used to store the value of the transmitted serial data
31:0 R/W 0x0
frame.
In the process of transmission, the LSB is transmitted first.
This register is only valid when Work Mode Select==0x10/0x11.
9.3.6.15 0x004C SPI RX Bit Register (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: SPI_RBR
Bit Read/Write Default/Hex Description
VRB
The Value of the Receive Bits
This register is used to store the value of the received serial data
31:0 R/W 0x0
frame.
In the process of transmission, the LSB is transmitted first.
This register is only valid when Work Mode Select==0x10/0x11.
9.3.6.16 0x0088 SPI Normal DMA Mode Control Register (Default Value: 0x0000_00E5)
Offset: 0x0088 Register Name: SPI_NDMA_MODE_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
SPI_ACT_M
SPI NDMA Active Mode
00: dma_active is low
7:6 R/W 0x11
01: dma_active is high
10: dma_active is controlled by dma_request (DRQ)
11: dma_active is controlled by controller
SPI_ACK_M
SPI NDMA Acknowledge Mode
5 R/W 0x1
0: active fall do not care ack
1: active fall must after detect ack is high
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Offset: 0x0088 Register Name: SPI_NDMA_MODE_CTL
Bit Read/Write Default/Hex Description
SPI_DMA_WAIT
4:0 R/W 0x05 The counts of hold cycles from DMA last signal high to dma_active
high
9.3.6.17 0x0200 SPI TX Data Register (Default Value: 0x0000_0000)
Offset: 0x0200 Register Name: SPI_TXD
Bit Read/Write Default/Hex Description
TDATA
Transmit Data
This register can be accessed in the byte, half-word, or word unit by
AHB. In the byte accessing method, if there are rooms in TXFIFO,
one burst data is written to TXFIFO and the depth is increased by 1.
In the half-word accessing method, two SPI burst data are written
31:0 R/W 0x0
and the TXFIFO depth is increased by 2. In the word accessing
method, four SPI burst data are written and the TXFIFO depth is
increased by 4.
Note: This address is writable-only if TF_TEST is ‘0’, and if TF_TEST
is set to ‘1’, this address is readable and writable to test the
TXFIFO through the AHB bus.
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9.3.6.18 0x0300 SPI RX Data Register (Default Value: 0x0000_0000)
Offset: 0x0300 Register Name: SPI_RXD
Bit Read/Write Default/Hex Description
RDATA
Receive Data
This register can be accessed in the byte, half-word, or word unit
by AHB. In the byte accessing method, if there are data in RXFIFO,
the top word is returned and the RXFIFO depth is decreased by 1.
In the half-word accessing method, two SPI bursts are returned and
31:0 R 0x0
the RXFIFO depth is decreased by 2. In the word accessing method,
the four SPI bursts are returned and the RXFIFO depth is decreased
by 4.
Note: This address is readable-only if RF_TEST is ‘0’, and if RF_TEST
is set to ‘1’, this address is readable and writable to test the
RXFIFO through the AHB bus.
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9.4 SPI_DBI
9.4.1 Overview
The F133 provides a 3/4 line SPI display bus interface (SPI_DBI) for video data transmission. It supports DBI
mode or SPI mode. The DBI mode is compatible with multiple video data formats at the same time. The SPI
mode is used for low-cost display schemes.
The SPI mode has the following features:
Full-duplex synchronous serial interface
Master/slave configurable
8-bit wide by 64-entry FIFO for both transmit and receive data
Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable
Supports interrupts and DMA
Supports mode0, mode1, mode2, and mode3
Supports 3-wire/4-wire SPI
Supports programmable serial data frame length: 1 bit to 32 bits
Supports standard SPI, dual-output/dual-input SPI, dual I/O SPI, quad-output/quad-input SPI
Supports maximum IO rate of the mass production: 100 MHz
The DBI mode has the following features:
Supports DBI Type C 3 Line/4 Line Interface Mode
Supports 2 Data Lane Interface Mode
Supports data source from CPU or DMA
Supports RGB111/444/565/666/888 video format
Maximum resolution of RGB666 240 x 320@30Hz with single data lane
Maximum resolution of RGB888 240 x 320@60Hz or 320 x 480@30Hz with dual data lane
Supports Tearing effect
Supports software flexible control video frame rate
9.4.2 Block Diagram
Figure 9-30 shows a block diagram of the SPI_DBI.
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Figure 9-30 SPI_DBI Block Diagram
spi_ctrl
spi_mosi/wp/hold_oen
spi_mosi/wp/hold_out
spi_tx
spi_miso_oen
spi_miso_out
sckt
spi_ss_oen[3:0]
spi_ss_out[3:0]
spi_ss_in[3:0]
spi_cmu
spi_top spi_sck_oen
spi_sck_out
spi_sck_in
sckr
tbuf txfifo spi_mosi_in
spi_rx
spi_miso_in
sclk
domain
spi_rf MUX
MUX
GPIO
DBI_TypeC
dbi_sda_oen
dbi_sda_out
rbuf rxfifo dbi_tx dbi_wrx_oen
INTC dbi_wrx_out
sckt
dbi_csx_oen
hclk dbi_csx_out
domain dbi_dcx_oen
dbi_ctrl dbi_dcx_out
dbi_scl_oen
dbi_scl_out
dbi_sdi_oen
sckr
dbi_sda_in
dbi_rx
dbi_sdi_in
pixel_clk
domain
SPI_DBI contains the following sub-blocks:
Table 9-12 SPI_DBI Sub-blocks
Sub-block Description
Responsible for implementing the internal register, interrupt, and DMA
spi_rf
Request.
The data length transmitted from AHB to TXFIFO is converted into 8 bits,
spi_tbuf
then the data is written into the RXFIFO.
The block is used to convert the RXFIFO data into the reading data length
spi_rbuf
of AHB.
The data transmitted from the SPI to the external serial device is written
txfifo, rxfifo into the TXFIFO; the data received from the external serial device into SPI
is pushed into the RXFIFO.
Responsible for implementing SPI bus clock, chip select, internal sample,
spi_cmu
and the generation of transfer clock.
Responsible for implementing SPI data transfer, the interface of the
spi_tx
internal TXFIFO, and status register.
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Sub-block Description
Responsible for implementing SPI data receive, the interface of the
spi_rx
internal RXFIFO, and status register.
Responsible for implementing DBI bus clock, chip select, data command
dbi_ctrl
select, RGB format reshape.
Responsible for implementing DBI data transfer, the interface of the
dbi_tx
internal TXFIFO, and status register.
Responsible for implementing DBI data receive, the interface of the
dbi_rx
internal RXFIFO, and status register.
9.4.3 Functional Description
9.4.3.1 External Signals
The following table describes the external signals of SPI_DBI. When using SPI_DBI, the corresponding PADs are
selected as SPI_DBI function via section 9.7 “GPIO”.
Table 9-13 SPI_DBI External Signals
External Signal Description Type
DBI-CSX Chip select signal, low active I/O
DBI-SCLK Serial clock signal I/O
DBI-SDO Data output signal I/O
Data input signal, the data is sampled on the rising edge and
DBI-SDI I/O
the falling edge
DBI Mode Tearing effect input, it is used to capture the external TE
DBI-TE I/O
signal edge.
DCX pin is the select output signal of data and command.
DBI-DCX DCX = 0: register command; I/O
DCX = 1: data or parameter.
When DBI operates in dual data lane format, the RGB666
DBI-WRX I/O
format 2 can use WRX to transfer data
SPI1 chip select signal, low active
SPI1-CS When the device is not selected, data will not be accepted I/O
via the SI pin, and the SO pin will stop transmission.
SPI Mode SPI1 clock signal
SPI1-CLK This pin is used to provide a clock to the device and is used I/O
to control the flow of data to and from the device.
SPI1-MOSI SPI1 master data out, slave data in I/O
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External Signal Description Type
SPI1-MISO SPI1 master data in, slave data out I/O
Write protection and active low
SPI1-WP It also can be used for serial data input and output for SPI I/O
Quad Input or Quad Output mode.
When the device is selected and a serial sequence is
underway, the HOLD pin is can be used to temporarily pause
the serial communication with the master device without
deselecting or resetting the device serial sequence. While
SPI1-HOLD the HOLD pin is asserted, the SO pin is at high impedance, I/O
and all transitions on the SCK pin and data on the SI pin are
ignored.
It also can be used for serial data input and output for SPI
Quad Input or Quad Output mode.
9.4.3.2 Clock Sources
The SPI_DBI controller gets 5 different clock sources, users can select one of them to make SPI_DBI clock source.
The following table describes the clock sources for SPI_DBI. For more details on the clock setting, configuration,
and gating information, see section 3.3 “CCU”.
Table 9-14 SPI_DBI Clock Sources
Clock Sources Description
HOSC 24 MHz Crystal
PLL_PERI(1X) Peripheral Clock, the default value is 600 MHz
PLL_PERI(2X) Peripheral Clock, the default value is 1200 MHz
PLL_AUDIO0(DIV2) Audio Clock, the default value is 1536 MHz
PLL_AUDIO0(DIV5) Audio Clock, the default value is 614.4 MHz
9.4.3.3 Typical Application
Figure 9-31 shows the application block diagram when the SPI master device is connected to a slave device.
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Figure 9-31 SPI Application Block Diagram
SoC
SPI-CLK
SCK
SPI-CS
CS# SPI-
SPI-MISO
SO/IO1 compliant
SPI SPI-MOSI SI/IO0 External
SPI-WP Device
WP#/IO2
SPI-HOLD
HOLD#/IO3
Figure 9-32 shows the application block diagram when the DBI master device is connected to a display bus
interface device.
Figure 9-32 DBI Application Block Diagram
SoC
DBI-CSX
CSX
DBI-SCLK
SCLK Display
DBI-DCX
DBI D/CX bus
DBI-SDI SDI interface
DBI-SDO device
SDO
9.4.3.4 SPI Transmission Format
The SPI supports 4 different formats for data transmission. The software can select one of the four modes in
which the SPI works by setting the bit1 (Polarity) and bit0 (Phase) of SPI_TCR. The SPI controller master uses
the SPI_SCLK signal to transfer data in and out of the shift register. Data is clocked using any one of four
programmable clock phase and polarity combinations.
The CPOL (SPI_TCR[1]) defines the polarity of the clock signal (SPI_SCLK). The SPI_SCLK is a high level when
CPOL is ‘1’ and it is a low level when CPOL is ‘0’. The CPHA (SPI_TCR[0]) decides whether the leading edge of
SPI_SCLK is used to setup or sample data. The leading edge is used to setup data when CPHA is ‘1’, and sample
data when CPHA is ‘0’. The following table lists the four modes.
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Table 9-15 SPI Transmit Format
SPI Mode Polarity (CPOL) Phase (CPHA) Leading Edge Trailing Edge
mode0 0 0 Sample on the rising edge Setup on the falling edge
mode1 0 1 Setup on the rising edge Sample on the falling edge
Sample on the falling
mode2 1 0 Setup on the rising edge
edge
mode3 1 1 Setup on the falling edge Sample on the rising edge
Figure 9-33 and Figure 9-34 describe four waveforms for SPI_SCLK.
Figure 9-33 SPI Phase 0 Timing Diagram
Figure 9-34 SPI Phase 1 Timing Diagram
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9.4.3.5 SPI Master and Slave Mode
The SPI controller can be configured to a master or slave device. The master mode is selected by setting the
MODE bit (SPI_GCR[1]); the slave mode is selected by clearing the MODE bit.
In master mode, the SPI_CLK is generated and transmitted to the external device, and the data from the TX
FIFO is transmitted on the MOSI pin, the data from the slave is received on the MISO pin and sent to RX FIFO.
The Chip Select (SPI_SS) is an active low signal, and it must be set low before the data are transmitted or
received. The SPI_SS can be selected the auto control mode or the software manual control mode. When using
auto control, the SS_OWNER (SPI_TCR[6]) must be cleared (default value is 0); when using manual control, the
SS_OWNER must be set. And the level of SPI_SS is controlled by SS_LEVEL (SPI_TCR[7]).
In slave mode, after the software selects the MODE bit (SPI_GCR[1]) to '0', it waits for master initiate a
transaction. When the master asserts SPI_SS, and SPI_CLK is transmitted to the slave, the slave data is
transmitted from TX FIFO on the MISO pin, and the data from the MOSI pin is received in RX FIFO.
9.4.3.6 SPI 3-Wire Mode
The SPI 3-wire mode is only valid when the SPI controller work in master mode, and is selected when the Work
Mode Select bit (SPI_BATC[1:0]) is equal to 0x2. And in the 3-wire mode, the input data and the output data
use the same single data line. The following figure describes the 3-wire mode.
Figure 9-35 SPI 3-Wire Mode
9.4.3.7 SPI Dual-Input/Dual-Output and Dual I/O Mode
The dual read mode (SPI x2) is selected when the DRM is set in SPI_BCC[28]. Using the dual mode allows data
to be transferred to or from the device at double the rate of standard single mode SPI devices, the data can be
read at fast speed using two data bits (MOSI and MISO) at a time. The following figure describes the dual-
input/dual-output SPI (Figure 9-36) and the dual I/O SPI (Figure 9-37).
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Figure 9-36 SPI Dual-Input/Dual-Output Mode
In the dual-input/dual-output SPI mode, the command, address, and the dummy bytes output in a unit of a
single bit in serial mode through the SPI_MOSI line, only the data bytes are output (write) and input (read) in
a unit of dual bits through the SPI_MOSI and SPI_MISO.
Figure 9-37 SPI Dual I/O Mode
In the dual I/O SPI mode, only the command bytes output in a unit of a single bit in serial mode through the
SPI_MOSI line. The address bytes and the dummy bytes output in a unit of dual bits through the SPI_MOSI and
SPI_MISO. And the data bytes output (write) and input (read) in a unit of dual bits through the SPI_MOSI and
SPI_MISO.
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9.4.3.8 SPI Quad-Input/Quad-Output Mode
The quad read mode (SPI x4) is selected when the Quad_EN is set in SPI_BCC[29]. Using the quad mode allows
data to be transferred to or from the device at 4 times the rate of standard single mode SPI devices, the data
can be read at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3 (HOLD#)) at the same time. The
following figure describes the quad-input/quad-output SPI.
Figure 9-38 SPI Quad-Input/Quad-Output Mode
In the quad-input/quad-output SPI mode, the command, address, and the dummy bytes output in a unit of a
single bit in serial mode through the SPI_MOSI line. Only the data bytes output (write) and input (read) in a
unit of quad bits through the SPI_MOSI, SPI_MISO, SPI_WP#, and SPI_HOLD#.
9.4.3.9 Transmission/Reception Bursts in Master Mode
In SPI master mode, the transmission and reception bursts (byte in unit) are configured before the SPI transfers
serial data between the processor and external device. The transmission bursts are written in MWTC (bit[23:0])
of the SPI Master Transmit Counter Register. The transmission bursts in single mode before automatically
sending dummy bursts are written in STC (bit[23:0]) of the SPI Master Transmit Counter Register. For dummy
data, the SPI controller can automatically send before receiving by writing DBC (bit[27:24]) in the SPI Master
Transmit Counter Register. If users do not use the SPI controller to send dummy data automatically, then the
dummy bursts are used as the transmission counters to write together in MWTC (bit[23:0]) of the SPI Master
Transmit Counter Register. In master mode, the total burst numbers are written in MBC (bit[23:0]) of the SPI
Master Transmit Counter Register. When all transmission and reception bursts are transferred, the SPI
controller will send a completed interrupt, at the same time, the SPI controller will clear DBC, MWTC, and MBC.
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9.4.3.10 SPI Sample Mode and Run Clock Configuration
The SPI controller runs at 3 kHz–100 MHz at its interface to external SPI devices. The internal SPI clock should
run at the same frequency as the outgoing clock in the master mode. The SPI clock is selected from different
clock sources, the SPI must configure different work mode. There are three work modes: normal sample mode,
delay half-cycle sample mode, delay one-cycle sample mode. Delay half-cycle sample mode is the default mode
of the SPI controller. When the SPI runs at 40 MHz or below 40 MHz, the SPI can work at normal sample mode
or delay half-cycle sample mode. When the SPI runs over 80 MHz, setting the SDC bit in the SPI Transfer Control
Register to ‘1’ makes the internal read sample point with a half-cycle delay of SPI_CLK, which is used in high
speed read operation to reduce the error caused by the time delay of SPI_CLK between master and slave. Table
9-16 and Table 9-17 show the different configurations of the SPI sample mode.
Table 9-16 SPI Old Sample Mode and Run Clock
SPI Sample Mode SDM(bit13) SDC(bit11) Run Clock
normal sample 1 0 <=24 MHz
delay half cycle sample 0 0 <=40 MHz
delay one cycle sample 0 1 >=80 MHz
CAUTION
The remaining spectrum is not recommended. Because when the output delay of SPI flash (refer to the
datasheet of the manufactures for the specific delay time) is the same with the half-cycle time of SPI working
clock, the variable edge of the output data for the device bumps into the clock sampling edge of the controller,
so setting 1 cycle of sampling delay would cause stability problem.
Table 9-17 SPI New Sample Mode
SPI Sample Mode SDM (bit13) SDC (bit11) SDC1 (bit15)
normal sample 1 0 0
delay half cycle sample 0 0 0
delay one cycle sample 0 1 0
delay 1.5 cycle sample 1 1 0
delay 2 cycle sample 1 0 1
delay 2.5 cycle sample 0 0 1
delay 3 cycle sample 0 1 1
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9.4.3.11 DBI 3-Line Interface Writing and Reading Timing
The 3-line DBI Interface I contains CSX, SDA, and SCL, where SDA shares this port for bidirectional port data
input and output.
The 3-line DBI Interface II contains CSX, SDA, SCL, and SDI; Data input and output ports are independent of each
other.
Since the 3-line display bus mode has no Data/Command data line indicating whether Data or Command is
currently being transmitted, an extra bit is added to the data-stream before MSB to indicate whether Data or
Command is currently being transmitted. (0: Command, 1: Data)
The following figure shows the writing operation format of 3-line DBI Interface I and Interface II.
Figure 9-39 DBI 3-Line Display Bus Serial Interface Writing Operation Format
The next Command
Command or following Data
CSX
Host SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 D/C D7 D6 D5 D4 D3 D2 D1 D0
SCL
The CSX can be high level between the data and next
command. The SDA and SCL are invalid during CSX is
high level.
The 3-line DBI Interface I uses the SDA port as bidirectional data input and output port. There are only three
cases of data reading volume, 8bits/24bits/32bits, and the first data sampled is high.
The following figure shows the 8 bits reading operation format of 3-line DBI Interface I and Interface II. After
the read command is transmitted, the data is read immediately with on dummy period.
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Figure 9-40 DBI 3-Line Display Bus Serial Interface 8-bit Reading Operation Format
Read Command Read Data
CSX
SCL
Interface I SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
SDO 0 D7 D6 D5 D4 D3 D2 D1 D0
Interface II
SDI Hi-Z D7 D6 D5 D4 D3 D2 D1 D0
The following figure shows the 24 bits reading operation format of 3-line DBI Interface I and Interface II. After
the read command is transmitted, the data is read after waiting for the dummy clock cycle.
Figure 9-41 DBI 3-Line Display Bus Serial Interface 24-bit Reading Operation Format
Read Command Read Data
CSX
SCL
Interface I SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D2 D1 D0
Hi-Z
SDO 0 D7 D6 D5 D4 D3 D2 D1 D0
Interface II Hi-Z
SDI D23 D22 D21 D2 D1 D0
Dummy clock cycle
The following figure shows the 32 bits reading operation format of 3-line DBI Interface I and Interface II. After
the read command is transmitted, the data is read after waiting for the dummy clock cycle.
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Figure 9-42 DBI 3-Line Display Bus Serial Interface 32-bit Reading Operation Format
Read Command Read Data
CSX
SCL
Interface I SDA 0 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D2 D1 D0
Hi-Z
SDO 0 D7 D6 D5 D4 D3 D2 D1 D0
Interface II Hi-Z
SDI D31 D30 D29 D2 D1 D0
Dummy clock cycle
9.4.3.12 DBI 4-Line Interface Writing and Reading Timing
The 4-line DBI Interface I contains CSX, D/CX, SDA, and SCL, where SDA shares this port for bidirectional port
data input and output.
The 4-line DBI Interface II contains CSX, D/CX, SDA, SCL, and SDI; Data input and output ports are independent
of each other.
Since the 4-line display bus mode has a Data/Command data line indicating whether Data or Command is
currently being transmitted (0: Command, 1: Data). So there is no need to add an extra bit to data-stream
before MSB like the 3-line DBI.
The following figure shows the writing operation format of 4-line DBI Interface I and Interface II.
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Figure 9-43 DBI 4-Line Display Bus Serial Interface Writing Operation Format
The next Command
Command or following Data
CSX
D/CX
Host
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL
The CSX can be high level between the data and
next command. The SDA and SCL are invalid
during CSX is high level.
The following figure shows the 8 bits reading operation format of 4-line DBI Interface I and Interface II.
Figure 9-44 DBI 4-Line Display Bus Serial Interface 8-bit Reading Operation Format
Read Command Read Data
CSX
D/CX
SCL
Interface I
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
SDO D7 D6 D5 D4 D3 D2 D1 D0
Interface II
SDI Hi-Z D7 D6 D5 D4 D3 D2 D1 D0
The following figure shows the 24 bits reading operation format of 4-line DBI Interface I and Interface II.
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Figure 9-45 DBI 4-Line Display Bus Serial Interface 24-bit Reading Operation Format
Read Command Read Data
CSX
D/CX
SCL
Interface I SDA D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D2 D1 D0
Hi-Z
SDO D7 D6 D5 D4 D3 D2 D1 D0
Interface II Hi-Z
SDI D23 D22 D21 D2 D1 D0
Dummy clock cycle
The following figure shows the 32 bits reading operation format of 4-line DBI Interface I and Interface II.
Figure 9-46 DBI 4-Line Display Bus Serial Interface 32-bit Reading Operation Format
Read Command Read Data
CSX
D/CX
SCL
Interface I SDA D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29 D2 D1 D0
Hi-Z
SDO D7 D6 D5 D4 D3 D2 D1 D0
Interface II Hi-Z
SDI D31 D30 D29 D2 D1 D0
Dummy clock cycle
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9.4.3.13 DBI 3-Line Interface Transmit Video Format
Figure 9-47 RGB111 3-Line Interface Transmit Video Format
CSX
Pixel n Pixel n+ 1
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 - - R1 G1 B1 R2 G2 B2 1 - - R3 G3 B3 R4 G4 B4 1 - - R5 G5 B5 R6 G6 B6
WRX/SCL
3 bits 3 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 9-48 RGB444 3-Line Interface Transmit Video Format
RESX
“1”
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R1 3 R1 2 R1 1 R1 0 G13 G12 G11 G10 1 B1 3 B1 2 B1 1 B1 0 R2 3 R2 2 R2 1 R2 0 1 G23 G2 2 G21 G20 B2 3 B22 B21 B2 0
Pixel n Pixel n+ 1
SCL
12 bits 12 bits
Loop-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 12-bit color depth information
Note 2. The mos t significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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Figure 9-49 RGB565 3-Line Interface Transmit Video Format
RESX
“1”
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R1 4 R13 R12 R11 R1 0 G1 S G1 4 G1 3 1 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 1 R1 4 R1 3 R1 2 R1 1 R1 0 G1 S G1 4 G1 3
Pixel n Pixel n+ 1
SCL
16 bits 16 bits
Loop-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 16-bit color depth information
Note 2. The mos t significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Figure 9-50 RGB666 3-Line Interface Transmit Video Format
RESX
“1”
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R1 5 R14 R13 R1 2 R11 R1 0 - - 1 G1 5 G1 4 G1 3 G1 2 G1 1 G1 0 - - 1 B1 5 B1 4 B1 3 B12 B1 1 B10 - -
Pixel n
SCL
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 18-bit color depth information
Note 2. The mos t significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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9.4.3.14 DBI 4-Line Interface Transmit Video Format
Figure 9-51 RGB111 4-Line Interface Transmit Video Format
CSX
D/CX 1 1 1
Pixel n Pixel n+ 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA - - R1 G1 B1 R2 G2 B2 - - R3 G3 B3 R4 G4 B4 - - R5 G5 B5 R6 G6 B6
WRX/SCL
3 bits 3 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Figure 9-52 RGB444 4-Line Interface Transmit Video Format
RESX
“1”
CSX
D/CX
“1”
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA R1 3 R12 R1 1 R10 G1 3 G1 2 G1 1 G1 0 B1 3 B1 2 B1 1 B1 0 R2 3 R2 2 R2 1 R2 0 G2 3 G2 2 G2 1 G2 0 B2 3 B2 2 B2 1 B2 0
Pixel n Pixel n+ 1
SCL
12 bits 12 bits
Loop-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 12-bit color depth information
Note 2. The mos t significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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Figure 9-53 RGB565 4-Line Interface Transmit Video Format
RESX
“1”
CSX
D/CX
“1”
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA R1 4 R13 R1 2 R11 R1 0 G1 5 G1 4 G1 3 G1 2 G1 1 G1 0 B1 4 B13 B1 2 B1 1 B1 0 R14 R1 3 R12 R1 1 R1 0 G15 G1 4 G1 3
Pixel n Pixel n+ 1
SCL
16 bits 16 bits
Loop-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 16-bit color depth information
Note 2. The mos t significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Figure 9-54 RGB666 4-Line Interface Transmit Video Format
RESX
“1”
CSX
D/CX
“1”
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA R1 5 R1 4 R13 R12 R1 1 R1 0 - - G1 5 G14 G1 3 G12 G1 1 G10 - - B15 B1 4 B13 B1 2 B11 B10 - -
Pixel n
SCL
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 18-bit color depth information
Note 2. The mos t significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
9.4.3.15 DBI 2 Data Lane Interface Transmit Video Format
For RGB444:
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Figure 9-55 RGB444 2 Data Lane Interface Transmit Video Format
RESX
“1”
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R1 3 R12 R11 R10 G1 3 G1 2 G1 1 G1 0 1 R1 3 R1 2 R1 1 R1 0 G1 3 G1 2 G1 1 G1 0
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 B1 3 B1 2 B1 1 B10 - - - - 1 B1 3 B1 2 B1 1 B1 0 - - - -
Pixel n Pixel n+ 1
SCL
12 bits 12 bits
Lo op-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 12-bit color in formation
Note 2. The mos t significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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Figure 9-56 RGB565 2 Data Lane Interface Transmit Video Format
RESX
“1”
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R14 R1 3 R1 2 R1 1 R1 0 G15 G1 4 G13 1 R1 4 R13 R12 R11 R1 0 G1 5 G1 4 G1 3
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 G12 G1 1 G1 0 B14 B1 3 B1 2 B1 1 B1 0 1 G1 2 G1 1 G1 0 B14 B1 3 B12 B11 B10
Pixel n Pixel n+ 1
SCL
16 bits 16 bits
Loop-up table for 65k color data mapp ing (16 bits to 18 bits)
18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 16-bit color information
Note 2. The mos t significan t bits are: Rx4, Gx5 and Bx4
Note 3. The least significan t bits are: Rx0, Gx0 and Bx0
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Figure 9-57 RGB666 2 Data Lane Interface Transmit Video Format 0
RESX
“1”
CSX
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R15 R1 4 R1 3 R12 R1 1 R1 0 G1 5 G1 4 G1 3 1 R1 5 R1 4 R1 3 R12 R1 1 R1 0 G1 5 G1 4 G13
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 G12 G1 1 G1 0 B15 B1 4 B1 3 B1 2 B1 1 B10 1 G12 G1 1 G10 B15 B1 4 B1 3 B1 2 B1 1 B10
Pixel n Pixel n+ 1
SCL
18 bits 18 bits
Frame Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with 18-bit color information
Note 2. The mos t significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Figure 9-58 RGB666 2 Data Lane Interface Transmit Video Format 1 (ilitek)
18 bit/pixel color order (R:6-bit, G:6-bit, B:6-bit), 262, 144 colors, Type1
S TB TB TB
CSX
Host SDA 1 R5 R4 R3 R2 R1 R0 1 B5 B4 B3 B2 B1 B0 1 G5 G4 G3 G2 G1 G0
(MCU to Driver)
D/CX(SDA2) 1 G5 G4 G3 G2 G1 G0 1 R5 R4 R3 R2 R1 R0 1 B5 B4 B3 B2 B1 B0
SCL
Pixel data 1 B5~B0: Pixel data 1 Pixel data 2
R5~R0: Pixel data 2
Figure 9-59 RGB666 2 Data Lane Interface Transmit Video Format 2 (New vision)
RGB666,mdt=01
CSX
SCL
SDA A0 R5 R4 R3 R2 R1 R0 A0 B5 B4 B3 B2 B1 B0 A0 G5 G4 G3 G2 G1 G0
WRX A0 G5 G4 G3 G2 G1 G0 A0 R5 R4 R3 R2 R1 R0 A0 B5 B4 B3 B2 B1 B0
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Figure 9-60 RGB888 2 Data Lane Interface Transmit Video Format
RGB888
CSX
SDA_0 1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 1 R7 R6 R5 R4
SDA_1 1 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 1 G3 G2 G1 G0
SCL
Note 1. Pixel data with 24-bit color information
Note 2. The mos t significant bits are: R7, G7 and B7
Note 3. The least significant bits are: R0, G0 and B0
9.4.4 Programming Guidelines
9.4.4.1 Writing/Reading Data Process Using SPI Mode
The SPI transfers serial data between the processor and the external device. CPU and DMA are the two main
operational modes for SPI. For each SPI, the data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). The SPI has 2 channels, including the TX channel and RX channel. The TX channel
has the path from TX FIFO to the external device. The RX channel has the path from the external device to RX
FIFO.
Write Data: CPU or DMA must write data on the SPI_TXD register, the data on the register are automatically
moved to TX FIFO.
Read Data: To read data from RX FIFO, CPU or DMA must access the register SPI_RXD and data are
automatically sent to the register SPI_RXD.
In CPU or DMA mode, the SPI sends a completed interrupt (SPI_ISR[TC]) to the processor at the end of each
transfer.
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CPU Mode
Figure 9-61 SPI Write/Read Data in CPU Mode
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DMA Mode
Figure 9-62 SPI Write/Read Data in DMA Mode
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9.4.4.2 Calibrate Delay Chain Using SPI Mode
The SPI has one delay chain which is used to generate delay to make proper timing between the internal SPI
clock signal and data signals. Delay chain is made up of 64 delay cells. The delay time of one delay cell can be
estimated through delay chain calibration.
The steps to calibrate delay chain are as follows:
Step 1 Enable SPI. To calibrate the delay chain by operation registers in SPI, the SPI must be enabled through
AHB reset and AHB clock gating control registers.
Step 2 Configure a proper clock for SPI. The calibration delay chain is based on the clock for SPI from CCU.
Step 3 Set proper initial delay value. Write 0xA0 to the SPI Sample Delay Control Register to set initial delay
value 0x20 to delay chain. Then write 0x0 to the SPI Sample Delay Control Register to clear this value.
Step 4 Write 0x8000 to the SPI Sample Delay Control Register to start to calibrate the delay chain.
Step 5 Wait until the flag (Bit14 in the SPI Sample Delay Control Register) of calibration done is set. The
number of delay cells is shown at Bit[13:8] in SPI Sample Delay Control Register. The delay time
generated by these delay cells is equal to the cycle of SPI’s clock nearly. This value is the result of
calibration.
Step 6 Calculate the delay time of one delay cell according to the cycle of the SPI clock and the result of
calibration.
9.4.4.3 Transmitting Write Command Using DBI Mode
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit[30:29]) of DBI_CTL_1 (0x0104) to 0 to select the trigger mode of DBI.
Step 3 Configure the DBI_CTL_0 (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to configure the writing command.
Set DBI_CTL_0[Write Command Dummy Cycles] (bit[30:20]) to configure the number of dummy
cycles between commands.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 0 to select the command path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to 0 to transmit the command.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
The remaining values of the DBI_CTL_0 register remain the default value.
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Step 4 Set DBI_CTL_1[DCX_DATA] (bit22) to 0 to send the command.
Step 5 DMA Path: Configure the SPI_FCR register (0x0018).
Set SPI_FCR[TF_DRQ_EN] (bit24) to 1 to enable TXFIFO DMA.
Set SPI_FCR[TX_TRIG_LEVEL] (bit[23:16]) to 255. It indicates the controller requests data from
DMA if the remaining space of TX FIFO is greater than 255.
CPU Path: Write the command to be sent to the 0x200 address.
Step 6 Set SPI_GCR[DBI_EN] (bit4) to 1 to start transmitting the command.
Step 7 Wait until the TX FIFO underrun interrupt (SPI_ISR[TF_UDF]) is 1. It indicates that the command
written to the TX FIFO is transmitted completely.
9.4.4.4 Transmitting Parameter Using DBI Mode
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit[30:29]) of DBI_CTL_1 (0x0104) to 0 to select the trigger mode of DBI.
Step 3 Configure the DBI_CTL_0 register (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to configure the writing command.
Set DBI_CTL_0[Write Command Dummy Cycles] (bit[30:20]) to configure the number of dummy
cycles between commands.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 0 to select the command path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to 0 to transmit the command.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
The remaining values of the DBI_CTL_0 register remain the default value.
Step 4 Set DBI_CTL_1[DCX_DATA] (bit22) to 1 to send the parameter.
Step 5 DMA Path: Configure the register (0x0018).
Set SPI_FCR[TF_DRQ_EN] (bit24) to 1 to enable TXFIFO DMA.
Set SPI_FCR[TX_TRIG_LEVEL] (bit[23:16]) to 255. It indicates the controller requests data from
DMA if the remaining space of TX FIFO is greater than 255.
CPU Path: Write the command to be sent to the 0x0200 address.
Step 6 Set SPI_GCR[DBI_EN] (bit4) to 1 to start transmitting the command.
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Step 7 Wait until the TX FIFO underrun interrupt (SPI_ISR[TF_UDF]) is 1. It indicates that the command
written to the TX FIFO is transmitted completely.
9.4.4.5 Transmitting Video Using DBI Mode
Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
If the data is from the CPU path, the controller writes the command to be sent to the 0x0200 address by the
AHB bus.
If the data is from the DMA path, configure DBI_CTL_1[DBI_FIFO_DRQ_EN] (bit15) to 1 and
DBI_CTL_1[TX_TRIG_LEVEL] (bit[14:8]) to 64, which indicates the controller requests data from DMA if the
remaining space of TX FIFO is greater than 64.
Software Trigger Mode
The software enables DBI_en_trigger when the edge interrupt of TE is detected.
After transmitting each frame image, the controller clears automatically the line_cnt, pixel_cnt and stops
transmitting data.
Wait for the edge interrupt of TE, the software needs to enable DBI_en_trigger, in circulation.
The operation process is as follows.
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit[30:29]) of DBI_CTL_1 (0x0104) to 1 to select the software trigger mode.
Step 3 Configure the DBI_CTL_0 register (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to set the writing command.
Set DBI_CTL_0[Write Command Dummy Cycles] (bit[30:20]) to configure the number of dummy
cycles between commands.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 1 to select the image path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to select RGB111//444/565/666/888.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
The remaining values of the DBI_CTL_0 register remain the default value.
Step 4 Set DBI_CTL_1[DCX_DATA] (bit22) to 0 to send the image data.
Step 5 Configure DBI_Video_Size (0x110) according to the sent image size.
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Step 6 Configure DBI_CTL_2 (0x0108) to set the TE-related parameter.
Step 7 Detect the TE interrupt of the DBI_INT (0x0120) register.
Step 8 Configure DBI_CTL_1[DBI_soft_trigger] to 1.
Timer Trigger Mode
The software configures timer_en to enable timer counting, and when the counter reaches the specified value,
the DBI_EN automatically can be enabled to start transmitting data.
After transmitting each frame image, the controller clears automatically the line_cnt, pixel_cnt, and stops
transmitting data.
The timer starts counting again. When the counter reaches the specified value, the controller automatically
enables DBI_EN, and in circulation until the software turns off the timer_en.
The operation process is as follows.
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit30:29) of DBI_CTL_1 (0x0104) to 2 to select the timer trigger mode.
Step 3 Configure the DBI_CTL_0 register (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to set the writing command.
Set DBI_CTL_0[Write Command Dummy Cycles] (bit[30:20]) to configure the number of dummy
cycles between commands.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 1 to select the image path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to select RGB111/444/565/666/888.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
The remaining values of the DBI_CTL_0 register remain the default value.
Step 4 Set DBI_CTL_1[DCX_DATA] (bit22) to 0 to send the image data.
Step 5 Configure DBI_Video_Size (0x110) to transmit the image size.
Step 6 Configure the related parameter of DBI_Timer (0x10C).
TE Trigger Mode
When the edge changes of the TE are detected (The rising and falling edges are optional), the DBI_EN
automatically can be enabled to start transmitting data.
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After transmitting each frame image, the controller clears automatically the line_cnt, pixel_cnt, and stops
transmitting data.
When the edge changes of the TE are detected (The rising and falling edges are optional), the DBI_EN
automatically can be enabled to start transmitting data until the software shuts down TE_EN or the screen no
longer sends TE signals.
The operation process is as follows.
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit30:29) of DBI_CTL_1 (0x0104) to 3 to select the TE trigger mode.
Step 3 Configure the DBI_CTL_0 register (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to set the writing command.
Set DBI_CTL_0[Write Command Dummy Cycles] (bit[30:20]) to configure the number of dummy
cycles between commands.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 1 to select the image path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to select RGB111/444/565/666/888.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
The remaining values of the DBI_CTL_0 register remain the default value.
Step 4 Configure DBI_CTL_1[DCX_DATA] (bit22) to 0 to send the image data.
Step 5 Configure DBI_Video_Size (0x0110) to transmit the image size.
Step 6 Configure DBI_CTL_2 (0x0108) to set the TE-related parameter.
9.4.4.6 Transmitting Read Command and Read Data Using DBI Mode
Step 1 Set the SPI_DBI_MODE_SEL (bit3) of SPI_GCR (0x0004) to 1 to select DBI mode.
Step 2 Set the DBI EN MODE SEL (bit[30:29]) of DBI_CTL_1 (0x0104) to 0.
Step 3 Configure the DBI_CTL_0 register (0x0100).
Set DBI_CTL_0[Command Type] (bit31) to 0 to set the reading command.
Set DBI_CTL_0[Output Data Sequence] (bit19) to select the MSB or LSB.
Set DBI_CTL_0[Transmit Mode] (bit15) to 0 to select the command path.
Set DBI_CTL_0[Output Data Format] (bit[14:12]) to 0.
Set DBI_CTL_0[DBI interface Select] (bit[10:8]) to select the DBI interface type.
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The remaining values of the DBI_CTL_0 register remain the default value.
Step 4 Configure the DBI_CTL_1 register (0x0104).
Configure DBI_CTL_1[DCX_DATA] (bit22) to 0 to send the command.
Configure DBI_CTL_1[Read_MSB_First] (bit20) to select whether the first bit of the read data is
the highest or lowest bit of data.
Configure DBI_CTL_1[Read Data Number of Bytes] to set the byte number to be read.
Configure DBI_CTL_1[Read Command Dummy Cycles] to set the dummy cycle between the read
command and the read data, when the dummy cycle is complete, the data starts to be sampled.
Step 5 DMA Path: Configure the SPI_FCR register (0x0018).
Set SPI_FCR[RF_DRQ_EN] (bit8) to 1 to enable RXFIFO DMA.
Set SPI_FCR[RX_TRIG_LEVEL] (bit[7:0]) to 32, which indicates the controller requests receiving
data from DMA if the data of the RX FIFO is greater than 64.
CPU Path: Read data in RX FIFO from the 0x0300 address.
Step 6 Set SPI_GCR[DBI_EN] (bit4) to 1 to start transmitting command.
Step 7 Wait until DBI_INT[RD_DONE_INT] is 1. It indicates that the data is read completely.
9.4.5 Register List
Module Name Base Address
SPI_DBI 0x04026000
Register Name Offset Description
SPI_GCR 0x0004 SPI Global Control Register
SPI_TCR 0x0008 SPI Transfer Control Register
SPI_IER 0x0010 SPI Interrupt Control Register
SPI_ISR 0x0014 SPI Interrupt Status Register
SPI_FCR 0x0018 SPI FIFO Control Register
SPI_FSR 0x001C SPI FIFO Status Register
SPI_WCR 0x0020 SPI Wait Clock Register
SPI_SAMP_DL 0x0028 SPI Sample Delay Control Register
SPI_MBC 0x0030 SPI Master Burst Counter Register
SPI_MTC 0x0034 SPI Master Transmit Counter Register
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Register Name Offset Description
SPI_BCC 0x0038 SPI Master Burst Control Register
SPI_BATCR 0x0040 SPI Bit-Aligned Transfer Configure Register
SPI_BA_CCR 0x0044 SPI Bit-Aligned Clock Configuration Register
SPI_TBR 0x0048 SPI TX Bit Register
SPI_RBR 0x004C SPI RX Bit Register
SPI_NDMA_MODE_CTL 0x0088 SPI Normal DMA Mode Control Register
DBI_CTL_0 0x0100 DBI Control Register 0
DBI_CTL_1 0x0104 DBI Control Register 1
DBI_CTL_2 0x0108 DBI Control Register 2
DBI_TIMER 0x010C DBI Timer Control Register
DBI_VIDEO_SZIE 0x0110 DBI Video Size Configuration Register
DBI_INT 0x0120 DBI Interrupt Register
DBI_DEBUG_0 0x0124 DBI BEBUG 0 Register
DBI_DEBUG_1 0x0128 DBI BEBUG 1 Register
SPI_TXD 0x0200 SPI TX Data register
SPI_RXD 0x0300 SPI RX Data register
9.4.6 Register Description
9.4.6.1 0x0004 SPI Global Control Register (Default Value: 0x0000_0080)
Offset:0x0004 Register Name: SPI_GCR
Bit Read/Write Default/Hex Description
SRST
Soft reset
31 R/WAC 0x0 Writing ‘1’ to this bit will clear the SPI controller, and auto clear to
‘0’ when reset operation completes.
Writing ‘0’ to this bit has no effect.
30:8 / / /
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Offset:0x0004 Register Name: SPI_GCR
Bit Read/Write Default/Hex Description
TP_EN
Transmit Pause Enable
In master mode, it is used to control transmit state machine to stop
7 R/W 0x1 smart burst sending when RX FIFO is full.
0: Normal operation, ignore RXFIFO status
1: Stop transmit data when RXFIFO full
Cannot be written when XCH=1.
6:5 / / /
DBI EN
DBI Module Enable Control
4 R/W 0x0
0: Disable
1: Enable
SPI_DBI_MODE_SEL
DBI Working Mode Select
3 R/W 0x0
0: SPI MODE
1: DBI MODE
MODE_SELEC
Sample Timing Mode Select
2 R/W 0x0 0: Old mode of Sample Timing
1: New mode of Sample Timing
Cannot be written when XCH=1.
MODE
SPI Function Mode Select
1 R/W 0x0 0: Slave mode
1: Master mode
Cannot be written when XCH=1.
EN
SPI Module Enable Control
0: Disable
0 R/W 0x0
1: Enable
After transforming from bit_mode to byte_mode, it must enable
the SPI module again.
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9.4.6.2 0x0008 SPI Transfer Control Register (Default Value: 0x0000_0087)
Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
XCH
Exchange Burst
In master mode, it is used to start SPI burst
0: Idle
31 R/WAC 0x0 1: Initiates exchange.
Writing “1” to this bit will start the SPI burst, and will auto-clear
after finishing the bursts transfer specified by BC. Writing “1” to
SRST will also clear this bit. Writing ‘0’ to this bit has no effect.
Cannot be written when XCH=1.
30:16 / / /
SDC1
Master Sample Data Control register1
Set this bit to ‘1’ to make the internal read sample point with a
delay of half-cycle of SPI_CLK. It is used in high speed read
15 R/W 0x0 operation to reduce the error caused by the time delay of SPI_CLK
between master and slave.
0: Normal operation, do not delay the internal read sample point
1: Delay the internal read sample point
Cannot be written when XCH=1.
SDDM
Sending Data Delay Mode
0: Normal sending
14 R/W 0x0 1: Delay sending
Set the bit to "1" to make the data that should be sent with a delay
of half-cycle of SPI_CLK in dual IO mode for SPI mode 0.
Cannot be written when XCH=1.
SDM
Master Sample Data Mode
0: Delay sample mode
1: Normal sample mode
In normal sample mode, the SPI master samples the data at the
13 R/W 0x0
correct edge for each SPI mode;
In delay sample mode, the SPI master samples data at the edge
that is half cycle delayed by the correct edge defined in respective
SPI mode.
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
FBS
First Transmit Bit Select
12 R/W 0x0 0: MSB first. The upper bits are transmitted first.
1: LSB first. The lower bits are transmitted first.
Cannot be written when XCH=1.
SDC
Master Sample Data Control
Set this bit to ‘1’ to make the internal read sample point with a
delay of half-cycle of SPI_CLK. It is used in high speed read
11 R/W 0x0 operation to reduce the error caused by the time delay of SPI_CLK
between master and slave.
0: Normal operation, do not delay the internal read sample point
1: Delay the internal read sample point
Cannot be written when XCH=1.
RPSM
Rapids Mode Select
Select rapid mode for high speed write.
10 R/W 0x0
0: Normal write mode
1: Rapid write mode
Cannot be written when XCH=1.
DDB
Dummy Burst Type
9 R/W 0x0 0: The bit value of dummy SPI burst is zero
1: The bit value of dummy SPI burst is one
Cannot be written when XCH=1.
DHB
Discard Hash Burst
In master mode, it controls whether discarding unused SPI bursts
8 R/W 0x0 0: Receiving all SPI bursts in the BC period
1: Discard unused SPI bursts, only fetching the SPI bursts during
the dummy burst period. The burst number is specified by TC.
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
SS_LEVEL
SPI Chip Select Level
When control SS signal manually (SS_OWNER (SPI_TCR[6])==1), set
7 R/W 0x1 this bit to ‘1’ or ‘0’ to control the level of SS signal.
0: Set SS to low
1: Set SS to high
Cannot be written when XCH=1.
SS_OWNER
SS Output Owner Select
Usually, the controller sends the SS signal automatically with data
together. When this bit is set to 1, the software must manually
6 R/W 0x0 write SS_LEVEL (SPI_TCR[7]) to 1 or 0 to control the level of the SS
signal.
0: SPI controller
1: Software
Cannot be written when XCH=1.
SS_SEL
SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
5:4 R/W 0x0
01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
Cannot be written when XCH=1.
SSCTL
In master mode, this bit selects the output waveform for the
SPI_SSx signal. Only valid when SS_OWNER (SPI_TCR[6])= 0.
3 R/W 0x0
0: SPI_SSx remains asserted between SPI bursts
1: Negate SPI_SSx between SPI bursts
Cannot be written when XCH=1.
SPOL
SPI Chip Select Signal Polarity Control
2 R/W 0x1 0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.
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Offset: 0x0008 Register Name: SPI_TCR
Bit Read/Write Default/Hex Description
CPOL
SPI Clock Polarity Control
1 R/W 0x1 0: Active high polarity (0 = Idle)
1: Active low polarity (1 = Idle)
Cannot be written when XCH=1.
CPHA
SPI Clock/Data Phase Control
0 R/W 0x1 0: Phase 0 (Leading edge for sample data)
1: Phase 1 (Leading edge for setup data)
Cannot be written when XCH=1.
9.4.6.3 0x0010 SPI Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: SPI_IER
Bit Read/Write Default/Hex Description
31:14 / / /
SS_INT_EN
SSI Interrupt Enable
13 R/W 0x0 Chip select signal (SSx) from the valid state to the invalid state
0: Disable
1: Enable
TC_INT_EN
Transfer Completed Interrupt Enable
12 R/W 0x0
0: Disable
1: Enable
TF_UDR_INT_EN
TXFIFO Underrun Interrupt Enable
11 R/W 0x0
0: Disable
1: Enable
TF_OVF_INT_EN
TX FIFO Overflow Interrupt Enable
10 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0010 Register Name: SPI_IER
Bit Read/Write Default/Hex Description
RF_UDR_INT_EN
RXFIFO Underrun Interrupt Enable
9 R/W 0x0
0: Disable
1: Enable
RF_OVF_INT_EN
RX FIFO Overflow Interrupt Enable
8 R/W 0x0
0: Disable
1: Enable
7 / / /
TF_FUL_INT_EN
TX FIFO Full Interrupt Enable
6 R/W 0x0
0: Disable
1: Enable
TX_EMP_INT_EN
TX FIFO Empty Interrupt Enable
5 R/W 0x0
0: Disable
1: Enable
TX_ERQ_INT_EN
TX FIFO Empty Request Interrupt Enable
4 R/W 0x0
0: Disable
1: Enable
3 / / /
RF_FUL_INT_EN
RX FIFO Full Interrupt Enable
2 R/W 0x0
0: Disable
1: Enable
RX_EMP_INT_EN
RX FIFO Empty Interrupt Enable
1 R/W 0x0
0: Disable
1: Enable
RF_RDY_INT_EN
RX FIFO Ready Request Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
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9.4.6.4 0x0014 SPI Interrupt Status Register (Default Value: 0x0000_0032)
Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
31:14 / / /
SSI
SS Invalid Interrupt
13 R/W1C 0x0
When SSI is 1, it indicates that SS has changed from the valid state
to the invalid state. Writing 1 to this bit clears it.
TC
Transfer Completed
In master mode, it indicates that all bursts specified by BC have
been exchanged. In other conditions, when set, this bit indicates
12 R/W1C 0x0 that all the data in TXFIFO has been loaded in the Shift register, and
the Shift register has shifted out all the bits. Writing 1 to this bit
clears it.
0: Busy
1: Transfer completed
TF_UDF
TXFIFO Underrun
This bit is set when the TXFIFO is underrun. Writing 1 to this bit
11 R/W1C 0x0
clears it.
0: TXFIFO is not underrun
1: TXFIFO is underrun
TF_OVF
TXFIFO Overflow
This bit is set when the TXFIFO is overflowed. Writing 1 to this bit
10 R/W1C 0x0
clears it.
0: TXFIFO is not overflowed
1: TXFIFO is overflowed
RX_UDF
RXFIFO Underrun
When set, this bit indicates that RXFIFO is underrun. Writing 1 to
9 R/W1C 0x0
this bit clears it.
0: RXFIFO is not underrun
1: RXFIFO is underrun
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Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
RX_OVF
RXFIFO Overflow
When set, this bit indicates that RXFIFO is overflowed. Writing 1 to
8 R/W1C 0x0
this bit clears it.
0: RXFIFO is not overflowed
1: RXFIFO is overflowed
7 / / /
TX_FULL
TXFIFO Full
6 R/W1C 0x0 This bit is set when the TXFIFO is full. Writing 1 to this bit clears it.
0: TXFIFO is not Full
1: TXFIFO is Full
TX_EMP
TXFIFO Empty
This bit is set when the TXFIFO is empty. Writing 1 to this bit clears
5 R/W1C 0x1
it.
0: TXFIFO contains one or more words.
1: TXFIFO is empty
TX_READY
TXFIFO Ready
0: TX_WL > TX_TRIG_LEVEL
4 R/W1C 0x1 1: TX_WL <= TX_TRIG_LEVEL
This bit will be immediately set to 1 if TX_WL <= TX_TRIG_LEVEL.
Writing “1” to this bit clears it. The TX_WL is the water level of
TXFIFO.
3 / / /
RX_FULL
RXFIFO Full
2 R/W1C 0x0 This bit is set when the RXFIFO is full. Writing 1 to this bit clears it.
0: Not Full
1: Full
RX_EMP
RXFIFO Empty
This bit is set when the RXFIFO is empty. Writing 1 to this bit clears
1 R/W1C 0x1
it.
0: Not empty
1: empty
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Offset: 0x0014 Register Name: SPI_ISR
Bit Read/Write Default/Hex Description
RX_RDY
RXFIFO Ready
0: RX_WL < RX_TRIG_LEVEL
0 R/W1C 0x0 1: RX_WL >= RX_TRIG_LEVEL
This bit will be immediately set to 1 if RX_WL >= RX_TRIG_LEVEL.
Writing “1” to this bit clears it. The RX_WL is the water level of
RXFIFO.
9.4.6.5 0x0018 SPI FIFO Control Register (Default Value: 0x0040_0001)
Offset: 0x0018 Register Name: SPI_FCR
Bit Read/Write Default/Hex Description
TX_FIFO_RST
TX FIFO Reset
31 R/WAC 0x0 Writing ‘1’ to this bit will reset the control portion of the TXFIFO
and auto clear to ‘0’ when completing the reset operation, writing
‘0’ to this bit has no effect.
TF_TEST_ENB
TX Test Mode Enable
0: Disable
1: Enable
30 R/W 0x0 In normal mode, the TXFIFO can only be read by the SPI controller,
writing ‘1’ to this bit will switch the read and write function of
TXFIFO to AHB bus. This bit is used to test the TXFIFO, do not set in
normal operation, and do not set RF_TEST and TF_TEST at the
same time.
29:25 / / /
TF_DRQ_EN
TX FIFO DMA Request Enable
24 R/W 0x0
0: Disable
1: Enable
TX_TRIG_LEVEL
23:16 R/W 0x40
TX FIFO Empty Request Trigger Level
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Offset: 0x0018 Register Name: SPI_FCR
Bit Read/Write Default/Hex Description
RF_RST
RXFIFO Reset
15 R/WAC 0x0 Writing ‘1’ to this bit will reset the control portion of the receiver
FIFO, and auto clear to ‘0’ when completing the reset operation,
writing ‘0’ to this bit has no effect.
RF_TEST
RX Test Mode Enable
0: Disable
1: Enable
14 R/W 0x0 In normal mode, the RXFIFO can only be written by the SPI
controller, writing ‘1’ to this bit will switch the read and write
function of RXFIFO to AHB bus. This bit is used to test the RXFIFO,
do not set in normal operation, and do not set RF_TEST and
TF_TEST at the same time.
13:9 / / /
RF_DRQ_EN
RXFIFO DMA Request Enable
8 R/W 0x0
0: Disable
1: Enable
RX_TRIG_LEVEL
7:0 R/W 0x1
RXFIFO Ready Request Trigger Level
9.4.6.6 0x001C SPI FIFO Status Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: SPI_FSR
Bit Read/Write Default/Hex Description
TB_WR
31 R 0x0
TXFIFO Write Buffer Write Enable
TB_CNT
30:28 R 0x0 TXFIFO Write Buffer Counter
These bits indicate the number of words in TXFIFO Write Buffer
27:24 / / /
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Offset: 0x001C Register Name: SPI_FSR
Bit Read/Write Default/Hex Description
TF_CNT
TXFIFO Counter
These bits indicate the number of words in TXFIFO
0: 0 byte in TXFIFO
23:16 R 0x0
1: 1 byte in TXFIFO
…
64: 64 bytes in TXFIFO
other: Reserved
RB_WR
15 R 0x0
RXFIFO Read Buffer Write Enable
RB_CNT
14:12 R 0x0 RXFIFO Read Buffer Counter
These bits indicate the number of words in RXFIFO Read Buffer
11:8 / / /
RF_CNT
RXFIFO Counter
These bits indicate the number of words in RXFIFO
0: 0 byte in RXFIFO
7:0 R 0x0
1: 1 byte in RXFIFO
…
64: 64 bytes in RXFIFO
other: Reserved
9.4.6.7 0x0020 SPI Wait Clock Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: SPI_WCR
Bit Read/Write Default/Hex Description
31:20 / / /
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Offset: 0x0020 Register Name: SPI_WCR
Bit Read/Write Default/Hex Description
SWC
Dual mode direction switch wait clock counter (for master mode
only).
These bits control the number of wait states to be inserted before
19:16 R/W 0x0 starting dual data transfer in dual SPI mode. The SPI module counts
SPI_SCLK by SWC for delaying the next word data transfer.
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Cannot be written when XCH=1.
WCC
Wait Clock Counter (In master mode)
These bits control the number of wait states to be inserted in data
transfers. The SPI module counts SPI_SCLK by WCC for delaying the
15:0 R/W 0x0
next word data transfer.
0: No wait states inserted
n: n SPI_SCLK wait states inserted
Cannot be written when XCH=1.
9.4.6.8 0x0028 SPI Sample Delay Control Register (Default Value: 0x0000_2000)
Offset: 0x0028 Register Name: SPI_SAMP_DL
Bit Read/Write Default/Hex Description
31:16 / / /
SAMP_DL_CAL_START
Sample Delay Calibration Start
15 R/W 0x0
When set, it indicates that start sample delay chain calibration.
Cannot be written when XCH=1.
SAMP_DL_CAL_DONE
Sample Delay Calibration Done
14 R 0x0 When set, it indicates that the sample delay chain calibration is
done and the result of calibration is shown in SAMP_DL.
Cannot be written when XCH=1.
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Offset: 0x0028 Register Name: SPI_SAMP_DL
Bit Read/Write Default/Hex Description
SAMP_DL
Sample Delay
It indicates the number of delay cells corresponding to the current
card clock. The delay time generated by these delay cells is equal
13:8 R 0x20 to the cycle of the card clock nearly.
Generally, it is necessary to do drive delay calibration when the
card clock is changed.
This bit is valid only when SAMP_DL_CAL_DONE is set.
Cannot be written when XCH=1.
SAMP_DL_SW_EN
Sample Delay Software Enable
7 R/W 0x0 When set, it indicates that enable sample delay specified at
SAMP_DL_SW.
Cannot be written when XCH=1.
6 / / /
SAMP_DL_SW
Sample Delay Software
The relative delay between the clock line and command line, data
5:0 R/W 0x0 lines.
It can be determined according to the value of SAMP_DL, the cycle
of the card clock, and the input timing requirement of the device.
Cannot be written when XCH=1.
9.4.6.9 0x0030 SPI Master Burst Counter Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: SPI_MBC
Bit Read/Write Default/Hex Description
31:24 / / /
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Offset: 0x0030 Register Name: SPI_MBC
Bit Read/Write Default/Hex Description
MBC
Master Burst Counter
In master mode, this field specifies the total burst number which
includes the TXD, RXD, and dummy burst.
23:0 R/W 0x0 0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
9.4.6.10 0x0034 SPI Master Transmit Counter Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: SPI_MTC
Bit Read/Write Default/Hex Description
31:24 / / /
MWTC
Master Write Transmit Counter
In master mode, this field specifies the burst number that should
be sent to TXFIFO before automatically sending dummy bursts. For
saving bus bandwidth, the dummy bursts (all zero bits or all one
23:0 R/W 0x0 bits) are sent by SPI Controller automatically.
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1.
9.4.6.11 0x0038 SPI Master Burst Control Counter Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: SPI_BCC
Bit Read/Write Default/Hex Description
31:30 / / /
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Offset: 0x0038 Register Name: SPI_BCC
Bit Read/Write Default/Hex Description
Quad_EN
Quad_Mode_EN
The Quad mode includes Quad-Input and Quad-Output.
29 R/W 0x0
0: Quad mode disable
1: Quad mode enable
Cannot be written when XCH=1.
DRM
Master Dual Mode RX Enable
It is only valid when Quad_Mode_EN=0.
28 R/W 0x0
0: RX uses the single-bit mode
1: RX uses the dual mode
Cannot be written when XCH=1.
DBC
Master Dummy Burst Counter
In master mode, this field specifies the burst number that should
be sent before receiving in dual SPI mode. The data does not care
by the device.
27:24 R/W 0x0
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1
STC
Master Single Mode Transmit Counter
In master mode, this field specifies the burst number that should
be sent in the single mode before automatically sending dummy
bursts. This is the first transmit counter in all bursts.
23:0 R/W 0x0
0: 0 burst
1: 1 burst
…
N: N bursts
Cannot be written when XCH=1
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9.4.6.12 0x0040 SPI Bit-Aligned Transfer Configure Register (Default Value: 0x0000_00A0)
Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
TCE
Transfer Control Enable
In master mode, it is used to start to transfer the serial bits frame,
it is only valid when Work Mode Select==0x10/0x11.
0: Idle
31 R/WAC 0x0
1: Initiates transfer
Writing “1” to this bit will start to transfer serial bits frame (the
value comes from the SPI TX Bit Register or SPI RX Bit Register), and
will auto-clear after the bursts transfer completely. Writing ‘0’ to
this bit has no effect.
MSMS
Master Sample Standard
0: Delay Sample Mode
1: Standard Sample Mode
30 R/W 0x0 In Standard Sample Mode, the SPI master samples the data at the
standard rising edge of SCLK for each SPI mode;
In Delay Sample Mode, the SPI master samples data at the edge
that is half cycle delayed by the standard rising edge of SCLK
defined in respective SPI mode.
29:26 / / /
TBC
Transfer Bits Completed
When set, this bit indicates that the last bit of the serial data frame
in SPI TX Bit Register (or SPI RX Bit Register) has been transferred
25 R/W1C 0x0
completely. Writing 1 to this bit clears it.
0: Busy
1: Transfer Completed
It is only valid when Work Mode Select==0x10/0x11.
TBC_INT_EN
Transfer Bits Completed Interrupt Enable
24 R/W 0x0 0: Disable
1: Enable
It is only valid when Work Mode Select==0x10/0x11.
23:22 / / /
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Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
RX_FEM_LEN
Configure the length of serial data frame (burst) of RX
000000: 0 bit
000001: 1 bit
21:16 R/W 0x00 …
100000: 32 bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot
be written when TCE (SPI_BATC[31])=1.
15:14 / / /
TX_FEM_LEN
Configure the length of serial data frame (burst) of TX
000000: 0 bit
000001: 1 bit
13:8 R/W 0x00 …
100000: 32 bits
Other values: reserved
It is only valid when Work Mode Select==0x10/0x11, and cannot
be written when TCE=1.
SS_LEVEL
When control SS signal manually, set this bit to ‘1’ or ‘0’ to control
the level of SS signal.
7 R/W 0x1 0: Set SS to low
1: Set SS to high
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE=1.
SS_OWNER
SS Output Owner Select
Usually, the controller sends the SS signal automatically with data
together. When this bit is set to 1, the software must manually
write SS_LEVEL (SPI_BATC[7]) to 1 or 0 to control the level of the
6 R/W 0x0
SS signal.
0: SPI controller
1: Software
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE=1.
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Offset: 0x0040 Register Name: SPI_BATC
Bit Read/Write Default/Hex Description
SPOL
SPI Chip Select Signal Polarity Control
0: Active high polarity (0 = Idle)
5 R/W 0x1
1: Active low polarity (1 = Idle)
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE=1.
4 / / /
SS_SEL
SPI Chip Select
Select one of four external SPI Master/Slave Devices
00: SPI_SS0 will be asserted
3:2 R/W 0x0 01: SPI_SS1 will be asserted
10: SPI_SS2 will be asserted
11: SPI_SS3 will be asserted
It is only valid when Work Mode Select==0x10/0x11, and only work
in Mode0, cannot be written when TCE=1.
WMS
Work Mode Select
00: Data frame is byte aligned in standard SPI, dual-output/dual
1:0 R/W 0x0 input SPI, dual IO SPI, and quad-output/quad-input SPI
01: Reserved
10: Data frame is bit aligned in 3-wire SPI
11: Data frame is bit aligned in standard SPI
9.4.6.13 0x0044 SPI Bit-Aligned Clock Configuration Register (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: SPI_BA_CCR
Bit Read/Write Default/Hex Description
31:8 / / /
CDR_N
Clock Divide Rate (Master Mode Only)
7:0 R/W 0x0 The SPI_SCLK is determined according to the following equation:
SPI_CLK = Source_CLK / (2*(CDR_N + 1)).
This register is only valid when Work Mode Select==0x10/0x11.
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9.4.6.14 0x0048 SPI TX Bit Register (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: SPI_TBR
Bit Read/Write Default/Hex Description
VTB
The Value of the Transmit Bits
This register is used to store the value of the transmitted serial data
31:0 R/W 0x0
frame.
In the process of transmission, the LSB is transmitted first.
This register is only valid when Work Mode Select==0x10/0x11.
9.4.6.15 0x004C SPI RX Bit Register (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: SPI_RBR
Bit Read/Write Default/Hex Description
VRB
The Value of the Receive Bits
This register is used to store the value of the received serial data
31:0 R/W 0x0
frame.
In the process of transmission, the LSB is transmitted first.
This register is only valid when Work Mode Select==0x10/0x11.
9.4.6.16 0x0088 SPI Normal DMA Mode Control Register (Default Value: 0x0000_00E5)
Offset: 0x0088 Register Name: SPI_NDMA_MODE_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
SPI_ACT_M
SPI NDMA Active Mode
00: dma_active is low
7:6 R/W 0x11
01: dma_active is high
10: dma_active is controlled by dma_request (DRQ)
11: dma_active is controlled by controller
SPI_ACK_M
SPI NDMA Acknowledge Mode
5 R/W 0x1
0: active fall do not care ack
1: active fall must after detect ack is high
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Offset: 0x0088 Register Name: SPI_NDMA_MODE_CTL
Bit Read/Write Default/Hex Description
SPI_DMA_WAIT
Delay Cycles
4:0 R/W 0x05
The counts of hold cycles from DMA last signal high to dma_active
high
9.4.6.17 0x0100 DBI Control Register 0 (Default Value: 0x0010_0000)
Offset: 0x0100 Register Name: DBI_CTL_0
Bit Read/Write Default/Hex Description
CMDT
Command Type
31 R/W 0x0
0: Write Command
1: Read Command
WCDC
Write Command Dummy Cycles
Controls dummy cycles between two write commands
30:20 R/W 0x1
Range 1~255
Default Condition: there is a dbi_clk cycle between each command
or parameter.
DAT_SEQ
Output Data Sequence
19 R/W 0x0
0: MSB First
1: LSB First
RGB_SEQ
Output RGB Sequence
000: RGB
001: RBG
18:16 R/W 0x0 010: GRB
011: GBR
100: BRG
101: BGR
110, 111: Reserved
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Offset: 0x0100 Register Name: DBI_CTL_0
Bit Read/Write Default/Hex Description
TRAN_MOD
Transmit Mode
15 R/W 0x0
0: Command/Parameter
1: Video
DAT_FMT
Output Data Format
000: RGB111
001: RGB444
14:12 R/W 0x0
010: RGB565
011: RGB666
100: RGB888 (only for 2 Data Lane Interface)
101~111: Reserved
11 / / /
DBI Interface
000: 3 Line Interface I
001: 3 Line Interface II
10:8 R/W 0x0
010: 4 Line Interface I
011: 4 Line Interface II
100: 2 Data Lane Interface
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Offset: 0x0100 Register Name: DBI_CTL_0
Bit Read/Write Default/Hex Description
RGB_Source_Format
When video_source_type is RGB32 (DBI_CTL_0[bit0] = 0)
0000: RGB
0001: RBG
0010: GRB
0011: GBR
0100: BRG
0101: BGR
Others: Reserved
7:4 R/W 0x0
When video_source_type is RGB16 (DBI_CTL_0[bit0] = 1)
0000: RGB
0001~0100: Reserved
0101: BGR
0110: GRBG_0 {G[5:3]R[4:0]B[4:0]G[2:0]}
0111: GBRG_0 {G[5:3]B[4:0]R[4:0]G[2:0]}
1000: GRBG_1 {G[2:0]R[4:0]B[4:0]G[5:3]}
1001: GBRG_1 {G[2:0]B[4:0]R[4:0]G[5:3]}
Others: Reserved
DUM_VAL
3 R/W 0x0 Dummy Cycle Value
Output Value During Dummy Cycle
RGB_BO
RGB Bit Order
2 R/W 0x0 0: Remain the sequence of RGB data
1: Swap the higher bit and the lower bit for each component of
DRAM RGB
ELEMENT_A_POS
Element A Position
1 R/W 0x0 Only for RGB32 Data Format
0: A component is in the bit[31:24] of data source
1: A component is in the bit[7:0] of data source
VI_SRC_TYPE
Video Source Type
0 R/W 0x0
0: RGB32
1: RGB16
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9.4.6.18 0x0104 DBI Control Register 1 (Default Value: 0x0000_0001)
Offset: 0x0104 Register Name: DBI_CTL_1
Bit Read/Write Default/Hex Description
DBI_SOFT_TRG
DBI soft trigger
31 R/WAC 0x0 It is only available for software trigger mode. Writing ‘1’ to this bit
will start DBI TX module and auto clear to ‘0’ when completing start
operation, writing ‘0’ to this bit has no effect.
DBI EN MODE SEL
DBI Enable Mode Select
00: Always on DBI mode
30:29 R/W 0x0
01: Software trigger mode
10: Timer trigger mode
11: TE trigger mode
28 / / /
RGB666_FMT
2 Data Lane RGB666 Format
27:26 R/W 0x0 00: Normal Format
01: Special Format for ILITEK
10: Special Format for New Vision
DBI_RXCLK_INV
DBI rx clock inverse
25 R/W 0x0
0: Sample data by using the positive edge of the output clock
1: Sample data by using the negative edge of the output clock
DBI_CLKO_MOD
DBI output clock mode
24 R/W 0x0 0: DBI clock always on (DCX Setup/hold equals one clock cycle)
1: DBI clock auto gating (DCX Setup/hold equals to a half clock
cycle)
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Offset: 0x0104 Register Name: DBI_CTL_1
Bit Read/Write Default/Hex Description
DBI_CLKO_INV
DBI clock output inverse
When the bit24 (DBI output clock mode) is 0.
0: The falling edge releases the CSX signal, and the falling edge
releases data
1: The rising edge releases the CSX signal, and the rising edge
23 R/W 0x0
releases data
When the bit24 (DBI output clock mode) is 1.
0: The rising edge releases the CSX signal, and the falling edge
releases data
1: The falling edge releases the CSX signal, and the rising edge
releases data
DCX_DATA
DCX Data Value
22 R/W 0x0
0: DCX Value equal to 0
1: DCX Value equal to 1
RGB 16 Data Source Select
RGB 16 Data Source Select
0: Pixel1 is stored in the higher bit of address, and Pixel0 is stored
21 R/W 0x0
in the lower bit of address
1: Pixel0 is stored in the higher bit of address, and Pixel1 is stored
in the lower bit of address
RDAT_LSB
Bit Order of Read Data
20 R/W 0x0
0: A reading data is the higher bit
1: A reading data is the lower bit
19:16 / / /
RCDC
Read Command Dummy Cycles
15:8 R/W 0x0
The dummy cycle between the read command and read data
Reading 1-byte (8 bits) data has not dummy cycle.
RDBN
7:0 R/W 0x1 Read Data Number of Bytes
Sample Bytes data based on configuration.
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9.4.6.19 0x0108 DBI Control Register 2 (Default Value: 0x0000_4000)
Offset: 0x0108 Register Name: DBI_CTL_2
Bit Read/Write Default/Hex Description
31:26 / / /
DBI_FIFO_DRQ_EN
DBI FIFO DMA Request Enable
15 R/W 0x0
0: Disable
1: Enable
DBI_TRIG_LEVEL
14:8 R/W 0x40
DBI FIFO Empty Request Trigger Level
7 / / /
DBI_SDI_OUT_SEL
DBI SDI PIN Output Select
The signal is used with the DBI SDI PIN Function Sel bit.
6 R/W 0x0
0: Output WRX (When DBI DCX PIN Function Sel = 0, the SDI pin
outputs data)
1: Output DCX
DBI_DCX_SEL
DBI DCX PIN Function Select
5 R/W 0x0
0: DBI DCX Function
1: WRX (2 Data Lane Interface)
DBI_SDI_SEL
DBI SDI PIN Function Select
00: DBI_SDI (Interface II)
4:3 R/W 0x0
01: DBI_TE
10: DBI_DCX
11: Reserved
TE_DBC_SEL
TE debounce function select
2 R/W 0x0
0: debounce
1: no-debounce
TE_TRIG_SEL
TE edge trigger select
1 R/W 0x0
0: TE rising edge
1: TE falling edge
TE_EN
TE enable
0 R/W 0x0
0: TE Disable
1: TE Enable
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9.4.6.20 0x010C DBI Timer Control Register (Default Value: 0x0000_0000)
Offset: 0x010C Register Name: DBI_Timer
Bit Read/Write Default/Hex Description
DBI_TM_EN
DBI Timer Enable
31 R/W 0x0
0: Enable
1: Disable
DBI Timer Value
It sets the time interval between sending data twice, which is
frame blanking.
It is used to set the time at which the interrupt of the DBI Timer is
30:0 R/W 0x0 triggered. When the Timer_EN is 1, the timer starts to count (the
clock of the counting is SCLK), and the counter reaches the target
value to trigger the Timer_INT of DBI, the data will start to send in
series.
Note: Do not count when sending the series data.
9.4.6.21 0x0110 DBI Video Size Register (Default Value: 0x01E0_0140)
Offset: 0x0110 Register Name: DBI_Video_Size
Bit Read/Write Default/Hex Description
31:27 / / /
V_SIZE
26:16 R/W 0x1E0
It is used to generate the Frame int.
15:11 / / /
H_SIZE
10:0 R/W 0x140
It is used to generate the Line int.
9.4.6.22 0x0120 DBI Interrupt Register (Default Value: 0x0000_4000)
Offset: 0x0120 Register Name: DBI_INT
Bit Read/Write Default/Hex Description
31:15 / / /
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Offset: 0x0120 Register Name: DBI_INT
Bit Read/Write Default/Hex Description
DBI_FIFO_EMPTY_INT
DBI FIFO Empty Interrupt Status
14 R/W1C 0x1
0: DBI_FIFO is not empty
1: DBI_FIFO is empty
DBI_FIFO_FULL_INT
DBI FIFO Full Interrupt Status
13 R/W1C 0x0
0: DBI_FIFO is not full
1: DBI_FIFO is full
TIMER_INT
It indicates that the timer has been count sclk cycles to the value
12 R/W1C 0x0 of DBI_Timer Register[30:0]. Writing 1 to this bit clears it.
0: Timer has not been achieved the objective
1: Timer has been achieved the objective
RD_DONE_INT
It indicates that the number of byte setting in DBI_Control
11 R/W1C 0x0 Register 1[19:8] has been read. Writing 1 to this bit clears it.
0: All data has not been read
1: All data has been read
TE_INT
It indicates that the TE signal has been changed. Writing 1 to this
10 R/W1C 0x0 bit clears it.
0: TE signal has not been changed
1: TE signal has been changed
FRAM_DONE_INT
It indicates that a frame video data has been sent. Writing 1 to this
9 R/W1C 0x0 bit clears it.
0: A frame video has not been sent
1: A frame video has been sent
LINE_DONE_INT
It indicates that a line of video data has been sent. Writing 1 to
8 R/W1C 0x0 this bit clears it.
0: A line of video data has not been sent
1: A line of video data has been sent
7 / / /
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Offset: 0x0120 Register Name: DBI_INT
Bit Read/Write Default/Hex Description
DBI_FIFO_EMPTY_INT_EN
DBI FIFO Empty Interrupt Enable
6 R/W 0x0
0: Disable
1: Enable
DBI_FIFO_FULL_INT_EN
DBI FIFO Full Interrupt Enable
5 R/W 0x0
0: Disable
1: Enable
TIMER_INT_EN
Timer Interrupt Enable
4 R/W 0x0
0: Disable
1: Enable
RD_DONE_INT_EN
Read Done Interrupt Enable
3 R/W 0x0
0: Disable
1: Enable
TE_INT_EN
TE Interrupt Enable
2 R/W 0x0
0: Disable
1: Enable
FRAM_DONE_INT_EN
Frame Done Interrupt Enable
1 R/W 0x0
0: Disable
1: Enable
LINE_DONE_INT_EN
Line Done Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
9.4.6.23 0x0124 DBI Debug Register 0 (Default Value: 0x007F_0000)
Offset: 0x0124 Register Name: DBI_Debug_0
Bit Read/Write Default/Hex Description
31:23 / / /
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Offset: 0x0124 Register Name: DBI_Debug_0
Bit Read/Write Default/Hex Description
DBI_FIFO_AVAIL
22:16 R 0x7F DBI_FIFO ROOM VALID
0~127 Words
15:13 / / /
TE_VAL
TE input value
12 R 0x0
0: TE not Trigger
1: TE Trigger
DBI_RXCS
11:8 R 0x0 FSM for DBI Receive
RX_BS0 ~ RX_BS6 , Gray - Code
SH_CS
7:4 R 0x0 FSM for shifter
0~11 : SH0~SH11
DBI_TXCS
FSM for DBI Transmit
00: IDLE
3:2 / /
01: SHIF
10: DUMY
11: READ
MEM_CS
FSM for DBI Memory
1:0 R 0x0 00: IDLE_FRM
01: FRM_POS
10: FRM_RDY
9.4.6.24 0x0128 DBI Debug Register 1 (Default Value: 0x0000_0000)
Offset: 0x0128 Register Name: DBI_Debug_1
Bit Read/Write Default/Hex Description
31:26 / / /
LCNT
25:16 R 0x0 Line counter
The number of pixel lines that are currently sent
15:12 / / /
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Offset: 0x0128 Register Name: DBI_Debug_1
Bit Read/Write Default/Hex Description
CCNT
Component counter
11:0 R 0x0
The number of RGB components that are currently sent
The field is equal to pixel_cnt *3.
9.4.6.25 0x0200 SPI TX Data Register (Default Value: 0x0000_0000)
Offset: 0x0200 Register Name: SPI_TXD
Bit Read/Write Default/Hex Description
TDATA
Transmit Data
This register can be accessed in the byte, half-word, or word unit by
AHB. In the byte accessing method, if there are rooms in TXFIFO,
one burst data is written to TXFIFO and the depth is increased by 1.
In the half-word accessing method, two SPI burst data are written
31:0 R/W 0x0
and the TXFIFO depth is increased by 2. In the word accessing
method, four SPI burst data are written and the TXFIFO depth is
increased by 4.
Note: This address is writable-only if TF_TEST is ‘0’, and if TF_TEST
is set to ‘1’, this address is readable and writable to test the TX
FIFO through the AHB bus.
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9.4.6.26 0x0300 SPI RX Data Register (Default Value: 0x0000_0000)
Offset: 0x0300 Register Name: SPI_RXD
Bit Read/Write Default/Hex Description
RDATA
Receive Data
This register can be accessed in the byte, half-word, or word unit
by AHB. In the byte accessing method, if there are data in RXFIFO,
the top word is returned and the RXFIFO depth is decreased by 1.
In the half-word accessing method, two SPI bursts are returned and
31:0 R 0x0
the RXFIFO depth is decreased by 2. In the word accessing method,
the four SPI bursts are returned and the RXFIFO depth is decreased
by 4.
Note: This address is readable-only if RF_TEST is ‘0’, and if RF_TEST
is set to ‘1’, this address is readable and writable to test the RX
FIFO through the AHB bus.
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9.5 USB2.0 DRD
9.5.1 Overview
The USB2.0 dual-role device (USB2.0 DRD) supports both device and host functions which can also be
configured as a Host-only or Device-only controller. It complies with the USB2.0 Specification.
For saving CPU bandwidth, the DMA interface of the DRD module can also support the external DMA controller
to do the data transfer between the memory and the DRD FIFO. The DRD core also supports USB power saving
functions.
The USB2.0 DRD has the following features:
Complies with USB2.0 Specification
Supports USB Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s), and Low-Speed (LS, 1.5 Mbit/s)
- Supports only 1 USB Root port shared between EHCI and OHCI
Supports USB Device function
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s)
- Supports bi-directional endpoint0 (EP0) for Control transfer
- Up to 10 user-configurable endpoints (EP1+, EP1-, EP2+, EP2-, EP3+, EP3-, EP4+, EP4-, EP5+, EP5-) for
Bulk transfer, Isochronous transfer and Interrupt transfer
- Up to (8 KB + 64 Bytes) FIFO for all EPs (including EP0)
- Supports interface to an external Normal DMA controller for every EP
Supports an internal DMA controller for data transfer with memory
Supports High-Bandwidth Isochronous & Interrupt transfers
Automated splitting/combining of packets for Bulk transfers
Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral modes
Includes automatic ping capabilities
Soft connect/disconnect function
Performs all transaction scheduling in hardware
Power optimization and power management capabilities
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Device and host controller share a 8K SRAM and a physical PHY
9.5.2 Block Diagram
The following figure shows the block diagram of USB2.0 DRD Controller.
Figure 9-63 USB2.0 DRD Controller Block Diagram
USB2.0 DRD
Device AHB Slave Interface
Host AHB Slave Interface USB2.0
Device
Host Master Interface
DM0 & DP0
Device EP DRQ PHY
Device IRQ
USB2.0
EHCI IRQ Host
OHCI IRQ
9.5.3 Functional Description
9.5.3.1 External Signals
Table 9-18 USB2.0 DRD External Signals
Signal Description Type
USB0-DP USB2.0 DRD differential signal positive AI/O
USB0-DM USB2.0 DRD differential signal negative AI/O
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9.5.3.2 Controller and PHY Connection Diagram
Figure 9-64 USB2.0 DRD Controller and PHY Connection Diagram
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9.6 USB2.0 HOST
9.6.1 Overview
The USB Host Controller is fully compliant with USB 2.0 Specification, Enhanced Host Controller Interface (EHCI)
Specification Revision 1.0 and Open Host Controller Interface (OHCI) Specification Release 1.0a.
The USB2.0 host controller includes the following features:
Complies with USB2.0 Specification
Supports USB2.0 Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) and Low-Speed (LS, 1.5 Mbit/s)
Device
- Supports only 1 USB Root port shared between EHCI and OHCI
An internal DMA Controller for data transfer with memory
9.6.2 Block Diagram
The following figure shows the block diagram of USB2.0 Host Controller.
Figure 9-65 USB2.0 Host Controller Block Diagram
USB2.0 Host
Host1 AHB Slave Interface
Host1 Master Interface
USB DM1 & DP1
EHCI1 IRQ UTMI PHY1
Host1
OHCI1 IRQ
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9.6.3 Functional Description
9.6.3.1 External Signals
Table 9-19 USB2.0 Host External Signals
Signal Description Type
USB1-DP USB2.0 Host differential signal positive AI/O
USB1-DM USB2.0 Host differential signal negative AI/O
9.6.3.2 Controller and PHY Connection Diagram
Figure 9-66 USB2.0 Host Controller and PHY Connection Diagram
VDD-SYS VCC-IO
SIE Control
Register
DP
USB
OHCI SCLK PHY DM
Gating 48M
Device
DCXO24M MUL FS/LS
12M OHCI
DIV
PLL_PERIPH
PHY Reset/Gating
OHCI Reset/Gating DCXO24M
9.6.4 Register List
Module Name Base Address
USB1 0x04200000
Register Name Offset Description
EHCI Capability Register
E_CAPLENGTH 0x0000 EHCI Capability Register Length Register
E_HCIVERSION 0x0002 EHCI Host Interface Version Number Register
E_HCSPARAMS 0x0004 EHCI Host Control Structural Parameter Register
E_HCCPARAMS 0x0008 EHCI Host Control Capability Parameter Register
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Register Name Offset Description
E_HCSPPORTROUTE 0x000C EHCI Companion Port Route Description
EHCI Operational Register
E_USBCMD 0x0010 EHCI USB Command Register
E_USBSTS 0x0014 EHCI USB Status Register
E_USBINTR 0x0018 EHCI USB Interrupt Enable Register
E_FRINDEX 0x001C EHCI USB Frame Index Register
E_CTRLDSSEGMENT 0x0020 EHCI 4G Segment Selector Register
E_PERIODICLISTBASE 0x0024 EHCI Frame List Base Address Register
E_ASYNCLISTADDR 0x0028 EHCI Next Asynchronous List Address Register
E_CONFIGFLAG 0x0050 EHCI Configured Flag Register
E_PORTSC 0x0054 EHCI Port Status/Control Register
OHCI Control and Status Partition Register
O_HcControl 0x0404 OHCI Control Register
O_HcCommandStatus 0x0408 OHCI Command Status Register
O_HcInterruptStatus 0x040C OHCI Interrupt Status Register
O_HcInterruptEnable 0x0410 OHCI Interrupt Enable Register
O_HcInterruptDisable 0x0414 OHCI Interrupt Disable Register
OHCI Memory Pointer Partition Register
O_HcHCCA 0x0418 OHCI HCCA Base
O_HcPeriodCurrentED 0x041C OHCI Period Current ED Base
O_HcControlHeadED 0x0420 OHCI Control Head ED Base
O_HcControlCurrentED 0x0424 OHCI Control Current ED Base
O_HcBulkHeadED 0x0428 OHCI Bulk Head ED Base
O_HcBulkCurrentED 0x042C OHCI Bulk Current ED Base
O_HcDoneHead 0x0430 OHCI Done Head Base
OHCI Frame Counter Partition Register
O_HcFmInterval 0x0434 OHCI Frame Interval Register
O_HcFmRemaining 0x0438 OHCI Frame Remaining Register
O_HcFmNumber 0x043C OHCI Frame Number Register
O_HcPerioddicStart 0x0440 OHCI Periodic Start Register
O_HcLSThreshold 0x0444 OHCI LS Threshold Register
OHCI Root Hub Partition Register
O_HcRhDescriptorA 0x0448 OHCI Root Hub Descriptor Register A
O_HcRhDesriptorB 0x044C OHCI Root Hub Descriptor Register B
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Register Name Offset Description
O_HcRhStatus 0x0450 OHCI Root Hub Status Register
O_HcRhPortStatus 0x0454 OHCI Root Hub Port Status Register
HCI Controller and PHY Interface Register
HCI_Interface 0x0800 HCI Interface Register
HCI_CTRL3 0x0808 HCI Control Register
PHY_Control 0x0810 PHY Control Register
PHY_STATUS 0x0824 PHY Status Register
HCI SIE Port Disable Control 0x0828 HCI SIE Port Disable Control Register
9.6.5 EHCI Register Description
9.6.5.1 0x0000 EHCI Identification Register (Default Value:0x10)
Offset:0x0000 Register Name: CAPLENGTH
Bit Read/Write Default/Hex Description
CAPLENGTH
7:0 R 0x10 The value in these bits indicates an offset to add to register base to
find the beginning of the Operational Register Space.
9.6.5.2 0x0002 EHCI Host Interface Version Number Register (Default Value:0x0100)
Offset: 0x0002 Register Name: HCIVERSION
Bit Read/Write Default/Hex Description
HCIVERSION
This is a 16-bit register containing a BCD encoding of the EHCI
15:0 R 0x0100 revision number supported by this host controller. The most
significant byte of this register represents a major revision and the
least significant byte is the minor revision.
9.6.5.3 0x0004 EHCI Host Control Structural Parameter Register (Default Value:0x0000_1101)
Offset: 0x0004 Register Name: HCSPARAMS
Bit Read/Write Default/Hex Description
31:24 / / /
23:20 R 0x0 Debug Port Number
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Offset: 0x0004 Register Name: HCSPARAMS
Bit Read/Write Default/Hex Description
This register identifies which of the host controller ports is the
debug port. The value is the port number (one based) of the debug
port.
This field will always be ‘0’.
19:16 / / /
Number of Companion Controller (N_CC)
This field indicates the number of companion controllers
associated with this USB2.0 host controller. A zero in this field
15:12 R 0x1 indicates there are no companion host controllers. And a value
larger than zero in this field indicates there are companion USB1.1
host controller(s).
This field will always be ‘0’.
Number of Port per Companion Controller (N_PCC)
This field indicates the number of ports supported per companion
11:8 R 0x1 host controller host controller. It is used to indicate the port
routing configuration to system software.
This field will always fix with ‘0’.
Port Routing Rules
This field indicates the method used by this implementation for
how all ports are mapped to companion controllers. The value of
this field has the following interpretation:
Value Meaning
0 The first N_PCC ports are routed to the lowest
7 R 0x0
numbered function companion host controller, the
next N_PCC port are routed to the next lowest
function companion controller, and so on.
1 The port routing is explicitly enumerated by the first
N_PORTS elements of the HCSP-PORTTOUTE array.
This field will always be ‘0’.
6:4 / / /
N_PORTS
This field specifies the number of physical downstream ports
implemented on this host controller. The value of this field
3:0 R 0x1 determines how many port registers are addressable in the
Operational Register Space. Valid values are in the range of 0x1 to
0x0f.
This field is always 1.
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9.6.5.4 0x0008 EHCI Host Control Capability Parameter Register (Default Value:0x0000_A026)
Offset: 0x0008 Register Name: HCCPARAMS
Bit Read/Write Default/Hex Description
31:16 / / /
EHCI Extended Capabilities Pointer (EECP)
This optional field indicates the existence of a capabilities list. A
value of 00b indicates no extended capabilities are implemented.
A non-zero value in this register indicates the offset in PCI
15:8 R 0xA0
configuration space of the first EHCI extended capabiliby. The
pointer value must be 40h or greater if implemented to maintain
to consistency of the PCI header defined for this calss of device.
The value of this field is always ‘00b’.
Isochronous Scheduling Threshold
This field indicates, relative to the current position of the executing
host controller, where software can reliably update the
isochronous schedule.
When bit[7] is zero, the value of the least significant 3 bits indicates
7:4 R 0x2
the number of micro-frames a host controller can hold a set of
isochronous data structures(one or more) before flushing the
state. When bit[7] is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire
frame.
3 / / /
Asynchronous Schedule Park Capability
If this bit is set to a one, then the host controller supports the park
feature for high-speed queue heads in the Asynchronous Schedule.
2 R 0x1 The feature can be disabled or enabled and set to a specific level
by using the Asynchronous Schedule Park Mode Enable and
Asynchronous Schedule Park Mode Count fields in the USBCMD
register.
Programmable Frame List Flag
If this bit is set to a zero, then system software must use a frame
list length of 1024 elements with this host controller. The USBCMD
register Frame List Size field is a read-only register and should be
set to zero.
1 R 0x1 If set to 1, then system software can specify and use the frame list
in the USBCMD register Frame List Size field to cofigure the host
controller.
The frame list must always aligned on a 4K page boundary. This
requirement ensures that the frame list is always physically
contiguous.
0 / / /
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9.6.5.5 0x000C EHCI Companion Port Route Description (Default Value:0x0000_0000)
Offset: 0x000C Register Name: HCSP-PORTROUTE
Bit Read/Write Default/Hex Description
HCSP-PORTROUTE
This optional field is valid only if Port Routing Rules field in
HCSPARAMS register is set to a one.
This field is used to allow a host controller implementation to
explicitly describe to which companion host controller each
implemented port is mapped. This field is a 15-element nibble
array (each 4 bit is one array element). Each array location
31:0 corresponds one-to-one with a physical port provided by the host
R 0x0
controller (e.g. PORTROUTE [0] corresponds to the first PORTSC
port, PORTROUTE [1] to the second PORTSC port, etc.). The value
of each element indicates to which the companion host controllers
this port is routed. Only the first N_PORTS elements have valid
information. A value of zero indicates that the port is routed to the
lowest numbered function companion host controller. A value of
one indicates that the port is routed to the next lowest numbered
function companion host controller, and so on.
9.6.5.6 0x0010 EHCI USB Command Register (Default Value:0x0008_0B00)
Offset: 0x0010 Register Name: USBCMD
Bit Read/Write Default/Hex Description
31:24 / / /
Interrupt Threshold Control
The value in this field is used by system software to select the
maximum rate at which the host controller will issue interrupts.
The only valid values are defined below:
Value Minimum Interrupt Interval
0x00 Reserved
23:16 R/W 0x08 0x01 1 micro-frame
0x02 2 micro-frame
0x04 4 micro-frame
0x08 8 micro-frame(default, equates to 1 ms)
0x10 16 micro-frame(2ms)
0x20 32 micro-frame(4ms)
0x40 64 micro-frame(8ms)
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Offset: 0x0010 Register Name: USBCMD
Bit Read/Write Default/Hex Description
Any other value in this register yields undefined results.
The default value in this field is 0x08 .
Software modifications to this bit while HC Halted bit is equal to
zero results in undefined behavior.
15:12 / / /
Asynchronous Schedule Park Mode Enable (OPTIONAL)
If the Asynchronous Park Capability bit in the HCCPARAMS register
is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit
11 R 0x1
must be a zero and is Read Only. Software uses this bit to enable
or disable Park mode. When this bit is one, Park mode is enabled.
When this bit is zero, Park mode is disabled.
10 / / /
Asynchronous Schedule Park Mode Count (OPTIONAL)
Asynchronous Park Capability bit in the HCCPARAMS register is a
one, then this field defaults to 0x3 and is W/R. Otherwise it
defaults to zero and is R. It contains a count of the number of
successive transactions the host controller is allowed to execute
9:8 R 0x3
from a high-speed queue head on the Asynchronous schedule
before continuing traversal of the Asynchronous schedule.
Valid value are 0x1 to 0x3.Software must not write a zero to this
bit when Park Mode Enable is a one as it will result in undefined
behavior.
Light Host Controller Reset (OPTIONAL)
This control bit is not required.
If implemented, it allows the driver to reset the EHCI controller
without affecting the state of the ports or relationship to the
companion host controllers. For example, the PORSTC registers
7 R/W 0x0 should not be reset to their default values and the CF bit setting
should not go to zero (retaining port ownership relationships).
A host software read of this bit as zero indicates the Light Host
Controller Reset has completed and it si safe for software to re-
initialize the host controller. A host software read of this bit as a
one indicates the Light Host
Interrupt on Async Advance Doorbell
This bit is used as a doorbell by software to tell the host controller
to issue an interrupt the next time it advances asynchronous
6 R/W 0x0 schedule. Software must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached
schedule state, it sets the Interrupt on Async Advance status bit in
the USBSTS. if the Interrupt on Async Advance Enable bit in the
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Offset: 0x0010 Register Name: USBCMD
Bit Read/Write Default/Hex Description
USBINTR register is a one then the host controller will assert an
interrupt at the next interrupt threshold.
The host controller sets this bit to a zero after it has set the
Interrupt on Async Advance status bit in the USBSTS register to a
one.
Software should not write a one to this bit when the asynchronous
schedule is disabled. Doing so will yield undefined results.
Asynchronous Schedule Enable
This bit controls whether the host controller skips processing the
Asynchronous Schedule. Values mean:
Bit Value Meaning
5 R/W 0x0
0 Do not process the Asynchronous Schedule.
Use the ASYNLISTADDR register to access the
1 Asynchronous Schedule.
The default value of this field is ‘0b’.
Periodic Schedule Enable
This bit controls whether the host controller skips processing the
Periodic Schedule. Values mean:
Bit Value Meaning
4 R/W 0x0
0 Do not process the Periodic Schedule.
Use the PERIODICLISTBASE register to access the
1 Periodic Schedule.
The default value of this field is ‘0b’.
Frame List Size
This field is R/W only if Programmable Frame List Flag in the
HCCPARAMS registers is set to a one. This field specifies the size of
the
Frame list. The size the frame list controls which bits in the Frame
Index
Register should be used for the Frame List Current index. Values
3:2 R/W 0x0 mean:
Bits Meaning
00b 1024 elements(4096bytes)Default value
01b 512 elements(2048byts)
10b 256 elements(1024bytes)For resource-constrained
condition
11b reserved
The default value is ‘00b’.
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Offset: 0x0010 Register Name: USBCMD
Bit Read/Write Default/Hex Description
Host Controller Reset
This control bit is used by software to reset the host controller. The
effects of this on Root Hub registers are similar to a Chip Hardware
Reset.
When software writes a one to this bit, the Host Controller resets
its internal pipelines, timers, counters, state machines, etc. to their
initial value. Any transaction currently in progress on USB is
immediately terminated. A USB reset is not driven on downstream
ports.
All operational registers, including port registers and port state
1 R/W 0x0
machines are set to their initial values. Port ownership reverts to
the companion host controller(s). Software must reinitialize the
host controller as described in Section 4.1 of the CHEI Specification
in order to return the host controller to an operational state.
This bit is set to zero by the Host Controller when the reset process
is complete. Software cannot terminate the reset process early by
writing a zero to this register.
Software should not set this bit to a one when the HC Halted bit in
the USBSTS register is a zero. Attempting to reset an actively
running host controller will result in undefined behavior.
Run/Stop
When set to a 1, the Host Controller proceeds with execution of
the schedule. When set to 0, the Host Controller completes the
current and any actively pipelined transactions on the USB and
then halts. The Host Controller must halt within 16 micro-frames
after software clears this bit.
0 R/W 0x0
The HC Halted bit indicates when the Host Controller has finished
its pending pipelined transactions and has entered the stopped
state.
Software must not write a one to this field unless the Host
Controller is in the Halt State.
The default value is 0x0.
9.6.5.7 0x0014 EHCI USB Status Register (Default Value:0x0000_1000)
Offset: 0x0014 Register Name: USBSTS
Bit Read/Write Default/Hex Description
31:16 / / /
15 R 0x0 Asynchronous Schedule Status
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Offset: 0x0014 Register Name: USBSTS
Bit Read/Write Default/Hex Description
The bit reports the current real status of Asynchronous Schedule.
If this bit is a zero then the status of the Asynchronous Schedule is
disabled. If this bit is a one then the status of the Asynchronous
Schedule is enabled. The Host Controller is not required to
immediately disable or enable the Asynchronous Schedule when
software transitions the Asynchronous Schedule Enable bit in the
USBCMD register. When this bit and the Asynchronous Schedule
Enable bit are the same value, the Asynchronous Schedule is either
enabled (1) or disabled (0).
Periodic Schedule Status
The bit reports the current real status of the Periodic Schedule. If
this bit is a zero then the status of the Periodic Schedule is disabled.
If this bit is a one then the status of the Periodic Schedule is
14 R 0x0 enabled. The Host Controller is not required to immediately
disable or enable the Periodic Schedule when software transitions
the Periodic Schedule Enable bit in the USBCMD register. When this
bit and the Periodic Schedule Enable bit are the same value, the
Periodic Schedule is either enabled (1) or disabled (0).
Reclamation
13 R 0x0 This is a read-only status bit, which is used to detect an empty
asynchronous schedule.
HC Halted
This bit is a zero whenever the Run/Stop bit is a one. The Host
Controller Sets this bit to one after it has stopped executing as a
12 R 0x1
result of the Run/Stop bit being set to 0, either by software or by
the Host Controller Hardware (e.g. internal error).
The default value is ‘1’.
11:6 / / /
Interrupt on Async Advance
System software can force the host controller to issue an interrupt
the next time the host controller advances the asynchronous
5 R/WC 0x0
schedule by writing a one to the Interrupt on Async Advance
Doorbell bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Host System Error
The Host Controller set this bit to 1 when a serious error occurs
during a host system access involving the Host Controller module.
4 R/WC 0x0
When this error occurs, the Host Controller clears the Run/Stop bit
in the Command register to prevent further execution of the
scheduled TDs.
3 R/WC 0x0 Frame List Rollover
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Offset: 0x0014 Register Name: USBSTS
Bit Read/Write Default/Hex Description
The Host Controller sets this bit to a one when the Frame List Index
rolls over from its maximum value to zero. The exact value at which
the rollover occurs depends on the frame list size. For example, if
the frame list size is 1024, the Frame Index Register rolls over every
time FRINDEX [13] toggles. Similarly, if the size is 512, the Host
Controller sets this bit to a one every time FRINDEX [12] toggles.
Port Change Detect
The Host Controller sets this bit to a one when any port for which
the Port Owner bit is set to zero has a change bit transition from a
zero to a one or a Force Port Resume bit transition from a zero to
2 R/WC 0x0 a one as a result of a J-K transition detected on a suspended port.
This bit will also be set as a result of the Connect Status Chang
being set to a one after system software has relinquished
ownership of a connected port by writing a one to a port’s Port
Owner bit.
USB Error Interrupt(USBERRINT)
The Host Controller sets this bit to 1 when completion of USB
transaction results in an error condition(e.g. error counter
1 R/WC 0x0
underflow).If the TD on which the error interrupt occurred also
had its IOC bit set, both.
This bit and USBINT bit are set.
USB Interrupt(USBINT)
The Host Controller sets this bit to a one on the completion of a
USB transaction, which results in the retirement of a Transfer
0 R/WC 0x0 Descriptor that had its IOC bit set.
The Host Controller also sets this bit to 1 when a short packet is
detected (actual number of bytes received was less than the
expected number of bytes)
9.6.5.8 0x0018 EHCI USB Interrupt Enable Register (Default Value:0x0000_0000)
Offset: 0x0018 Register Name: USBINTR
Bit Read/Write Default/Hex Description
31:6 / / /
Interrupt on Async Advance Enable
When this bit is 1, and the Interrupt on Async Advance bit in the
5 R/W 0x0 USBSTS register is 1, the host controller will issue an interrupt at
the next interrupt threshold. The interrupt is acknowledged by
software clearing the Interrupt on Async Advance bit.
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Offset: 0x0018 Register Name: USBINTR
Bit Read/Write Default/Hex Description
Host System Error Enable
When this bit is 1, and the Host System Error Status bit in the
4 R/W 0x0 USBSTS register is 1, the host controller will issue an interrupt. The
interrupt is acknowledged by software clearing the Host System
Error bit.
Frame List Rollover Enable
When this bit is 1, and the Frame List Rollover bit in the USBSTS
3 R/W 0x0 register is 1, the host controller will issue an interrupt. The
interrupt is acknowledged by software clearing the Frame List
Rollover bit.
Port Change Interrupt Enable
When this bit is 1, and the Port Chang Detect bit in the USBSTS
2 R/W 0x0 register is 1, the host controller will issue an interrupt. The
interrupt is acknowledged by software clearing the Port Chang
Detect bit.
USB Error Interrupt Enable
When this bit is 1, and the USBERRINT bit in the USBSTS register is
1,the host controller will issue an interrupt at the next interrupt
1 R/W 0x0
threshold.
The interrupt is acknowledged by software clearing the USBERRINT
bit.
USB Interrupt Enable
When this bit is 1, and the USBINT bit in the USBSTS register is 1,the
0 R/W 0x0 host controller will issue an interrupt at the next interrupt
threshold.
The interrupt is acknowledged by software clearing the USBINT bit
9.6.5.9 0x001C EHCI Frame Index Register (Default Value:0x0000_0000)
Offset: 0x001C Register Name: FRINDEX
Bit Read/Write Default/Hex Description
31:14 / / /
Frame Index
The value in this register increment at the end of each time frame
(e.g. micro-frame). Bits[N:3] are used for the Frame List current
13:0 R/W 0 index. It means that each location of the frame list is accessed 8
times (frames or Micro-frames) before moving to the next index.
The following illustrates values of N based on the value of the
Frame List Size field in the USBCMD register.
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Offset: 0x001C Register Name: FRINDEX
Bit Read/Write Default/Hex Description
USBCMD[Frame List Size] Number Elements N
00b 1024 12
01b 512 11
10b 256 10
11b Reserved
NOTE
This register must be written as a DWord. Byte writes produce undefined results.
9.6.5.10 0x0024 EHCI Periodic Frame List Base Address Register (Default Value:0x0000_0000)
Offset: 0x0024 Register Name: PERIODICLISTBASE
Bit Read/Write Default/Hex Description
Base Address
These bits correspond to memory address signals [31:12],
respectively.
This register contains the beginning address of the Periodic Frame
List in the system memory.
31:12 R/W 0x0 System software loads this register prior to starting the schedule
execution by the Host Controller. The memory structure
referenced by this physical memory pointer is assumed to be 4
Kbyte aligned. The contents of this register are combined with the
Frame Index Register (FRINDEX) to enable the Host Controller to
step through the Periodic Frame List in sequence.
11:0 / / /
NOTE
Writes must be Dword Writes.
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9.6.5.11 0x0028 EHCI Current Asynchronous List Address Register (Default Value:0x0000_0000)
Offset: 0x0028 Register Name: ASYNCLISTADDR
Bit Read/Write Default/Hex Description
Link Pointer (LP)
This field contains the address of the next asynchronous queue
31:5 R/W 0x0 head to be executed.
These bits correspond to memory address signals [31:5],
respectively.
4:0 / / /
NOTE
Write must be DWord Writes.
9.6.5.12 0x0050 EHCI Configure Flag Register (Default Value:0x0000_0000)
Offset: 0x0050 Register Name: CONFIGFLAG
Bit Read/Write Default/Hex Description
31:1 / / /
Configure Flag (CF)
Host software sets this bit as the last action in its process of
configuring the Host Controller. This bit controls the default port-
routing control logic as follow:
Value Meaning
0 R/W 0x0
0 Port routing control logic default-routs each port to an
implementation dependent classic host controller.
1 Port routing control logic default-routs all ports to this
host controller.
The default value of this field is ‘0’.
NOTE
This register is not used in the normal implementation.
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9.6.5.13 0x0054 EHCI Port Status and Control Register (Default Value:0x0000_2000)
Offset: 0x0054 Register Name: PORTSC
Bit Read/Write Default/Hex Description
31:22 / / /
Wake on Disconnect Enable (WKDSCNNT_E)
Writing this bit to a one enables the port to be sensitive to device
21 R/W 0x0 disconnects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Wake on Connect Enable (WKCNNT_E)
Writing this bit to a one enable the port to be sensitive to device
20 R/W 0x0 connects as wake-up events.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Port Test Control
The value in this field specifies the test mode of the port. The
encoding of the test mode bits are as follows:
Bits Test Mode
0000b The port is NOT operating in a test mode.
0001b Test J_STATE
19:16 R/W 0x0 0010b Test K_STATE
0011b Test SE0_NAK
0100b Test Packet
0101b Test FORCE_ENABLE
0110b-
1111b Reserved
The default value in this field is ‘0000b’.
15:14 / / /
Port Owner
This bit unconditionally goes to a 0b when the Configured bit in the
CONFIGFLAG register makes a 0b to 1b transition. This bit
unconditionally goes to 1b whenever the Configured bit is zero.
System software uses this field to release ownership of the port to
13 R/W 0x1
selected host controller (in the event that the attached device is
not a high-speed device).Software writes a one to this bit when the
attached device is not a high-speed device. A one in this bit means
that a companion host controller owns and controls the port.
Default Value = 1b.
12 / / /
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Offset: 0x0054 Register Name: PORTSC
Bit Read/Write Default/Hex Description
Line Status
These bits reflect the current logical levels of the D+ (bit11) and D-
(bit10) signal lines. These bits are used for detection of low-speed
USB devices prior to port reset and enable sequence. This read
only field is valid only when the port enable bit is zero and the
current connect status bit is set to a one.
The encoding of the bits are:
Bit[11:10] USB State Interpretation
11:10 R 0x0 00b SE0 Not Low-speed device, perform EHCI
reset.
10b J-state Not Low-speed device, perform EHCI
reset.
01b K-state Low-speed device, release
ownership of port.
11b Undefined Not Low-speed device, perform EHCI
reset.
This value of this field is undefined if Port Power is zero.
9 / / /
Port Reset
1=Port is in Reset. 0=Port is not in Reset. Default value = 0.
When software writes a one to this bit (from a zero), the bus reset
sequence as defined in the USB Specification Revision 2.0 is
started. Software writes a zero to this bit to terminate the bus
reset sequence. Software must keep this bit at a one long enough
to ensure the reset sequence, as specified in the USB Specification
Revision 2.0, completes.
Note: When software writes this bit to a one , it must also write
a zero to the Port Enable bit.
8 R/W 0x0
Note that when software writes a zero to this bit there may be a
delay before the bit status changes to a zero. The bit status will not
read as a zero until after the reset has completed. If the port is in
high-speed mode after reset is complete, the host controller will
automatically enable this port (e.g. set the Port Enable bit to a
one). A host controller must terminate the reset and stabilize the
state of the port within 2 milliseconds of software transitioning this
bit from a one to a zero. For example: if the port detects that the
attached device is high-speed during reset, then the host
controller must have the port in the enabled state with 2ms of
software writing this bit to a zero.
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Offset: 0x0054 Register Name: PORTSC
Bit Read/Write Default/Hex Description
The HC Halted bit in the USBSTS register should be a zero before
software attempts to use this bit. The host controller may hold Port
Reset asserted to a one when the HC Halted bit is a one.
This field is zero if Port Power is zero.
Suspend
Port Enabled Bit and Suspend bit of this register define the port
states as follows:
Bits[Port Enables, Port State
Suspend]
0x Disable
10 Enable
11 Suspend
When in suspend state, downstream propagation of data is
blocked on this port, except for port reset. The blocking occurs at
the end of the current transaction, if a transaction was in progress
when this bit was written to 1. In the suspend state, the port is
7 R/W 0x0
sensitive to resume detection. Not that the bit status does not
change until the port is suspend and that there may be a delay in
suspending a port if there is a transaction currently in progress on
the USB.
A write of zero to this bit is ignored by the host controller. The host
controller will unconditionally set this bit to a zero when:
① Software sets the Force Port Resume bit to a zero(from a one).
② Software sets the Port Reset bit to a one(from a zero).
If host software sets this bit to a one when the port is not
enabled(i.e. Port enabled bit is a zero), the results are undefined.
This field is zero if Port Power is zero.
The default value in this field is ‘0’.
Force Port Resume
1 = Resume detected/driven on port. 0 = No resume (K-state)
detected/driven on port. Default value = 0.
This functionality defined for manipulating this bit depends on the
value of the Suspend bit. For example, if the port is not suspend
and software transitions this bit to a one, then the effects on the
6 R/W 0x0
bus are undefined.
Software sets this bit to 1 to drive resume signaling. The Host
Controller sets this bit to a 1 if a J-to-K transition is detected while
the port is in the Suspend state. When this bit transitions to a one
because a J-to-K transition is detected, the Port Change Detect bit
in the USBSTS register is also set to a one. If software sets this bit
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Offset: 0x0054 Register Name: PORTSC
Bit Read/Write Default/Hex Description
to a one, the host controller must not set the Port Change Detect
bit.
Note that when the EHCI controller owns the port, the resume
sequence follows the defined sequence documented in the USB
Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is
driven on the port as long as this remains a one. Software must
appropriately time the Resume and set this bit to a zero when the
appropriate amount of time has elapsed. Writing a zero (from one)
causes the port to return high-speed mode (forcing the bus below
the port into a high-speed idle). This bit will remain a one until the
port has switched to high-speed idle. The host controller must
complete this transition within 2 milliseconds of software setting
this bit to a zero.
This field is zero if Port Power is zero.
Over-current Change
5 R/WC 0x0 This bit gets set to a one when there is a change to Over-current
Active. Software clears this bit by writing a one to this bit position.
Over-current Active
0 = This port does not have an over-current condition
1 = This port currently has an over-current condition
4 R 0x0
This bit will automatically transition from a one to a zero when the
over current condition is removed.
The default value of this bit is ‘0’.
Port Enable/Disable Change
1 = Port enabled/disabled status has changed
0 = No change
For the root hub, this bit gets set to a one only when a port is
3 R/WC 0x0
disabled due to the appropriate conditions existing at the EOF2
point (See Chapter 11 of the USB Specification for the definition of
a Port Error). Software clears this bit by writing a 1 to it.
This field is zero if Port Power is zero.
Port Enabled/Disabled
1=Enable
0=Disable
2 R/W 0x0 Ports can only be enabled by the host controller as a part of the
reset and enable. Software cannot enable a port by writing a one
to this field. The host controller will only set this bit to a one when
the reset sequence determines that the attached device is a high-
speed device.
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Offset: 0x0054 Register Name: PORTSC
Bit Read/Write Default/Hex Description
Ports can be disabled by either a fault condition(disconnect event
or other fault condition) or by host software. Note that the bit
status does not change until the port state actually changes. There
may be a delay in disabling or enabling a port due to other host
controller and bus events.
When the port is disabled, downstream propagation of data is
blocked on this port except for reset.
The default value of this field is ‘0’.
This field is zero if Port Power is zero.
Connect Status Change
1=Change in Current Connect Status
0=No change
Indicates a change has occurred in the current connect status of
the port. The host controller sets this bit for all changes to the port
1 R/WC 0x0 device connect status, even if system software has not cleared an
existing connect status change. For example, the insertion status
changes twice before system software has cleared the changed
condition, hub hardware will be “setting” an already-set bit.
Software sets this bit to 0 by writing a 1 to it.
This field is zero if Port Power is zero.
Current Connect Status
Device is present on port when the value of this field is a one, and
no device is present on port when the value of this field is a zero.
0 R 0x0 This value reflects the current state of the port, and may not
correspond directly to the event that caused the Connect Status
Change(Bit 1) to be set.
This field is zero if Port Power zero.
NOTE
This register is only reset by hardware or in response to a host controller reset.
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9.6.6 OHCI Register Description
9.6.6.1 0x0404 OHCI Control Register (Default Value: 0x0000_0000)
Offset: 0x0404 Register Name: HcRevision
Read/Write
Bit Default/Hex Description
HCD HC
31:11 / / / /
RemoteWakeupEnable
This bit is used by HCD to enable or disable the remote wakeup
feature upon the detection of upstream resume signaling. When
10 R/W R 0x0
this bit is set and the ResumeDetected bit in HcInterruptStatus is
set, a remote wakeup is signaled to the host system. Setting this
bit has no impact on the generation of hardware interrupt.
RemoteWakeupConnected
This bit indicates whether HC supports remote wakeup signaling. If
remote wakeup is supported and used by the system, it is the
9 R/W R/W 0x0 responsibility of system firmware to set this bit during POST. HC
clear the bit upon a hardware reset but does not alter it upon a
software reset. Remote wakeup signaling of the host system is
host-bus-specific and is not described in this specification.
InterruptRouting
This bit determines the routing of interrupts generated by events
registered in HcInterruptStatus. If clear, all interrupt are routed to
the normal host bus interrupt mechanism. If set interrupts are
8 R/W R 0x0
routed to the System Management Interrupt. HCD clears this bit
upon a hardware reset, but it does not alter this bit upon a
software reset. HCD uses this bit as a tag to indicate the ownership
of HC.
HostControllerFunctionalState for USB
00b USBReset
01b USBResume
10b USBOperational
11b USBSuspend
A transition to USBOperational from another state causes SOF
generation to begin 1 ms later. HCD may determine whether HC
7:6 R/W R/W 0x0 has begun sending SOFs by reading the StartoFrame field of
HcInterruptStatus.
This field may be changed by HC only when in the USBSUSPEND
state. HC may move from the USBSUSPEND state to the
USBRESUME state after detecting the resume signaling from a
downstream port.
HC enters USBSUSPEND after a software reset, whereas it enters
USBRESET after a hardware reset. The latter also resets the Root
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Offset: 0x0404 Register Name: HcRevision
Read/Write
Bit Default/Hex Description
HCD HC
Hub and asserts subsequent reset signaling to downstream ports.
BulkListEnable
This bit is set to enable the processing of the Bulk list in the next
Frame. If cleared by HCD, the processing of the Bulk list does not
occur after the next SOF. HC checks this bit whenever it
5 R/W R 0x0
determines to process the list. When disabled, HCD may modify
the list. If HcBulkCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating HcBulkCurrentED
before re-enabling processing of the list.
ControlListEnable
This bit is set to enable the processing of the Control list in the next
Frame. If cleared by HCD, the processing of the Control list does
not occur after the next SOF. HC must check this bit whenever it
4 R/W R 0x0
determines to process the list. When disabled, HCD may modify
the list. If HcControlCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating HcControlCurrentED
before re-enabling processing of the list.
IsochronousEnable
This bit is used by HCD to enable/disable processing of isochronous
EDs. While processing the periodic list in a Frame, HC checks the
status of this bit when it finds an Isochronous ED (F=1). If set
3 R/W R 0x0 (enabled), HC continues processing the EDs. If cleared (disabled),
HC halts processing of the periodic list (which now contains only
isochronous EDs) and begins processing the Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame (not
the current Frame).
PeriodicListEnable
This bit is set to enable the processing of periodic list in the next
2 R/W R 0x0 Frame. If cleared by HCD, processing of the periodic list does not
occur after the next SOF. HC must check this bit before it starts
processing the list.
ControlBulkServiceRatio
This specifies the service ratio between Control and Bulk EDs.
Before processing any of the nonperiodic lists, HC must compare
the ratio specified with its internal count on how many nonempty
Control EDs have been processed, in determining whether to
1:0 R/W R 0x0
continue serving another Control ED or switching to Bulk EDs. The
internal count will be retained when crossing the frame boundary.
In case of reset, HCD is responsible for restoring this value.
CBSR No. of Control EDs Over Bulk EDs Served
0 1:1
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Offset: 0x0404 Register Name: HcRevision
Read/Write
Bit Default/Hex Description
HCD HC
1 2:1
2 3:1
3 4:1
The default value is 0x0.
9.6.6.2 0x0408 OHCI Command Status Register (Default Value: 0x0000_0000)
Offset: 0x0408 Register Name: HcCommandStatus
Read/Write
Bit Default/Hex Description
HCD HC
31:18 / / 0x0 Reserved
SchedulingOverrunCount
These bits are incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be
17:16 R R/W 0x0
incremented when a scheduling overrun is detected even if
SchedulingOverrun in HcInterruptStatus has already been set.
This is used by HCD to monitor any persistent scheduling problem.
15:4 / / / /
OwershipChangeRequest
This bit is set by an OS HCD to request a change of control of the
3 R/W R/W 0x0 HC. When set HC will set the OwnershipChange field in
HcInterruptStatus. After the changeover, this bit is cleared and
remains so until the next request from OS HCD.
BulklListFilled
This bit is used to indicate whether there are any TDs on the Bulk
list. It is set by HCD whenever it adds a TD to an ED in the Bulk list.
When HC begins to process the head of the Bulk list, it checks BLF.
As long as BulkListFilled is 0, HC will not start processing the Bulk
list. If BulkListFilled is 1, HC will start processing the Bulk list and
2 R/W R/W 0x0
will set BF to 0. If HC finds a TD on the list, then HC will set
BulkListFilled to 1 causing the Bulk list processing to continue. If
no TD is found on the Bulk list, and if HCD does not set
BulkListFilled, then BulkListFilled will still be 0 when HC
completes processing the Bulk list and Bulk list processing will
stop.
ControlListFilled
This bit is used to indicate whether there are any TDs on the
1 R/W R/W 0x0 Control list. It is set by HCD whenever it adds a TD to an ED in the
Control list.
When HC begins to process the head of the Control list, it checks
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Offset: 0x0408 Register Name: HcCommandStatus
Read/Write
Bit Default/Hex Description
HCD HC
CLF. As long as ControlListFilled is 0, HC will not start processing
the Control list. If CF is 1, HC will start processing the Control list
and will set ControlListFilled to 0. If HC finds a TD on the list, then
HC will set ControlListFilled to 1 causing the Control list processing
to continue. If no TD is found on the Control list, and if the HCD
does not set ControlListFilled, then ControlListFilled will still be 0
when HC completes processing the Control list and Control list
processing will stop.
HostControllerReset
This bit is by HCD to initiate a software reset of HC. Regardless of
the functional state of HC, it moves to the USBSuspend state in
which most of the operational registers are reset except those
stated otherwise; e.g, the InteruptRouting field of HcControl, and
0 R/W R/E 0x0
no Host bus accesses are allowed. This bit is cleared by HC upon
the completion of the reset operation. The reset operation must
be completed within 10 ms. This bit, when set, should not cause a
reset to the Root Hub and no subsequent reset signaling should
be asserted to its downstream ports.
9.6.6.3 0x040C OHCI Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x040C Register Name: HcInterruptStatus
Read/Write
Bit Default/Hex Description
HCD HC
31:7 / / / /
RootHubStatusChange
6 R/W R/W 0x0 This bit is set when the content of HcRhStatus or the content of
any of HcRhPortStatus[NumberofDownstreamPort] has changed.
FrameNumberOverflow
This bit is set when the MSb of HcFmNumber (bit 15) changes
5 R/W R/W 0x0
value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has
been updated.
UnrecoverableError
This bit is set when HC detects a system error not related to USB.
4 R/W R/W 0x0 HC should not proceed with any processing nor signaling before
the system error has been corrected. HCD clears this bit after HC
has been reset.
ResumeDetected
3 R/W R/W 0x0 This bit is set when HC detects that a device on the USB is asserting
resume signaling. It is the transition from no resume signaling to
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Offset: 0x040C Register Name: HcInterruptStatus
Read/Write
Bit Default/Hex Description
HCD HC
resume signaling causing this bit to be set. This bit is not set when
HCD sets the USBRseume state.
StartofFrame
This bit is set by HC at each start of frame and after the update of
2 R/W R/W 0x0
HccaFrameNumber. HC also generates a SOF token at the same
time.
WritebackDoneHead
This bit is set immediately after HC has written HcDoneHead to
1 R/W R/W 0x0 HccaDoneHead. Further updates of the HccaDoneHead will not
occur until this bit has been cleared. HCD should only clear this bit
after it has saved the content of HccaDoneHead.
SchedulingOverrun
This bit is set when the USB schedule for the current Frame
0 R/W R/W 0x0 overruns and after the update of HccaFrameNumber. A
scheduling overrun will also cause the SchedulingOverrunCount
of HcCommandStatus to be incremented.
9.6.6.4 0x0410 OHCI Interrupt Enable Register (Default Value: 0x0000_0000)
Offset: 0x0410 Register Name: HcInterruptEnable Register
Read/Write
Bit Default/Hex Description
HCD HC
MasterInterruptEnable
A ‘0’ writtern to this field is ignored by HC. A ‘1’ written to this field
31 R/W R 0x0
enables interrupt generation due to events specified in the other
bits of this register. This is used by HCD as Master Interrupt Enable.
30:7 / / / /
RootHubStatusChange Interrupt Enable
0 Ignore;
6 R/W R 0x0
1 Enable interrupt generation due to Root Hub Status
Change;
FrameNumberOverflow Interrupt Enable
0 Ignore;
5 R/W R 0x0
1 Enable interrupt generation due to Frame Number Over
Flow;
UnrecoverableError Interrupt Enable
4 R/W R 0x0 0 Ignore;
1 Enable interrupt generation due to Unrecoverable Error;
3 R/W R 0x0 ResumeDetected Interrupt Enable
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Offset: 0x0410 Register Name: HcInterruptEnable Register
Read/Write
Bit Default/Hex Description
HCD HC
0 Ignore;
1 Enable interrupt generation due to Resume Detected;
StartofFrame Interrupt Enable
2 R/W R 0x0 0 Ignore;
1 Enable interrupt generation due to Start of Flame;
WritebackDoneHead Interrupt Enable
1 R/W R 0x0 0 Ignore;
1 Enable interrupt generation due to Write back Done Head;
SchedulingOverrun Interrupt Enable
0 R/W R 0x0 0 Ignore;
1 Enable interrupt generation due to Scheduling Overrun;
9.6.6.5 0x0414 OHCI Interrupt Disable Register (Default Value: 0x0000_0000)
Offset: 0x0414 Register Name: HcInterruptDisable Register
Read/Write
Bit Default/Hex Description
HCD HC
MasterInterruptEnable
A written ‘0’ to this field is ignored by HC. A ‘1’ written to this field
31 R/W R 0x0
disables interrupt generation due events specified in the other bits
of this register. This field is set after a hardware or software reset.
30:7 / / / /
RootHubStatusChange Interrupt Disable
0 Ignore;
6 R/W R 0x0
1 Disable interrupt generation due to Root Hub Status
Change;
FrameNumberOverflow Interrupt Disable
0 Ignore;
5 R/W R 0x0
1 Disable interrupt generation due to Frame Number Over
Flow;
UnrecoverableError Interrupt Disable
4 R/W R 0x0 0 Ignore;
1 Disable interrupt generation due to Unrecoverable Error;
ResumeDetected Interrupt Disable
3 R/W R 0x0 0 Ignore;
1 Disable interrupt generation due to Resume Detected;
StartofFrame Interrupt Disable
2 R/W R 0x0 0 Ignore;
1 Disable interrupt generation due to Start of Flame;
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Offset: 0x0414 Register Name: HcInterruptDisable Register
Read/Write
Bit Default/Hex Description
HCD HC
WritebackDoneHead Interrupt Disable
0 Ignore;
1 R/W R 0x0
1 Disable interrupt generation due to Write back Done
Head;
SchedulingOverrun Interrupt Disable
0 R/w R 0x0 0 Ignore;
1 Disable interrupt generation due to Scheduling Overrun;
9.6.6.6 0x0418 OHCI HCCA Register (Default Value: 0x0000_0000)
Offset: 0x0418 Register Name: HcHCCA
Read/Write
Bit Default/Hex Description
HCD HC
HCCA[31:8]
This is the base address of the Host Controller Communication
31:8 R/W R 0x0 Area. This area is used to hold the control structures and the
Interrupt table that are accessed by both the Host Controller and
the Host Controller Driver.
HCCA[7:0]
The alignment restriction in HcHCCA register is evaluated by
7:0 R R 0x0 examining the number of zeros in the lower order bits. The
minimum alignment is 256 bytes, therefore, bits 0 through 7 must
always return 0 when read.
9.6.6.7 0x041C OHCI Period Current ED Register (Default Value: 0x0000_0000)
Offset: 0x041C Register Name: HcPeriodCurrentED[PCED]
Read/Write
Bit Default/Hex Description
HCD HC
PCED[31:4]
This is used by HC to point to the head of one of the Periodec list
which will be processed in the current Frame. The content of this
31:4 R R/W 0x0
register is updated by HC after a periodic ED has been processed.
HCD may read the content in determining which ED is currently
being processed at the time of reading.
PCED[3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
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9.6.6.8 0x0420 OHCI Control Head ED Register (Default Value: 0x0000_0000)
Offset: 0x0420 Register Name: HcControlHeadED[CHED]
Read/Write
Bit Default/Hex Description
HCD HC
EHCD[31:4]
The HcControlHeadED register contains the physical address of
31:4 R/W R 0x0 the first Endpoint Descriptor of the Control list. HC traverse the
Control list starting with the HcControlHeadED pointer. The
content is loaded from HCCA during the initialization of HC.
EHCD[3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
9.6.6.9 0x0424 OHCI Control Current ED Register (Default Value: 0x0000_0000)
Offset: 0x0424 Register Name: HcControlCurrentED[CCED]
Read/Write
Bit Default/Hex Description
HCD HC
CCED[31:4]
The pointer is advanced to the next ED after serving the present
one. HC will continue processing the list from where it left off in
the last Frame. When it reaches the end of the Control list, HC
checks the ControlListFilled of in HcCommandStatus. If set, it
31:4 R/W R/W 0x0 copies the content of HcControlHeadED to HcControlCurrentED
and clears the bit. If not set, it does nothing.
HCD is allowed to modify this register only when the
ControlListEnable of HcControl is cleared. When set, HCD only
reads the instantaneous value of this register. Initially, this is set
to zero to indicate the end of the Control list.
CCED[3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
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9.6.6.10 0x0428 OHCI Bulk Head ED Register (Default Value: 0x0000_0000)
Offset: 0x0428 Register Name: HcBulkHeadED[BHED]
Read/Write
Bit Default/Hex Description
HCD HC
BHED[31:4]
The HcBulkHeadED register contains the physical address of the
31:4 R/W R 0x0 first Endpoint Descriptor of the Bulk list. HC traverses the Bulk list
starting with the HcBulkHeadED pointer. The content is loaded
from HCCA during the initialization of HC.
BHED[3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
9.6.6.11 0x042C OHCI Bulk Current ED Register (Default Value: 0x0000_0000)
Offset: 0x042C Register Name: HcBulkCurrentED[BCED]
Read/Write
Bit Default/Hex Description
HCD HC
BulkCurrentED[31:4]
This is advanced to the next ED after the HC has served the present
one. HC continues processing the list from where it left off in the
last Frame. When it reaches the end of the Bulk list, HC checks the
ControlListFilled of HcControl. If set, it copies the content of
31:4 R/W R/W 0x0
HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not
set, it does nothing. HCD is only allowed to modify this register
when the BulkListEnable of HcControl is cleared. When set, the
HCD only reads the instantaneous value of this register. This is
initially set to zero to indicate the end of the Bulk list.
BulkCurrentED [3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
9.6.6.12 0x0430 OHCI Done Head Register (Default Value: 0x0000_0000)
Offset: 0x0430 Register Name: HcDoneHead
Read/Write
Bit Default/Hex Description
HCD HC
HcDoneHead[31:4]
31:4 R R/W 0x0
When a TD is completed, HC writes the content of HcDoneHead to
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Offset: 0x0430 Register Name: HcDoneHead
Read/Write
Bit Default/Hex Description
HCD HC
the NextTD field of the TD. HC then overwrites the content of
HcDoneHead with the address of this TD. This is set to zero
whenever HC writes the content of this register to HCCA. It also
sets the WritebackDoneHead of HcInterruptStatus.
HcDoneHead[3:0]
Because the general TD length is 16 bytes, the memory structure
3:0 R R 0x0
for the TD must be aligned to a 16-byte boundary. So the lower
bits in the PCED, through bit 0 to bit 3 must be zero in this field.
9.6.6.13 0x0434 OHCI Frame Interval Register (Default Value: 0x0000_2EDF)
Offset: 0x0434 Register Name: HcFmInterval Register
Read/Write
Bit Default/Hex Description
HCD HC
FrameIntervalToggler
31 R/W R 0x0 HCD toggles this bit whenever it loads a new value to
FrameInterval.
FSLargestDataPacket
This field specifies a value which is loaded into the Largest Data
Packet Counter at the beginning of each frame. The counter value
30:16 R/W R 0x0 represents the largest amount of data in bits which can be sent or
received by the HC in a single transaction at any given time
without causing scheduling overrun. The field value is calculated
by the HCD.
15:14 / / / /
FrameInterval
This specifies the interval between two consecutive SOFs in bit
times. The nominal value is set to be 11,999. HCD should store the
current value of this field before resetting HC. By setting the
13:0 R/W R 0x2edf
HostControllerReset field of HcCommandStatus as this will cause
the HC to reset this field to its nominal value. HCD may choose to
restore the stored value upon the completion of the Reset
sequence.
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9.6.6.14 0x0438 OHCI Frame Remaining Register (Default Value: 0x0000_0000)
Offset: 0x0438 Register Name: HcFmRemaining
Read/Write
Bit Default/Hex Description
HCD HC
FrameRemaining Toggle
This bit is loaded from the FrameIntervalToggle field of
31 R R/W 0x0 HcFmInterval whenever FrameRemaining reaches 0. This bit is
used by HCD for the synchronization between FrameInterval and
FrameRemaining.
30:14 / / / /
FramRemaining
This counter is decremented at each bit time. When it reaches
zero, it is reset by loading the FrameInterval value specified in
13:0 R RW 0x0 HcFmInterval at the next bit time boundary. When entering the
USBOPERATIONAL state, HC re-loads the content with the
FrameInterval of HcFmInterval and uses the updated value from
the next SOF.
9.6.6.15 0x043C OHCI Frame Number Register (Default Value: 0x0000_0000)
Offset: 0x043C Register Name: HcFmNumber
Read/Write
Bit Default/Hex Description
HCD HC
31:16 / / / /
FrameNumber
This is incremented when HcFmRemaining is re-loaded. It will be
rolled over to 0x0 after 0x0ffff. When entering the
USBOPERATIONAL state, this will be incremented automatically.
15:0 R R/W 0x0
The content will be written to HCCA after HC has incremented the
FrameNumber at each frame boundary and sent a SOF but before
HC reads the first ED in that Frame. After writing to HCCA, HC will
set the StartofFrame in HcInterruptStatus.
9.6.6.16 0x0440 OHCI Periodic Start Register (Default Value: 0x0000_0000)
Offset: 0x0440 Register Name: HcPeriodicStatus
Read/Write
Bit Default/Hex Description
HCD HC
31:14 / / / /
PeriodicStart
13:0 R/W R 0x0
After a hardware reset, this field is cleared. This is then set by HCD
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Offset: 0x0440 Register Name: HcPeriodicStatus
Read/Write
Bit Default/Hex Description
HCD HC
during the HC initialization. The value is calculated roughly as 10%
off from HcFmInterval. A typical value will be 0x2A3F (or 0x3e67).
When HcFmRemaining reaches the value specified, processing of
the periodic lists will have priority over Control/Bulk processing.
HC will therefore start processing the Interrupt list after
completing the current Control or Bulk transaction that is in
progress.
9.6.6.17 0x0444 OHCI LS Threshold Register (Default Value: 0x0000_0628)
Offset: 0x0444 Register Name: HcLSThreshold
Read/Write
Bit Default/Hex Description
HCD HC
31:12 / / / /
LSThreshold
This field contains a value which is compared to the
FrameRemaining field prior to initiating a Low Speed transaction.
11:0 R/W R 0x0628
The transaction is started only if FrameRemaining this field. The
value is calculated by HCD with the consideration of transmission
and setup overhead.
9.6.6.18 0x0448 OHCI Root Hub DescriptorA Register (Default Value: 0x0200_1201)
Offset: 0x0448 Register Name: HcRhDescriptorA
Read/Write
Bit Default/Hex Description
HCD HC
PowerOnToPowerGoodTime[POTPGT]
This byte specifies the duration HCD has to wait before accessing
31:24 R/W R 0x2 a powered-on port of the Root Hub. It is implementation-specific.
The unit of time is 2 ms. The duration is calculated as POTPGT *
2ms.
23:13 / / / /
NoOverCurrentProtection
This bit describes how the overcurrent status for the Root Hub
ports are reported. When this bit is cleared, the
12 R/W R 0x1 OverCurrentProtectionMode field specifies global or per-port
reporting.
0 Over-current status is reported collectively for all
downstream ports.
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Offset: 0x0448 Register Name: HcRhDescriptorA
Read/Write
Bit Default/Hex Description
HCD HC
1 No overcurrent protection supported.
OverCurrentProtectionMode
This bit describes how the overcurrent status for the Root Hub
ports are reported. At reset, these fields should reflect the same
mode as PowerSwitchingMode. This field is valid only if the
11 R/W R 0x0
NoOverCurrentProtection field is cleared.
0 Over-current status is reported collectively for all
downstream ports.
1 Over-current status is reported on per-port basis.
Device Type
This bit specifies that the Root Hub is not a compound device. The
10 R R 0x0
Root Hub is not permitted to be a compound device. This field
should always read/write 0.
PowerSwitchingMode
This bit is used to specify how the power switching of the Root
Hub ports is controlled. It is implementation-specific. This field is
only valid if the NoPowerSwitching field is cleared.
0 All ports are powered at the same time.
1 Each port is powered individually. This mode allows port
9 R/W R 0x1 power to be controlled by either the global switch or per-
port
switching. If the PortPowerControlMask bit is set, the port
responds only to port power commands
(Set/ClearPortPower). If the port mask is cleared, then the
port is controlled only by the global power switch
(Set/ClearGlobalPower).
NoPowerSwithcing
These bits are used to specify whether power switching is
supported or ports are always powered. It is implementation-
8 R/W R 0x0 specific. When this bit is cleared, the PowerSwitchingMode
specifies global or per-port switching.
0 Ports are power switched.
1 Ports are always powered on when the HC is powered on.
NumberDownstreamPorts
These bits specify the number of downstream ports supported by
7:0 R R 0x01
the Root Hub. It is implementation-specific. The minimum
number of ports is 1. The maximum number of ports supported.
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9.6.6.19 0x044C HcRhDescriptorB Register (Default Value: 0x0000_0000)
Offset: 0x044C Register Name: HcRhDescriptorB Register
Read/Write
Bit Default/Hex Description
HCD HC
PortPowerControlMask
Each bit indicates if a port is affected by a global power control
command when PowerSwitchingMode is set. When set, the
port's power state is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is controlled by the
global power switch (Set/ClearGlobalPower). If the device is
31:16 R/W R 0x0 configured to global switching mode (PowerSwitchingMode = 0 ),
this field is not valid.
Bit0 Reserved
Bit1 Ganged-power mask on Port #1.
Bit2 Ganged-power mask on Port #2.
…
Bit15 Ganged-power mask on Port #15.
DeviceRemovable
Each bit is dedicated to a port of the Root Hub. When cleared, the
attached device is removable. When set, the attached device is
not removable.
15:0 R/W R 0x0 Bit0 Reserved
Bit1 Device attached to Port #1.
Bit2 Device attached to Port #2.
…
Bit15 Device attached to Port #15.
9.6.6.20 0x0450 HcRhStatus Register (Default Value: 0x0000_0000)
Offset: 0x0450 Register Name: HcRhStatus Register
Read/Write
Bit Default/Hex Description
HCD HC
(write)ClearRemoteWakeupEnable
31 W R 0x0 Write a ‘1’ clears DeviceRemoteWakeupEnable. Writing a ‘0’ has
no effect.
30:18 / / / /
OverCurrentIndicatorChang
This bit is set by hardware when a change has occurred to the
17 R/W R 0x0
OverCurrentIndicator field of this register. The HCD clears this bit
by writing a ‘1’. Writing a ‘0’ has no effect.
16 R/W R 0x0 (read)LocalPowerStartusChange
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Offset: 0x0450 Register Name: HcRhStatus Register
Read/Write
Bit Default/Hex Description
HCD HC
The Root Hub does not support the local power status features,
thus, this bit is always read as ‘0’.
(write)SetGlobalPower
In global power mode (PowerSwitchingMode=0), This bit is
written to ‘1’ to turn on power to all ports (clear
PortPowerStatus). In per-port power mode, it sets
PortPowerStatus only on ports whose PortPowerControlMask bit
is not set. Writing a ‘0’ has no effect.
(read)DeviceRemoteWakeupEnable
This bit enables a ConnectStatusChange bit as a resume event,
causing a USBSUSPEND to USBRESUME state transition and
setting the ResumeDetected interrupt.
0 ConnectStatusChange is not a remote wakeup event.
15 R/W R 0x0
1 ConnectStatusChange is a remote wakeup event.
(write)SetRemoteWakeupEnable
Writing a ‘1’ sets DeviceRemoveWakeupEnable. Writing a ‘0’ has
no effect.
14:2 / / / /
OverCurrentIndicator
This bit reports overcurrent conditions when the global reporting
is implemented. When set, an overcurrent condition exists. When
1 R R/W 0x0
cleared, all power operations are normal.
If per-port overcurrent protection is implemented this bit is
always ‘0’
(Read)LocalPowerStatus
When read, this bit returns the LocalPowerStatus of the Root Hub.
The Root Hub does not support the local power status feature;
thus, this bit is always read as ‘0’.
(Write)ClearGlobalPower
0 R/W R 0x0
When write, this bit is operated as the ClearGlobalPower. In global
power mode (PowerSwitchingMode=0), This bit is written to ‘1’
to turn off power to all ports (clear PortPowerStatus). In per-port
power mode, it clears PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.
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9.6.6.21 0x0454 HcRhPortStatus Register (Default Value: 0x0000_0100)
Offset: 0x0454 Register Name: HcRhPortStatus
Read/Write
Bit Default/Hex Description
HCD HC
31:21 / / / /
PortResetStatusChange
This bit is set at the end of the 10-ms port reset signal. The HCD
20 R/W R/W 0x0 writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
0 port reset is not complete
1 port reset is complete
PortOverCurrentIndicatorChange
This bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when Root Hub changes the
19 R/W R/W 0x0 PortOverCurrentIndicator bit. The HCD writes a ‘1’ to clear this
bit. Writing a ‘0’ has no effect.
0 no change in PortOverCurrentIndicator
1 PortOverCurrentIndicator has changed
PortSuspendStatusChange
This bit is set when the full resume sequence has been completed.
This sequence includes the 20-s resume pulse, LS EOP, and 3-ms
resychronization delay. The HCD writes a ‘1’ to clear this bit.
18 R/W R/W 0x0
Writing a ‘0’ has no effect. This bit is also cleared when
ResetStatusChange is set.
0 resume is not completed
1 resume completed
PortEnableStatusChange
This bit is set when hardware events cause the PortEnableStatus
bit to be cleared. Changes from HCD writes do not set this bit. The
17 R/W R/W 0x0
HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
0 no change in PortEnableStatus
1 change in PortEnableStatus
ConnectStatusChange
This bit is set whenever a connect or disconnect event occurs. The
HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. If
CurrentConnectStatus is cleared when a
SetPortReset,SetPortEnable, or SetPortSuspend write occurs,
this bit is set to force the driver to re-evaluate the connection
16 R/W R/W 0x0
status since these writes should not occur if the port is
disconnected.
0 no change in PortEnableStatus
1 change in PortEnableStatus
Note: If the DeviceRemovable[NDP] bit is set, this bit is set only
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Offset: 0x0454 Register Name: HcRhPortStatus
Read/Write
Bit Default/Hex Description
HCD HC
after a Root Hub reset to inform the system that the device is
attached.
15:10 / / / /
(read)LowSpeedDeviceAttached
This bit indicates the speed of the device attached to this port.
When set, a Low Speed device is attached to this port. When clear,
a Full Speed device is attached to this port. This field is valid only
when the CurrentConnectStatus is set.
9 R/W R/W 0x0 0 full speed device attached
1 low speed device attached
(write)ClearPortPower
The HCD clears the PortPowerStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect.
(read)PortPowerStatus
This bit reflects the port’s power status, regardless of the type of
power switching implemented. This bit is cleared if an overcurrent
condition is detected. HCD sets this bit by writing SetPortPower
or SetGlobalPower. HCD clears this bit by writing ClearPortPower
or ClearGlobalPower. Which power control switches are enabled
is determined by PowerSwitchingMode and
PortPortControlMask[NumberDownstreamPort]. In global
switching mode(PowerSwitchingMode=0), only
Set/ClearGlobalPower controls
this bit. In per-port power switching (PowerSwitchingMode=1), if
the PortPowerControlMask[NDP] bit for the port is set, only
8 R/W R/W 0x1 Set/ClearPortPower commands are enabled. If the mask is not
set, only Set/ClearGlobalPower commands are enabled. When
port power is disabled, CurrentConnectStatus, PortEnableStatus,
PortSuspendStatus, and PortResetStatus should be reset.
0 port power is off
1 port power is on
(write)SetPortPower
The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a ‘0’
has no effect.
Note: This bit is always reads ‘1b’ if power switching is not
supported.
7:5 / / / /
4 R/W R/W 0x0 (read)PortResetStatus
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Offset: 0x0454 Register Name: HcRhPortStatus
Read/Write
Bit Default/Hex Description
HCD HC
When this bit is set by a write to SetPortReset, port reset signaling
is asserted. When reset is completed, this bit is cleared when
PortResetStatusChange is set. This bit cannot be set if
CurrentConnectStatus is cleared.
0 port reset signal is not active
1 port reset signal is active
(write)SetPortReset
The HCD sets the port reset signaling by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this
write does not set PortResetStatus, but instead sets
ConnectStatusChange. This informs the driver that it attempted
to reset a disconnected port.
(read)PortOverCurrentIndicator
This bit is only valid when the Root Hub is configured in such a way
that overcurrent conditions are reported on a per-port basis. If
per-port overcurrent reporting is not supported, this bit is set to
0. If cleared, all power operations are normal for this port. If set,
an overcurrent condition exists on this port. This bit always
3 R/W R/W 0x0 reflects the overcurrent input signal.
0 no overcurrent condition.
1 overcurrent condition detected.
(write)ClearSuspendStatus
The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has no
effect. A resume is initiated only if PortSuspendStatus is set.
(read)PortSuspendStatus
This bit indicates the port is suspended or in the resume sequence.
It is set by a SetSuspendState write and cleared when
PortSuspendStatusChange is set at the end of the resume
interval. This bit cannot be set if CurrentConnectStatus is cleared.
This bit is also cleared when PortResetStatusChange is set at the
end of the port reset or when the HC is placed in the USBRESUME
2 R/W R/W 0x0 state. If an upstream resume is in progress, it should propagate to
the HC.
0 port is not suspended
1 port is suspended
(write)SetPortSuspend
The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this
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Offset: 0x0454 Register Name: HcRhPortStatus
Read/Write
Bit Default/Hex Description
HCD HC
write does not set PortSuspendStatus; instead it sets
ConnectStatusChange. This informs the driver that it attempted
to suspend a disconnected port.
(read)PortEnableStatus
This bit indicates whether the port is enabled or disabled. The
Root Hub may clear this bit when an overcurrent condition,
disconnect event, switched-off power, or operational bus error
such as babble is detected. This change also causes
PortEnabledStatusChange to be set. HCD sets this bit by writing
SetPortEnable and clears it by writing ClearPortEnable. This bit
cannot be set when CurrentConnectStatus is cleared. This bit is
also set, if not already, at the completion of a port reset when
ResetStatusChange is set or port suspend when
1 R/W R/W 0x0
SuspendStatusChange is set.
0 port is disabled
1 port is enabled
(write)SetPortEnable
The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has
no effect. If CurrentConnectStatus is cleared, this write does not
set PortEnableStatus, but instead sets ConnectStatusChange.
This informs the driver that it attempted to enable a disconnected
Port.
(read)CurrentConnectStatus
This bit reflects the current state of the downstream port.
0 No device connected
1 Device connected
(write)ClearPortEnable
0 R/W R/W 0x0
The HCD writes a ‘1’ to clear the PortEnableStatus bit. Writing ‘0’
to this bit has no effect. The CurrentConnectStatus is not affected
by any write.
Note: This bit is always read ‘1’ when the attached device is
nonremovalble (DviceRemoveable[NumberDownstreamPort]).
9.6.6.22 0x0800 HCI Interface Register (Default Value: 0x1000_0000)
Offset: 0x0800 Register Name: USB_CTRL
Bit Read/Write Default/Hex Description
31:29 / / Reserved
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Offset: 0x0800 Register Name: USB_CTRL
Bit Read/Write Default/Hex Description
DMA Transfer Status Enable
28 R 1 0: Disable
1: Enable
27:26 / / /
OHCI count select
1: Simulation mode. The counters will be much shorter then real
25 R/W 0
time
0: Normal mode. The counters will count full time
24:19 / / /
1: Within 2 us of the resume-K to SE0 transition
18 R/W 0
0: Random time value of the resume-K to SE0 transition
17:13 / / /
PP2VBUS
1: ULPI wrapper interface will automatically set or clear DrvVbus
register in ULPI PHY according to the port power status form the
12 R/W 0
root hub
0: ULPI wrapper will ignore the difference between power status
of root hub and ULPI PHY
AHB Master interface INCR16 enable
1: Use INCR16 when appropriate
11 R/W 0
0: Do not use INCR16, use other enabled INCRX or unspecified
length burst INCR
AHB Master interface INCR8 enable
1: Use INCR8 when appropriate
10 R/W 0
0: Do not use INCR8, use other enabled INCRX or unspecified
length burst INCR
AHB Master interface burst type INCR4 enable
1: Use INCR4 when appropriate
9 R/W 0
0: Do not use INCR4, use other enabled INCRX or unspecified
length burst INCR
AHB Master interface INCRX align enable
1: Start INCRx burst only on burst x-align address
8 R/W 0
0: Start burst on any double word boundary
Note: This bit must enable if any bit of bit[11:9] is enabled
7:1 / / /
ULPI bypass enable
0 R/W 0 1: Enable UTMI interface, disable ULPI interface
0: Enable ULPI interface, disable UTMI interface
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9.6.6.23 0x0808 HCI Control 3 Register (Default Value: 0x0001_0000)
Offset: 0x0808 Register Name: HCI_CTRL3
Bit Read/Write Default/Hex Description
31:17 / / Reserved
Linestate Change Detect
0: Linestate change not dected
16 R/W1C 1
1: Linestate change dected
Write ‘1’ to clear.
15:4 / / Reserved
Remote Wakeup Enable
3 R/W 0 1: Enable
0: Disable
2 / / Reserved
Linestate Change Interrupt Enable
1 R/W 0 1: Enable
0: Disable
Linestate Change Detect Enable
0 R/W 0 1: Enable
0: Disable
9.6.6.24 0x0810 PHY Control Register (Default Value: 0x0000_0008)
Offset: 0x0810 Register Name: PHY_CTRL
Bit Read/Write Default/Hex Description
31:17 / / /
16 R/W 0 bist_en_a
15:8 R/W 0 vc_addr
7 R/W 0 vc_di
6:4 / / /
SIDDQ
3 R/W 0x1 1: Write 1 to disable phy
0: Write 0 to enable phy
2:1 / / /
0 R/W 0x0 vc_clk
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9.6.6.25 0x0824 PHY Status Register (Default Value: 0x0000_0000)
Offset: 0x0824 Register Name: PHY_STATUS
Bit Read/Write Default/Hex Description
31:18 / / /
17 R 0 Bist_error
16 R 0 bist_done
15:1 / / /
0 R 0 vc_do
9.6.6.26 0x0828 HCI SIE Port Disable Control Register (Default Value: 0x0000_0000)
Offset: 0x0828 Register Name: USB_SPDCR
Bit Read/Write Default/Hex Description
31:17 / / /
SE0 Status
16 R/W 0 This bit is set when no-se0 is detected before SOF when bit[1:0]
is 10b or 11b
15:5 / / /
resume_sel
4 R/W 0 When set k-se0 transition 2 us, setting this bit to 1, which is
cooperated with ss_utmi_backward_enb_i.
3:2 / / /
Port Disable Control
00: Port Disable when no-se0 detect before SOF
01: Port Disable when no-se0 detect before SOF
1:0 R/W 0
10: No Port Disable when no-se0 detect before SOF
11: Port Disable when no-se0 3 time detect before SOF during 8
frames
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9.7 GPIO
9.7.1 Overview
The general purpose input/output (GPIO) is one of the blocks controlling the chip multiplexing pins. The F133
supports 6 groups of GPIO pins. Each pin can be configured as input or output and these pins are used to
generate input signals or output signals for special purposes.
The Port Controller has the following features:
6 groups of ports (PB, PC, PD, PE, PF, PG)
Software control for each signal pin
Data input (capture)/output (drive)
Each GPIO peripheral can produce an interrupt
Pull-up/Pull-down/no-Pull register control
Control the direction of every signal
4 drive strengths in each operating mode
Up to 72 interrupts
Configurable interrupt edges
9.7.2 Block Diagram
The following figure shows the block diagram of the GPIO.
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Figure 9-67 GPIO Block Diagram
The GPIO consists of the digital part (GPIO, external interface) and IO analog part (output buffer, dual pull down,
pad). The digital part can select the output interface by the MUX switch; the analog part can configure pull
up/down and buffer strength.
When executing GPIO read state, the GPIO reads the current level of the pin into the internal register bus.
When not executing GPIO read state, the external pin and the internal register bus are off-status, which is high-
impedance.
9.7.3 Functional Description
9.7.3.1 Multi-function Port
The F133 includes 72 multi-functional input/output port pins. There are 6 ports as listed below.
Table 9-20 Multi-function Port
Port Number Input Output
Multiplex Pins Power
Name of Pins Driver Driver
PB 6 Schmitt CMOS LCD/I2S/TWI/PWM/IR/UART/PB-EINT 3.3 V
PC 6 Schmitt CMOS SPI/SMHC/UART/BOOT/TWI/TCON/PC-EINT 3.3 V
LCD/LVDS/OWA/TWI/IR/DSI/SPI-DBI/DMIC/ 3.3 V/
PD 23 Schmitt CMOS
UART/PWM/IR/PD-EINT 1.8 V
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Port Number Input Output
Multiplex Pins Power
Name of Pins Driver Driver
3.3 V/
NCSI/TWI/UART/PWM/LCD/OWA/LEDC/IR/
PE 14 Schmitt CMOS 2.8 V/
JTAG/EMAC/PE-EINT
1.8 V
SMHC/JTAG/UART/OWA/TWI/IR/I2S/LEDC/
PF 7 Schmitt CMOS 3.3 V
PWM/PF-EINT
SMHC/UART/PWM/I2S/TWI/EMAC/OWA/ 3.3 V/
PG 16 Schmitt CMOS
IR/TCON/LEDC/SPI/PG-EINT 1.8 V
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9.7.3.2 GPIO Multiplex Function
Table 9-21 to Table 9-26 show the multiplex function pins of the F133.
NOTE
For each GPIO, Function0 is input function; Function1 is output function; Function9 to Function13 are reserved.
Table 9-21 PB Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
PB2 LCD0-D0 I2S2-DOUT2 TWI0-SDA I2S2-DIN2 LCD0-D18 UART4-TX PB-EINT2
PB3 LCD0-D1 I2S2-DOUT1 TWI0-SCK I2S2-DIN0 LCD0-D19 UART4-RX PB-EINT3
PB4 LCD0-D8 I2S2-DOUT0 TWI1-SCK I2S2-DIN1 LCD0-D20 UART5-TX PB-EINT4
PB5 LCD0-D9 I2S2-BCLK TWI1-SDA PWM0 LCD0-D21 UART5-RX PB-EINT5
PB6 LCD0-D16 I2S2-LRCK TWI3-SCK PWM1 LCD0-D22 UART3-TX CPUBIST0 PB-EINT6
PB7 LCD0-D17 I2S2-MCLK TWI3-SDA IR-RX LCD0-D23 UART3-RX CPUBIST1 PB-EINT7
Table 9-22 PC Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
PC2 SPI0-CLK SDC2-CLK PC-EINT2
PC3 SPI0-CS0 SDC2-CMD PC-EINT3
PC4 SPI0-MOSI SDC2-D2 BOOT-SEL0 PC-EINT4
PC5 SPI0-MISO SDC2-D1 BOOT-SEL1 PC-EINT5
PC6 SPI0-WP SDC2-D0 UART3-TX TWI3-SCK DBG-CLK PC-EINT6
PC7 SPI0-HOLD SDC2-D3 UART3-RX TWI3-SDA TCON-TRIG PC-EINT7
Table 9-23 PD Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
PD0 LCD0-D2 LVDS0-V0P DSI-D0P TWI0-SCK PD-EINT0
PD1 LCD0-D3 LVDS0-V0N DSI-D0N UART2-TX PD-EINT1
PD2 LCD0-D4 LVDS0-V1P DSI-D1P UART2-RX PD-EINT2
PD3 LCD0-D5 LVDS0-V1N DSI-D1N UART2-RTS PD-EINT3
PD4 LCD0-D6 LVDS0-V2P DSI-CKP UART2-CTS PD-EINT4
PD5 LCD0-D7 LVDS0-V2N DSI-CKN UART5-TX PD-EINT5
PD6 LCD0-D10 LVDS0-CKP DSI-D2P UART5-RX PD-EINT6
PD7 LCD0-D11 LVDS0-CKN DSI-D2N UART4-TX PD-EINT7
PD8 LCD0-D12 LVDS0-V3P DSI-D3P UART4-RX PD-EINT8
PD9 LCD0-D13 LVDS0-V3N DSI-D3N PWM6 PD-EINT9
PD10 LCD0-D14 LVDS1-V0P SPI1-CS/DBI-CSX UART3-TX PD-EINT10
SPI1-CLK/
PD11 LCD0-D15 LVDS1-V0N UART3-RX PD-EINT11
DBI-SCLK
SPI1-MOSI/
PD12 LCD0-D18 LVDS1-V1P TWI0-SDA PD-EINT12
DBI-SDO
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GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
SPI1-MISO/
PD13 LCD0-D19 LVDS1-V1N UART3-RTS PD-EINT13
DBI-SDI/DBI-TE/
DBI-DCX
SPI1-HOLD/
PD14 LCD0-D20 LVDS1-V2P UART3-CTS PD-EINT14
DBI-DCX/
DBI-WRX
PD15 LCD0-D21 LVDS1-V2N SPI1-WP/DBI-TE IR-RX PD-EINT15
PD16 LCD0-D22 LVDS1-CKP DMIC-DATA3 PWM0 PD-EINT16
PD17 LCD0-D23 LVDS1-CKN DMIC-DATA2 PWM1 PD-EINT17
PD18 LCD0-CLK LVDS1-V3P DMIC-DATA1 PWM2 PD-EINT18
PD19 LCD0-DE LVDS1-V3N DMIC-DATA0 PWM3 PD-EINT19
PD20 LCD0-HSYNC TWI2-SCK DMIC-CLK PWM4 PD-EINT20
PD21 LCD0-VSYNC TWI2-SDA UART1-TX PWM5 PD-EINT21
PD22 OWA-OUT IR-RX UART1-RX PWM7 PD-EINT22
Table 9-24 PE Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
RGMII-RXCTRL/
PE0 NCSI0-HSYNC UART2-RTS TWI1-SCK LCD0-HSYNC PE-EINT0
RMII-CRS-DV
RGMII-RXD0/
PE1 NCSI0-VSYNC UART2-CTS TWI1-SDA LCD0-VSYNC PE-EINT1
RMII-RXD0
RGMII-RXD1/
PE2 NCSI0-PCLK UART2-TX TWI0-SCK CLK-FANOUT0 UART0-TX PE-EINT2
RMII-RXD1
RGMII-TXCK/
PE3 NCSI0-MCLK UART2-RX TWI0-SDA CLK-FANOUT1 UART0-RX PE-EINT3
RMII-TXCK
RGMII-TXD0/
PE4 NCSI0-D0 UART4-TX TWI2-SCK CLK-FANOUT2 R-JTAG-MS PE-EINT4
RMII-TXD0
RGMII-TXD1/
PE5 NCSI0-D1 UART4-RX TWI2-SDA LEDC-DO R-JTAG-DI PE-EINT5
RMII-TXD1
RGMII-TXCTRL/
PE6 NCSI0-D2 UART5-TX TWI3-SCK OWA-IN R-JTAG-DO PE-EINT6
RMII-TXEN
RGMII-CLKIN/
PE7 NCSI0-D3 UART5-RX TWI3-SDA OWA-OUT R-JTAG-CK PE-EINT7
RMII-RXER
PE8 NCSI0-D4 UART1-RTS PWM2 UART3-TX MDC PE-EINT8
PE9 NCSI0-D5 UART1-CTS PWM3 UART3-RX MDIO PE-EINT9
PE10 NCSI0-D6 UART1-TX PWM4 IR-RX EPHY-25M PE-EINT10
PE11 NCSI0-D7 UART1-RX RGMII-TXD2 PE-EINT11
PE12 TWI2-SCK NCSI0-FIELD RGMII-TXD3 PE-EINT12
PE13 TWI2-SDA PWM5 DMIC-DATA3 RGMII-RXD2 PE-EINT13
Table 9-25 PF Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
PF0 SDC0-D1 R-JTAG-MS I2S2-DOUT1 I2S2-DIN0 PF-EINT0
PF1 SDC0-D0 R-JTAG-DI I2S2-DOUT0 I2S2-DIN1 PF-EINT1
PF2 SDC0-CLK UART0-TX TWI0-SCK LEDC-DO OWA-IN PF-EINT2
PF3 SDC0-CMD R-JTAG-DO I2S2-BCLK PF-EINT3
PF4 SDC0-D3 UART0-RX TWI0-SDA PWM6 IR-TX PF-EINT4
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GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
PF5 SDC0-D2 R-JTAG-CK I2S2-LRCK PF-EINT5
PF6 OWA-OUT IR-RX I2S2-MCLK PWM5 PF-EINT6
Table 9-26 PG Multiplex Function
GPIO Port Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 14
RGMII-RXCTRL/
PG0 SDC1-CLK UART3-TX PWM7 PG-EINT0
RMII-CRS-DV
RGMII-RXD0/
PG1 SDC1-CMD UART3-RX PWM6 PG-EINT1
RMII-RXD0
RGMII-RXD1/
PG2 SDC1-D0 UART3-RTS UART4-TX PG-EINT2
RMII-RXD1
RGMII-TXCK/
PG3 SDC1-D1 UART3-CTS UART4-RX PG-EINT3
RMII-TXCK
RGMII-TXD0/
PG4 SDC1-D2 UART5-TX PWM5 PG-EINT4
RMII-TXD0
RGMII-TXD1/
PG5 SDC1-D3 UART5-RX PWM4 PG-EINT5
RMII-TXD1
PG6 UART1-TX TWI2-SCK RGMII-TXD2 PWM1 PG-EINT6
PG7 UART1-RX TWI2-SDA RGMII-TXD3 OWA-IN PG-EINT7
PG8 UART1-RTS TWI1-SCK RGMII-RXD2 UART3-TX PG-EINT8
PG9 UART1-CTS TWI1-SDA RGMII-RXD3 UART3-RX PG-EINT9
PG10 PWM3 TWI3-SCK RGMII-RXCK CLK-FANOUT0 IR-RX PG-EINT10
PG11 I2S1-MCLK TWI3-SDA EPHY-25M CLK-FANOUT1 TCON-TRIG PG-EINT11
RGMII-TXCTRL/
PG12 I2S1-LRCK TWI0-SCK CLK-FANOUT2 PWM0 UART1-TX PG-EINT12
RMII-TXEN
RGMII-CLKIN/
PG13 I2S1-BCLK TWI0-SDA PWM2 LEDC-DO UART1-RX PG-EINT13
RMII-RXER
PG14 I2S1-DIN0 TWI2-SCK MDC I2S1-DOUT1 SPI0-WP UART1-RTS PG-EINT14
PG15 I2S1-DOUT0 TWI2-SDA MDIO I2S1-DIN1 SPI0-HOLD UART1-CTS PG-EINT15
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9.7.3.3 Port Function
The Port Controller supports 6 GPIOs, every GPIO can configure as Input, Output, Function Peripheral, IO
disable or Interrupt function. The configuration instruction of every function is as follows.
Table 9-27 Port Function
Function Buffer Strength Pull Up Pull Down
Input GPIO/Multiplexing Input / X X
Output GPIO/Multiplexing Output Y X X
Pull Up / Y N
Disable
Pull Down / N Y
Interrupt Trigger / X X
/: non-configure, configuration is invalid
Y: configure
X: Select configuration according to the actual situation
N: Forbid to configure
9.7.3.4 Pull Up/Down and High-Impedance Logic
Each IO pin can configure the internal pull-up/down function or high-impedance.
Figure 9-68 Pull up/down Logic
VCC
Rpu
PAD
Rpd
GND
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High-impedance, the output is float state, all buffer is off, the level is decided by external high/low level. When
high-impedance, the software configures the switch on Rpu and Rpd as off, and the multiplexing function of IO
is set as IO disable or input by software.
Pull-up, an uncertain signal is pulled high by resistance, the resistance has a current-limiting function. When
pulling up, the switch on Rpu is conducted by software configuration, the IO is pulled up to VCC by Rpu.
Pull-down, an uncertain signal is pulled low by a resistance. When pulling down, the switch on Rpd is conducted
by software configuration, the IO is pulled down to GND by Rpd.
The pull-up/down of each IO is weak pull-up/down.
The setting of pull-down, pull-up, high-impedance is decided by the external circuit.
9.7.3.5 Buffer Strength
Each IO can be set as different buffer strength. The IO buffer diagram is as follows.
Figure 9-69 IO Buffer Strength Diagram
VCC
P0 P1 P2 P3
ro ro ro ro
ro ro ro ro
n0 n1 n2 n3
GND
When output high level, the n0, n1, n2, n3 of NMOS is off, the p0, p1, p2, p3 of PMOS is on. When the buffer
strength is set to 0 (buffer strength is weakest), only the p0 is on, the output impedance is maximum, the
impedance value is r0. When the buffer strength is set to 1, only the p0 and p1 is on, the output impedance is
equivalent to two r0 in parallel, the impedance value is r0/2. When the buffer strength is 2, only the p0, p1,
and p2 is on, the output impedance is equivalent to three r0 in parallel, the impedance value is r0/3. When
buffer strength is 3, the p0, p1, p2, and p3 is on, the output impedance is equivalent to four r0 in parallel, the
impedance value is r0/4.
When output low level, the p0, p1, p2, p3 of PMOS is off, the n0, n1, n2, n3 of NMOS is on. When the buffer
strength is set to 0 (buffer strength is weakest), only the n0 is on, the output impedance is maximum, the
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impedance value is r0. When the buffer strength is set to 1, only the n0 and n1 is on, the output impedance is
equivalent to two r0 in parallel, the impedance value is r0/2. When the buffer strength is 2, only the n0, n1,
and n2 is on, the output impedance is equivalent to three r0 in parallel, the impedance value is r0/3. When the
buffer strength is 3, the n0, n1, n2, and n3 is on, the output impedance is equivalent to four r0 in parallel, the
impedance value is r0/4.
When GPIO is set to input or interrupt function, between the output driver circuit and the port is unconnected,
the driver configuration is invalid.
NOTE
The typical value of r0 is 180Ω.
9.7.3.6 Interrupt
Each group IO has an independent interrupt number. The IO within-group uses one interrupt number when
one IO generates interrupt, the GPIO pins sent interrupt request to interrupt module. External Interrupt Status
Register is used to query which IO generates interrupt.
The interrupt trigger of GPIO supports the following trigger types.
Positive Edge: When a low level changes to a high level, the interrupt will generate. No matter how long
a high level keeps, the interrupt generates only once.
Negative Edge: When a high level changes to a low level, the interrupt will generate. No matter how long
a low level keeps, the interrupt generates only once.
High Level: Just keep a high level and the interrupt will always generate.
Low Level: Just keep a low level and the interrupt will always generate.
Double Edge: Positive and negative edge.
External Interrupt Configure Register is used to configure the trigger type.
The GPIO interrupt supports hardware debounce function by setting External Interrupt Debounce Register.
Sample trigger signal using a lower sample clock, to reach the debounce effect because the dither frequency
of the signal is higher than the sample frequency.
Set the sample clock source by PIO_INT_CLK_SELECT and the prescale factor by DEB_CLK_PRE_SCALE.
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9.7.4 Register List
Module Name Base Address
GPIO 0x02000000
Register Name Offset Description
PB_CFG0 0x0030 PB Configure Register 0
PB_CFG1 0x0034 PB Configure Register 1
PB_DAT 0x0040 PB Data Register
PB_DRV0 0x0044 PB Multi_Driving Register 0
PB_DRV1 0x0048 PB Multi_Driving Register 1
PB_PULL0 0x0054 PB Pull Register 0
PC_CFG0 0x0060 PC Configure Register 0
PC_DAT 0x0070 PC Data Register
PC_DRV0 0x0074 PC Multi_Driving Register 0
PC_PULL0 0x0084 PC Pull Register 0
PD_CFG0 0x0090 PD Configure Register 0
PD_CFG1 0x0094 PD Configure Register 1
PD_CFG2 0x0098 PD Configure Register 2
PD_DAT 0x00A0 PD Data Register
PD_DRV0 0x00A4 PD Multi_Driving Register 0
PD_DRV1 0x00A8 PD Multi_Driving Register 1
PD_DRV2 0x00AC PD Multi_Driving Register 2
PD_PULL0 0x00B4 PD Pull Register 0
PD_PULL1 0x00B8 PD Pull Register 1
PE_CFG0 0x00C0 PE Configure Register 0
PE_CFG1 0x00C4 PE Configure Register 1
PE_DAT 0x00D0 PE Data Register
PE_DRV0 0x00D4 PE Multi_Driving Register 0
PE_DRV1 0x00D8 PE Multi_Driving Register 1
PE_PULL0 0x00E4 PE Pull Register 0
PF_CFG0 0x00F0 PF Configure Register 0
PF_DAT 0x0100 PF Data Register
PF_DRV0 0x0104 PF Multi_Driving Register 0
PF_PULL0 0x0114 PF Pull Register 0
PG_CFG0 0x0120 PG Configure Register 0
PG_CFG1 0x0124 PG Configure Register 1
PG_DAT 0x0130 PG Data Register
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Register Name Offset Description
PG_DRV0 0x0134 PG Multi_Driving Register 0
PG_DRV1 0x0138 PG Multi_Driving Register 1
PG_DRV3 0x0140 PG Multi_Driving Register 3
PG_PULL0 0x0144 PG Pull Register 0
PB_EINT_CFG0 0x0220 PB External Interrupt Configure Register 0
PB_EINT_CTL 0x0230 PB External Interrupt Control Register
PB_EINT_STATUS 0x0234 PB External Interrupt Status Register
PB_EINT_DEB 0x0238 PB External Interrupt Debounce Register
PC_EINT_CFG0 0x0240 PC External Interrupt Configure Register 0
PC_EINT_CTL 0x0250 PC External Interrupt Control Register
PC_EINT_STATUS 0x0254 PC External Interrupt Status Register
PC_EINT_DEB 0x0258 PC External Interrupt Debounce Register
PD_EINT_CFG0 0x0260 PD External Interrupt Configure Register 0
PD_EINT_CFG1 0x0264 PD External Interrupt Configure Register 1
PD_EINT_CFG2 0x0268 PD External Interrupt Configure Register 2
PD_EINT_CTL 0x0270 PD External Interrupt Control Register
PD_EINT_STATUS 0x0274 PD External Interrupt Status Register
PD_EINT_DEB 0x0278 PD External Interrupt Debounce Register
PE_EINT_CFG0 0x0280 PE External Interrupt Configure Register 0
PE_EINT_CFG1 0x0284 PE External Interrupt Configure Register 1
PE_EINT_CTL 0x0290 PE External Interrupt Control Register
PE_EINT_STATUS 0x0294 PE External Interrupt Status Register
PE_EINT_DEB 0x0298 PE External Interrupt Debounce Register
PF_EINT_CFG0 0x02A0 PF External Interrupt Configure Register 0
PF_EINT_CTL 0x02B0 PF External Interrupt Control Register
PF_EINT_STATUS 0x02B4 PF External Interrupt Status Register
PF_EINT_DEB 0x02B8 PF External Interrupt Debounce Register
PG_EINT_CFG0 0x02C0 PG External Interrupt Configure Register 0
PG_EINT_CFG1 0x02C4 PG External Interrupt Configure Register 1
PG_EINT_CTL 0x02D0 PG External Interrupt Control Register
PG_EINT_STATUS 0x02D4 PG External Interrupt Status Register
PG_EINT_DEB 0x02D8 PG External Interrupt Debounce Register
PIO Group Withstand Voltage Mode Select
PIO_POW_MOD_SEL 0x0340 Register
PIO Group Withstand Voltage Mode Select Control
PIO_POW_MS_CTL 0x0344 Register
PIO_POW_VAL 0x0348 PIO Group Power Value Register
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Register Name Offset Description
PIO_POW_VOL_SEL_CTL 0x0350 PIO Group Power Voltage Select Control Register
9.7.5 Register Description
9.7.5.1 0x0030 PB Configure Register 0 (Default Value: 0xFFFF_FFFF)
Offset: 0x0030 Register Name: PB_CFG0
Bit Read/Write Default/Hex Description
PB7_SELECT
PB7 Select
0000:Input 0001:Output
0010:LCD0-D17 0011:I2S2-MCLK
31:28 R/W 0xF
0100:TWI3-SDA 0101:IR-RX
0110:LCD0-D23 0111:UART3-RX
1000:CPUBIST1 1001:Reserved
1110:PB-EINT7 1111:IO Disable
PB6_SELECT
PB6 Select
0000:Input 0001:Output
0010:LCD0-D16 0011:I2S2-LRCK
27:24 R/W 0xF
0100:TWI3-SCK 0101:PWM1
0110:LCD0-D22 0111:UART3-TX
1000:CPUBIST0 1001:Reserved
1110:PB-EINT6 1111:IO Disable
PB5_SELECT
PB5 Select
0000:Input 0001:Output
0010:LCD0-D9 0011:I2S2-BCLK
23:20 R/W 0xF
0100:TWI1-SDA 0101:PWM0
0110:LCD0-D21 0111:UART5-RX
1000:Reserved 1001:Reserved
1110:PB-EINT5 1111:IO Disable
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Offset: 0x0030 Register Name: PB_CFG0
Bit Read/Write Default/Hex Description
PB4_SELECT
PB4 Select
0000:Input 0001:Output
0010:LCD0-D8 0011:I2S2-DOUT0
19:16 R/W 0xF
0100:TWI1-SCK 0101:I2S2-DIN1
0110:LCD0-D20 0111:UART5-TX
1000:Reserved 1001:Reserved
1110:PB-EINT4 1111:IO Disable
PB3_SELECT
PB3 Select
0000:Input 0001:Output
0010:LCD0-D1 0011:I2S2-DOUT1
15:12 R/W 0xF
0100:TWI0-SCK 0101:I2S2-DIN0
0110:LCD0-D19 0111:UART4-RX
1000:Reserved 1001:Reserved
1110:PB-EINT3 1111:IO Disable
PB2_SELECT
PB2 Select
0000:Input 0001:Output
0010:LCD0-D0 0011:I2S2-DOUT2
11:8 R/W 0xF
0100:TWI0-SDA 0101:I2S2-DIN2
0110:LCD0-D18 0111:UART4-TX
1000:Reserved 1001:Reserved
1110:PB-EINT2 1111:IO Disable
7:4 R/W 0xF Reserved
3:0 R/W 0xF Reserved
9.7.5.2 0x0034 PB Configure Register 1 (Default Value: 0x000F_FFFF)
Offset: 0x0034 Register Name: PB_CFG1
Bit Read/Write Default/Hex Description
31:20 / / /
19:16 R/W 0xF Reserved
15:12 R/W 0xF Reserved
11:8 R/W 0xF Reserved
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Offset: 0x0034 Register Name: PB_CFG1
Bit Read/Write Default/Hex Description
7:4 R/W 0xF Reserved
3:0 R/W 0xF Reserved
9.7.5.3 0x0040 PB Data Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: PB_DAT
Bit Read/Write Default/Hex Description
31:8 / / /
PB_DAT
If the port is configured as the input function, the corresponding
bit is the pin state. If the port is configured as the output function,
7:0 R/W 0x0
the pin state is the same as the corresponding bit. The read bit
value is the value set up by software. If the port is configured as
a functional pin, the undefined value will be read.
9.7.5.4 0x0044 PB Multi_Driving Register 0 (Default Value: 0x1111_1111)
Offset: 0x0044 Register Name: PB_DRV0
Bit Read/Write Default/Hex Description
31:30 / / /
PB7_DRV
PB7 Multi_Driving Select
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PB6_DRV
PB6 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PB5_DRV
PB5 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
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Offset: 0x0044 Register Name: PB_DRV0
Bit Read/Write Default/Hex Description
19:18 / / /
PB4_DRV
PB4 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PB3_DRV
PB3 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PB2_DRV
PB2 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
5:4 R/W 0x1 Reserved
3:2 / / /
1:0 R/W 0x1 Reserved
9.7.5.5 0x0048 PB Multi_Driving Register 1 (Default Value: 0x0001_1111)
Offset: 0x0048 Register Name: PB_DRV1
Bit Read/Write Default/Hex Description
31:18 / / /
17:16 R/W 0x1 Reserved
15:14 / / /
13:12 R/W 0x1 Reserved
11:10 / / /
9:8 R/W 0x1 Reserved
7:6 / / /
5:4 R/W 0x1 Reserved
3:2 / / /
1:0 R/W 0x1 Reserved
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9.7.5.6 0x0054 PB Pull Register 0 (Default Value: 0x0000_0000)
Offset: 0x0054 Register Name: PB_PULL0
Bit Read/Write Default/Hex Description
31:16 / / /
PB7_PULL
PB7 Pull_up or down Select
15:14 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PB6_PULL
PB6 Pull_up or down Select
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PB5_PULL
PB5 Pull_up or down Select
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PB4_PULL
PB4 Pull_up or down Select
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PB3_PULL
PB3 Pull_up or down Select
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PB2_PULL
PB2 Pull_up or down Select
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
3:2 R/W 0x0 Reserved
1:0 R/W 0x0 Reserved
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9.7.5.7 0x0060 PC Configure Register 0 (Default Value: 0xFFFF_FFFF)
Offset: 0x0060 Register Name: PC_CFG0
Bit Read/Write Default/Hex Description
PC7_SELECT
PC7 Select
0000:Input 0001:Output
0010:SPI0-HOLD 0011:SDC2-D3
31:28 R/W 0xF
0100:UART3-RX 0101:TWI3-SDA
0110:TCON-TRIG 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT7 1111:IO Disable
PC6_SELECT
PC6 Select
0000:Input 0001:Output
0010:SPI0-WP 0011:SDC2-D0
27:24 R/W 0xF
0100:UART3-TX 0101:TWI3-SCK
0110:DBG-CLK 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT6 1111:IO Disable
PC5_SELECT
PC5 Select
0000:Input 0001:Output
0010:SPI0-MISO 0011:SDC2-D1
23:20 R/W 0xF
0100:BOOT-SEL1 0101:Reserved
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT5 1111:IO Disable
PC4_SELECT
PC4 Select.
0000:Input 0001:Output
0010:SPI0-MOSI 0011:SDC2-D2
19:16 R/W 0xF
0100:BOOT-SEL0 0101:Reserved
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT4 1111:IO Disable
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Offset: 0x0060 Register Name: PC_CFG0
Bit Read/Write Default/Hex Description
PC3_SELECT
PC3 Select
0000:Input 0001:Output
0010:SPI0-CS0 0011:SDC2-CMD
15:12 R/W 0xF
0100:Reserved 0101:Reserved
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT3 1111:IO Disable
PC2_SELECT
PC2 Select
0000:Input 0001:Output
0010:SPI0-CLK 0011:SDC2-CLK
11:8 R/W 0xF
0100:Reserved 0101:Reserved
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PC-EINT2 1111:IO Disable
7:4 R/W 0xF Reserved
3:0 R/W 0xF Reserved
9.7.5.8 0x0070 PC Data Register (Default Value: 0x0000_0000)
Offset: 0x0070 Register Name: PC_DAT
Bit Read/Write Default/Hex Description
31:8 / / /
PC_DAT
If the port is configured as the input function, the corresponding
bit is the pin state. If the port is configured as the output
7:0 R/W 0x0
function, the pin state is the same as the corresponding bit. The
read bit value is the value set up by software. If the port is
configured as a functional pin, the undefined value will be read.
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9.7.5.9 0x0074 PC Multi_Driving Register 0 (Default Value: 0x1111_1111)
Offset: 0x0074 Register Name: PC_DRV0
Bit Read/Write Default/Hex Description
31:30 / / /
PC7_DRV
PC7 Multi_Driving Select
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PC6_DRV
PC6 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PC5_DRV
PC5 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PC4_DRV
PC4 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PC3_DRV
PC3 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PC2_DRV
PC2 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
5:4 R/W 0x1 Reserved
3:2 / / /
1:0 R/W 0x1 Reserved
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9.7.5.10 0x0084 PC Pull Register 0 (Default Value: 0x0000_0540)
Offset: 0x0084 Register Name: PC_PULL0
Bit Read/Write Default/Hex Description
31:16 / / /
PC7_PULL
PC7 Pull_up/down Select
15:14 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PC6_PULL
PC6 Pull_up/down Select
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PC5_PULL
PC5 Pull_up/down Select
11:10 R/W 0x1
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PC4_PULL
PC4 Pull_up/down Select
9:8 R/W 0x1
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PC3_PULL
PC3 Pull_up/down Select
7:6 R/W 0x1
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PC2_PULL
PC2 Pull_up/down Select
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
3:2 R/W 0x0 Reserved
1:0 R/W 0x0 Reserved
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9.7.5.11 0x0090 PD Configure Register 0 (Default Value: 0xFFFF_FFFF)
Offset: 0x0090 Register Name: PD_CFG0
Bit Read/Write Default/Hex Description
PD7_SELECT
PD7 Select
0000:Input 0001:Output
0010:LCD0-D11 0011:LVDS0-CKN
31:28 R/W 0xF
0100:DSI-D2N 0101:UART4-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT7 1111:IO Disable
PD6_SELECT
PD6 Select
0000:Input 0001:Output
0010:LCD0-D10 0011:LVDS0-CKP
27:24 R/W 0xF
0100:DSI-D2P 0101:UART5-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT6 1111:IO Disable
PD5_SELECT
PD5 Select
0000:Input 0001:Output
0010:LCD0-D7 0011:LVDS0-V2N
23:20 R/W 0xF
0100:DSI-CKN 0101:UART5-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT5 1111:IO Disable
PD4_SELECT
PD4 Select
0000:Input 0001:Output
0010:LCD0-D6 0011:LVDS0-V2P
19:16 R/W 0xF
0100:DSI-CKP 0101:UART2-CTS
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT4 1111:IO Disable
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Offset: 0x0090 Register Name: PD_CFG0
Bit Read/Write Default/Hex Description
PD3_SELECT
PD3 Select
0000:Input 0001:Output
0010:LCD0-D5 0011:LVDS0-V1N
15:12 R/W 0xF
0100:DSI-D1N 0101:UART2-RTS
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT3 1111:IO Disable
PD2_SELECT
PD2 Select
0000:Input 0001:Output
0010:LCD0-D4 0011:LVDS0-V1P
11:8 R/W 0xF
0100:DSI-D1P 0101:UART2-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT2 1111:IO Disable
PD1_SELECT
PD1 Select
0000:Input 0001:Output
0010:LCD0-D3 0011:LVDS0-V0N
7:4 R/W 0xF
0100:DSI-D0N 0101:UART2-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT1 1111:IO Disable
PD0_SELECT
PD0 Select
0000:Input 0001:Output
0010:LCD0-D2 0011:LVDS0-V0P
3:0 R/W 0xF
0100:DSI-D0P 0101:TWI0-SCK
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT0 1111:IO Disable
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9.7.5.12 0x0094 PD Configure Register 1 (Default Value: 0xFFFF_FFFF)
Offset: 0x0094 Register Name: PD_CFG1
Bit Read/Write Default/Hex Description
PD15_SELECT
PD15 Select
0000:Input 0001:Output
0010:LCD0-D21 0011:LVDS1-V2N
31:28 R/W 0xF
0100:SPI1-WP/DBI-TE 0101:IR-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT15 1111:IO Disable
PD14_SELECT
PD14 Select
0000:Input 0001:Output
0010:LCD0-D20 0011:LVDS1-V2P
27:24 R/W 0xF
0100:SPI1-HOLD/DBI-DCX/DBI-WRX 0101:UART3-CTS
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT14 1111:IO Disable
PD13_SELECT
PD13 Select
0000:Input 0001:Output
0010:LCD0-D19 0011:LVDS1-V1N
23:20 R/W 0xF
0100:SPI1-MISO/DBI-SDI/DBI-TE/DBI-DCX 0101:UART3-RTS
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT13 1111:IO Disable
PD12_SELECT
PD12 Select
0000:Input 0001:Output
0010:LCD0-D18 0011:LVDS1-V1P
19:16 R/W 0xF
0100:SPI1-MOSI/DBI-SDO 0101:TWI0-SDA
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT12 1111:IO Disable
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Offset: 0x0094 Register Name: PD_CFG1
Bit Read/Write Default/Hex Description
PD11_SELECT
PD11 Select
0000:Input 0001:Output
0010:LCD0-D15 0011:LVDS1-V0N
15:12 R/W 0xF
0100:SPI1-CLK/DBI-SCLK 0101:UART3-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT11 1111:IO Disable
PD10_SELECT
PD10 Select
0000:Input 0001:Output
0010:LCD0-D14 0011:LVDS1-V0P
11:8 R/W 0xF
0100:SPI1-CS/DBI-CSX 0101:UART3-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT10 1111:IO Disable
PD9_SELECT
PD9 Select
0000:Input 0001:Output
0010:LCD0-D13 0011:LVDS0-V3N
7:4 R/W 0xF
0100:DSI-D3N 0101:PWM6
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT9 1111:IO Disable
PD8_SELECT
PD8 Select
0000:Input 0001:Output
0010:LCD0-D12 0011:LVDS0-V3P
3:0 R/W 0xF
0100:DSI-D3P 0101:UART4-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT8 1111:IO Disable
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9.7.5.13 0x0098 PD Configure Register 2 (Default Value: 0x0FFF_FFFF)
Offset: 0x0098 Register Name: PD_CFG2
Bit Read/Write Default/Hex Description
31:28 / / /
PD22_SELECT
PD22 Select
0000:Input 0001:Output
0010:OWA-OUT 0011:IR-RX
27:24 R/W 0xF
0100:UART1-RX 0101:PWM7
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT22 1111:IO Disable
PD21_SELECT
PD21 Select
0000:Input 0001:Output
0010:LCD0-VSYNC 0011:TWI2-SDA
23:20 R/W 0xF
0100:UART1-TX 0101:PWM5
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT21 1111:IO Disable
PD20_SELECT
PD20 Select
0000:Input 0001:Output
0010:LCD0-HSYNC 0011:TWI2-SCK
19:16 R/W 0xF
0100:DMIC-CLK 0101:PWM4
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT20 1111:IO Disable
PD19_SELECT
PD19 Select
0000:Input 0001:Output
0010:LCD0-DE 0011:LVDS1-V3N
15:12 R/W 0xF
0100:DMIC-DATA0 0101:PWM3
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT19 1111:IO Disable
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Offset: 0x0098 Register Name: PD_CFG2
Bit Read/Write Default/Hex Description
PD18_SELECT
PD18 Select
0000:Input 0001:Output
0010:LCD0-CLK 0011:LVDS1-V3P
11:8 R/W 0xF
0100:DMIC-DATA1 0101:PWM2
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT18 1111:IO Disable
PD17_SELECT
PD17 Select.
0000:Input 0001:Output
0010:LCD0-D23 0011:LVDS1-CKN
7:4 R/W 0xF
0100:DMIC-DATA2 0101:PWM1
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT17 1111:IO Disable
PD16_SELECT
PD16 Select
0000:Input 0001:Output
0010:LCD0-D22 0011:LVDS1-CKP
3:0 R/W 0xF
0100:DMIC-DATA3 0101:PWM0
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PD-EINT16 1111:IO Disable
9.7.5.14 0x00A0 PD Data Register (Default Value: 0x0000_0000)
Offset: 0x00A0 Register Name: PD_DAT
Bit Read/Write Default/Hex Description
31:23 / / /
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Offset: 0x00A0 Register Name: PD_DAT
Bit Read/Write Default/Hex Description
PD_DAT
PD Data
If the port is configured as the input function, the corresponding
22:0 R/W 0x0 bit is the pin state. If the port is configured as the output function,
the pin state is the same as the corresponding bit. The read bit
value is the value set up by software. If the port is configured as
a functional pin, the undefined value will be read.
9.7.5.15 0x00A4 PD Multi_Driving Register 0 (Default Value: 0x1111_1111)
Offset: 0x00A4 Register Name: PD_DRV0
Bit Read/Write Default/Hex Description
31:30 / / /
PD7_DRV
PD7 Multi_Driving Select.
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PD6_DRV
PD6 Multi_Driving Select.
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PD5_DRV
PD5 Multi_Driving Select.
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PD4_DRV
PD4 Multi_Driving Select.
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
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Offset: 0x00A4 Register Name: PD_DRV0
Bit Read/Write Default/Hex Description
PD3_DRV
PD3 Multi_Driving Select.
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PD2_DRV
PD2 Multi_Driving Select.
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PD1_DRV
PD1 Multi_Driving Select.
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PD0_DRV
PD0 Multi_Driving Select.
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.16 0x00A8 PD Multi_Driving Register 1 (Default Value: 0x1111_1111)
Offset: 0x00A8 Register Name: PD_DRV1
Bit Read/Write Default/Hex Description
31:30 / / /
PD15_DRV
PD15 Multi_Driving Select.
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PD14_DRV
PD14 Multi_Driving Select.
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
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Offset: 0x00A8 Register Name: PD_DRV1
Bit Read/Write Default/Hex Description
PD13_DRV
PD13 Multi_Driving Select.
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PD12_DRV
PD12 Multi_Driving Select.
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PD11_DRV
PD11 Multi_Driving Select.
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PD10_DRV
PD10 Multi_Driving Select.
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PD9_DRV
PD9 Multi_Driving Select.
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PD8_DRV
PD8 Multi_Driving Select.
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.17 0x00AC PD Multi_Driving Register 2 (Default Value: 0x0111_1111)
Offset: 0x00AC Register Name: PD_DRV2
Bit Read/Write Default/Hex Description
31:26 / / /
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Offset: 0x00AC Register Name: PD_DRV2
Bit Read/Write Default/Hex Description
PD22_DRV
PD22 Multi_Driving Select.
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PD21_DRV
PD21 Multi_Driving Select.
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PD20_DRV
PD20 Multi_Driving Select.
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PD19_DRV
PD19 Multi_Driving Select.
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PD18_DRV
PD18 Multi_Driving Select.
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PD17_DRV
PD17 Multi_Driving Select.
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PD16_DRV
PD16 Multi_Driving Select.
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
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9.7.5.18 0x00B4 PD Pull Register 0 (Default Value: 0x0000_0000)
Offset: 0x00B4 Register Name: PD_PULL0
Bit Read/Write Default/Hex Description
PD15_PULL
PD15 Pull_up or down Select.
31:30 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD14_PULL
PD14 Pull_up or down Select.
29:28 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD13_PULL
PD13 Pull_up or down Select.
27:26 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD12_PULL
PD12 Pull_up or down Select.
25:24 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD11_PULL
PD11 Pull_up or down Select.
23:22 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD10_PULL
PD10 Pull_up or down Select.
21:20 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD9_PULL
PD9 Pull_up or down Select.
19:18 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD8_PULL
PD8 Pull_up or down Select.
17:16 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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Offset: 0x00B4 Register Name: PD_PULL0
Bit Read/Write Default/Hex Description
PD7_PULL
PD7 Pull_up or down Select.
15:14 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD6_PULL
PD6 Pull_up or down Select.
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD5_PULL
PD5 Pull_up or down Select.
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD4_PULL
PD4 Pull_up or down Select.
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD3_PULL
PD3 Pull_up or down Select.
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD2_PULL
PD2 Pull_up or down Select.
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD1_PULL
PD1 Pull_up or down Select.
3:2 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD0_PULL
PD0 Pull_up or down Select.
1:0 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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9.7.5.19 0x00B8 PD Pull Register 1 (Default Value: 0x0000_0000)
Offset: 0x00B8 Register Name: PD_PULL1
Bit Read/Write Default/Hex Description
31:14 / / /
PD22_PULL
PD22 Pull_up or down Select.
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD21_PULL
PD21 Pull_up or down Select.
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD20_PULL
PD20 Pull_up or down Select.
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD19_PULL
PD19 Pull_up or down Select.
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD18_PULL
PD18 Pull_up or down Select.
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD17_PULL
PD17 Pull_up or down Select.
3:2 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PD16_PULL
PD16 Pull_up or down Select.
1:0 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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9.7.5.20 0x00C0 PE Configure Register 0 (Default Value: 0xFFFF_FFFF)
Offset: 0x00C0 Register Name: PE_CFG0
Bit Read/Write Default/Hex Description
PE7_SELECT
PE7 Select
0000:Input 0001:Output
0010:NCSI0-D3 0011:UART5-RX
31:28 R/W 0xF
0100:TWI3-SDA 0101:OWA-OUT
0110:Reserved 0111:R-JTAG-CK
1000:RGMII-CLKIN/RMII-RXER 1001:Reserved
1110:PE-EINT7 1111:IO Disable
PE6_SELECT
PE6 Select
0000:Input 0001:Output
0010:NCSI0-D2 0011:UART5-TX
27:24 R/W 0xF
0100:TWI3-SCK 0101:OWA-IN
0110:Reserved 0111:R-JTAG-DO
1000:RMII-TXCTRL/RMII-TXEN 1001:Reserved
1110:PE-EINT6 1111:IO Disable
PE5_SELECT
PE5 Select
0000:Input 0001:Output
0010:NCSI0-D1 0011:UART4-RX
23:20 R/W 0xF
0100:TWI2-SDA 0101:LEDC-DO
0110:Reserved 0111:R-JTAG-DI
1000:RGMII-TXD1/RMII-TXD1 1001:Reserved
1110:PE-EINT5 1111:IO Disable
PE4_SELECT
PE4 Select
0000:Input 0001:Output
0010:NCSI0-D0 0011:UART4-TX
19:16 R/W 0xF
0100:TWI2-SCK 0101:CLK-FANOUT2
0110:Reserved 0111:R-JTAG-MS
1000:RGMII-TXD0/RMII-TXD0 1001:Reserved
1110:PE-EINT4 1111:IO Disable
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Offset: 0x00C0 Register Name: PE_CFG0
Bit Read/Write Default/Hex Description
PE3_SELECT
PE3 Select
0000:Input 0001:Output
0010:NCSI0-MCLK 0011:UART2-RX
15:12 R/W 0xF
0100:TWI0-SDA 0101:CLK-FANOUT1
0110:UART0-RX 0111:Reserved
1000:RGMII-TXCK/RMII-TXCK 1001:Reserved
1110:PE-EINT3 1111:IO Disable
PE2_SELECT
PE2 Select
0000:Input 0001:Output
0010:NCSI0-PCLK 0011:UART2-TX
11:8 R/W 0xF
0100:TWI0-SCK 0101:CLK-FANOUT0
0110:UART0-TX 0111:Reserved
1000:RGMII-RXD1/RMII-RXD1 1001:Reserved
1110:PE-EINT2 1111:IO Disable
PE1_SELECT
PE1 Select
0000:Input 0001:Output
0010:NCSI0-VSYNC 0011:UART2-CTS
7:4 R/W 0xF
0100:TWI1-SDA 0101:LCD0-VSYNC
0110:Reserved 0111:Reserved
1000:RGMII-RXD0/RMII-RXD0 1001:Reserved
1110:PE-EINT1 1111:IO Disable
PE0_SELECT
PE0 Select
0000:Input 0001:Output
0010:NCSI0-HSYNC 0011:UART2-RTS
3:0 R/W 0xF
0100:TWI1-SCK 0101:LCD0-HSYNC
0110:Reserved 0111:Reserved
1000:RGMII-RXCTRL/RMII-CRS-DV 1001:Reserved
1110:PE-EINT0 1111:IO Disable
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9.7.5.21 0x00C4 PE Configure Register 1 (Default Value: 0xFFFF_FFFF)
Offset: 0x00C4 Register Name: PE_CFG1
Bit Read/Write Default/Hex Description
31:28 R/W 0xF Reserved
27:24 R/W 0xF Reserved
PE13_SELECT
PE13 Select
0000:Input 0001:Output
0010:TWI2-SDA 0011:PWM5
23:20 R/W 0xF
0100:Reserved 0101:Reserved
0110:DMIC-DATA3 0111:Reserved
1000:RGMII-RXD2 1001:Reserved
1110:PE-EINT13 1111:IO Disable
PE12_SELECT
PE12 Select
0000:Input 0001:Output
0010:TWI2-SCK 0011:NCSI0-FIELD
19:16 R/W 0xF
0100:Reserved 0101:Reserved
0110:Reserved 0111:Reserved
1000:RGMII-TXD3 1001:Reserved
1110:PE-EINT12 1111:IO Disable
PE11_SELECT
PE11 Select
0000:Input 0001:Output
0010:NCSI0-D7 0011:UART1-RX
15:12 R/W 0xF
0100:Reserved 0101:Reserved
0110:Reserved 0111:Reserved
1000:RGMII-TXD2 1001:Reserved
1110:PE-EINT11 1111:IO Disable
PE10_SELECT
PE10 Select
0000:Input 0001:Output
0010:NCSI0-D6 0011:UART1-TX
11:8 R/W 0xF
0100:PWM4 0101:IR-RX
0110:Reserved 0111:Reserved
1000:EPHY-25M 1001:Reserved
1110:PE-EINT10 1111:IO Disable
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Offset: 0x00C4 Register Name: PE_CFG1
Bit Read/Write Default/Hex Description
PE9_SELECT
PE9 Select
0000:Input 0001:Output
0010:NCSI0-D5 0011:UART1-CTS
7:4 R/W 0xF
0100:PWM3 0101:UART3-RX
0110:Reserved 0111:Reserved
1000:MDIO 1001:Reserved
1110:PE-EINT9 1111:IO Disable
PE8_SELECT
PE8 Select
0000:Input 0001:Output
0010:NCSI0-D4 0011:UART1-RTS
3:0 R/W 0xF
0100:PWM_2 0101:UART3-TX
0110:Reserved 0111:Reserved
1000:MDC 1001:Reserved
1110:PE_EINT8 1111:IO Disable
9.7.5.22 0x00D0 PE Data Register (Default Value: 0x0000_0000)
Offset: 0x00D0 Register Name: PE_DAT
Bit Read/Write Default/Hex Description
31:14 / / /
PE_DAT
PE Data
If the port is configured as input, the corresponding bit is the pin
13:0 R/W 0x0 state. If the port is configured as output, the pin state is the same
as the corresponding bit. The read bit value is the value setup by
software. If the port is configured as functional pin, the
undefined value will be read.
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9.7.5.23 0x00D4 PE Multi_Driving Register 0 (Default Value: 0x1111_1111)
Offset: 0x00D4 Register Name: PE_DRV0
Bit Read/Write Default/Hex Description
31:30 / / /
PE7_DRV
PE7 Multi_Driving Select
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PE6_DRV
PE6 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PE5_DRV
PE5 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PE4_DRV
PE4 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PE3_DRV
PE3 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PE2_DRV
PE2 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
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Offset: 0x00D4 Register Name: PE_DRV0
Bit Read/Write Default/Hex Description
PE1_DRV
PE1 Multi_Driving Select
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PE0_DRV
PE0 Multi_Driving Select
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.24 0x00D8 PE Multi_Driving Register 1 (Default Value: 0x1111_1111)
Offset: 0x00D8 Register Name: PE_DRV1
Bit Read/Write Default/Hex Description
31:30 / / /
29:28 R/W 0x1 Reserved
27:26 / / /
25:24 R/W 0x1 Reserved
23:22 / / /
PE13_DRV
PE13 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PE12_DRV
PE12 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PE11_DRV
PE11 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
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Offset: 0x00D8 Register Name: PE_DRV1
Bit Read/Write Default/Hex Description
PE10_DRV
PE10 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PE9_DRV
PE9 Multi_Driving Select
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PE8_DRV
PE8 Multi_Driving Select
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.25 0x00E4 PE Pull Register 0 (Default Value: 0x0000_0000)
Offset: 0x00E4 Register Name: PE_PULL0
Bit Read/Write Default/Hex Description
31:30 R/W 0x0 Reserved
29:28 R/W 0x0 Reserved
PE13_PULL
PE13 Pull_up or down Select
27:26 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE12_PULL
PE12 Pull_up or down Select
25:24 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE11_PULL
PE11 Pull_up or down Select
23:22 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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Offset: 0x00E4 Register Name: PE_PULL0
Bit Read/Write Default/Hex Description
PE10_PULL
PE10 Pull_up or down Select
21:20 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE9_PULL
PE9 Pull_up or down Select
19:18 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE8_PULL
PE8 Pull_up or down Select
17:16 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE7_PULL
PE7 Pull_up or down Select
15:14 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE6_PULL
PE6 Pull_up or down Select
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE5_PULL
PE5 Pull_up or down Select
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE4_PULL
PE4 Pull_up or down Select
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE3_PULL
PE3 Pull_up or down Select
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE2_PULL
PE2 Pull_up or down Select
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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Offset: 0x00E4 Register Name: PE_PULL0
Bit Read/Write Default/Hex Description
PE1_PULL
PE1 Pull_up or down Select
3:2 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PE0_PULL
PE0 Pull_up or down Select
1:0 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
9.7.5.26 0x00F0 PF Configure Register 0 (Default Value: 0x0FFF_FFFF)
Offset: 0x00F0 Register Name: PF_CFG0
Bit Read/Write Default/Hex Description
31:28 / / /
PF6_SELECT
PF6 Select
0000:Input 0001:Output
0010:Reserved 0011:OWA-OUT
27:24 R/W 0xF
0100:IR-RX 0101:I2S2-MCLK
0110:PWM5 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT6 1111:IO Disable
PF5_SELECT
PF5 Select
0000:Input 0001:Output
0010:SDC0-D2 0011:Reserved
23:20 R/W 0xF
0100:R-JTAG-CK 0101:I2S2-LRCK
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT5 1111:IO Disable
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Offset: 0x00F0 Register Name: PF_CFG0
Bit Read/Write Default/Hex Description
PF4_SELECT
PF4 Select
0000:Input 0001:Output
0010:SDC0-D3 0011:UART0-RX
19:16 R/W 0xF
0100:TWI0-SDA 0101:PWM6
0110:IR-TX 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT4 1111:IO Disable
PF3_SELECT
PF3 Select
0000:Input 0001:Output
0010:SDC0-CMD 0011:Reserved
15:12 R/W 0xF
0100:R-JTAG-DO 0101:I2S2-BCLK
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT3 1111:IO Disable
PF2_SELECT
PF2 Select
0000:Input 0001:Output
0010:SDC0-CLK 0011:UART0-TX
11:8 R/W 0xF
0100:TWI0-SCK 0101:LEDC-DO
0110:OWA-IN 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT2 1111:IO Disable
PF1_SELECT
PF1 Select
0000:Input 0001:Output
0010:SDC0-D0 0011:Reserved
7:4 R/W 0xF
0100:R-JTAG-DI 0101:I2S2-DOUT0
0110:I2S2-DIN1 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT1 1111:IO Disable
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Offset: 0x00F0 Register Name: PF_CFG0
Bit Read/Write Default/Hex Description
PF0_SELECT
PF0 Select
0000:Input 0001:Output
0010:SDC0-D1 0011:Reserved
3:0 R/W 0xF
0100:R-JTAG-MS 0101:I2S2-DOUT1
0110:I2S2-DIN0 0111:Reserved
1000:Reserved 1001:Reserved
1110:PF-EINT0 1111:IO Disable
9.7.5.27 0x0100 PF Data Register (Default Value: 0x0000_0000)
Offset: 0x0100 Register Name: PF_DAT
Bit Read/Write Default/Hex Description
31:7 / / /
PF_DAT
PF Data
If the port is configured as input, the corresponding bit is the pin
6:0 R/W 0 state. If the port is configured as output, the pin state is the same
as the corresponding bit. The read bit value is the value setup by
software. If the port is configured as functional pin, the
undefined value will be read.
9.7.5.28 0x0104 PF Multi_Driving Register 0 (Default Value: 0x0111_1111)
Offset: 0x0104 Register Name: PF_DRV0
Bit Read/Write Default/Hex Description
31:26 / / /
PF6_DRV
PF6 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
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Offset: 0x0104 Register Name: PF_DRV0
Bit Read/Write Default/Hex Description
PF5_DRV
PF5 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PF4_DRV
PF4 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PF3_DRV
PF3 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PF2_DRV
PF2 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PF1_DRV
PF1 Multi_Driving Select
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PF0_DRV
PF0 Multi_Driving Select
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.29 0x0114 PF Pull Register 0 (Default Value: 0x0000_0000)
Offset: 0x0114 Register Name: PF_PULL0
Bit Read/Write Default/Hex Description
31:14 / / /
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Offset: 0x0114 Register Name: PF_PULL0
Bit Read/Write Default/Hex Description
PF6_PULL
PF6 Pull_up or down Select
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF5_PULL
PF5 Pull_up or down Select
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF4_PULL
PF4 Pull_up or down Select
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF3_PULL
PF3 Pull_up or down Select
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF2_PULL
PF2 Pull_up or down Select
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF1_PULL
PF1 Pull_up or down Select
3:2 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PF0_PULL
PF0 Pull_up or down Select
1:0 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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9.7.5.30 0x0120 PG Configure Register 0 (Default Value: 0xFFFF_FFFF)
Offset: 0x0120 Register Name: PG_CFG0
Bit Read/Write Default/Hex Description
PG7_SELECT
PG7 Select
0000:Input 0001:Output
0010:UART1-RX 0011:TWI2-SDA
31:28 R/W 0xF
0100:RGMII-TXD3 0101:OWA-IN
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT7 1111:IO Disable
PG6_SELECT
PG6 Select
0000:Input 0001:Output
0010:UART1-TX 0011:TWI2-SCK
27:24 R/W 0xF
0100:RGMII-TXD2 0101:PWM1
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT6 1111:IO Disable
PG5_SELECT
PG5 Select
0000:Input 0001:Output
0010:SDC1-D3 0011:UART5-RX
23:20 R/W 0xF
0100:RGMII-TXD1/RMII-TXD1 0101:PWM4
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT5 1111:IO Disable
PG4_SELECT
PG4 Select
0000:Input 0001:Output
0010:SDC1-D2 0011:UART5-TX
19:16 R/W 0xF
0100:RGMII-TXD0/RMII-TXD0 0101:PWM5
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT4 1111:IO Disable
Copyright©Allwinner Technology Co.,Ltd. All Rights Reserved. 1080
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Offset: 0x0120 Register Name: PG_CFG0
Bit Read/Write Default/Hex Description
PG3_SELECT
PG3 Select
0000:Input 0001:Output
0010:SDC1-D1 0011:UART3-CTS
15:12 R/W 0xF
0100:RGMII-TXCK/RMII-TXCK 0101:UART4-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT3 1111:IO Disable
PG2_SELECT
PG2 Select
0000:Input 0001:Output
0010:SDC1-D0 0011:UART3-RTS
11:8 R/W 0xF
0100:RGMII-RXD1/RMII-RXD1 0101:UART4-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT2 1111:IO Disable
PG1_SELECT
PG1 Select
0000:Input 0001:Output
0010:SDC1-CMD 0011:UART3-RX
7:4 R/W 0xF
0100:RGMII-RXD0/RMII-RXD0 0101:PWM6
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT1 1111:IO Disable
PG0_SELECT
PG0 Select
0000:Input 0001:Output
0010:SDC1-CLK 0011:UART3-TX
3:0 R/W 0xF
0100:RGMII-RXCTRL/RMII-CRS-DV 0101:PWM7
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT0 1111:IO Disable
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9.7.5.31 0x0124 PG Configure Register 1 (Default Value: 0xFFFF_FFFF)
Offset: 0x0124 Register Name: PG_CFG1
Bit Read/Write Default/Hex Description
PG15_SELECT
PG15 Select
0000:Input 0001:Output
0010:I2S1-DOUT0 0011:TWI2-SDA
31:28 R/W 0xF
0100:MDIO 0101:I2S1-DIN1
0110:SPI0-HOLD 0111:UART1-CTS
1000:Reserved 1001:Reserved
1110:PG-EINT15 1111:IO Disable
PG14_SELECT
PG14 Select
0000:Input 0001:Output
0010:I2S1-DIN0 0011:TWI2-SCK
27:24 R/W 0xF
0100:MDC 0101:I2S1-DOUT1
0110:SPI0-WP 0111:UART1-RTS
1000:Reserved 1001:Reserved
1110:PG-EINT14 1111:IO Disable
PG13_SELECT
PG13 Select.
0000:Input 0001:Output
0010:I2S1-BCLK 0011:TWI0-SDA
23:20 R/W 0xF
0100:RGMII-CLKIN/RMII-RXER 0101:PWM2
0110:LEDC-DO 0111:UART1_RX
1000:Reserved 1001:Reserved
1110:PG-EINT13 1111:IO Disable
PG12_SELECT
PG12 Select
0000:Input 0001:Output
0010:I2S1-LRCK 0011:TWI0-SCK
19:16 R/W 0xF
0100:RGMII-TXCTRL/RMII-TXEN 0101:CLK-FANOUT2
0110:PWM0 0111:UART1-TX
1000:Reserved 1001:Reserved
1110:PG-EINT12 1111:IO Disable
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Offset: 0x0124 Register Name: PG_CFG1
Bit Read/Write Default/Hex Description
PG11_SELECT
PG11 Select
0000:Input 0001:Output
0010:I2S1-MCLK 0011:TWI3-SDA
15:12 R/W 0xF
0100:EPHY-25M 0101:CLK-FANOUT1
0110:TCON-TRIG 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT11 1111:IO Disable
PG10_SELECT
PG10 Select
0000:Input 0001:Output
0010:PWM3 0011:TWI3-SCK
11:8 R/W 0xF
0100:RGMII-RXCK 0101:CLK-FANOUT0
0110:IR-RX 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT10 1111:IO Disable
PG9_SELECT
PG9 Select.
0000:Input 0001:Output
0010:UART1-CTS 0011:TWI1-SDA
7:4 R/W 0xF
0100:RGMII-RXD3 0101:UART3-RX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT9 1111:IO Disable
PG8_SELECT
PG8 Select
0000:Input 0001:Output
0010:UART1-RTS 0011:TWI1-SCK
3:0 R/W 0xF
0100:RGMII-RXD2 0101:UART3-TX
0110:Reserved 0111:Reserved
1000:Reserved 1001:Reserved
1110:PG-EINT8 1111:IO Disable
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9.7.5.32 0x0130 PG Data Register (Default Value: 0x0000_0000)
Offset: 0x0130 Register Name: PG_DAT
Bit Read/Write Default/Hex Description
31:16 / / /
PG_DAT
If the port is configured as the input function, the corresponding
bit is the pin state. If the port is configured as the output
15:0 R/W 0x0
function, the pin state is the same as the corresponding bit. The
read bit value is the value set up by software. If the port is
configured as a functional pin, the undefined value will be read.
9.7.5.33 0x0134 PG Multi_Driving Register 0 (Default Value: 0x1111_1111)
Offset: 0x0134 Register Name: PG_DRV0
Bit Read/Write Default/Hex Description
31:30 / / /
PG7_DRV
PG7 Multi_Driving Select
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PG6_DRV
PG6 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
PG5_DRV
PG5 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PG4_DRV
PG4 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
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Offset: 0x0134 Register Name: PG_DRV0
Bit Read/Write Default/Hex Description
PG3_DRV
PG3 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PG2_DRV
PG2 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PG1_DRV
PG1 Multi_Driving Select
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PG0_DRV
PG0 Multi_Driving Select
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
9.7.5.34 0x0138 PG Multi_Driving Register 1 (Default Value: 0x1111_1111)
Offset: 0x0138 Register Name: PG_DRV1
Bit Read/Write Default/Hex Description
31:30 / / /
PG15_DRV
PG15 Multi_Driving Select
29:28 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
27:26 / / /
PG14_DRV
PG14 Multi_Driving Select
25:24 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
23:22 / / /
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Offset: 0x0138 Register Name: PG_DRV1
Bit Read/Write Default/Hex Description
PG13_DRV
PG13 Multi_Driving Select
21:20 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
19:18 / / /
PG12_DRV
PG12 Multi_Driving Select
17:16 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
15:14 / / /
PG11_DRV
PG11 Multi_Driving Select
13:12 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
11:10 / / /
PG10_DRV
PG10 Multi_Driving Select
9:8 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
7:6 / / /
PG9_DRV
PG9 Multi_Driving Select
5:4 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
3:2 / / /
PG8_DRV
PG8 Multi_Driving Select
1:0 R/W 0x1
00: Level 0 01: Level 1
10: Level 2 11: Level 3
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9.7.5.35 0x0144 PG Pull Register 0 (Default Value: 0x0000_0000)
Offset: 0x0144 Register Name: PG_PULL0
Bit Read/Write Default/Hex Description
PG15_PULL
PG15 Pull_up or down Select.
31:30 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG14_PULL
PG14 Pull_up or down Select.
29:28 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG13_PULL
PG13 Pull_up or down Select.
27:26 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG12_PULL
PG12 Pull_up or down Select.
25:24 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG11_PULL
PG11 Pull_up or down Select.
23:22 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG10_PULL
PG10 Pull_up or down Select.
21:20 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG9_PULL
PG9 Pull_up or down Select.
19:18 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG8_PULL
PG8 Pull_up or down Select.
17:16 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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Confidential
Offset: 0x0144 Register Name: PG_PULL0
Bit Read/Write Default/Hex Description
PG7_PULL
PG7 Pull_up or down Select.
15:14 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG6_PULL
PG6 Pull_up or down Select.
13:12 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG5_PULL
PG5 Pull_up or down Select.
11:10 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG4_PULL
PG4 Pull_up or down Select.
9:8 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG3_PULL
PG3 Pull_up or down Select.
7:6 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG2_PULL
PG2 Pull_up or down Select.
5:4 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG1_PULL
PG1 Pull_up or down Select.
3:2 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
PG0_PULL
PG0 Pull_up or down Select.
1:0 R/W 0x0
00: Pull_up/down disable 01: Pull_up
10: Pull_down 11: Reserved
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9.7.5.36 0x0220 PB External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x0220 Register Name:PB_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT7_CFG
External INT7 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0220 Register Name:PB_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
7:4 R/W 0x0 Reserved
3:0 R/W 0x0 Reserved
9.7.5.37 0x0230 PB External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0230 Register Name: PB_EINT_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
EINT7_CTL
External INT7 Enable
7 R/W 0x0
0: Disable
1: Enable
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0230 Register Name: PB_EINT_CTL
Bit Read/Write Default/Hex Description
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
1 R/W 0x0 Reserved
0 R/W 0x0 Reserved
9.7.5.38 0x0234 PB External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0234 Register Name: PB_EINT_STATUS
Bit Read/Write Default/Hex Description
31:8 / / /
EINT7_STATUS
External INT7 Pending Bit
7 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0234 Register Name: PB_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
1 R/W 0x0 Reserved
0 R/W 0x0 Reserved
9.7.5.39 0x0238 PB External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x0238 Register Name: PB_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
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Offset: 0x0238 Register Name: PB_EINT_DEB
Bit Read/Write Default/Hex Description
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.40 0x0240 PC External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x0240 Register Name:PC_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT7_CFG
External INT7 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0240 Register Name:PC_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
7:4 R/W 0x0 Reserved
3:0 R/W 0x0 Reserved
9.7.5.41 0x0250 PC External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0250 Register Name: PC_EINT_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x0250 Register Name: PC_EINT_CTL
Bit Read/Write Default/Hex Description
EINT7_CTL
External INT7 Enable
7 R/W 0x0
0: Disable
1: Enable
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
1 R/W 0x0 Reserved
0 R/W 0x0 Reserved
9.7.5.42 0x0254 PC External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0254 Register Name: PC_EINT_STATUS
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x0254 Register Name: PC_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT7_STATUS
External INT7 Pending Bit
7 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
1 R/W 0x0 Reserved
0 R/W 0x0 Reserved
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9.7.5.43 0x0258 PC External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x0258 Register Name: PC_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.44 0x0260 PD External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x0260 Register Name:PD_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT7_CFG
External INT7 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0260 Register Name:PD_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0260 Register Name:PD_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT1_CFG
External INT1 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT0_CFG
External INT0 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.45 0x0264 PD External Interrupt Configure Register 1 (Default Value: 0x0000_0000)
Offset: 0x0264 Register Name:PD_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT15_CFG
External INT15 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0264 Register Name:PD_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT14_CFG
External INT14 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT13_CFG
External INT13 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT12_CFG
External INT12 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT11_CFG
External INT11 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0264 Register Name:PD_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT10_CFG
External INT10 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT9_CFG
External INT9 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT8_CFG
External INT8 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.46 0x0268 PD External Interrupt Configure Register 2 (Default Value: 0x0000_0000)
Offset: 0x0268 Register Name:PD_EINT_CFG2
Bit Read/Write Default/Hex Description
31:28 / / /
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Offset: 0x0268 Register Name:PD_EINT_CFG2
Bit Read/Write Default/Hex Description
EINT22_CFG
External INT22 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT21_CFG
External INT21 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT20_CFG
External INT20 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT19_CFG
External INT19 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0268 Register Name:PD_EINT_CFG2
Bit Read/Write Default/Hex Description
EINT18_CFG
External INT18 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT17_CFG
External INT17 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT16_CFG
External INT16 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.47 0x0270 PD External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0270 Register Name: PD_EINT_CTL
Bit Read/Write Default/Hex Description
31:23 / / /
EINT22_CTL
External INT22 Enable
22 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0270 Register Name: PD_EINT_CTL
Bit Read/Write Default/Hex Description
EINT21_CTL
External INT21 Enable
21 R/W 0x0
0: Disable
1: Enable
EINT20_CTL
External INT20 Enable
20 R/W 0x0
0: Disable
1: Enable
EINT19_CTL
External INT19 Enable
19 R/W 0x0
0: Disable
1: Enable
EINT18_CTL
External INT18 Enable
18 R/W 0x0
0: Disable
1: Enable
EINT17_CTL
External INT17 Enable
17 R/W 0x0
0: Disable
1: Enable
EINT16_CTL
External INT16 Enable
16 R/W 0x0
0: Disable
1: Enable
EINT15_CTL
External INT15 Enable
15 R/W 0x0
0: Disable
1: Enable
EINT14_CTL
External INT14 Enable
14 R/W 0x0
0: Disable
1: Enable
EINT13_CTL
External INT13 Enable
13 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0270 Register Name: PD_EINT_CTL
Bit Read/Write Default/Hex Description
EINT12_CTL
External INT12 Enable
12 R/W 0x0
0: Disable
1: Enable
EINT11_CTL
External INT11 Enable
11 R/W 0x0
0: Disable
1: Enable
EINT10_CTL
External INT10 Enable
10 R/W 0x0
0: Disable
1: Enable
EINT9_CTL
External INT9 Enable
9 R/W 0x0
0: Disable
1: Enable
EINT8_CTL
External INT8 Enable
8 R/W 0x0
0: Disable
1: Enable
EINT7_CTL
External INT7 Enable
7 R/W 0x0
0: Disable
1: Enable
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0270 Register Name: PD_EINT_CTL
Bit Read/Write Default/Hex Description
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
EINT1_CTL
External INT1 Enable
1 R/W 0x0
0: Disable
1: Enable
EINT0_CTL
External INT0 Enable
0 R/W 0x0
0: Disable
1: Enable
9.7.5.48 0x0274 PD External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0274 Register Name: PD_EINT_STATUS
Bit Read/Write Default/Hex Description
31:23 / / /
EINT22_STATUS
External INT22 Pending Bit
22 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT21_STATUS
External INT21 Pending Bit
21 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0274 Register Name: PD_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT20_STATUS
External INT20 Pending Bit
20 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT19_STATUS
External INT19 Pending Bit
19 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT18_STATUS
External INT18 Pending Bit
18 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT17_STATUS
External INT17 Pending Bit
17 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT16_STATUS
External INT16 Pending Bit
16 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT15_STATUS
External INT15 Pending Bit
15 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT14_STATUS
External INT14 Pending Bit
14 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0274 Register Name: PD_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT13_STATUS
External INT13 Pending Bit
13 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT12_STATUS
External INT12 Pending Bit
12 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT11_STATUS
External INT11 Pending Bit
11 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT10_STATUS
External INT10 Pending Bit
10 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT9_STATUS
External INT9 Pending Bit
9 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT8_STATUS
External INT8 Pending Bit
8 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT7_STATUS
External INT7 Pending Bit
7 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0274 Register Name: PD_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT1_STATUS
External INT1 Pending Bit
1 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT0_STATUS
External INT0 Pending Bit
0 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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9.7.5.49 0x0278 PD External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x0278 Register Name: PD_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.50 0x0280 PE External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x0280 Register Name:PE_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT7_CFG
External INT7 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0280 Register Name:PE_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0280 Register Name:PE_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT1_CFG
External INT1 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT0_CFG
External INT0 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.51 0x0284 PE External Interrupt Configure Register 1 (Default Value: 0x0000_0000)
Offset: 0x0284 Register Name: PE_EINT_CFG1
Bit Read/Write Default/Hex Description
31:28 R/W 0x0 Reserved
27:24 R/W 0x0 Reserved
EINT13_CFG
External INT13 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0284 Register Name: PE_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT12_CFG
External INT12 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT11_CFG
External INT11 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT10_CFG
External INT10 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT9_CFG
External INT9 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x0284 Register Name: PE_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT8_CFG
External INT8 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.52 0x0290 PE External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0290 Register Name: PE_EINT_CTL
Bit Read/Write Default/Hex Description
31:14 / / /
EINT13_CTL
External INT13 Enable
13 R/W 0x0
0: Disable
1: Enable
EINT12_CTL
External INT12 Enable
12 R/W 0x0
0: Disable
1: Enable
EINT11_CTL
External INT11 Enable
11 R/W 0x0
0: Disable
1: Enable
EINT10_CTL
External INT10 Enable
10 R/W 0x0
0: Disable
1: Enable
EINT9_CTL
External INT9 Enable
9 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0290 Register Name: PE_EINT_CTL
Bit Read/Write Default/Hex Description
EINT8_CTL
External INT8 Enable
8 R/W 0x0
0: Disable
1: Enable
EINT7_CTL
External INT7 Enable
7 R/W 0x0
0: Disable
1: Enable
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
EINT1_CTL
External INT1 Enable
1 R/W 0x0
0: Disable
1: Enable
EINT0_CTL
External INT0 Enable
0 R/W 0x0
0: Disable
1: Enable
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9.7.5.53 0x0294 PE External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0294 Register Name: PE_EINT_STATUS
Bit Read/Write Default/Hex Description
31:14 / / /
EINT13_STATUS
External INT13 Pending Bit
13 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT12_STATUS
External INT12 Pending Bit
12 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT11_STATUS
External INT11 Pending Bit
11 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT10_STATUS
External INT10 Pending Bit
10 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT9_STATUS
External INT9 Pending Bit
9 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT8_STATUS
External INT8 Pending Bit
8 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0294 Register Name: PE_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT7_STATUS
External INT7 Pending Bit
7 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT1_STATUS
External INT1 Pending Bit
1 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x0294 Register Name: PE_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT0_STATUS
External INT0 Pending Bit
0 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
9.7.5.54 0x0298 PE External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x0298 Register Name: PE_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.55 0x02A0 PF External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x02A0 Register Name: PF_EINT_CFG0
Bit Read/Write Default/Hex Description
31:28 / / /
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02A0 Register Name: PF_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02A0 Register Name: PF_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT1_CFG
External INT1 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT0_CFG
External INT0 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.56 0x02B0 PF External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x02B0 Register Name: PF_EINT_CTL
Bit Read/Write Default/Hex Description
31:7 / / /
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
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Offset: 0x02B0 Register Name: PF_EINT_CTL
Bit Read/Write Default/Hex Description
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
EINT1_CTL
External INT1 Enable
1 R/W 0x0
0: Disable
1: Enable
EINT0_CTL
External INT0 Enable
0 R/W 0x0
0: Disable
1: Enable
9.7.5.57 0x02B4 PF External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x02B4 Register Name: PF_EINT_STATUS
Bit Read/Write Default/Hex Description
31:7 / / /
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x02B4 Register Name: PF_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT1_STATUS
External INT1 Pending Bit
1 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT0_STATUS
External INT0 Pending Bit
0 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
9.7.5.58 0x02B8 PF External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x02B8 Register Name: PF_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
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Offset: 0x02B8 Register Name: PF_EINT_DEB
Bit Read/Write Default/Hex Description
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.59 0x02C0 PG External Interrupt Configure Register 0 (Default Value: 0x0000_0000)
Offset: 0x02C0 Register Name:PG_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT7_CFG
External INT7 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT6_CFG
External INT6 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT5_CFG
External INT5 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02C0 Register Name:PG_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT4_CFG
External INT4 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT3_CFG
External INT3 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT2_CFG
External INT2 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT1_CFG
External INT1 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02C0 Register Name:PG_EINT_CFG0
Bit Read/Write Default/Hex Description
EINT0_CFG
External INT0 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.60 0x02C4 PG External Interrupt Configure Register 1 (Default Value: 0x0000_0000)
Offset: 0x02C4 Register Name: PG_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT15_CFG
External INT15 Mode
0x0: Positive Edge
0x1: Negative Edge
31:28 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT14_CFG
External INT14 Mode
0x0: Positive Edge
0x1: Negative Edge
27:24 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02C4 Register Name: PG_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT13_CFG
External INT13 Mode
0x0: Positive Edge
0x1: Negative Edge
23:20 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT12_CFG
External INT12 Mode
0x0: Positive Edge
0x1: Negative Edge
19:16 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT11_CFG
External INT11 Mode
0x0: Positive Edge
0x1: Negative Edge
15:12 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT10_CFG
External INT10 Mode
0x0: Positive Edge
0x1: Negative Edge
11:8 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
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Offset: 0x02C4 Register Name: PG_EINT_CFG1
Bit Read/Write Default/Hex Description
EINT9_CFG
External INT9 Mode
0x0: Positive Edge
0x1: Negative Edge
7:4 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
EINT8_CFG
External INT8 Mode
0x0: Positive Edge
0x1: Negative Edge
3:0 R/W 0x0
0x2: High Level
0x3: Low Level
0x4: Double Edge (Positive/Negative)
Others: Reserved
9.7.5.61 0x02D0 PG External Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x02D0 Register Name: PG_EINT_CTL
Bit Read/Write Default/Hex Description
31:16 / / /
EINT15_CTL
External INT15 Enable
15 R/W 0x0
0: Disable
1: Enable
EINT14_CTL
External INT14 Enable
14 R/W 0x0
0: Disable
1: Enable
EINT13_CTL
External INT13 Enable
13 R/W 0x0
0: Disable
1: Enable
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Offset: 0x02D0 Register Name: PG_EINT_CTL
Bit Read/Write Default/Hex Description
EINT12_CTL
External INT12 Enable
12 R/W 0x0
0: Disable
1: Enable
EINT11_CTL
External INT11 Enable
11 R/W 0x0
0: Disable
1: Enable
EINT10_CTL
External INT10 Enable
10 R/W 0x0
0: Disable
1: Enable
EINT9_CTL
External INT9 Enable
9 R/W 0x0
0: Disable
1: Enable
EINT8_CTL
External INT8 Enable
8 R/W 0x0
0: Disable
1: Enable
EINT7_CTL
External INT7 Enable
7 R/W 0x0
0: Disable
1: Enable
EINT6_CTL
External INT6 Enable
6 R/W 0x0
0: Disable
1: Enable
EINT5_CTL
External INT5 Enable
5 R/W 0x0
0: Disable
1: Enable
EINT4_CTL
External INT4 Enable
4 R/W 0x0
0: Disable
1: Enable
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Offset: 0x02D0 Register Name: PG_EINT_CTL
Bit Read/Write Default/Hex Description
EINT3_CTL
External INT3 Enable
3 R/W 0x0
0: Disable
1: Enable
EINT2_CTL
External INT2 Enable
2 R/W 0x0
0: Disable
1: Enable
EINT1_CTL
External INT1 Enable
1 R/W 0x0
0: Disable
1: Enable
EINT0_CTL
External INT0 Enable
0 R/W 0x0
0: Disable
1: Enable
9.7.5.62 0x02D4 PG External Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x02D4 Register Name: PG_EINT_STATUS
Bit Read/Write Default/Hex Description
31:16 / / /
EINT15_STATUS
External INT15 Pending Bit
15 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT14_STATUS
External INT14 Pending Bit
14 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x02D4 Register Name: PG_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT13_STATUS
External INT13 Pending Bit
13 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT12_STATUS
External INT12 Pending Bit
12 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT11_STATUS
External INT11 Pending Bit
11 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT10_STATUS
External INT10 Pending Bit
10 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT9_STATUS
External INT9 Pending Bit
9 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT8_STATUS
External INT8 Pending Bit
8 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT7_STATUS
External INT7 Pending Bit
7 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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Offset: 0x02D4 Register Name: PG_EINT_STATUS
Bit Read/Write Default/Hex Description
EINT6_STATUS
External INT6 Pending Bit
6 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT5_STATUS
External INT5 Pending Bit
5 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT4_STATUS
External INT4 Pending Bit
4 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT3_STATUS
External INT3 Pending Bit
3 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT2_STATUS
External INT2 Pending Bit
2 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT1_STATUS
External INT1 Pending Bit
1 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
EINT0_STATUS
External INT0 Pending Bit
0 R/W1C 0x0 0: No IRQ pending
1: IRQ pending
Write ‘1’ to clear
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9.7.5.63 0x02D8 PG External Interrupt Debounce Register (Default Value: 0x0000_0000)
Offset: 0x02D8 Register Name: PG_EINT_DEB
Bit Read/Write Default/Hex Description
31:7 / / /
DEB_CLK_PRE_SCALE
6:4 R/W 0x0 Debounce Clock Pre_scale n
The selected clock source is prescaled by 2^n.
3:1 / / /
PIO_INT_CLK_SELECT
PIO Interrupt Clock Select
0 R/W 0x0
0: LOSC 32KHz
1: HOSC 24MHz
9.7.5.64 0x0340 PIO Group Withstand Voltage Mode Select Register (Default Value: 0x0000_0000)
When the power domain of GPIO is larger than 1.8 V, the withstand voltage is set to 3.3 V mode, the
corresponding value in the 0x0340 register is set to 0.
When the power domain of GPIO is 1.8 V, the withstand voltage is set to 1.8 V mode, the corresponding value
in the 0x0340 register is set to 1.
Offset: 0x0340 Register Name: PIO_POW_MOD_SEL
Bit Read/Write Default/Hex Description
31:13 / / /
VCCIO_PWR_MOD_SEL
VCC_IO POWER MODE Select
12 R/W 0x0
0: 3.3 V
1: 1.8 V
11:7 / / /
PG_PWR_MOD_SEL
PG_POWER MODE Select
6 R/W 0x0 0: 3.3 V
1: 1.8 V
If PG_Port Power Source selects VCC_IO, this bit is invalid.
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Offset: 0x0340 Register Name: PIO_POW_MOD_SEL
Bit Read/Write Default/Hex Description
PF_PWR_MOD_SEL
PF_POWER MODE Select
5 R/W 0x0 0: 3.3 V
1: 1.8 V
If PF_Port Power Source selects VCC_IO, this bit is invalid.
PE_PWR_MOD_SEL
PE_POWER MODE Select
4 R/W 0x0 0: 3.3 V
1: 1.8 V
If PE_Port Power Source selects VCC_IO, this bit is invalid.
PD_PWR_MOD_SEL
PD_POWER MODE Select
3 R/W 0x0 0: 3.3 V
1: 1.8 V
If PD_Port Power Source selects VCC_IO, this bit is invalid.
PC_PWR_MOD_SEL
PC_POWER MODE Select
2 R/W 0x0 0: 3.3 V
1: 1.8 V
If PC_Port Power Source selects VCC_IO, this bit is invalid.
1:0 / / /
9.7.5.65 0x0344 PIO Group Withstand Voltage Mode Select Control Register (Default Value: 0x0000_0000)
For 1.8 V and 3.3 V power, the withstand function is enabled by default, the corresponding bit in the 0x0344
register is set to 0.
For 2.5 V power, the withstand function is disabled, the corresponding bit in the 0x0344 register is set to 1, and
the corresponding withstand voltage in the 0x0340 register needs to be set to 3.3 V.
Offset: 0x0344 Register Name: PIO_POW_MS_CTL
Bit Read/Write Default/Hex Description
31:13 / / /
VCCIO_WS_VOL_MOD_SEL
VCC_IO Withstand Voltage Mode Select Control
12 R/W 0x0
0: Enable
1: Disable
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Offset: 0x0344 Register Name: PIO_POW_MS_CTL
Bit Read/Write Default/Hex Description
11:7 / / /
VCC_PG_WS_VOL_MOD_SEL
VCC_PG Withstand Voltage Mode Select Control
6 R/W 0x0
0: Enable
1: Disable
VCC_PF_WS_VOL_MOD_SEL
VCC_PF Withstand Voltage Mode Select Control
5 R/W 0x0
0: Enable
1: Disable
VCC_PE_WS_VOL_MOD_SEL
VCC_PE Withstand Voltage Mode Select Control
4 R/W 0x0
0: Enable
1: Disable
VCC_PD_WS_VOL_MOD_SEL
VCC_PD Withstand Voltage Mode Select Control
3 R/W 0x0
0: Enable
1: Disable
VCC_PC_WS_VOL_MOD_SEL
VCC_PC Withstand Voltage Mode Select Control
2 R/W 0x0
0: Enable
1: Disable
1:0 / / /
9.7.5.66 0x0348 PIO Group Power Value Register (Default Value: 0x0000_0000)
When the reading value of the 0x0348 register is 0, it indicates that the IO power voltage is greater than 2.5 V.
When the reading value of the 0x0348 register is 1, it indicates that the IO power voltage is less than 2.0 V.
Offset: 0x0348 Register Name: PIO_POW_VAL
Bit Read/Write Default/Hex Description
31:17 / / /
VCCIO_PWR_VAL
16 R 0x0
VCC_IO Power Value
15:7 / / /
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Offset: 0x0348 Register Name: PIO_POW_VAL
Bit Read/Write Default/Hex Description
PG_PWR_VAL
6 R 0x0 PG_Port Power Value
If PG_Port power source selects VCC_IO, this bit is invalid.
PF_PWR_VAL
5 R 0x0 PF_Port Power Value
If PF_Port power source selects VCC_IO, this bit is invalid.
PE_PWR_VAL
4 R 0x0 PE_Port Power Value
If PE_Port power source selects VCC_IO, this bit is invalid.
PD_PWR_VAL
3 R 0x0 PD_Port Power Value
If PD_Port power source selects VCC_IO, this bit is invalid.
PC_PWR_VAL
2 R 0x0 PC_Port Power Value
If PC_Port power source selects VCC_IO, this bit is invalid.
1:0 / / /
9.7.5.67 0x0350 PIO Group Power Voltage Select Control Register (Default Value: 0x0000_0001)
Offset: 0x0350 Register Name: PIO_POW_VOL_SEL_CTL
Bit Read/Write Default/Hex Description
31:1 / / /
VCC-PF Power Voltage Select Control
0 R/W 0x1 0: 1.8 V
1: 3.3 V
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9.8 GPADC
9.8.1 Overview
The General Purpose ADC (GPADC) can convert the external signal into a certain proportion of digital value, to
realize the measurement of analog signal, which can be applied to power detection and key detection. This
ADC is a type of successive approximation register (SAR) A/D converter.
The GPADC has the following features:
One independent channel
12-bit sampling resolution and 8-bit precision
64 FIFO depth of data register
Power reference voltage: AVCC, and analog input voltage range: 0 to AVCC
Maximum sampling frequency: 1 MHz
Supports data compare and interrupt
Supports three operation modes
- Single conversion mode
- Continuous conversion mode
- Burst conversion mode
9.8.2 Block Diagram
Figure 9-70 shows the block diagram of the GPADC.
Figure 9-70 GPADC Block Diagram
CLK_N Clock Div APB
Digital
GPADC0 ADC Logic Reg
Process
Vref IRQ
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9.8.3 Functional Description
9.8.3.1 External Signals
The following table describes the external signals of the GPADC.
Table 9-28 GPADC External Signals
Signal Description Type
GPADC0 ADC Input Channel0 AI
9.8.3.2 Clock Sources
The GPADC has one clock source. The following table describes the clock source for GPADC. Users can see
section 3.3 “CCU” for clock setting, configuration, and gating information.
Table 9-29 GPADC Clock Sources
Clock Sources Description
HOSC 24 MHz
9.8.3.3 GPADC Work Mode
Single conversion mode
The GPADC completes one conversion in a specified channel, the converted data is updated at the data register
of the corresponding channel.
Continuous conversion mode
The GPADC has continuous conversion in a specified channel until the software stops, the converted data is
updated at the data register of the corresponding channel.
Burst conversion mode
The GPADC samples and converts in a specified channel, and sequentially stores the results in FIFO.
9.8.3.4 Clock and Timing Requirements
CLK_IN = 24 MHz
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CONV_TIME(Conversion Time) = 1/(24MHz/14Cycles) =0.583 (us)
TACQ > 10RC (R is output impedance of ADC sample circuit, C = 6.4 pF)
ADC Sample Frequency > TACQ+CONV_TIME
Figure 9-71 GPADC Clock and Timing Requirement
TACQ CONV_TIME
ADC Sample Rate
9.8.3.5 GPADC Calculate Formula
GPADC calculate formula: GPADC_DATA = Vin/VREF*4095
Where:
VREF = 1.8 V
9.8.4 Programming Guidelines
The GPADC initial process is as follows.
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Figure 9-72 GPADC Initial Process
Start
Set GPADC GATING,RESET(in CCU)
Set TACQ,FS_DIV,Work Mode,
Compare Data,Interrupt Enable
Enable GPADC
(1).Query Mode
Step 1 Write 0x1 to the bit[16] of GPADC_BGR_REG to dessert reset.
Step 2 Write 0x1 to the bit[0] of GPADC_BGR_REG to enable the GPADC clock.
Step 3 Write 0x2F to the bit[15:0] of GP_SR_CON to set the acquiring time of ADC.
Step 4 Write 0x1DF to the bit[31:16] of GP_SR_CON to set the ADC sample frequency divider.
Step 5 Write 0x2 to the bit[19:18] of GP_CTRL to set the continuous conversion mode.
Step 6 Write 0x1 to the bit[0] of GP_CS_EN to enable the analog input channel.
Step 7 Write 0x1 to the bit[16] of GP_CTRL to enable the ADC function.
Step 8 Read the bit[0] of GP_DATA_INTS, if the bit is 1, then data conversion is complete.
Step 9 Read the bit[11:0] of GP_CH0_DATA, and calculate voltage value based on GPADC formula.
(2).Interrupt Mode
Step 1 Write 0x1 to the bit[16] of GPADC_BGR_REG to dessert reset.
Step 2 Write 0x1 to the bit[0] of GPADC_BGR_REG to enable the GPADC clock.
Step 3 Write 0x2F to the bit[15:0] of GP_SR_CON to set the acquiring time of ADC.
Step 4 Write 0x1DF to the bit[31:16] of GP_SR_CON to set the ADC sample frequency divider.
Step 5 Write 0x2 to the bit[19:18] of GP_CTRL to set the continuous conversion mode.
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Step 6 Write 0x1 to the bit[0] of GP_CS_EN to enable the analog input channel.
Step 7 Write 0x1 to the bit[0] of GP_DATA_INTC to enable the GPADC data interrupt.
Step 8 Set interrupt based on PLIC module.
Step 9 Put interrupt handler address into interrupt vector table.
Step 10 Write 0x1 to the bit16 of GP_CTRL to enable the ADC function.
Step 11 Read the bit[11:0] of GP_CH0_DATA from the interrupt handler, calculate voltage value based on
GPADC formula.
9.8.5 Register List
Module Name Base Address
GPADC 0x02009000
Register Name Offset Description
GP_SR_CON 0x0000 GPADC Sample Rate Configure Register
GP_CTRL 0x0004 GPADC Control Register
GP_CS_EN 0x0008 GPADC Compare and Select Enable Register
GP_FIFO_INTC 0x000C GPADC FIFO Interrupt Control Register
GP_FIFO_INTS 0x0010 GPADC FIFO Interrupt Status Register
GP_FIFO_DATA 0x0014 GPADC FIFO Data Register
GP_CDATA 0x0018 GPADC Calibration Data Register
GP_DATAL_INTC 0x0020 GPADC Data Low Interrupt Configure Register
GP_DATAH_INTC 0x0024 GPADC Data High Interrupt Configure Register
GP_DATA_INTC 0x0028 GPADC Data Interrupt Configure Register
GP_DATAL_INTS 0x0030 GPADC Data Low Interrupt Status Register
GP_DATAH_INTS 0x0034 GPADC Data High Interrupt Status Register
GP_DATA_INTS 0x0038 GPADC Data Interrupt Status Register
GP_CH0_CMP_DATA 0x0040 GPADC CH0 Compare Data Register
GP_CH0_DATA 0x0080 GPADC CH0 Data Register
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9.8.6 Register Description
9.8.6.1 0x0000 GPADC Sample Rate Configure Register (Default Value: 0x01DF_002F)
Offset: 0x0000 Register Name: GP_SR_CON
Bit Read/Write Default/Hex Description
FS_DIV
ADC sample frequency divider
31: 16 R/W 0x1DF
CLK_IN/(n+1)
Default value: 50K
TACQ
ADC acquire time
15:0 R/W 0x2F
(n+1)/CLK_IN
Default value: 2 us
9.8.6.2 0x0004 GPADC Control Register (Default Value: 0x0080_0000)
Offset: 0x0004 Register Name: GP_CTRL
Bit Read/Write Default/Hex Description
ADC_FIRST_DLY
31:24 R/ W 0x0 ADC First Convert Delay Setting
ADC conversion of each channel is delayed by N samples.
ADC_AUTOCALI_EN
23 R/ W 0x1
ADC Auto Calibration
22 / / /
ADC_OP_BIAS
21:20 R/W 0x0 ADC OP Bias
Adjust the bandwidth of the ADC amplifier
GPADC Work Mode
00: Single conversion mode
19:18 R/W 0x0 01: Reserved
10: Continuous conversion mode
11: Burst conversion mode
ADC_CALI_EN
17 R/W 0x0 ADC Calibration
1: Start Calibration, it is cleared to 0 after calibration
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Offset: 0x0004 Register Name: GP_CTRL
Bit Read/Write Default/Hex Description
ADC_EN
ADC Function Enable
Before the bit is enabled, configure ADC parameters including the
work mode and channel number, etc.
16 R/W 0x0
0: Disable
1: Enable
Note: When selecting a single conversion mode, the bit can be
cleared automatically after the switch is completed.
15:0 / / /
9.8.6.3 0x0008 GPADC Compare and Select Enable Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: GP_CS_EN
Bit Read/Write Default/Hex Description
31:17 / / /
ADC_CH0_CMP_EN
Channel 0 Compare Enable
16 R/W 0x0
0: Disable
1: Enable
15:1 / / /
ADC_CH0_SELECT
Analog Input Channel 0 Select
0 R/W 0x0
0: Disable
1: Enable
9.8.6.4 0x000C GPADC FIFO Interrupt Control Register (Default Value: 0x0000_1F00)
Offset: 0x000C Register Name: GP_FIFO_INTC
Bit Read/Write Default/Hex Description
31:19 / / /
FIFO_DATA_DRQ_EN
ADC FIFO Date DRQ Enable
18 R/W 0x0
0: Disable
1: Enable
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Offset: 0x000C Register Name: GP_FIFO_INTC
Bit Read/Write Default/Hex Description
FIFO_OVERRUN_IRQ_EN
ADC FIFO Overrun IRQ Enable
17 R/W 0x0
0: Disable
1: Enable
FIFO_DATA_IRQ_EN
ADC FIFO Data Available IRQ Enable
16 R/W 0x0
0: Disable
1: Enable
15:14 / / /
FIFO_TRIG_LEVEL
13:8 R/W 0x1F Interrupt trigger level for ADC
Trigger Level = TXTL + 1
7:5 / / /
FIFO_FLUSH
4 R/WAC 0x0 ADC FIFO Flush
Write ‘1’ to flush TX FIFO, clear automatically to ‘0’.
3:0 / / /
9.8.6.5 0x0010 GPADC FIFO Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: GP_FIFO_INTS
Bit Read/Write Default/Hex Description
31:18 / / /
FIFO_OVERRUN_PENDING
ADC FIFO Overrun IRQ Pending
0: No Pending IRQ
17 R/W1C 0x0
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
FIFO_DATA_PENDING
ADC FIFO Data Available Pending Bit
0: NO Pending IRQ
16 R/W1C 0x0
1: FIFO Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
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Offset: 0x0010 Register Name: GP_FIFO_INTS
Bit Read/Write Default/Hex Description
15:14 / / /
RXA_CNT
13:8 R 0x0
ADC FIFO available sample word counter
7:0 / / /
9.8.6.6 0x0014 GPADC FIFO Data Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: GP_FIFO_DATA
Bit Read/Write Default/Hex Description
31:12 / / /
GP_FIFO_DATA
11:0 R 0x0
GPADC Data in FIFO
9.8.6.7 0x0018 GPADC Calibration Data Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: GP_CDATA
Bit Read/Write Default/Hex Description
31:12 / / /
GP_CDATA
11:0 R/W 0x0
GPADC Calibration Data
9.8.6.8 0x0020 GPADC Low Interrupt Configure Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: GP_DATAL_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_LOW_IRQ_EN
Channel 0 Voltage Low Available Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
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9.8.6.9 0x0024 GPADC High Interrupt Configure Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: GP_DATAH_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_HIG_IRQ_EN
Channel 0 Voltage High Available Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
9.8.6.10 0x0028 GPADC DATA Interrupt Configure Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: GP_DATA_INTC
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_DATA_IRQ_EN
0 R/W 0x0 0: Disable
1: Enable
9.8.6.11 0x0030 GPADC Low Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: GP_DATAL_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_LOW_PENGDING
Channel 0 Voltage Low Available Interrupt Status
0: NO Pending IRQ
0 R/W1C 0x0
1: Channel 0 Voltage Low Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
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9.8.6.12 0x0034 GPADC High Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: GP_DATAH_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_HIG_PENGDING
0: No Pending IRQ
0 R/W1C 0x0 1: Channel 0 Voltage High Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
9.8.6.13 0x0038 GPADC Data Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: GP_DATA_INTS
Bit Read/Write Default/Hex Description
31:1 / / /
CH0_DATA_PENGDING
Channel 0 Data Available Interrupt Status
0: No Pending IRQ
0 R/W1C 0x0
1: Channel 0 Data Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if the
interrupt condition fails.
9.8.6.14 0x0040 GPADC CH0 Compare Data Register (Default Value: 0x0BFF_0400)
Offset: 0x0040 Register Name: GP_CH0_CMP_DATA
Bit Read/Write Default/Hex Description
31:28 / / /
CH0_CMP_HIG_DATA
27:16 R/W 0xBFF
Channel 0 Voltage High Value
15:12 / / /
CH0_CMP_LOW_DATA
11:0 R/W 0x400
Channel 0 Voltage Low Value
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9.8.6.15 0x0080 GPADC CH0 Data Register (Default Value: 0x0000_0000)
Offset: 0x0080 Register Name: GP_CH0_DATA
Bit Read/Write Default/Hex Description
31:12 / / /
GP_CH0_DATA
11:0 R 0x000
Channel 0 Data
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9.9 TPADC
9.9.1 Overview
The Touch Panel ADC (TPADC) is a 4-wire resistive touch screen controller, including a 12-bit SAR type A/D
converter.
The TPADC has the following features:
12 bit SAR type A/D converter
Configurable sample frequency up to 1 MHz
One 32x12 FIFO for storing A/D conversion result
Supports DMA slave interface
Supports 4-wire resistive touch panel input detection
- Supports pen down detection with programmable sensitivity
- Supports single touch coordinate measurement
- Supports dual touch detection
- Supports touch pressure measurement with programmable threshold
- Supports median and averaging filter for noise reduction
- Supports X and Y coordinate exchange function
Supports Aux ADC with up to 4 channels
9.9.2 Functional Description
9.9.2.1 External Signals
The following table describes the external signals of the TPADC.
Table 9-30 TPADC External Signals
Signal Description Type
TP-X1 Touch Panel X1 Input AI
TP-X2 Touch Panel X2 Input AI
TP-Y1 Touch Panel Y1 Input AI
TP-Y2 Touch Panel Y2 Input AI
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9.9.2.2 Single-ended Mode and Differential Mode
The controller is a typical type of successive approximation ADC (SAR ADC) which contains a sample/hold,
analog-to-digital conversion, serial data output functions.
The analog inputs (X+, X-, Y+, Y-) enter the ADC through the control register, the ADC can work in single-ended
or differential mode. Selecting Aux ADC should work in single-ended mode; for a touch screen application, it
works in a differential mode, which can effectively eliminate the impact on conversion accuracy caused by the
parasitic resistance of the driver switch and external interference.
Figure 9-73 shows TPADC Single-Ended Mode for the measurement of Aux, using the 1.8 V reference source as
the ADC reference voltage.
Figure 9-73 TPADC Single-Ended Mode for AUX ADC
VCC_REF(3V)
X+
+IN +REF
X- 4:1
Converter
MUX
Y+ -IN
-REF
Y-
Figure 9-74 shows TPADC differential mode for the measurement of X/Y/Z coordinate of Touch Panel. The
advantage of differential mode: +REF and –REF can directly input to the Y+ and Y-(or X+ and X-), which can
eliminate the measurement error of X+/X-(or Y+/Y-) because of the switch on resistance. The disadvantage is
that: both the sample or conversion process, the driver will need to be enabled. Compared with single-ended
mode, the power consumption increases.
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Figure 9-74 TPADC Differential Mode for Touch Panel
VCC_REF(3V)
+IN +REF
Converter
-IN
-REF
9.9.2.3 Single Touch Measurement
The following figure shows the operation principle of the single touch X-Coordinate measurement.
Figure 9-75 Single Touch X-Coordinate Measurement for Touch Panel
MEASURE
X POSITION
X+
TOUCH
X-POSITION
X-
For an X coordinate measurement, the X+ pin is internally switched to VCC_REF and X- to GND. The X plate
becomes a potential divider, and the voltage at the point of contact is proportional to its X co-ordinate. This
voltage is measured on the Y+, which carries no current (hence there is no voltage drop in RY+ or RY-). Due to
the ratio metric measurement method, the supply voltage does not affect measurement accuracy. The voltage
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references VREF+ and VREF- are taken from after the matrix switches, so that any voltage drop in these
switches has no effect on the ADC measurement.
Y coordinate measurements are similar to X coordinate measurements, with the X and Y plates interchanged.
9.9.2.4 Dual Touch Measurement
In single touch mode, it only needs to test X+ and Y+ signals. But in dual touch mode, it needs to test X+, X-, Y+,
and Y- signals. The following figure shows the operation principle of dual touch detection for touch panel.
Figure 9-76 Dual Touch Detection for Touch Panel
MEASURE
X+ X+ Position
TOUCH
X-POSITION
X-
MEASURE
X- Position
For X coordinates measurement, the X+ pin is internally switched to 3 V and X- to GND. The controller needs
to test Y+ and Y-, Y coordinates measurement is similar. And record △X=|X+ - X-|, △Y= | Y+ - Y-|. In practice,
we can set a threshold. If △X or △Y is greater than the threshold, we consider it as a dual touch, otherwise as
a single touch.
9.9.2.5 Touch Pressure Measurement
The pressure applied to the touch screen by a pen or finger to filter unavailable can also be measured by the
controller using some simple calculations. The contact resistance between the X and Y plates is measured,
which provides a good indication of the size of the depressed area and the applied pressure. The area of the
touch spot t is proportional to the size of the object touching it. And the value of this resistance (Rtouch) can be
calculated using two different methods.
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Figure 9-77 Touch Pressure Measurement for Touch Panel
MEASURE MEASURE
X-POSITION Z1-POSITION
Y+
X+ X+ Y+ X+ Y+
TOUCH TOUCH
X-POSITION Z1-POSITION Z2-POSITION
X- Y- X- Y- X- Y-
MEASURE
Z2-POSITION
(1) First Method
The first method requires the user to know the total resistance of the X plate tablet (RXPLATE). Three touch
screen conversions are required: measurement of the X position, XPOSITION(Y+ input); measurement of the
X+ input with the excitation voltage applied to Y+ and X− (Z1 measurement); and measurement of the Y−
input with the excitation voltage applied to Y+ and X− (Z2 measurement). These three measurements are
illustrated in following Figure. The controller have two special ADC channel settings to configure the X and
Y switches for the Z1 and Z2 measurements and store the results in the Z1 and Z2 result registers. The
touch resistance (RTOUCH) can then be calculated using the following equation.
RTOUCH = (RXPLATE) × (XPOSITION/4096) × [(Z2/Z1) − 1]
(2) Second Method
The second method requires the user to know the resistance of the X-plate and Y-plate tablets. Three touch
screen conversions are required: a measurement of the X position (XPOSITION), the Y position (YPOSITION), and
the Z1 position. The following equation also calculates the touch resistance (RTOUCH).
RTOUCH = RXPLATE × (XPOSITION/4096) × [(4096/Z1) − 1] − RYPLATE × [1 − (YPOSITION/4096)]
9.9.2.6 Pen Down Detection
Pen down detection is used as an interrupt to the host. RIRQ is an internal pull-up resistor with a programmable
value from 6 kΩ to 96 kΩ (default 48 kΩ).
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Figure 9-78 Pen Down Detection for Touch Panel
AVCC
RIRQ
ADC
X+ Y+
RTOUCH
X- Y-
The pen down IRQ output is pulled high by an internal pull-up. In the pen down detection, the Y– driver is
enabled and connected to GND, and the pen down IRQ output is connected to the X+ input. When the panel is
touched, the X+ input is pulled to ground through the touch screen, and the pen down IRQ output goes low
because of the current path through the panel to GND, initiating an interrupt to the processor.
During the measurement cycle for X-, Y-, and Z-position, the X+ input is disconnected from the pen down IRQ
pull-down transistor to eliminate any pull-up resistor leakage current from flowing through the touch screen,
thus causing no errors.
9.9.2.7 Median and Averaging Filter
Touch screens are composed of two resistive layers, normally placed over an LCD screen. Because these layers
are in close proximity to the LCD screen, noise can be coupled from the screen onto these resistive layers,
causing errors in the touch screen positional measurements.
The controller contain a filtering block to process the data and discard the spurious noise before sending the
information to the host. The purpose of this block is not only the suppression of noise; the on-chip filtering also
greatly reduces the host processing loading.
The processing function consists of two filters that are applied to the converted results: the median filter and
the averaging filter. The median filter suppresses the isolated out-of-range noise and sets the number of
measurements to be taken. These measurements are arranged in a temporary array, where the first value is
the smallest measurement and the last value is the largest measurement. Then the averaging filter size
determines the number of values to average. There are four choices which is configured by TP_CTRL3 register
(bit 1 and bit 0) to filtrate the ADC sampling data.
Figure 9-79 Median and Averaging Filter Size
Bit1 Bit0 Averaging Filter Size Median Filter Size
0 0 2 4
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Bit1 Bit0 Averaging Filter Size Median Filter Size
0 1 3 5
1 0 4 8
1 1 8 16
Example: In this example, the bit[1:0] of TP_CTRL_REG3 is configured as 2’b11. So the median filter has a
window size of 16. This means that 16 measurements are taken and arranged in descending order in a
temporary array. The averaging window size in this example is 8. The output is the average of the middle eight
values of the 16 measurements taken with the median filter.
Figure 9-80 Median and Averaging Filter Example
12-BIT MEDIAN AVERAGING FIFO
SAR ADC FILTER FILTER
Average Of Middle
Converted Results 16 Measurements Arranged 8 Values
2 1 1
3 2 2
5 3 3
1 4 4
6 5 5
7 6 6
9 7 7
8 8 8
M=16 A=8
10 9 9
12 10 10
11 11 11
15 12 12
13 13 13
4 14 14
16 15 15
14 16 16
9.9.3 Register List
Module Name Base Address
TPADC 0x02009C00
Register Name Offset Description
TP_CTRL_REG0 0x0000 TP Control Register 0
TP_CTRL_REG1 0x0004 TP Control Register 1
TP_CTRL_REG2 0x0008 TP Control Register 2
TP_CTRL_REG3 0x000C TP Control Register 3
TP_INT_FIFO_CTRL_REG 0x0010 TP Interrupt FIFO Control Register
TP_INT_FIFO_STAT_REG 0x0014 TP Interrupt FIFO Status Register
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Register Name Offset Description
TP_CALI_DATA_REG 0x001C TP Calibration Data Register
TP_DATA_REG 0x0024 TP Data Register
9.9.4 Register Description
9.9.4.1 0x0000 TP Control Register 0 (Default Value:0x0F80_0000)
Offset: 0x0000 Register Name: TP_CTRL0
Bit Read/Write Default/Hex Description
ADC_FIRST_DLY
ADC First Convert Delay Time (T_FCDT) Setting
31:24 R/W 0xF
Based on ADC first convert delay mode select (Bit 23)
T_FCDT = ADC_FIRST_DLY * ADC_FIRST_DLY_MODE
ADC_FIRST_DLY_MODE
ADC First Convert Delay Mode Select
23 R/W 0x1
0: CLK_IN/16
1: CLK_IN/16*256
22 / / /
ADC_CLK_DIVIDER
ADC Clock Divider (CLK_IN)
00: CLK/2
21:20 R/W 0x0
01: CLK/3
10: CLK/6
11: CLK/1
FS_DIV
ADC Sample Frequency Divider
0000: CLK_IN/2(20-0)
19:16 R/W 0x0 0001: CLK_IN/2(20-1)
0010: CLK_IN/2(20-2)
….
1111: CLK_IN/2(20-15)
TACQ
15:0 R/W 0x0 Touch panel ADC acquire time
CLK_IN/(16*(N+1))
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9.9.4.2 0x0004 TP Control Register 1 (Default Value:0x0000_0101)
Offset: 0x0004 Register Name: TP_CTRL_REG1
Bit Read/Write Default/Hex Description
31:20 / / /
STYLUS_UP_DEBOUNCE
Stylus Up De-bounce Time Setting
19:12 R/W 0x0 0x00: 0
….
0xFF: 2N*(CLK_IN/16*256)
11:10 / / /
STYLUS_UP_DEBOUCE_EN
Stylus Up Debounce Function Select
9 R/W 0x0
0: Disable
1: Enable
CHOPPER_EN
T-sensor Chopping Enable
8 R/W 0x1 0: Disable
1: Enable
This field is not used when there is no T-sensor in TPADC
TOUCH_PAN_CALI_EN
7 R/W 0x0 Touch Panel Calibration
1: Start calibration, it is cleared to 0 after calibration
TP_DUAL_EN
Touch Panel Double Point Enable
6 R/W 0x0
0: Disable
1: Enable
TP_EN.
TP Function Enable
5 R/W 0x0
0: Disable
1: Enable
TP_MODE_SELECT.
Touch Panel Mode and Auxiliary ADC Mode Select
4 R/W 0x0
0: TP
1: Auxiliary ADC
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Offset: 0x0004 Register Name: TP_CTRL_REG1
Bit Read/Write Default/Hex Description
ADC_CHAN3_SELECT
Analog Input Channel 3 Select
3 R/W 0x0
0: Disable
1: Enable
ADC_CHAN2_SELECT
Analog Input Channel 2 Select
2 R/W 0x0
0: Disable
1: Enable
ADC_CHAN1_SELECT
Analog Input Channel 1 Select
1 R/W 0x0
0: Disable
1: Enable
ADC_CHAN0_SELECT
Analog Input Channel 0 Select
0 R/W 0x1
0: Disable
1: Enable
CHAN0–3 can be selected at the same time. If N channel is selected, each channel has 1/N full speed of the
ADC. If only one channel is selected, it has the full conversion rate. CHAN0–3 correspond to TP_YN, TP_YP,
TP_XN, TP_XP.
9.9.4.3 0x0008 TP Control Register 2 (Default Value:0x8000_0FFF)
Offset: 0x0008 Register Name: TP_CTRL_REG2
Bit Read/Write Default/Hex Description
TP_SENSITIVE_ADJUST
Internal Pull-up Resistor Control
0000: least sensitive
31:28 R/W 0x8
……
1111: most sensitive
This field is used to adjust sensitivity of pen down detection.
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Offset: 0x0008 Register Name: TP_CTRL_REG2
Bit Read/Write Default/Hex Description
TP_FIFO_MODE_SELECT
TP FIFO Access Data Mode Select
00: FIFO store X1,Y1 data for single touch no pressure mode
01: FIFO store X1,Y1, △X, △Y data for dual touch no pressure mode
10: FIFO store X1,Y1, X2,Y2 data for dual touch no pressure mode
11: FIFO store X1,Y1, X2,Y2,Z1,Z2 data for dual touch and pressure
mode
27:26 R/W 0x0 The ADC output data in single touch mode can store in FIFO with
TP_FIFO_MODE_SELECT configured as 01,10,11. But the data △X,
△Y is theoretically equal to X1,Y1, and X2,Y2 is equal to 0.
When PRE_MEA_EN is set and TP_FIFO_MODE_SELECT is not
configured as 2’b11, X and Y data will not be stored unless x1*(z2-
z1)/z1 < PRE_MEA_THRE_CNT.
Z data will always be zero when TP_FIFO_MODE_SELECT is
configured as 2’b11 but PRE_MEA_EN is not set.
25 / / /
PRE_MEA_EN
TP Pressure Measurement Enable Control
24 R/W 0x0
0: Disable
1: Enable
PRE_MEA_THRE_CNT
TP Pressure Measurement Threshold Control
23:0 R/W 0xFFF 0x000000:least sensitive
0xFFFFFF: most sensitive
This field is used to adjust sensitivity of touch.
9.9.4.4 0x000C TP Control Register 3 (Default Value:0x0000_0001)
Offset: 0x000C Register Name: TP_CTRL_REG3
Bit Read/Write Default/Hex Description
31:3 / / /
FILTER_EN
Filter Enable
2 R/W 0x0
0: Disable
1: Enable
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Offset: 0x000C Register Name: TP_CTRL_REG3
Bit Read/Write Default/Hex Description
FILTER_TYPE
Filter Type
00: 4/2
1:0 R/W 0x1
01: 5/3
10: 8/4
11: 16/8
9.9.4.5 0x0010 TP Interrupt& FIFO Control Register (Default Value:0x0000_0F00)
Offset: 0x0010 Register Name: TP_INT_FIFO_CTRL_REG
Bit Read/Write Default/Hex Description
31:18 / / /
TP_OVERRUN_IRQ_EN
TP FIFO Overrun IRQ Enable
17 R/W 0x0
0: Disable
1: Enable
TP_DATA_IRQ_EN
TP FIFO Data Available IRQ Enable
16 R/W 0x0
0: Disable
1: Enable
15:14 / / /
TP_DATA_XY_CHANGE
TP FIFO X,Y Data Interchange Function Select
13 R/W 0x0
0: Disable
1: Enable
TP_FIFO_TRIG_LEVEL
TP FIFO Data Available Trigger Level
12:8 R/W 0xF
Interrupt and DMA request trigger level for TP or Auxiliary ADC
Trigger Level = TXTL + 1
TP_DATA_DRQ_EN
TP FIFO Data Available DRQ Enable
7 R/W 0x0
0: Disable
1: Enable
6:5 / / /
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Offset: 0x0010 Register Name: TP_INT_FIFO_CTRL_REG
Bit Read/Write Default/Hex Description
TP_FIFO_FLUSH
4 R/WAC 0x0 TP FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’
3:2 / / /
TP_UP_IRQ_EN
Touch Panel Last Touch (Stylus Up) IRQ Enable
1 R/W 0x0
0: Disable
1: Enable
TP_DOWN_IRQ_EN
Touch Panel First Touch (Stylus Down) IRQ Enable
0 R/W 0x0
0: Disable
1: Enable
9.9.4.6 0x0014 TP Interrupt& FIFO Status Register (Default Value:0x0000_0000)
Offset: 0x0014 Register Name: TP_INT_FIFO_STAT_REG
Bit Read/Write Default/Hex Description
31:18 / / /
FIFO_OVERRUN_PENDING
TP FIFO Overrun IRQ pending
0: No Pending IRQ
17 R/W1C 0x0
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if interrupt
condition fails.
FIFO_DATA_PENDING
TP FIFO Data Available Pending Bit
0: NO Pending IRQ
16 R/W1C 0x0
1: FIFO Available Pending IRQ
Write ‘1’ to clear this interrupt or automatically clear if FIFO
flushed.
15:14 / / /
RXA_CNT
13:8 R 0x0
TP FIFO Available Sample Word Counter
7:3 / / /
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Offset: 0x0014 Register Name: TP_INT_FIFO_STAT_REG
Bit Read/Write Default/Hex Description
TP_IDLE_FLG
Touch Panel Idle Flag
2 R 0x0
0: idle
1: not idle
TP_UP_PENDING
Touch Panel Last Touch (Stylus Up) IRQ Pending bit
0: No IRQ
1 R/W1C 0x0
1: IRQ
Writing 1 to the bit clears it and its corresponding interrupt if the
interrupt is enabled.
TP_DOWN_PENDING
Touch Panel First Touch (Stylus Down) IRQ Pending bit
0: No IRQ
0 R/W1C 0x0
1: IRQ
Writing 1 to the bit clears it and its corresponding interrupt if the
interrupt is enabled.
9.9.4.7 0x001C TP Calibration Data Register (Default Value:0x0000_0800)
Offset: 0x001C Register Name: TP_CALI_DATA_REG
Bit Read/Write Default/Hex Description
31:12 / / /
TP_CDAT
11:0 R/W 0x800 TP Common Data
It is used to adjust the tolerance of the internal ADC.
9.9.4.8 0x0024 TP Data Register (Default Value:0x0000_0000)
In touch panel mode, the data stored in this register bases on TP_FIFO_MODE_SELECT. In Auxiliary ADC mode,
the data stored in this register bases on ADC_CHAN_SELECT. If four channels are enabled, FIFO will access the
input data in successive turn (ADC_CHAN0 -> ADC_CHAN1 -> ADC_CHAN2 -> ADC_CHAN3). If only two or three
channels are selected, such as ADC_CHAN0 and ADC_CHAN3, firstly ADC_CHAN0 input data is accessed, then
ADC_CHAN3 input data.
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Offset: 0x0024 Register Name: TP_DATA_REG
Bit Read/Write Default/Hex Description
31:12 / / /
TP_DATA
11:0 R 0x0 Touch Panel X ,Y data or Auxiliary analogy input data converted by
the internal ADC.
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9.10 PWM
9.10.1 Overview
The Pulse Width Modulation (PWM) module can output the configurable PWM waveforms and measure the
external input waveforms.
The PWM has the following features:
Supports 8 independent PWM channels (PWM0 to PWM7)
- Supports PWM continuous mode output
- Supports PWM pulse mode output, and the pulse number is configurable
- Output frequency range: 0 to 24 MHz or 100 MHz
- Various duty-cycle: 0% to 100%
- Minimum resolution: 1/65536
Supports 4 complementary pairs output
- PWM01 pair (PWM0 + PWM1), PWM23 pair (PWM2 + PWM3), PWM45 pair (PWM4 + PWM5),
PWM67 pair (PWM6 + PWM7)
- Supports dead-zone generator, and the dead-zone time is configurable
Supports 4 group of PWM channel output for controlling stepping motors
- Supports any plural channels to form a group, and output the same duty-cycle pulse
- In group mode, the relative phase of the output waveform for each channel is configurable
Supports 8 channels capture input
- Supports rising edge detection and falling edge detection for input waveform pulse
- Supports pulse-width measurement for input waveform pulse
9.10.2 Block Diagram
The PWM includes multi PWM channels. Each channel can generate different PWM waveform by the
independent counter and duty-ratio configuration register. Each PWM pair shares one group of clock and dead-
zone generator to generate PWM waveform.
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Figure 9-81 PWM Block Diagram
PWM67
PWM45
PWM23
PWM01
PWM0 Logic Dead Zone PWM0 GPIO
I/O
Module Generator
PWM01 Clock PWM01_CLK
Controller
PWM1 Logic PWM1 GPIO
I/O
Module
Each PWM pair consists of 1 clock module, 2 timer logic module, and 1 programmable dead-zone generator.
9.10.3 Functional Description
9.10.3.1 External Signals
The following table describes the external signals of the PWM.
Table 9-31 PWM External Signals
Signal Description Type
PWM0 Pulse Width Module Channel0 I/O
PWM1 Pulse Width Module Channel1 I/O
PWM2 Pulse Width Module Channel2 I/O
PWM3 Pulse Width Module Channel3 I/O
PWM4 Pulse Width Module Channel4 I/O
PWM5 Pulse Width Module Channel5 I/O
PWM6 Pulse Width Module Channel6 I/O
PWM7 Pulse Width Module Channel7 I/O
9.10.3.2 Typical Application
Suitable for display device, such as LCD
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Suitable for electric motor control
9.10.3.3 Clock Controller
Using PWM01 as an example. The other PWM pairs are the same as PWM01.
Figure 9-82 PWM01 Clock Controller Diagram
PWM01_CLK_DIV_M PWM0_PRESCAL_K
PWM0_CLK_GATING
PWM01_CLK_SRC_SEL /1 0000 div pwm0_clk
/2 0001
/4 PWM0_CLK_SRC_BYPASS_TO_PWM 0
0010 PWM 0 PIN
OSC24M 00 /8 0011
APB0 01 PWM01_CLK_SRC /16 0100 PWM01_CLK
/ /32 0101
/
10 /64 PWM1_PRESCAL_K
11 0110
/128 0111 PWM1_CLK_GATING
/256 1000
div
PWM1_CLK_SRC_BYPASS_TO_PWM 1
PWM 1 PIN
The clock controller of each PWM pair includes clock source select (PWM01_CLK_SRC), 1~256 scaler
(PWM01_CLK_DIV_M). Each PWM channel has the secondary frequency division (PWM_PRESCAL_K), clock
source bypass (PWMx_CLK_BYPASS) and clock switch (PWMx_CLK_GATING).
The clock sources have HOSC and APB0. The HOSC comes from the external high-frequency oscillator; the APB0
is APB0 bus clock.
The bypass function of the clock source is that the clock source directly accesses PWM output, the PWM output
waveform is the waveform of the clock controller output. The BYPASS gridlines in the above figure indicate the
bypass function of the clock source, see Figure 9-83 for the details about implement. At last, the output clock
of the clock controller is sent to the PWM logic module.
9.10.3.4 PWM Output
Taking PWM01 as an example, Figure 9-83 indicates the PWM01 output logic diagram. The logic diagrams of
other PWM pairs are the same as PWM01.
The timer logic module of PWM consists of one 16-bit up-counter (PCNTR) and three 16-bit parameters
(PWM_ENTIRE_CYCLE, PWM_ACT_CYCLE, PWM_COUNTER_START). The PWM_ENTIRE_CYCLE is used to
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control the PWM cycle, the PWM_ACT_CYCLE is used to control the duty-cycle, the PWM_COUNTER_START is
used to control the output phase (multi-channel synchronization work requirements).
The PWM_ENTIRE_CYCLE and the PWM_ACT_CYCLE support the cache load, after PWM output is enabled, the
register values of the PWM_ENTIRE_CYCLE and the PWM_ACT_CYCLE can be changed anytime, the changed
value caches into the cache register. When the PCNTR counter outputs a period of PWM waveform, the value
of the cache register can be updated for the PCNTR control. The purpose of the cache load is to avoid the
unstable PWM output waveform with the burred feature when updating the values of the PWM_ENTIRE_CYCLE
and PWM_ACT_CYCLE.
The PWM supports cycle and pulse waveform output.
Cycle mode: The PWM outputs the setting PWM waveform continually, that is, the output waveform is a
continuous PWM square wave.
Pulse mode: After setting the PWM_PUL_NUM parameter, the PWM outputs (PWM_PULNUM+1) periods of
PWM waveform, that is, the waveform with several pulses are output.
Figure 9-83 PWM01 Output Logic Module Diagram
9.10.3.5 Up-Counter and Comparator
The period, duty-cycle, and phase of PWM output waveform are decided by the PCNTR, PWM_ENTIRE_CYCLE,
PWM_ACT_CYCLE, and PWM_COUNTER_START. The rules are as follows.
PCNTR= (PCNTR==PWM_ENTIRE_CYCLE)?0 : PCNTR + 1
PCNTR starts to count by PWM_COUNTER_START, the counter of a PWM period is
(PWM_ENTIRE_CYCLE+1).
PCNTR > (PWM_ENTIRE_CYCLE - PWM_ACT_CYCLE), output “active state”
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PCNTR <= (PWM_ENTIRE_CYCLE - PWM_ACT_CYCLE), output “~ (active state)”
Active state of PWM0 channel is high level (PCR0. PWM_ACT_STA = 1)
When PCNTR0 > (PPR0. PWM_ENTIRE_CYCLE - PPR0.PWM_ACT_CYCLE), then PWM0 outputs 1 (high level).
When PCNTR0 <= (PPR0. PWM_ENTIRE_CYCLE - PPR0.PWM_ACT_CYCLE), then PWM0 outputs 0 (low level).
The formula of the output period and the duty-cycle for PWM are as follows.
Tperiod = (PWM01_CLK / PWM0_PRESCALE_K)-1 * (PPR0.PWM_ENTIRE_CYCLE + 1)
Thigh-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * PPR0.PWM_ACT_CYCLE
Tlow-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * (PPR0.PWM_ENTIRE_CYCLE + 1 - PPR0.PWM_ACT_CYCLE)
Duty-cycle = (high level time) / (1 period time) = Thigh-level / Tperiod
Figure 9-84 PWM0 High Level Active State
active state = high level 1 period
active state = high
Initial state
PWM0 High level
Low level
Active state of PWM0 channel is low level (PCR0. PWM_ACT_STA = 0)
When PCNTR0 > (PPR0.PWM_ENTIRE_CYCLE - PPR0.PWM_ACT_CYCLE), then PWM0 outputs 0.
When PCNTR0 <= (PPR0.PWM_ENTIRE_CYCLE - PPR0.PWM_ACT_CYCLE), then PWM0 outputs 1.
The formula of the output period and the duty-cycle for PWM are as follows.
Tperiod = (PWM01_CLK / PWM0_PRESCALE_K)-1 * (PPR0.PWM_ENTIRE_CYCLE + 1)
Thigh-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * (PPR0.PWM_ENTIRE_CYCLE + 1 - PPR0.PWM_ACT_CYCLE)
Tlow-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * PPR0.PWM_ACT_CYCLE
Duty-cycle = (low level time) / (1 period time) = Tlow-level /Tperiod
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Figure 9-85 PWM0 Low Level Active State
active state = low level 1 period
Initial state
PWM0
Low level
High level
active state = low
The counter of PCNTR starts from 0 by default, it can output the pulse control of the waveform by setting
PWM_COUNTER_START. The figure is as follows.
Figure 9-86 Phase of PWM0 High Level Active State
active state: high level
PWM_ENTIRE_CYCLE=3
PWM_ACTIVE_CYCLE=2
PWM_CNTSTART=0
PWM_CNTSTART=1
PWM_CNTSTART=2
PWM_CNTSTART=3
9.10.3.6 Pulse Mode and Cycle Mode
The PWM output supports pulse mode and cycle mode. PWM in pulse mode outputs one pulse waveform, but
PWM in cycle mode outputs continuous waveform. Figure 9-87 shows the PWM output waveform in pulse
mode and cycle mode.
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Figure 9-87 PWM0 Output Waveform in Pulse Mode and Cycle Mode
active state = low level
PPR0.PWM_ENTIRE_CYCLE =10 PPR0.PWM_ENTIRE_CYCLE =10
Initial state PPR0.PWM_ACT_CYCLE = 3 PPR0.PWM_ACT_CYCLE = 1
long-period mode
PCR0.PWM_MODE = 0
PWM0_EN = 1 active state
PPR0.PWM_ACT_CYCLE = 3 PPR0.PWM_ACT_CYCLE = 1
Initial state
single-pulse mode
PCR0.PWM_MODE = 1
PWM0_EN = 1 active state active state active state
PCR0.PWM_PUL_START = 1 PCR0.PWM_PUL_START = 1 PCR0.PWM_PUL_START = 1
active state = high level PPR0.PWM_ENTIRE_CYCLE =10
Initial state PPR0.PWM_ACT_CYCLE = 3
long-period mode
PCR0.PWM_MODE = 0
PWM0_EN = 1
PPR0.PWM_ACT_CYCLE = 3
Initial state
single-pulse mode
PCR0.PWM_MODE = 1
PWM0_EN = 1 active state active state
PCR0.PWM_PUL_START = 1 PCR0.PWM_PUL_START = 1
Each channel of the PWM module supports the PWM output of pulse mode and cycle mode, the active state
of the PWM output waveform can be programmed to control.
When PCR0[PWM_MODE] is 0, the PWM0 outputs in cycle mode. When PCR0[PWM_MODE] is 1, the PWM0
outputs in pulse mode.
Specifically, in pulse mode, after the PWM0 channel enabled, PCR0[PWM_PUL_START] needs to be set to 1
when the PWM0 needs to output pulse waveform, after completed the output, PCR0[PWM_PUL_START] can
be cleared to 0 by hardware. The next setting 1 can be operated after PCR0[PWM_PUL_START] is cleared.
9.10.3.7 Complementary Pair Output
Every PWM pair supports complementary pair output and PWM pair with dead-time. Figure 9-88 shows the
complementary pair output of PWM01.
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Figure 9-88 PWM01 Complementary Pair Output
Initial state
PWM0
PWM0_EN = 1 active state = low
PWM1_EN = 1
active state = high
Initial state
PWM1
The complementary pair output needs to satisfy the following conditions:
PWM0 and PWM1 have the same clock divider, frequency, duty-cycle, and phase
PWM0 and PWM1 have an opposite active state
Enable the clock gating of PWM0 and PWM1 at the same time
Enable the waveform output of PWM0 and PWM1 at the same time
9.10.3.8 Dead-time Generator
Every PWM pair has a programmable dead-time generator. When the dead-time function of the PWM pair
enabled, the PWM01 output waveform is decided by PWM timer logic and DeadZone Generator. Figure 9-89
shows the output waveform.
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Figure 9-89 Dead-time Output Waveform
Before dead-time inserted
(complementary pair) 1 2 3
Initial state
PWM0
Initial state
PWM1 4 5 6
After dead-time inserted
(non-complementary pair) dead-time
Initial state
PWM0
Initial state
PWM1
The PWM waveform before the insertion of dead-time indicates a complementary waveform pair of non-
inserted dead-time in Dead Zone Generator 01.
The PWM waveform after the insertion of dead-time indicates a non-complementary PWM waveform pair
inserted dead-time in a complementary waveform pair of Dead Zone Generator 01. The PWM waveform pair
at last outputs to PWM0 pin and PWM1 pin.
For the complementary pair of Dead Zone Generator 01, the principle of inserting dead-time is that to insert
dead-time as soon as the rising edge came. If the high level time for mark② in the above figure is less than
dead-time, then dead-time will override the high level. The setting of dead-time needs to consider the period
and the duty-cycle of the output waveform. The dead-time formula is defined as follows:
Dead-time = (PWM01_CLK / PWM0_PRESCALE_K)-1 * PDZINTV01
9.10.3.9 PWM Group Mode
Taking PWM Group0 as an example. The same group of PWM channel is selected to work by PGR0.CS; the same
PWM_ENTIRE_CYCLE, PWM_ACT_CYCLE are set by the same clock configuration; the different
PWM_COUNTER_START can output PWM group signals with the same duty-cycle and the different phase.
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Figure 9-90 Group 0–3 PWM Signal Output
active state:high level
PWM_GROUP0_EN=1 PWM_ENTIRE_CYCLE=3 PWM_MODE=1
PWM_GROUP0_CS=16'h000f PWM_ACTIVE_CYCLE=2 PWM_PUL_NUM=2
PWM0_CNTSTART=0
PWM1_CNTSTART=1
PWM2_CNTSTART=2
PWM3_CNTSTART=3
PWM_GROUP0_START=1
9.10.3.10 Capture Input
Figure 9-91 PWM01 Capture Logic Module Diagram
CFLR0
CRLR0
CCR0
PPR0 PCNTR0
PCR0.PWM_PRESCAL_K CCR0.CAPINV
CAP0_EN
8-bit PWM TIMER0 0 PWM0 PIN
prescaler LOGIC 1
CFIE0 CCR0.CFLF
CFIS0
CRIE0 CCR0.CRLF
CRIS0
CAP0_EN
PWM01_CLK
CFLR1
CRLR1
CCR1
PPR1 PCNTR1
PCR1.PWM_PRESCAL_K CCR1.CAPINV
CAP1_EN
8-bit PWM TIMER1 0 PWM1 PIN
prescaler LOGIC 1
CFIE1 CCR1.CFLF
CFIS1
CRIE1 CCR1.CRLF
CRIS1
CAP1_EN
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Besides the timer logic module of every PWM channel generates PWM output, it can be used to capture the
rising edge and the falling edge of the external clock. Using the PWM0 channel as an example, the PWM0
channel has one CFLR0 and one CRLR0 for capturing up-counter value on the falling edge and rising edge,
respectively. You can calculate the period of the external clock by CFLR0 and CRLR0.
Thigh-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * CRLR0
Tlow-level = (PWM01_CLK / PWM0_PRESCALE_K)-1 * CFLR0
Tperiod = Thigh-level + Tlow-level
Figure 9-92 PWM0 Channel Capture Timing
16-bit adding-counter 0 0 0 1 2 3 4 0 1 2 3 0 1 2 3 4 5
reload
external clock reload
CAP0_EN
No reload because of no CRIS0 or CFIS0 set
CRIE0
CFIE0
Set by HW
CRIS0 Clear by SW
Set by HW
CFIS0 Clear by SW
Set by HW Set by HW
Clear by SW Clear by SW
CCR0.CRLF
Set by HW Set by HW
CCR0.CFLF Clear by SW Clear by SW
rising lock
CRLR0 4 falling lock
CFLR0 3
When the capture input function of the PWM0 channel is enabled, the PCNTR of the PWM0 channel starts to
work.
When the timer logic module of PWM0 captures a rising edge, the current value of the up-counter is locked to
CRLR0 and CCR0[CRLF] is set to 1. If CRIE0 is 1, then CRIS0 is set to 1, the PWM0 channel sends interrupt
requests, and the up-counter is loaded to 0 and continues to count. If CRIE0 is 0, the timer logic module of
PWM0 captures a rising edge, CRIS0 cannot be set to 1, the up-counter is not loaded to 0.
When the timer logic module of PWM0 captures one falling edge, the current value of PCNTR is locked to CFLR0
and CCR0[CFLF] is set to 1. If CFIE0 is 1, then CFIS0 is set to 1, the PWM0 channel sends interrupt requests, and
the up-counter is loaded to 0 and continues to count. If CFIE0 is 0, the timer logic module of PWM0 captures a
falling edge, CFIS0 cannot be set to 1, the up-counter is not loaded to 0.
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9.10.3.11 Interrupt
The PWM supports an interrupt generation when configuring the PWM channel to PWM output or capturing
input.
For PWM output function, when the controller outputs one period of PWM waveform in cycle mode, the PIS
of the corresponding PWM channel is set to 1; when the controller outputs (PWM_PULNUM+1) periods of
PWM waveform in pulse mode, the PIS of the corresponding PWM channel is set to 1.
NOTE
The PIS bit is set to 1 automatically by hardware and cleared by software.
For capturing input function, when the timer logic module of the capture channel0 captures rising edge, and
CRIE0 is 1, then CRIS0 is set to 1; when the timer logic module of the capture channel0 captures falling edge,
and CFIE0 is 1, then CFIS0 is set to 1.
9.10.4 Programming Guidelines
The following working mode takes PWM01 as an example, other PWM pairs and PWM01 are consistent.
9.10.4.1 Configuring Clock
Step 1 PWM gating: When using PWM, write 1 to PCGR[PWMx_CLK_GATING].
Step 2 PWM clock source select: Set PCCR01[PWM01_CLK_SRC] to select HOSC or APB0 clock.
Step 3 PWM clock divider: Set PCCR01[PWM01_CLK_DIV_M] to select different frequency division
coefficient (1/2/4/8/16/32/64/128/256).
Step 4 PWM clock bypass: Set PCGR[PWM_CLK_SRC_BYPASS_TO_PWM] to 1, output the PWM clock after
the secondary frequency division to the corresponding PWM output pin.
Step 5 PWM internal clock configuration: Set PCR[PWM_PRESCAL_K] to select any frequency division
coefficient from 1 to 256.
NOTE
For the channel of complementary output and group mode, firstly, set the same clock configurations (clock
source selects APB0, clock division configures the same division factor); secondly, open clock gating at the
same time; thirdly, configure PWM parameters; finally, enable PWM output at the same time to ensure each
channel sync.
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We suggest that the two channels of the same PWM pair cannot subject to two groups because of they have
the same first level clock division and gating. If must allocate based on this way, the first level of clock division
of the channel used by all groups needs to set to the same coefficient and open gating at the same time.
And the total module needs to be reset when the group mode regroups.
9.10.4.2 Configuring PWM
Step 1 PWM mode: Set PCR[PWM_MODE] to select cycle mode or pulse mode, if pulse mode,
PCR[PWM_PUL_NUM] needs to be configured.
Step 2 PWM active level: Set PCR[PWM_ACT_STA] to select a low level or high level.
Step 3 PWM duty-cycle: Configure PPR[PWM_ENTIRE_CYCLE] and PPR[PWM_ACT_CYCLE] after clock gating
is opened.
Step 4 PWM starting/stoping phase: Configure PCNTR[PWM_COUNTER_START] after the clock gating is
enabled and before the PWM is enabled. You can verify whether the configuration was successful by
reading back PCNTR[PWM_COUNTER_STATUS].
Step 5 Enable PWM: Configure PER to select the corresponding PWM enable bit; when selecting pulse mode,
PCR[PWM_PUL_START] needs to be enabled.
9.10.4.3 Configuring Deadzone
Step 1 Set initial value: set [PDZINTV01].
Step 2 Enable Deadzone: set [PWM01_DZ_CN].
9.10.4.4 Configuring Capture Input
Step 1 Enable capture: Configure CER to enable the corresponding channel.
Step 2 Capture mode: Configure CCR[CRLF] and CCR[CFLF] to select rising edge capture or falling edge
capture, configure CCR[CAPINV] to select whether the input signal does reverse processing.
9.10.5 Register List
Module Name Base Address
PWM 0x02000C00
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Register Name Offset Description
PIER 0x0000 PWM IRQ Enable Register
PISR 0x0004 PWM IRQ Status Register
CIER 0x0010 Capture IRQ Enable Register
CISR 0x0014 Capture IRQ Status Register
PCCR01 0x0020 PWM01 Clock Configuration Register
PCCR23 0x0024 PWM23 Clock Configuration Register
PCCR45 0x0028 PWM45 Clock Configuration Register
PCCR67 0x002C PWM67 Clock Configuration Register
PCGR 0x0040 PWM Clock Gating Register
PDZCR01 0x0060 PWM01 Dead Zone Control Register
PDZCR23 0x0064 PWM23 Dead Zone Control Register
PDZCR45 0x0068 PWM45 Dead Zone Control Register
PDZCR67 0x006C PWM67 Dead Zone Control Register
PER 0x0080 PWM Enable Register
PGR0 0x0090 PWM Group0 Register
PGR1 0x0094 PWM Group1 Register
PGR2 0x0098 PWM Group2 Register
PGR3 0x009C PWM Group3 Register
CER 0x00C0 Capture Enable Register
0x0100+0x0000+N*0x0020
PCR PWM Control Register
(N= 0–7)
0x0100+0x0004+N*0x0020
PPR PWM Period Register
(N= 0–7)
0x0100+0x0008+N*0x0020
PCNTR PWM Count Register
(N= 0–7)
0x0100+0x000C+N*0x0020
PPCNTR PWM Pulse Count Register
(N= 0–7)
0x0100+0x0010+N*0x0020
CCR Capture Control Register
(N= 0–7)
0x0100+0x0014+N*0x0020
CRLR Capture Rise Lock Register
(N= 0–7)
0x0100+0x0018+N*0x0020
CFLR Capture Fall Lock Register
(N= 0–7)
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9.10.6 Register Description
9.10.6.1 0x0000 PWM IRQ Enable Register (Default Value: 0x0000_0000)
Offset:0x0000 Register Name: PIER
Bit Read/Write Default/Hex Description
31:20 / / /
PGIE3
PWM Group 3 Interrupt Enable
19 R/W 0x0
0: Disable
1: Enable
PGIE2
PWM Group 2 Interrupt Enable
18 R/W 0x0
0: Disable
1: Enable
PGIE1
PWM Group 1 Interrupt Enable
17 R/W 0x0
0: Disable
1: Enable
PGIE0
PWM Group 0 Interrupt Enable
16 R/W 0x0
0: Disable
1: Enable
15:8 / / /
PCIE7
PWM Channel 7 Interrupt Enable
7 R/W 0x0
0: PWM Channel 7 Interrupt Disable
1: PWM Channel 7 Interrupt Enable
PCIE6
PWM Channel 6 Interrupt Enable
6 R/W 0x0
0: PWM Channel 6 Interrupt Disable
1: PWM Channel 6 Interrupt Enable
PCIE5
PWM Channel 5 Interrupt Enable
5 R/W 0x0
0: PWM Channel 5 Interrupt Disable
1: PWM Channel 5 Interrupt Enable
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Offset:0x0000 Register Name: PIER
Bit Read/Write Default/Hex Description
PCIE4
PWM Channel 4 Interrupt Enable
4 R/W 0x0
0: PWM Channel 4 Interrupt Disable
1: PWM Channel 4 Interrupt Enable
PCIE3
PWM Channel 3 Interrupt Enable
3 R/W 0x0
0: PWM Channel 3 Interrupt Disable
1: PWM Channel 3 Interrupt Enable
PCIE2
PWM Channel 2 Interrupt Enable
2 R/W 0x0
0: PWM Channel 2 Interrupt Disable
1: PWM Channel 2 Interrupt Enable
PCIE1
PWM Channel 1 Interrupt Enable
1 R/W 0x0
0: PWM Channel 1 Interrupt Disable
1: PWM Channel 1 Interrupt Enable
PCIE0
PWM Channel 0 Interrupt Enable
0 R/W 0x0
0: PWM Channel 0 Interrupt Disable
1: PWM Channel 0 Interrupt Enable
9.10.6.2 0x0004 PWM IRQ Status Register (Default Value: 0x0000_0000)
Offset:0x0004 Register Name: PISR
Bit Read/Write Default/Hex Description
31:20 / / /
PGIS3
19 R/W1C 0x0
PWM Group 3 Interrupt Status
PGIS2
18 R/W1C 0x0
PWM Group 2 Interrupt Status
PGIS1
17 R/W1C 0x0
PWM Group 1 Interrupt Status
PGIS0
16 R/W1C 0x0
PWM Group 0 Interrupt Status
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Offset:0x0004 Register Name: PISR
Bit Read/Write Default/Hex Description
15:8 / / /
PIS7
PWM Channel 7 Interrupt Status
When the PWM channel 7 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
7 R/W1C 0x0
Reads 0: PWM channel 7 interrupt is not pending.
Reads 1: PWM channel 7 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 7 interrupt status.
PIS6
PWM Channel 6 Interrupt Status
When the PWM channel 6 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
6 R/W1C 0x0
Reads 0: PWM channel 6 interrupt is not pending.
Reads 1: PWM channel 6 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 6 interrupt status.
PIS5
PWM Channel 5 Interrupt Status
When the PWM channel 5 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
5 R/W1C 0x0
Reads 0: PWM channel 5 interrupt is not pending.
Reads 1: PWM channel 5 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 5 interrupt status.
PIS4
PWM Channel 4 Interrupt Status
When the PWM channel 4 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
4 R/W1C 0x0
Reads 0: PWM channel 4 interrupt is not pending.
Reads 1: PWM channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 4 interrupt status.
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Offset:0x0004 Register Name: PISR
Bit Read/Write Default/Hex Description
PIS3
PWM Channel 3 Interrupt Status
When the PWM channel 3 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
3 R/W1C 0x0
Reads 0: PWM channel 3 interrupt is not pending.
Reads 1: PWM channel 3 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 3 interrupt status.
PIS2
PWM Channel 2 Interrupt Status
When the PWM channel 2 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
2 R/W1C 0x0
Reads 0: PWM channel 2 interrupt is not pending.
Reads 1: PWM channel 2 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 2 interrupt status.
PIS1
PWM Channel 1 Interrupt Status
When the PWM channel 1 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
1 R/W1C 0x0
Reads 0: PWM channel 1 interrupt is not pending.
Reads 1: PWM channel 1 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 1 interrupt status.
PIS0
PWM Channel 0 Interrupt Status
When the PWM channel 0 counter reaches the Entire Cycle
Value, this bit is set 1 by hardware. Writing 1 to clear this bit.
0 R/W1C 0x0
Reads 0: PWM channel 0 interrupt is not pending.
Reads 1: PWM channel 0 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear PWM channel 0 interrupt status.
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9.10.6.3 0x0010 PWM Capture IRQ Enable Register (Default Value: 0x0000_0000)
Offset:0x0010 Register Name: CIER
Bit Read/Write Default/Hex Description
31:16 / / /
CFIE7
If the enable bit is set to 1, when the capture channel 7 captures
15 R/W 0x0 falling edge, it generates a capture channel 7 pending.
0: Capture channel 7 fall lock interrupt disable
1: Capture channel 7 fall lock interrupt enable
CRIE7
If the enable bit is set to 1, when the capture channel 7 captures
14 R/W 0x0 rising edge, it generates a capture channel 7 pending.
0: Capture channel 7 rise lock interrupt disable
1: Capture channel 7 rise lock interrupt enable
CFIE6
If the enable bit is set to 1, when the capture channel 6 captures
13 R/W 0x0 falling edge, it generates a capture channel 6 pending.
0: Capture channel 6 fall lock interrupt disable
1: Capture channel 6 fall lock interrupt enable
CRIE6
If the enable bit is set to 1, when the capture channel 6 captures
12 R/W 0x0 rising edge, it generates a capture channel 6 pending.
0: Capture channel 6 rise lock interrupt disable
1: Capture channel 6 rise lock interrupt enable
CFIE5
If the enable bit is set to 1, when the capture channel 5 captures
11 R/W 0x0 falling edge, it generates a capture channel 5 pending.
0: Capture channel 5 fall lock interrupt disable
1: Capture channel 5 fall lock interrupt enable
CRIE5
If the enable bit is set to 1, when the capture channel 5 captures
10 R/W 0x0 rising edge, it generates a capture channel 5 pending.
0: Capture channel 5 rise lock interrupt disable
1: Capture channel 5 rise lock interrupt enable
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Offset:0x0010 Register Name: CIER
Bit Read/Write Default/Hex Description
CFIE4
If the enable bit is set to 1, when the capture channel 4 captures
9 R/W 0x0 falling edge, it generates a capture channel 4 pending.
0: Capture channel 4 fall lock interrupt disable
1: Capture channel 4 fall lock interrupt enable
CRIE4
If the enable bit is set to 1, when the capture channel 4 captures
8 R/W 0x0 rising edge, it generates a capture channel 4 pending.
0: Capture channel 4 rise lock interrupt disable
1: Capture channel 4 rise lock interrupt enable
CFIE3
If the enable bit is set to 1, when the capture channel 3 captures
7 R/W 0x0 falling edge, it generates a capture channel 3 pending.
0: Capture channel 3 fall lock interrupt disable
1: Capture channel 3 fall lock interrupt enable
CRIE3
If the enable bit is set to 1, when the capture channel 3 captures
6 R/W 0x0 rising edge, it generates a capture channel 3 pending.
0: Capture channel 3 rise lock interrupt disable
1: Capture channel 3 rise lock interrupt enable
CFIE2
If the enable bit is set to 1, when the capture channel 2 captures
5 R/W 0x0 falling edge, it generates a capture channel 2 pending.
0: Capture channel 2 fall lock interrupt disable
1: Capture channel 2 fall lock interrupt enable
CRIE2
If the enable bit is set to 1, when the capture channel 2 captures
4 R/W 0x0 rising edge, it generates a capture channel 2 pending.
0: Capture channel 2 rise lock interrupt disable
1: Capture channel 2 rise lock interrupt enable
CFIE1
If the enable bit is set to 1, when the capture channel 1 captures
3 R/W 0x0 falling edge, it generates a capture channel 1 pending.
0: Capture channel 1 fall lock interrupt disable
1: Capture channel 1 fall lock interrupt enable
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Offset:0x0010 Register Name: CIER
Bit Read/Write Default/Hex Description
CRIE1
If the enable bit is set to 1, when the capture channel 1 captures
2 R/W 0x0 rising edge, it generates a capture channel 1 pending.
0: Capture channel 1 rise lock interrupt disable
1: Capture channel 1 rise lock interrupt enable
CFIE0
If the enable bit is set to 1, when the capture channel 0 captures
1 R/W 0x0 falling edge, it generates a capture channel 0 pending.
0: Capture channel 0 fall lock interrupt disable
1: Capture channel 0 fall lock interrupt enable
CRIE0
If the enable bit is set to 1, when the capture channel 0 captures
0 R/W 0x0 rising edge, it generates a capture channel 0 pending.
0: Capture channel 0 rise lock interrupt disable
1: Capture channel 0 rise lock interrupt enable
9.10.6.4 0x0014 PWM Capture IRQ Status Register (Default Value: 0x0000_0000)
Offset:0x0014 Register Name: CISR
Bit Read/Write Default/Hex Description
31:18 / / /
CFIS7
Status of the capture channel 7 falling lock interrupt
When the capture channel 7 captures falling edge, if the fall lock
interrupt (CFIE7) is enabled, this bit is set to 1 by hardware.
15 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 7 interrupt is not pending.
Reads 1: The capture channel 7 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 7 interrupt.
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Offset:0x0014 Register Name: CISR
Bit Read/Write Default/Hex Description
CRIS7
Status of the capture channel 7 rising lock interrupt
When the capture channel 7 captures rising edge, if the rise lock
interrupt (CRIE7) is enabled, this bit is set to 1 by hardware. Write
14 R/W1C 0x0 1 to clear this bit.
Reads 0: The capture channel 7 interrupt is not pending.
Reads 1: The capture channel 7 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 7 interrupt.
CFIS6
Status of the capture channel 6 falling lock interrupt
When the capture channel 6 captures falling edge, if the fall lock
interrupt (CFIE6) is enabled, this bit is set to 1 by hardware.
13 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 6 interrupt is not pending.
Reads 1: The capture channel 6 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 6 interrupt.
CRIS6
Status of the capture channel 6 rising lock interrupt.
When the capture channel 6 captures rising edge, if the rise lock
interrupt (CRIE6) is enabled, this bit is set to 1 by hardware.
12 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 6 interrupt is not pending.
Reads 1: The capture channel 6 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 6 interrupt.
CFIS5
Status of the capture channel 5 falling lock interrupt
When the capturing channel 5 captures falling edge, if the fall lock
interrupt (CFIE5) is enabled, this bit is set to 1 by hardware.
11 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 5 interrupt is not pending.
Reads 1: The capture channel 5 interrupt is pending.
Writes 0: No effect.
Reads 1: Clear the status of the capture channel 5 interrupt.
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Offset:0x0014 Register Name: CISR
Bit Read/Write Default/Hex Description
CRIS5
Status of the capture channel 5 rising lock interrupt
When the capture channel 5 captures rising edge, if the rise lock
interrupt (CRIE5) is enabled, this bit is set to 1 by hardware.
10 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 5 interrupt is not pending.
Reads 1: The capture channel 5 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 5 interrupt.
CFIS4
Status of the capture channel 4 falling lock interrupt
When the capture channel 4 captures falling edge, if the fall lock
interrupt (CFIE4) is enabled, this bit is set to 1 by hardware.
9 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 4 interrupt is not pending.
Reads 1: The capture channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 4 interrupt.
CRIS4
Status of the capture channel 4 rising lock interrupt.
When the capture channel 4 captures rising edge, if the rise lock
interrupt (CRIE4) is enabled, this bit is set to 1 by hardware.
Writing 1 to clear this bit.
8 R/W1C 0x0
Reads 0: The capture channel 4 interrupt is not pending.
Reads 1: The capture channel 4 interrupt is pending.
Writes 0: No effect.
Writes 1: Clear the status of the capture channel 4 interrupt
status.
CFIS3
Status of the capture channel 3 falling lock interrupt.
When the capture channel 3 captures falling edge, if the fall lock
interrupt (CFIE3) is enabled, this bit is set to 1 by hardware.
7 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 3 interrupt is not pending.
Reads 1: The capture channel 3 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 3 interrupt.
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Offset:0x0014 Register Name: CISR
Bit Read/Write Default/Hex Description
CRIS3
Status of the capture channel 3 rising lock interrupt
When the capture channel 3 captures rising edge, if the rise lock
interrupt (CRIE3) is enabled, this bit is set to 1 by hardware.
6 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 3 interrupt is not pending.
Reads 1: The capture channel 3 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 3 interrupt.
CFIS2
Status of the capture channel 2 falling lock interrupt
When the capture channel 2 captures falling edge, if the fall lock
interrupt (CFIE2) is enabled, this bit is set to 1 by hardware.
5 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 2 interrupt is not pending.
Reads 1: The capture channel 2 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 2 interrupt.
CRIS2
Status of the capture channel 2 rising lock interrupt.
When the capture channel 2 captures rising edge, if the rise lock
interrupt (CRIE2) is enabled, this bit is set to 1 by hardware.
4 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 2 interrupt is not pending.
Reads 1: The capture channel 2 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 2 interrupt.
CFIS1
Status of the capture channel 1 falling lock interrupt
When the capture channel 1 captures falling edge, if the fall lock
interrupt (CFIE1) is enabled, this bit is set to 1 by hardware.
3 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 1 interrupt is not pending.
Reads 1: The capture channel 1 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 1 interrupt.
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Offset:0x0014 Register Name: CISR
Bit Read/Write Default/Hex Description
CRIS1
Status of the capture channel 1 rising lock interrupt.
When the capture channel 1 captures rising edge, if the rise lock
interrupt (CRIE1) is enabled, this bit is set to 1 by hardware.
2 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 1 interrupt is not pending.
Reads 1: The capture channel 1 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 1 interrupt.
CFIS0
Status of the capture channel 0 falling lock interrupt
When the capture channel 0 captures falling edge, if the fall lock
interrupt (CFIE0) is enabled, this bit is set to 1 by hardware.
1 R/W1C 0x0 Writing 1 to clear this bit.
Reads 0: The capture channel 0 interrupt is not pending.
Reads 1: The capture channel 0 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 0 interrupt.
CRIS0
Status of the capture channel 0 rising lock interrupt
When the capture channel 0 captures rising edge, if the rise lock
interrupt (CRIE0) is enabled, this bit is set 1 by hardware. Writing
0 R/W1C 0x0 1 to clear this bit.
Reads 0: The capture channel 0 interrupt is not pending.
Reads 1: The capture channel 0 interrupt is pending.
Writes 0: no effect.
Writes 1: Clear the status of the capture channel 0 interrupt.
9.10.6.5 0x0020 PWM01 Clock Configuration Register (Default Value: 0x0000_0000)
Offset:0x0020 Register Name: PCCR01
Bit Read/Write Default/Hex Description
31:9 / / /
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Offset:0x0020 Register Name: PCCR01
Bit Read/Write Default/Hex Description
PWM01_CLK_SRC
Select PWM01 Clock Source
8:7 R/W 0x0 00: HOSC
01: APB0
Others: Reserved
6:4 / / /
PWM01_CLK_DIV_M
PWM01 Clock Divide M
0000: /1
0001: /2
0010: /4
0011: /8
3:0 R/W 0x0
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
Others: Reserved
9.10.6.6 0x0024 PWM23 Clock Configuration Register (Default Value: 0x0000_0000)
Offset:0x0024 Register Name: PCCR23
Bit Read/Write Default/Hex Description
31:9 / / /
PWM23_CLK_SRC_SEL
Select PWM23 Clock Source
8:7 R/W 0x0 00: HOSC
01: APB0
Others: Reserved
6:4 / / /
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Offset:0x0024 Register Name: PCCR23
Bit Read/Write Default/Hex Description
PWM23_CLK_DIV_M
PWM23 Clock Divide M
0000: /1
0001: /2
0010: /4
0011: /8
3:0 R/W 0x0
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
Others: Reserved
9.10.6.7 0x0028 PWM45 Clock Configuration Register (Default Value: 0x0000_0000)
Offset:0x0028 Register Name: PCCR45
Bit Read/Write Default/Hex Description
31:9 / / /
PWM45_CLK_SRC_SEL
Select PWM45 Clock Source
8:7 R/W 0x0 00: HOSC
01: APB0
Others: Reserved
6:4 / / /
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Offset:0x0028 Register Name: PCCR45
Bit Read/Write Default/Hex Description
PWM45_CLK_DIV_M
PWM45 Clock Divide M
0000: /1
0001: /2
0010: /4
0011: /8
3:0 R/W 0x0
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
Others: Reserved
9.10.6.8 0x002C PWM67 Clock Configuration Register (Default Value: 0x0000_0000)
Offset:0x002C Register Name: PCCR67
Bit Read/Write Default/Hex Description
31:9 / / /
PWM67_CLK_SRC_SEL
Select PWM67 Clock Source
8:7 R/W 0x0 00: HOSC
01: APB0
Others: Reserved
6:4 / / /
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Offset:0x002C Register Name: PCCR67
Bit Read/Write Default/Hex Description
PWM67_CLK_DIV_M
PWM67 Clock Divide M
0000: /1
0001: /2
0010: /4
0011: /8
3:0 R/W 0x0
0100: /16
0101: /32
0110: /64
0111: /128
1000: /256
Others: Reserved
9.10.6.9 0x0040 PWM Clock Gating Register (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: PCGR
Bit Read/Write Default/Hex Description
31:24 / / /
PWM7_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM7 output
23 R/W 0x0
0: not bypass
1: bypass
PWM6_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM6 output
22 R/W 0x0
0: not bypass
1: bypass
PWM5_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM5 output
21 R/W 0x0
0: not bypass
1: bypass
PWM4_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM4 output
20 R/W 0x0
0: not bypass
1: bypass
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Offset: 0x0040 Register Name: PCGR
Bit Read/Write Default/Hex Description
PWM3_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM3 output
19 R/W 0x0
0: not bypass
1: bypass
PWM2_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM2 output
18 R/W 0x0
0: not bypass
1: bypass
PWM1_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM1 output
17 R/W 0x0
0: not bypass
1: bypass
PWM0_CLK_BYPASS
Bypass clock source (after pre-scale) to PWM0 output
16 R/W 0x0
0: not bypass
1: bypass
15:8 / / /
PWM7_CLK_GATING
Gating clock for PWM7
7 R/W 0x0
0: Mask
1: Pass
PWM6_CLK_GATING
Gating clock for PWM6
6 R/W 0x0
0: Mask
1: Pass
PWM5_CLK_GATING
Gating clock for PWM5
5 R/W 0x0
0: Mask
1: Pass
PWM4_CLK_GATING
Gating clock for PWM4
4 R/W 0x0
0: Mask
1: Pass
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Offset: 0x0040 Register Name: PCGR
Bit Read/Write Default/Hex Description
PWM3_CLK_GATING
Gating clock for PWM3
3 R/W 0x0
0: Mask
1: Pass
PWM2_CLK_GATING
Gating clock for PWM2
2 R/W 0x0
0: Mask
1: Pass
PWM1_CLK_GATING
Gating clock for PWM1
1 R/W 0x0
0: Mask
1: Pass
PWM0_CLK_GATING
Gating clock for PWM0
0 R/W 0x0
0: Mask
1: Pass
9.10.6.10 0x0060 PWM01 Dead Zone Control Register (Default Value: 0x0000_0000)
Offset:0x0060 Register Name: PDZCR01
Bit Read/Write Default/Hex Description
31:16 / / /
PWM01_DZ_INTV
15:8 R/W 0x0
PWM01 Dead Zone Interval Value
7:1 / / /
PWM01_DZ_EN
PWM01 Dead Zone Enable
0 R/W 0x0
0: Dead Zone disable
1: Dead Zone enable
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9.10.6.11 0x0064 PWM23 Dead Zone Control Register (Default Value: 0x0000_0000)
Offset:0x0064 Register Name: PDZCR23
Bit Read/Write Default/Hex Description
31:16 / / /
PWM23_DZ_INTV
15:8 R/W 0x0
PWM23 Dead Zone Interval Value
7:1 / / /
PWM23_DZ_EN
PWM23 Dead Zone Enable
0 R/W 0x0
0: Dead Zone disable
1: Dead Zone enable
9.10.6.12 0x0068 PWM45 Dead Zone Control Register (Default Value: 0x0000_0000)
Offset:0x0068 Register Name: PDZCR45
Bit Read/Write Default/Hex Description
31:16 / / /
PWM45_DZ_INTV
15:8 R/W 0x0
PWM45 Dead Zone Interval Value
7:1 / / /
PWM45_DZ_EN
PWM45 Dead Zone Enable
0 R/W 0x0
0: Dead Zone disable
1: Dead Zone enable
9.10.6.13 0x006C PWM67 Dead Zone Control Register (Default Value: 0x0000_0000)
Offset:0x006C Register Name: PDZCR67
Bit Read/Write Default/Hex Description
31:16 / / /
PWM67_DZ_INTV
15:8 R/W 0x0
PWM67 Dead Zone Interval Value
7:1 / / /
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Offset:0x006C Register Name: PDZCR67
Bit Read/Write Default/Hex Description
PWM67_DZ_EN
PWM67 Dead Zone Enable
0 R/W 0x0
0: Dead Zone disable
1: Dead Zone enable
9.10.6.14 0x0080 PWM Enable Register (Default Value: 0x0000_0000)
Offset:0x0080 Register Name: PER
Bit Read/Write Default/Hex Description
31:8 / / /
PWM7_EN
When PWM is enabled, the 16-bit up-counter starts working and
7 R/W 0x0 PWM channel7 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM6_EN
When PWM is enabled, the 16-bit up-counter starts working and
6 R/W 0x0 PWM channel6 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM5_EN
When PWM is enabled, the 16-bit up-counter starts working and
5 R/W 0x0 PWM channel5 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM4_EN
When PWM is enabled, the 16-bit up-counter starts working and
4 R/W 0x0 PWM channel4 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM3_EN
When PWM is enabled, the 16-bit up-counter starts working and
3 R/W 0x0 PWM channel3 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
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Offset:0x0080 Register Name: PER
Bit Read/Write Default/Hex Description
PWM2_EN
When PWM is enabled, the 16-bit up-counter starts working and
2 R/W 0x0 PWM channel2 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM1_EN
When PWM is enabled, the 16-bit up-counter starts working and
1 R/W 0x0 PWM channel1 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
PWM0_EN
When PWM is enabled, the 16-bit up-counter starts working and
0 R/W 0x0 PWM channel0 is permitted to output PWM waveform.
0: PWM disable
1: PWM enable
9.10.6.15 0x0090 PWM Group0 Register (Default Value: 0x0000_0000)
Offset: 0x0090 Register Name: PGR0
Bit Read/Write Default/Hex Description
31:18 / / /
PWMG0_START
17 R/WAC 0x0 The PWM channels selected in PWMG0_CS start to output PWM
waveform at the same time.
PWMG0_EN
16 R/W 0x0
PWM Group0 Enable.
PWMG0_CS
15:0 R/W 0x0
If bit[i] is set, the PWM i is selected as one channel of PWM Group0.
9.10.6.16 0x0094 PWM Group1 Register (Default Value: 0x0000_0000)
Offset: 0x0094 Register Name: PGR1
Bit Read/Write Default/Hex Description
31:18 / / /
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Offset: 0x0094 Register Name: PGR1
Bit Read/Write Default/Hex Description
PWMG1_START
17 R/WAC 0x0 The PWM channels selected in PWMG1_CS start to output PWM
waveform at the same time.
PWMG1_EN
16 R/W 0x0
PWM Group1 Enable.
PWMG1_CS
15:0 R/W 0x0
If bit[i] is set, the PWM i is selected as one channel of PWM Group1.
9.10.6.17 0x0098 PWM Group2 Register (Default Value: 0x0000_0000)
Offset: 0x0098 Register Name: PGR2
Bit Read/Write Default/Hex Description
31:18 / / /
PWMG2_START
17 R/WAC 0x0 The PWM channels selected in PWMG2_CS start to output PWM
waveform at the same time.
PWMG2_EN
16 R/W 0x0
PWM Group2 Enable.
PWMG2_CS
15:0 R/W 0x0
If bit[i] is set, the PWM i is selected as one channel of PWM Group2.
9.10.6.18 0x009C PWM Group3 Register (Default Value: 0x0000_0000)
Offset: 0x009C Register Name: PGR3
Bit Read/Write Default/Hex Description
31:18 / / /
PWMG3_START
17 R/WAC 0x0 The PWM channels selected in PWMG3_CS start to output PWM
waveform at the same time.
PWMG3_EN
16 R/W 0x0
PWM Group3 Enable.
PWMG3_CS
15:0 R/W 0x0
If bit[i] is set, the PWM i is selected as one channel of PWM Group3.
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9.10.6.19 0x00C0 Capture Enable Register (Default Value: 0x0000_0000)
Offset: 0x00C0 Register Name: CER
Bit Read/Write Default/Hex Description
31:8 / / /
CAP7_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel7 is permitted to capture external
7 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP6_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel6 is permitted to capture external
6 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP5_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel5 is permitted to capture external
5 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP4_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel4 is permitted to capture external
4 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP3_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel3 is permitted to capture external
3 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
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Offset: 0x00C0 Register Name: CER
Bit Read/Write Default/Hex Description
CAP2_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel2 is permitted to capture external
2 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP1_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel1 is permitted to capture external
1 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
CAP0_EN
When enabling the capture function, the 16-bit up-counter starts
working, and the capture channel is permitted to capture external
0 R/W 0x0
falling edge or rising edge.
0: Capture disable
1: Capture enable
9.10.6.20 0x0100 + N*0x20 PWM Control Register (Default Value: 0x0000_0000)
Offset:0x0100+0x0+N*0x20 (N=0~7) Register Name: PCR
Bit Read/Write Default/Hex Description
PWM_PUL_NUM
31:16 R/W 0x0 In pulse mode, the PWM outputs pulse for PWM_CYCLE_NUM+1
times and then stops.
15:12 / / /
PWM_PERIOD_RDY
PWM Period Register Ready
11 R 0x0
0: PWM period register is ready to write
1: PWM period register is busy
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Offset:0x0100+0x0+N*0x20 (N=0~7) Register Name: PCR
Bit Read/Write Default/Hex Description
PWM_PUL_START
PWM Pulse Output Start
0: No effect
10 R/WAC 0x0 1: Output pulse for PWM_CYCLE_NUM+1.
After finishing configuration for the output pulse, set this bit once ,
then PWM would output waveform. After the waveform is finished,
the bit will be cleared automatically.
PWM_MODE
PWM Output Mode Select
9 R/W 0x0
0: Cycle mode
1: Pulse mode
PWM_ACT_STA
PWM Active State
8 R/W 0x0
0: Low Level
1: High Level
PWM_PRESCAL_K
PWM pre-scale K, actual pre-scale is (K+1).
K = 0, actual pre-scale: 1
K = 1, actual pre-scale: 2
7:0 R/W 0x0
K = 2, actual pre-scale: 3
K = 3, actual pre-scale: 4
...
K = 255, actual pre-scale: 256
9.10.6.21 0x0104 + N*0x20 PWM Period Register (Default Value: 0x0000_0000)
Offset:0x0100+0x04+N*0x20 (N=0~7) Register Name: PPR
Bit Read/Write Default/Hex Description
PWM_ENTIRE_CYCLE
Number of the entire cycles in the PWM clock.
0: 1 cycle
1: 2 cycles
31:16 R/W 0x0
…
N: N+1 cycles
If the register needs to be modified dynamically, the PCLK should
be faster than the PWM CLK.
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Offset:0x0100+0x04+N*0x20 (N=0~7) Register Name: PPR
Bit Read/Write Default/Hex Description
PWM_ACT_CYCLE
Number of the active cycles in the PWM clock.
0: 0 cycle
15:0 R/W 0x0
1: 1 cycle
…
N: N cycles
9.10.6.22 0x0108 + N*0x20 PWM Counter Register (Default Value: 0x0000_0000)
Offset:0x0100+0x08+N*0x20 (N=0~7) Register Name: PCNTR
Bit Read/Write Default/Hex Description
PWM_COUNTER_START
31:16 R/W 0x0
PWM counter value is set for phase control.
PWM_COUNTER_STATUS
15:0 R 0x0 On PWM output or capture input, reading this register could get
the current value of the PWM 16-bit up-counter.
9.10.6.23 0x010C + N*0x20 PWM Pulse Counter Register (Default Value: 0x0000_0000)
Offset: 0x0100+0x0C+N*0x20 (N=0~7) Register Name: PPCNTR
Bit Read/Write Default/Hex Description
31:16 / / /
PWM_PUL_COUNTER_STATUS
15:0 R 0x0 On PWM output, reading this register could get the current
value of the PWM pulse counter.
9.10.6.24 0x0110 + N*0x20 PWM Capture Control Register (Default Value: 0x0000_0000)
Offset:0x0100+0x10+N*0x20 (N=0~7) Register Name: CCR
Bit Read/Write Default/Hex Description
31:5 / / /
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Offset:0x0100+0x10+N*0x20 (N=0~7) Register Name: CCR
Bit Read/Write Default/Hex Description
CRLF
When the capture channel captures a rising edge, the current
4 R/W1C 0x0 value of the 16-bit up-counter is latched to CRLR, and then this bit
is set 1 by hardware.
Write 1 to clear this bit.
CFLF
When the capture channel captures a falling edge, the current
3 R/W1C 0x0 value of the 16-bit up-counter is latched to CFLR, and then this bit
is set 1 by hardware.
Write 1 to clear this bit.
CRTE
2 R/W 0x0
Rising edge capture trigger enable
CFTE
1 R/W 0x0
Falling edge capture trigger enable
CAPINV
Inverse the signal input from capture channel before 16-bit
0 R/W 0x0 counter of capture channel.
0: not inverse
1: inverse
9.10.6.25 0x0114 + N*0x20 PWM Capture Rise Lock Register (Default Value: 0x0000_0000)
Offset:0x0100+0x14+N*0x20 (N=0~7) Register Name: CRLR
Bit Read/Write Default/Hex Description
31:16 / / /
CRLR
15:0 R 0x0 When the capture channel captures a rising edge, the current
value of the 16-bit up-counter is latched to the register.
9.10.6.26 0x0118 + N*0x20 PWM Capture Fall Lock Register (Default Value: 0x0000_0000)
Offset:0x0100+0x18+N*0x20 (N=0~7) Register Name: CFLR
Bit Read/Write Default/Hex Description
31:16 / / /
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Offset:0x0100+0x18+N*0x20 (N=0~7) Register Name: CFLR
Bit Read/Write Default/Hex Description
CFLR
15:0 R 0x0 When the capture channel captures a falling edge, the current
value of the 16-bit up-counter is latched to the register.
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9.11 LEDC
9.11.1 Overview
The LEDC is used to control the external LED lamp.
The LEDC has the following features:
Configurable LED output high-/low-level width
Configurable LED reset time
LEDC data supports DMA configuration mode and CPU configuration mode
Maximum 1024 LEDs serial connect
LED data transfer rate up to 800 kbit/s
Configurable RGB display mode
The default level of non-data output is configurable
9.11.2 Block Diagram
The following figure shows a block diagram of the LEDC.
Figure 9-93 LEDC Block Diagram
APB config control
Data_trans LED LED ... LED
24*32
DMA FIFO
LEDC
LEDC contains the following sub-blocks:
Table 9-32 LEDC Sub-blocks
Sub-block Description
config register configuration
control LEDC timing control and status control
FIFO 24-bit width x 32 depth
Data_trans Convert input data to the 0 and 1 characters of LED
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9.11.3 Functional Description
9.11.3.1 External Signals
The following table describes the external signals of the LEDC.
Table 9-33 LEDC External Signals
Signal Description Type
LEDC-DO Intelligent Control LED Signal Output O
9.11.3.2 Clock Sources
The following table describes the clock sources of the LEDC.
Table 9-34 LEDC Clock Sources
Clock Sources Description
HOSC 24 MHz
PLL_PERI(1X) Peripheral Clock. The default value is 600 MHz
9.11.3.3 LEDC Timing
Figure 9-94 LEDC Package Output Timing Diagram
Package
t1H t1L t0H t0L
led_data_out
…
1 0
data reset
LED data format
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Figure 9-95 LEDC 1-frame Output Timing Diagram
wait wait
time0 time1
24bit 24bit ... 24bit 24bit
9.11.3.4 LEDC Input Data Structure
The RGB mode of LEDC data is configurable. By default, the data is sent in GRB order, and the higher bit is
transmitted first.
Figure 9-96 LEDC Input Data Structure
G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 B7 B6 B5 B4 B3 B2 B1 B0
9.11.3.5 LEDC Typical Circuit
Figure 9-97 LEDC Typical Circuit
GND GND
L1 L2 LN
GND DO GND DO GND DO DO
C1 C1 C1
DI DI VDD DI VDD DI VDD
VDD- VDD-
5V 5V
C1 is the bypass capacitor of LED light, and its value is usually 100 nF.
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9.11.3.6 LEDC Data Input Code
Figure 9-98 LEDC Data Input Code
0 code T0h T0L
1 code T1h
Reset code Treset
9.11.3.7 LEDC Data Transfer Time
The time parameter of the typical LED specification shows as follows.
T0H 0 code, high-level time 220 ns to 380 ns
T0L 0 code, low-level time 580 ns to 1.6 us
T1H 1 code, high-level time 580 ns to 1.6 us
T1L 1 code, low-level time 220 ns to 420 ns
RESET Frame unit, low-level time > 280 us
9.11.3.8 LEDC Data Transfer Mode
Figure 9-99 LEDC Data Transfer Mode
Treset
D0 The 1st 24bit The 2nd 24bit The 3rd 24bit The nth 24bit The 1st 24bit The 2nd 24bit The 3rd 24bit The nth 24bit
D1 The 2nd 24bit The 3rd 24bit The nth 24bit The 2nd 24bit The 3rd 24bit The nth 24bit
D2 The 3rd 24bit The nth 24bit The 3rd 24bit The nth 24bit
Dn The nth 24bit The nth 24bit
9.11.3.9 LEDC Parameter
1. PAD rate > 800 kbit/s
2. LED number supported:
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T0-code: 800 ns to 1980 ns, T1-code: 800 ns to 2020 ns
When the LED refresh rate is 30 frame/s, LED number supported is (1 s/30-280 us)/((800 ns to 2020 ns)*24)
=1024 ￬to 681.
When the LED refresh rate is 60 frame/s, LED number supported is (1 s/60-280 us)/((800 ns to 2020 ns)*24)
=853 ￬to 338.
9.11.3.10 LEDC Data Transfer
The LEDC supports DMA data transfer mode or CPU data transfer mode. The DMA data transfer mode is set by
LEDC_DMA_EN.
Data transfer in DMA mode
When the valid space of internal FIFO is greater than the setting FIFO free space threshold, the LEDC sends
DMA_REQ to require DMA to transfer data from DRAM to LEDC. The maximum data transfer size in DMA mode
is 16 words. (The internal FIFO level is 32.)
Data transfer in CPU mode
When the valid space of internal FIFO is greater than the setting FIFO free space threshold, the LEDC sends
LEDC_CPUREQ_INT to require CPU to transfer data to LEDC. The transfer data size in CPU mode is controlled
by software. The internal FIFO destination address is 0x06700014. The data width is 32-bit. (The lower 24-bit
is valid.)
9.11.3.11 LEDC Interrupt
Module Name Description
FIFO overflow interrupt.
The data written by external is more than the maximum storage
space of LED FIFO, the LEDC will be in data loss state. At this time,
software needs to deal with the abnormal situation. The processing
FIFO_OVERFLOW_INT
mode is as follows.
The software can query LED_FIFO_DATA_REG to determine which
data has been stored in the internal FIFO of LEDC. The LEDC
performs soft_reset operation to refresh all data.
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Module Name Description
Wait for data timeout interrupt
When internal FIFO of LEDC cannot get data because of some
abnormal situation, the timeout interrupt is set after
led_wait_data_time, now the LEDC is in WAIT_DATA state, and the
LEDC outputs a level state configured by LED_POLARITY; in the
WAITDATA_TIMEOUT_INT course of wait_data, if the new data arrives, the LEDC will continue
to send data, at this time the software needs to notice whether the
waiting time of the LEDC exceeds the operation time of reset. If the
waiting time of the LEDC exceeds the operation time of reset (this
is equivalent to reset operation sent by LEDC), the LED may enter
in refresh state, the data has not been sent.
FIFO request CPU data interrupt
FIFO_CPUREQ_INT When FIFO data is less than a threshold, the interrupt will be
reported to the CPU.
Data transfer complete interrupt
LEDC_TRANS_FINISH_INT The value indicates that the data configured as total_data_length
has been transferred completely.
LEDC interrupt usage scenario:
CPU mode
The software can enable GLOBAL_INT_EN, FIFO_CPUREQ_INT_EN, WAITDATA_TIMEOUT_INT_EN,
FIFO_OVERFLOW_INT_EN, LEDC_TRANS_FINISH_INT_EN, and cooperate with LEDC_FIFO_TRIG_LEVEL to use.
When FIFO_CPUREQ_INT is set to 1, the software can configure data of LEDC_FIFO_TRIG_LEVEL to LEDC.
DMA mode
The software can enable GLOBAL_INT_EN, WAITDATA_TIMEOUT_INT_EN, FIFO_OVERFLOW_INT_EN,
LEDC_TRANS_FINISH_INT_EN, and cooperate with LEDC_FIFO_TRIG_LEVEL to use. When DMA receives LEDC
DMA_REQ, DMA can transfer data of LEDC_FIFO_TRIG_LEVEL to LEDC.
9.11.4 Programming Guidelines
9.11.4.1 LEDC Normal Configuration Process
Step 1 Configure LEDC_CLK and bus pclk.
Step 2 Configure the written LEDC data.
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Step 3 Configure LED_T01_TIMING_CTRL_REG, LEDC_DATA_FINISH_CNT_REG,
LED_RESET_TIMING_CTRL_REG, LEDC_WAIT_TIME0_CTRL_REG, LEDC_DMA_CTRL_REG,
LEDC_INTERRUPT_CTRL_REG. Configure 0-code, 1-code, reset time, LEDC waiting time, and the
number of external connected LEDC and the threshold of DMA transfer data.
Step 4 Configure LEDC_CTRL_REG to enable LEDC_EN, the LEDC will start to output data.
Step 5 When the LEDC interrupt is pulled up, it indicates the configured data has transferred complete, at
this time LED_EN will be set to 0, and the read/write point of LEDC FIFO is cleared to 0.
Step 6 Repeat step1, 2, 3, 4 to re-execute a new round of configuration, enable LEDC_EN, the LEDC will start
new data transfer.
Figure 9-100 LEDC Normal Configuration Process
Start
APB BUS Clk control
LEDC data configuration
LEDC register configuration
{
LED_T0&1_TIMING_CTRL_REG
LEDC_DATA_FINISH_CNT_REG
LED_RESET_TIMING_CTRL_REG
LEDC_WAIT_TIME_CTRL_REG
LEDC_DMA_CTRL_REG
LEDC_INTERRUPT_CTRL_REG
}
LEDC enable
{LEDC_CTRL_REG}
LED_EN is set to 0
Finish
LEDC_FINSIH_INT
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9.11.4.2 LEDC Abnormal Scene Processing Flow
WAITDATA_TIMEOUT Abnormal Status
Step 1 When WAITDATA_TIMEOUT_INT appears, it indicates the internal FIFO data request of LEDC cannot
obtain a response, at this time if the default output level is low, then the external LED may think there
was a reset operation and cause LED data to be flushed incorrectly.
Step 2 The LEDC needs to be performed soft_reset operation (LEDC_SOFT_RESET=1); after soft_reset, the
LEDC_EN will be pulled-down automatically, all internal status register and control state machine will
return to the idle state, the LEDC FIFO read & write point is cleared to 0, the LEDC interrupt is cleared.
Step 3 Setting reset_led_en to 1 indicates LEDC can actively send a reset operation to ensure the external
LED lamp in the right state.
Step 4 The software reads the status of reset_led_en, when the status value is 1, it indicates LEDC does not
perform the transmission of LED reset operation; when the status value is 0, the LEDC completes the
transmission of LED reset operation.
Step 5 When LEDC reset operation finishes, the LEDC data and register configuration need to be re-operated
to start re-transmission data operation.
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Figure 9-101 LEDC Timeout Abnormal Processing Flow
Start
APB BUS clk control
LEDC data configuration
LEDC register configuration
{
LED_T0&1_TIMING_CTRL_REG
LEDC_DATA_FINISH_CNT_REG
LED_RESET_TIMING_CTRL_REG
LEDC_WAIT_TIME_CTRL_REG
LEDC_DMA_CTRL_REG
LEDC_INTERRUPT_CTRL_REG
}
LEDC enable
{LEDC_CTRL_REG}
WAITDATA_TIMEOUT_INT
clear interrupt
LEDC_CTRL_REG
(soft_reset)
LEDC_CTRL_REG
(reset_led_en=1)
FIFO Overflow Abnormal Status
Step 1 When FIFO_OVERFLOW_INT appears, it indicates the data configured by software exceeds the LEDC
FIFO space, at this time the redundant data will be lost.
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Step 2 The software needs to read data in LEDC_FIFO_DATA_X to confirm the lost data.
Step 3 The software re-configures the lost data to the LEDC.
Step 4 If the software uses the soft_reset operation, the operation is the same with the timeout abnormal
processing flow.
Figure 9-102 FIFO Overflow Abnormal Processing Flow
Start
APB BUS clk control
LEDC data configuration
LEDC register configuration
{
LED_T0&1_TIMING_CTRL_REG
LEDC_DATA_FINISH_CNT_REG
LED_RESET_TIMING_CTRL_REG
LEDC_WAIT_TIME_CTRL_REG
LEDC_DMA_CTRL_REG
LEDC_INTERRUPT_CTRL_REG
}
LEDC enable
{LEDC_CTRL_REG}
FIFO_OVERFLOW_INT
clear interrupt
Software reads FIFO data to confirm
the lost data
{FIFO_DATA_REG_X}
Software re-configures the lost data
to LEDC
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9.11.5 Register List
Module Name Base Address
LEDC 0x02008000
Register Name Offset Description
LEDC_CTRL_REG 0x0000 LEDC Control Register
LED_T01_TIMING_CTRL_REG 0x0004 LEDC T0 & T1 Timing Control Register
LEDC_DATA_FINISH_CNT_REG 0x0008 LEDC Data Finish Counter Register
LED_RESET_TIMING_CTRL_REG 0x000C LEDC Reset Timing Control Register
LEDC_WAIT_TIME0_CTRL_REG 0x0010 LEDC Wait Time0 Control Register
LEDC_DATA_REG 0x0014 LEDC Data Register
LEDC_DMA_CTRL_REG 0x0018 LEDC DMA Control Register
LEDC_INT_CTRL_REG 0x001C LEDC Interrupt Control Register
LEDC_INT_STS_REG 0x0020 LEDC Interrupt Status Register
LEDC_WAIT_TIME1_CTRL_REG 0x0028 LEDC Wait Time1 Control Register
LEDC_FIFO_DATA_REG 0x0030+0x04*N LEDC FIFO Data Register
9.11.6 Register Description
9.11.6.1 0x0000 LEDC Control Register (Default Value: 0x0000_003C)
Offset: 0x0000 Register Name: LEDC_CTRL_REG
Bit Read/Write Default/Hex Description
31:29 / / /
TOTAL_DATA_LENGTH
Total length of transfer data (range: 0 to 8K, unit: 32-bit, only
low 24-bit is valid)
The field is recommended to be set to an integer multiple of
28:16 R/W 0x0
(LED_NUM+1).
If TOTAL_DATA_LENGTH is greater than (LED_NUM+1), but non-
integer multiple, the last frame of data will transfer data less
than (LED_NUM+1).
15:11 / / /
RESET_LED_EN
10 R/W 0x0
Write operation:
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Offset: 0x0000 Register Name: LEDC_CTRL_REG
Bit Read/Write Default/Hex Description
The software writes 1 to the bit, the CPU triggers LEDC to
transfer a reset to LED.
Only when LEDC is in IDLE status, the reset can be performed.
After the reset finished, the control state machine returns to
the IDLE status. To return LEDC to the IDLE status, it also needs
to be used with SOFT_RESET.
When the software sets the bit, the software can read the bit
to check if the reset is complete.
Read operation:
0: LEDC completes the transmission of the LED reset operation
1: LEDC does not complete the transmission of the LED reset
operation
9 / / /
LED_RGB_MODE
000 GRB (bypass)
001 GBR
010 RGB
011 RBG
100 BGR
101 BRG
By default, the software configures data to LEDC according to
GRB (MSB) mode, the LEDC internal combines data to output to
the external LED.
Other modes configure as follows.
Software Input
8:6 R/W 0x0 Configuration LEDC Output Mode
Mode
000 GRB
001 GBR
010 RGB
GRB
011 RBG
100 BGR
101 BRG
000 GBR
001 GRB
GBR
010 BGR
011 BRG
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Offset: 0x0000 Register Name: LEDC_CTRL_REG
Bit Read/Write Default/Hex Description
100 RGB
101 RBG
000 RGB
001 RBG
010 GRB
RGB
011 GBR
100 BRG
101 BGR
000 RBG
001 RGB
010 BRG
RBG
011 BGR
100 GRB
101 GBR
000 BGR
001 BRG
010 GBR
BGR
011 GRB
100 RBG
101 RGB
000 BRG
001 BGR
010 RBG
BRG
011 RGB
100 GBR
101 GRB
LED_MSB_TOP
Adjust sequence of the combined GRB data
5 R/W 0x1
0: LSB
1: MSB
LED_MSB_G
4 R/W 0x1 MSB control for Green data
0: LSB
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Offset: 0x0000 Register Name: LEDC_CTRL_REG
Bit Read/Write Default/Hex Description
1: MSB
LED_MSB_R
MSB control for Red data
3 R/W 0x1
0: LSB
1: MSB
LED_MSB_B
MSB control for Blue data
2 R/W 0x1
0: LSB
1: MSB
LEDC_SOFT_RESET
LEDC soft reset
Write 1 to clear it automatically.
The ranges of LEDC soft reset include the following points: all
internal status registers, the control state machine returns to in
idle status, the LEDC FIFO read & write point is cleared to 0, the
LEDC interrupt is cleared; and the affected registers are
followed.
1.LEDC_CTRL_REG (LEDC_EN is cleared to 0);
1 R/W1C 0x0 2. PLL_T0&1_TIMING_CTRL_REG remains unchanged;
3. LEDC_DATA_FINISH_CNT_REG (LEDC_DATA_FINISH_CNT is
cleared to 0);
4.LED_RESET_TIMING_CTRL_REG remains unchanged;
5. LEDC_WAIT_TIME_CTRL_REG remains unchanged;
6. LEDC_DMA_CTRL_REG remains unchanged;
7. LEDC_INTERRUPT_CTRL_REG remains unchanged;
8.LEDC_INT_STS _REG is cleared to 0;
9. LEDC_CLK_GATING_REG remains unchanged;
10.LEDC_FIFO_DATA_REG remains unchanged;
LEDC_EN
LEDC Enable
0: Disable
0 R/W 0x0 1: Enable
That the bit is enabled indicates LEDC can be started when LEDC
data finished transmission or LEDC_EN is cleared to 0 by
hardware in LEDC_SOFT_RESET situation.
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9.11.6.2 0x0004 LEDC T0 & T1 Timing Control Register (Default Value: 0x0286_01D3)
Offset: 0x0004 Register Name: LED_T01_TIMING_CTRL_REG
Bit Read/Write Default/Hex Description
31:27 / / /
T1H_TIME
LED T1H time
26:21 R/W 0x14 Unit: cycle (24 MHz), T1H_TIME =42 ns*(N+1)
The default value is 882 ns, the range is 80 ns–2560 ns.
N: 1–3F. When is 0, T1H_TIME = 3F
T1L_TIME
LED T1L time
20:16 R/W 0x6 Unit: cycle (24 MHz), T1L_TIME =42 ns*(N+1)
The default value is 294 ns, the range is 80 ns–1280 ns.
N: 1–1F. When is 0, T1L_TIME = 1F
15:11 / / /
T0H_TIME
LED T0h time
10:6 R/W 0x7 Unit: cycle (24 MHz), T0H_TIME =42 ns*(N+1)
The default value is 336 ns, the range is 80 ns–1280 ns.
N: 1–1F. When is 0, T0H_TIME = 1F
T0L_TIME
LED T0l time
5:0 R/W 0x13 Unit: cycle (24 MHz), T0L_TIME =42 ns*(N+1)
The default value is 840 ns, the range is 80 ns–2560 ns.
N: 1–3F. When is 0, T0L_TIME = 3F
9.11.6.3 0x0008 LEDC Data Finish Counter Register (Default Value: 0x1D4C_0000)
Offset: 0x0008 Register Name: LEDC_DATA_FINISH_CNT_REG
Bit Read/Write Default/Hex Description
31:30 / / /
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Offset: 0x0008 Register Name: LEDC_DATA_FINISH_CNT_REG
Bit Read/Write Default/Hex Description
LED_WAIT_DATA_TIME
The value is the time that internal FIFO in LEDC is waiting for
data. When the time is exceeded, the LEDC will send the
wait_data_timeout_int interrupt. (This is an abnormal situation,
29:16 R/W 0x1D4C software needs to reset LEDC.)
The value is about 300 us by default.
The adjust range is 80 ns–655 us.
led_wait_data_time=42ns*(N+1).
N: 1–1FFF. When the field is 0, LEDC_WAIT_DATA_TIME=1FFF
15:13 / / /
LED_DATA_FINISH_CNT
12:0 R 0x0 The value is the total LED data that have been sent. (Range: 0–
8k)
9.11.6.4 0x000C LEDC Reset Timing Control Register (Default Value: 0x1D4C_0000)
Offset: 0x000C Register Name: LED_RESET_TIMING_CTRL_REG
Bit Read/Write Default/Hex Description
31:29 / / /
TR_TIME
Reset time control of LED lamp
Unit: cycle (24 MHz), tr_time=42 ns*(N+1)
28:16 R/W 0x1D4C
The default value is 300 us.
The adjust range is 80 ns–327 us.
N: 1–1FFF
15:10 / / /
LED_NUM
The value is the number of external LED lamp. Maximum up to
9:0 R/W 0x0 1024.
The default value 0 indicates that 1 LED lamp is external
connected. The range is from 0 to 1023.
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9.11.6.5 0x0010 LEDC Wait Time 0 Control Register (Default Value: 0x0000_00FF)
Offset: 0x0010 Register Name: LEDC_WAIT_TIME0_CTRL_REG
Bit Read/Write Default/Hex Description
31:9 / / /
WAIT_TIM0_EN
WAIT_TIME0 enable
When it is 1, the controller automatically inserts waiting time
8 R/W 0x0
between LED package data.
0: Disable
1: Enable
TOTAL_WAIT_TIME0
Waiting time between 2 LED data. The LEDC output is low level.
The adjust range is 80 ns–10 us.
7:0 R/W 0xFF
wait_time0=42 ns*(N+1)
Unit: cycle(24 MHz)
N: 1–FF
9.11.6.6 0x0014 LEDC Data Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: LEDC_DATA_REG
Bit Read/Write Default/Hex Description
LEDC DATA
31:0 W 0x0
LED display data (the lower 24-bit is valid)
9.11.6.7 0x0018 LEDC DMA Control Register (Default Value: 0x0000_002F)
Offset: 0x0018 Register Name: LEDC_DMA_CTRL_REG
Bit Read/Write Default/Hex Description
31:6 / / /
LEDC_DMA_EN
LEDC DMA request enable
5 R/W 0x1
0: Disable request of DMA transfer data
1: Enable request of DMA transfer data
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Offset: 0x0018 Register Name: LEDC_DMA_CTRL_REG
Bit Read/Write Default/Hex Description
LEDC_FIFO_TRIG_LEVEL
The remaining space of internal FIFO in LEDC
The internal FIFO in LEDC is 24*32.
When the remaining space of internal FIFO in LEDC is more than
4:0 R/W 0x0F or equal to LEDFIFO_TRIG_LEVEL, the DMA or the CPU request
will generate. The default value is 15.
The adjusted value is from 1 to 31. The recommended
configuration is 7 or 15. When the configuration value is 0,
LEDFIFO_TRIG_LEVEL=F.
9.11.6.8 0x001C LEDC Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: LEDC_INTERRUPT_CTRL_REG
Bit Read/Write Default/Hex Description
31:6 / / /
GLOBAL_INT_EN
Global interrupt enable
5 R/W 0x0
0: Disable
1: Enable
FIFO_OVERFLOW_INT_EN
FIFO overflow interrupt enable
When the data written by the software is more than the internal
4 R/W 0x0
FIFO level of LEDC, the LEDC is in the data loss state.
0: Disable
1: Enable
WAITDATA_TIMEOUT_INT_EN
The internal FIFO in LEDC cannot get data because of some
abnormal situation, after the time of led_wait_data_time, the
3 R/W 0x0
interrupt will be enabled.
0: Disable
1: Enable
2 / / /
FIFO_CPUREQ_INT_EN
FIFO request CPU data interrupt enable
1 R/W 0x0
0: Disable
1: Enable
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Offset: 0x001C Register Name: LEDC_INTERRUPT_CTRL_REG
Bit Read/Write Default/Hex Description
LED_TRANS_FINISH_INT_EN
Data transmission complete interrupt enable
0 R/W 0x0
0: Disable
1: Enable
9.11.6.9 0x0020 LEDC Interrupt Status Register (Default Value: 0x0002_0000)
Offset: 0x0020 Register Name: LEDC_INT_STS_REG
Bit Read/Write Default/Hex Description
31:18 / / /
FIFO_EMPTY
17 R 0x1
FIFO empty status flag
FIFO_FULL
16 R 0x0
FIFO full status flag
FIFO_WLW
15:10 R 0x0 FIFO internal valid data depth
It indicates the space FIFO has been occupied.
9:5 / / /
FIFO_OVERFLOW_INT
FIFO overflow interrupt
The data written by external is more than the maximum storage
space of LED FIFO, the LEDC will be in the data loss state. At this
time, the software needs to deal with the abnormal situation.
4 R/W1C 0x0 The processing mode is as follows.
(1) The software can query LED_FIFO_DATA_REG to determine
which data has been stored in the internal FIFO of LEDC.
(2) The LEDC performs soft_reset operation to refresh all data.
0: FIFO not overflow
1: FIFO overflow
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Offset: 0x0020 Register Name: LEDC_INT_STS_REG
Bit Read/Write Default/Hex Description
WAITDATA_TIMEOUT_INT
When internal FIFO of LEDC cannot get data because of some
abnormal situation, after led_wait_data_time, the timeout
interrupt is set, the LEDC is in WAIT_DATA state, the LEDC
outputs a level state configured by LED_POLARITY; in the course
of wait_data, if the new data arrives, the LEDC will continue to
3 R/W1C 0x0 send data, at this time software needs to notice whether the
waiting time of LEDC exceeds the operation time of reset. If the
waiting time of LEDC exceeds the operation time of reset (this is
equivalent to reset operation sent by LEDC), the LED may enter
in refresh state, the data has not been sent.
0: LEDC not timeout
1: LEDC timeout
2 / / /
FIFO_CPUREQ_INT
FIFO request CPU data interrupt
When FIFO data is less than the threshold, the interrupt will be
1 R/W1C 0x0
reported to the CPU.
0: FIFO does not request that CPU transfers data
1: FIFO requests that CPU transfers data
LED_TRANS_FINISH_INT
Data transfer complete interrupt
The value indicates that the data configured as
0 R/W1C 0x0
total_data_length is transferred completely.
0: Data is not transferred completely
1: Data is transferred completely
9.11.6.10 0x0028 LEDC Wait Time 1 Control Register (Default Value: 0x01FF_FFFF)
Offset: 0x0028 Register Name: LEDC_WAIT_TIME1_CTRL_REG
Bit Read/Write Default/Hex Description
WAIT_TIM1_EN
0: Disable
1: Enable
31 R/W 0x0
WAIT_TIME1 enable
When the bit is 1, the controller automatically inserts the
waiting time between the LED frame data.
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Offset: 0x0028 Register Name: LEDC_WAIT_TIME1_CTRL_REG
Bit Read/Write Default/Hex Description
TOTAL_WAIT_TIME1
Waiting time between 2 frame data.
The LEDC output is low level.
30:0 R/W 0x01FFFFFF The adjust range is 80 ns– 85 s. wait_time1=42 ns*(N+1)
Unit: cycle (24 MHz)
N: 0x80–0x7FFFFFFF
If the value is 0, TOTAL_WAIT_TIME1=0x7FFFFFFF
9.11.6.11 0x0030+N*0x04 LEDC FIFO Data Register X (Default Value: 0x0000_0000)
Offset: 0x0030+N*0x04 (N=0–31) Register Name: LEDC_FIFO_DATA_X
Bit Read/Write Default/Hex Description
LEDC_FIFO_DATA_X
31:0 R 0x0 Internal FIFO data of LEDC
The lower 24-bit is valid.
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9.12 EMAC
9.12.1 Overview
The Ethernet Medium Access Controller (EMAC) enables a host to transmit and receive data over Ethernet in
compliance with the IEEE 802.3-2002 standard. It supports 10/100/1000 Mbit/s external PHY with RMII/RGMII
interface in full-duplex and half-duplex modes. The internal DMA is designed for packet-oriented data transfers
based on a linked list of descriptors.
The EMAC has the following features:
One 10/100/1000 Mbit/s Ethernet port with reduced gigabit media independent interface (RGMII) and
reduced media independent interface (RMII) interfaces, for connecting the external EPHY
Compliant with IEEE 802.3-2002 standard
Provides the management data input/output (MDIO) interface for PHY device configuration and
management with configurable clock frequencies
Supports both full-duplex and half-duplex operations
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
Supports a variety of flexible address filtering modes
Separate 32-bit status returned for transmission and reception packets
Optimization for packet-oriented DMA transfers with frame delimiters
- Supports linked-list descriptor list structure
- Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each
descriptor can transfer up to 4 KB of data
- Comprehensive status reporting for normal operation and transfers with errors
4 KB TXFIFO for transmission packets and 16 KB RXFIFO for reception packets
Programmable interrupt options for different operational conditions
9.12.2 Block Diagram
The following figure shows the block diagram of EMAC.
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Figure 9-103 EMAC Block Diagram
TXFIFO RXFIFO
DMA TXFC RXFC
EMAC
xMII
AHB
RMII/RGMII SEL
Master
MAC CSR External
OMR PHY
DMA CSR
Register MDC
MDIO
AHB Slave
9.12.3 Functional Description
9.12.3.1 External Signals
The following table describes the pin mapping of EMAC.
Table 9-35 EMAC Pin Mapping
Pin Name RGMII RMII
RGMII-RXD3 RXD3 /
RGMII-RXD2 RXD2 /
RGMII-RXD1/RMII-RXD1 RXD1 RXD1
RGMII-RXD0/RMII-RXD0 RXD0 RXD0
RGMII-RXCK RXCK /
RGMII-RXCTRL/RMII-CRS-DV RXCTL CRS-DV
RGMII-TXD3 TXD3 /
RGMII-TXD2 TXD2 /
RGMII-TXD1/RMII-TXD1 TXD1 TXD1
RGMII-TXD0/RMII-TXD0 TXD0 TXD0
RGMII-TXCK/RMII-TXCK TXCK TXCK
RGMII-TXCTRL/RMII-TXEN TXCTL TXEN
RGMII-CLKIN/RMII-RXER CLKIN RXER
MDC MDC MDC
MDIO MDIO MDIO
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Pin Name RGMII RMII
EPHY-25M EPHY-25M EPHY-25M
The following table describes the pin list of RGMII.
Table 9-36 EMAC RGMII Pin List
Pin Name Description Type
RGMII-TXD[3:0] EMAC RGMII transmit data O
RGMII-TXCTRL EMAC RGMII transmit control O
RGMII-TXCK EMAC RGMII transmit clock O
RGMII-RXD[3:0] EMAC RGMII receive data I
RGMII-RXCTRL EMAC RGMII receive control I
RGMII-RXCK EMAC RGMII receive clock I
RGMII-CKIN EMAC RGMII 125M reference clock input I
MDC EMAC management data clock O
MDIO EMAC management data input output I/O
EPHY-25M 25 MHz output for EMAC PHY O
The following table describes the pin list of RMII.
Table 9-37 EMAC RMII Pin List
Pin Name Description Type
RMII-TXD[1:0] EMAC RMII transmit data O
RMII-TXEN EMAC RMII transmit enable O
RMII-TXCK EMAC RMII transmit clock I
RMII-RXD[1:0] EMAC RMII receive data I
RMII-CRS-DV EMAC RMII receive data valid I
RMII-RXER EMAC RMII receive error I
MDC EMAC management data clock O
MDIO EMAC management data input output I/O
EPHY-25M 25 MHz output for EMAC PHY O
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9.12.3.2 Clock Characteristics
The following table describes the clock of EMAC.
Table 9-38 EMAC Clock Characteristics
Clock Name Description Type
In RGMII mode, output 2.5 MHz/25 MHz/125 MHz.
RGMII0-TXCK/RMII0-TXCK O/I
In RMII mode, input 5 MHz/50 MHz.
In RGMII mode, input 2.5 MHz/25 MHz/125 MHz.
RGMII0-RXCK I
In RMII mode, no input.
In RGMII mode, input 125M Reference Clock.
RGMII0-CLKIN I
In RMII mode, no clock.
9.12.3.3 Typical Application
Figure 9-104 EMAC Typical Application
xMII
TX+/TX- TX+/TX-
RX+/RX- RX+/RX-
External
EMAC Transformer RJ45
PHY
MDC
MDIO
9.12.3.4 EMAC RX/TX Descriptor
The internal DMA of EMAC transfers data between host memory and internal RX/TX FIFO by a linked list of
descriptors. Each descriptor consists of four words and contains some necessary information to transfer TX and
RX frames. The following figure shows the descriptor list structure. The address of each descriptor must be 32-
bit aligned.
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Figure 9-105 EMAC RX/TX Descriptor List
1st Desc 2nd Desc 3rd Desc N-th Desc
Desc List Base Addr
1st: Status 1st: Status 1st: Status … 1st: Status
2nd: Buffer Size 2nd: Buffer Size 2nd: Buffer Size 2nd: Buffer Size
2rd: Buffer Addr 2rd: Buffer Addr 2rd: Buffer Addr 2rd: Buffer Addr
4th: Next Desc 4th: Next Desc 4th: Next Desc 4th: Next Desc
9.12.3.5 TX Descriptor
1st Word of TX Descriptor
Bits Description
TX_DESC_CTL
31 When set, the current descriptor can be used by DMA. This bit is cleared by DMA when the
whole frame is transmitted or all data in the buffer of the current descriptor are transmitted.
30:17 Reserved
TX_HEADER_ERR
16
When set, the checksum of the header for the transmitted frame is wrong.
15 Reserved
TX_LENGHT_ERR
14
When set, the length of the transmitted frame is wrong.
13 Reserved
TX_PAYLOAD_ERR
12
When set, the checksum of the payload for the transmitted frame is wrong.
11 Reserved
TX_CRS_ERR
10
When set, the carrier is lost during transmission.
TX_COL_ERR_0
9
When set, the frame is aborted because of a collision after the contention period.
TX_COL_ERR_1
8
When set, the frame is aborted because of too many collisions.
7 Reserved
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Bits Description
TX_COL_CNT
6:3
The number of collisions before transmission.
TX_DEFER_ERR
2
When set, the frame is aborted because of too much deferral.
TX_UNDERFLOW_ERR
1
When set, the frame is aborted because of the TX FIFO underflow error.
TX_DEFER
0
When set in Half-Duplex mode, the EMAC defers the frame transmission.
2nd Word of TX Descriptor
Bits Description
TX_INT_CTL
31 When it is set and the current frame has been transmitted, the TX_INT in Interrupt Status
Register will be set.
LAST_DESC
30
When it is set, the current descriptor is the last one of the current frame.
FIR_DESC
29
When it is set, the current descriptor is the first one of the current frame.
CHECKSUM_CTL
28:27
These bits control to insert checksum in the transmit frame.
CRC_CTL
26
When it is set, the CRC field is not transmitted.
25:11 Reserved
BUF_SIZE
10:0
The size of the buffer specified by the current descriptor.
3rd Word of TX Descriptor
Bits Description
BUF_ADDR
31:0
The address of the buffer specified by the current descriptor.
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4th Word of TX Descriptor
Bits Description
NEXT_DESC_ADDR
31:0
The address of the next descriptor. It must be 32-bit aligned.
9.12.3.6 RX Descriptor
1st Word of RX Descriptor
Bits Description
RX_DESC_CTL
31 When it is set, the current descriptor can be used by DMA. This bit is cleared by DMA when the
complete frame is received or the buffer of the current descriptor is full.
RX_DAF_FAIL
30
When it is set, the current frame does not pass the DA filter.
RX_FRM_LEN
When LAST_DESC is not set and no error bit is set, this field is the length of received data for
29:16 the current frame.
When LAST_DESC is set, RX_OVERFLOW_ERR and RX_NO_ENOUGH_BUF_ERR are not set, this
field is the length of the received frame.
15 Reserved
RX_NO_ENOUGH_BUF_ERR
14
When it is set, the current frame is clipped because of no enough buffer.
RX_SAF_FAIL
13
When it is set, the current fame does not pass the SA filter.
12 Reserved
RX_OVERFLOW_ERR
11
When it is set, a buffer overflow error occurred and the current frame is wrong.
10 Reserved
FIR_DESC
9
When it is set, the current descriptor is the first descriptor of the current frame.
LAST_DESC
8
When it is set, the current descriptor is the last descriptor of the current frame.
RX_HEADER_ERR
7
When it is set, the checksum of the frame header is wrong.
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Bits Description
RX_COL_ERR
6
When it is set, there is a late collision during the reception in half-duplex mode.
5 Reserved
RX_LENGTH_ERR
4
When it is set, the length of the current frame is wrong.
RX_PHY_ERR
3
When it is set, the receive error signal from PHY is asserted during the reception.
2 Reserved
RX_CRC_ERR
1
When it is set, the CRC field of the received frame is wrong.
RX_PAYLOAD_ERR
0
When it is set, the checksum or length of the payload for the received frame is wrong.
2nd Word of RX Descriptor
Bits Description
RX_INT_CTL
31
When it is set and a frame has been received, the RX_INT will not be set.
30:11 Reserved
BUF_SIZE
10:0
The size of the buffer is specified by the current descriptor.
3rd Word of RX Descriptor
Bits Description
BUF_ADDR
31:0
The address of the buffer specified by the current descriptor.
4th Word of RX Descriptor
Bits Description
NEXT_DESC_ADDR
31:0
The address of the next descriptor. This field must be 32-bit aligned.
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9.12.4 Programming Guidelines
9.12.4.1 EMAC System Configuration
Perform the following steps:
Step 1 Write 0 to EMAC_BGR_REG[bit16] to assert the module reset.
Step 2 Write 1 to EMAC_BGR_REG[bit16] to deassert the module reset.
Step 3 Write 1 to EMAC_BGR_REG[bit0] to enable the bus clock of the module.
Step 4 Configure the pin interfaces of EMAC by setting GPIO module.
Step 5 Configure EMAC_EPHY_CLK_REG0 to set the transmission clock source of RGMII/RMII.
For RGMII RXCLK/CLK125M:
In RGMII mode, in addition to the configuration of the transmission clock source, it is generally
necessary to adjust the timing by configuring the transmission clock delay, reception clock delay,
transmission clock reverse, reception clock reverse.
Write 0 to the bit[13] and write 1 to the bit[2] to select the RGMII interface.
If selecting RXCLK as the clock source of RGMII, write 2 to the bit[1:0]; if selecting CLK125M as
the clock source of RGMII, write 1 to the bit[1:0].
Write 0 to the bit[3], write 0 to the bit[4], write 31 to the bit[9:5], and write 7 to the bit[12:10]
to transmit the reception sequence adjustment.
For RMII TXCLK:
Write 1 to the bit[13] and write 0 to the bit[2] to select the RMII interface.
Write 0 to the bit[0] to select TXCLK as the clock source of RMII.
The configuration value of EMAC_EPHY_CLK_REG0 can refer to the following table.
Table 9-39 EMAC_EPHY_CLK_REG0 Configuration Value
EMAC_EPHY PHY_SEL RMII_EN ETXDC ERXDC ERXIE ETXIE RMII/ ETCS
_CLK_REG0 RGMII
Bit15 Bit13 Bit[12:10] Bit[9:5] Bit4 Bit3 Bit2 Bit[1:0]
RGMII 0 0 7 31 0 0 1 1/2
RMII 0 1 0 0 0 0 0 0
9.12.4.2 EMAC Initialization
Step 1 Write 1 to EMAC_BASIC_CTL1[bit0] to perform the software reset.
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Step 2 Write 1 to EMAC_BASIC_CTL1[bit1] to set the DMA priority of TX/RX.
Step 3 Configure EMAC_TX_CTL1 and EMAC_RX_CTL1 to set the configuration of DMA TX and DMA RX.
Step 4 Configure EMAC_INT_EN to set the corresponding interrupts and shield the needless interrupts.
Step 5 Configure EMAC_TX_DMA_LIST and EMAC_RX_DMA_LIST to set the first address of the TX descriptor
and the RX descriptor, respectively.
Step 6 Configure EMAC_TX_CTL0 and EMAC_RX_CTL0 to set the TX and RX parameters. Configure
EMAC_BASIC_CTL0 to set the speed, duplex mode, loopback configuration. (If enabled the auto-
negotiation, the configuration is performed as a result of the negotiation)
Step 7 Configure EMAC_RX_FRM_FLT to set the RX frame filter.
Step 8 Configure EMAC_TX_FLOW_CTL and EMAC_RX_CTL0 to set the control mechanism of TX and RX.
Step 9 Clear all interrupt flags.
Step 10 Write 1 to EMAC_TX_CTL0[bit31] and write 1 to EMAC_RX_CTL0[bit31] to enable the TX and RX
functions.
9.12.5 Register List
Module Name Base Address
EMAC 0x04500000
Register Name Offset Description
EMAC_BASIC_CTL0 0x0000 EMAC Basic Control Register0
EMAC_BASIC_CTL1 0x0004 EMAC Basic Control Register1
EMAC_INT_STA 0x0008 EMAC Interrupt Status Register
EMAC_INT_EN 0x000C EMAC Interrupt Enable Register
EMAC_TX_CTL0 0x0010 EMAC Transmit Control Register0
EMAC_TX_CTL1 0x0014 EMAC Transmit Control Register1
EMAC_TX_FLOW_CTL 0x001C EMAC Transmit Flow Control Register
EMAC_TX_DMA_DESC_LIST 0x0020 EMAC Transmit Descriptor List Address Register
EMAC_RX_CTL0 0x0024 EMAC Receive Control Register0
EMAC_RX_CTL1 0x0028 EMAC Receive Control Register1
EMAC_RX_DMA_DESC_LIST 0x0034 EMAC Receive Descriptor List Address Register
EMAC_RX_FRM_FLT 0x0038 EMAC Receive Frame Filter Register
EMAC_RX_HASH0 0x0040 EMAC Hash Table Register0
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Register Name Offset Description
EMAC_RX_HASH1 0x0044 EMAC Hash Table Register1
EMAC_MII_CMD 0x0048 EMAC Management Interface Command Register
EMAC_MII_DATA 0x004C EMAC Management Interface Data Register
EMAC_ADDR_HIGH0 0x0050 EMAC MAC Address High Register0
EMAC_ADDR_LOW0 0x0054 EMAC MAC Address Low Register0
0x0050+0x08*N
EMAC_ADDR_HIGHN EMAC MAC Address High Register N (N=1–7)
(N=1–7)
0x0054+0x08*N
EMAC_ADDR_LOWN EMAC MAC Address Low Register N (N=1–7)
(N=1–7)
EMAC_TX_DMA_STA 0x00B0 EMAC Transmit DMA Status Register
EMAC_TX_CUR_DESC 0x00B4 EMAC Current Transmit Descriptor Register
EMAC_TX_CUR_BUF 0x00B8 EMAC Current Transmit Buffer Address Register
EMAC_RX_DMA_STA 0x00C0 EMAC Receive DMA Status Register
EMAC_RX_CUR_DESC 0x00C4 EMAC Current Receive Descriptor Register
EMAC_RX_CUR_BUF 0x00C8 EMAC Current Receive Buffer Address Register
EMAC_RGMII_STA 0x00D0 EMAC RGMII Status Register
9.12.6 Register Description
9.12.6.1 0x0000 EMAC Basic Control Register0 (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: EMAC_BASIC_CTL0
Bit Read/Write Default/Hex Description
31:4 / / /
SPEED
EMAC Working Speed
00: 1000 Mbit/s
3:2 R/W 0x0
01: Reserved
10: 10 Mbit/s
11: 100 Mbit/s
LOOPBACK
EMAC Loopback Mode For Test
1 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0000 Register Name: EMAC_BASIC_CTL0
Bit Read/Write Default/Hex Description
DUPLEX
EMAC Transfer Mode
0 R/W 0x0
0: Half-duplex
1: Full-duplex
9.12.6.2 0x0004 EMAC Basic Control Register1 (Default Value: 0x0800_0000)
Offset: 0x0004 Register Name: EMAC_BASIC_CTL1
Bit Read/Write Default/Hex Description
31:30 / / /
BURST_LEN
29:24 R/W 0x8
The burst length of RX and TX DMA transfer.
23:2 / / /
RX_TX_PRI
RX TX DMA Priority
1 R/W 0x0
0: Same priority
1: RX priority is over TX
SOFT_RST
Soft Reset all Registers and Logic
0: No valid
0 R/W 0x0 1: Reset
All clock inputs must be valid before soft reset. This bit is
cleared internally when the reset operation is completed fully.
Before writing any register, this bit should read a 0.
9.12.6.3 0x0008 EMAC Interrupt Status Register (Default Value: 0x4000_0000)
Offset: 0x0008 Register Name: EMAC_INT_STA
Bit Read/Write Default/Hex Description
31:17 R 0x2000 Reserved
RGMII_LINK_STA_P
RMII Link Status Changed Interrupt Pending
16 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
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Offset: 0x0008 Register Name: EMAC_INT_STA
Bit Read/Write Default/Hex Description
15:14 / / /
RX_EARLY_P
RX DMA Filled First Data Buffer of the Receive Frame Interrupt
Pending
13 R/W1C 0x0
0: No Pending
1: Pending
Write ‘1’ to clear it.
RX_OVERFLOW_P
RX FIFO Overflow Error Interrupt Pending
12 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
RX_TIMEOUT_P
RX Timeout Interrupt Pending
0: No Pending
11 R/W1C 0x0 1: Pending
Write ‘1’ to clear it. When this bit is asserted, the length of the
received frame is greater than 2048 bytes (10240 when
JUMBO_FRM_EN is set)
RX_DMA_STOPPED_P
10 R/W1C 0x0
When this bit asserted, the RX DMA FSM is stopped.
RX_BUF_UA _P
RX Buffer UA Interrupt Pending
0: No Pending
1: Pending
9 R/W1C 0x0 Write ‘1’ to clear it. When this bit is asserted, the RX DMA cannot
acquire the next RX descriptor and RX DMA FSM is suspended. The
ownership of the next RX descriptor should be changed to RX DMA.
The RX DMA FSM will resume when the RX_DMA_START is written
or the next receive frame is coming.
RX_P
Frame RX Completed Interrupt Pending
0: No Pending
8 R/W1C 0x0
1: Pending
Write ‘1’ to clear it. When this bit is asserted, a frame reception is
completed. The RX DMA FSM remains running.
7:6 / / /
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Offset: 0x0008 Register Name: EMAC_INT_STA
Bit Read/Write Default/Hex Description
TX_EARLY_P
Total interrupt pending which the frame is transmitted to FIFO
5 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
TX_UNDERFLOW_P
TX FIFO Underflow Interrupt Pending
4 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
TX_TIMEOUT_P
Transmitter Timeout Interrupt Pending
3 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
TX_BUF_UA_P
TX Buffer UA Interrupt Pending
0: No Pending
1: Pending
2 R/W1C 0x0
When this asserted, the TX DMA can not acquire the next TX
descriptor and the TX DMA FSM is suspended. The ownership of
the next TX descriptor should be changed to TX DMA. The TX DMA
FSM will resume when writing to TX_DMA_START bit.
TX_DMA_STOPPED_P
Transmission DMA Stopped Interrupt Pending
1 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
TX_P
Frame Transmission Interrupt Pending
0 R/W1C 0x0 0: No Pending
1: Pending
Write ‘1’ to clear it.
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9.12.6.4 0x000C EMAC Interrupt Enable Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: EMAC_INT_EN
Bit Read/Write Default/Hex Description
31:14 / / /
RX_EARLY_INT_EN
Early Receive Interrupt
13 R/W 0x0
0: Disable
1: Enable
RX_OVERFLOW_INT_EN
Receive Overflow Interrupt
12 R/W 0x0
0: Disable
1: Enable
RX_TIMEOUT_INT_EN
Receive Timeout Interrupt
11 R/W 0x0
0: Disable
1: Enable
RX_DMA_STOPPED_INT_EN
Receive DMA FSM Stopped Interrupt
10 R/W 0x0
0: Disable
1: Enable
RX_BUF_UA_INT_EN
Receive Buffer Unavailable Interrupt
9 R/W 0x0
0: Disable
1: Enable
RX_INT_EN
Receive Interrupt
8 R/W 0x0
0: Disable
1: Enable
7:6 / / /
TX_EARLY_INT_EN
Early Transmit Interrupt
5 R/W 0x0
0: Disable
1: Enable
TX_UNDERFLOW_INT_EN
Transmit Underflow Interrupt
4 R/W 0x0
0: Disable
1: Enable
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Offset: 0x000C Register Name: EMAC_INT_EN
Bit Read/Write Default/Hex Description
TX_TIMEOUT_INT_EN
Transmit Timeout Interrupt
3 R/W 0x0
0: Disable
1: Enable
TX_BUF_UA_INT_EN
Transmit Buffer Available Interrupt
2 R/W 0x0
0: Disable
1: Enable
TX_DMA_STOPPED_INT_EN
Transmit DMA FSM Stopped Interrupt
1 R/W 0x0
0: Disable
1: Enable
TX_INT_EN
Transmit Interrupt
0 R/W 0x0
0: Disable
1: Enable
9.12.6.5 0x0010 EMAC Transmit Control Register0 (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: EMAC_TX_CTL0
Bit Read/Write Default/Hex Description
TX_EN
Enable Transmitter
0: Disable
31 R/W 0x0
1: Enable
When disabled, the transmission will continue until the current
transmission finishes.
TX_FRM_LEN_CTL
Frame Transmit Length Control
0: Up to 2,048 bytes (JUMBO_FRM_EN==0)
30 R/W 0x0
Up to 10,240 bytes (JUMBO_FRM_EN==1)
1: Up to 16,384 bytes
Any bytes after that is cut off.
29:0 / / /
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9.12.6.6 0x0014 EMAC Transmit Control Register1 (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: EMAC_TX_CTL1
Bit Read/Write Default/Hex Description
TX_DMA_START
Transmit DMA FSM Start
31 R/W 0x0 0: No valid
1: Start
It is cleared internally and always read a 0.
TX_DMA_EN
30 R/W 0x0 0: Stop TX DMA after the completion of current frame transmission
1: Start and run TX DMA
29:11 / / /
TX_TH
Threshold value of TX DMA FIFO
When TX_MD is 0, the transmission starts when the frame size in
TX DMA FIFO is greater than the threshold. In addition, the full
frames with a length less than the threshold are transferred
10:8 R/W 0x0 automatically.
000: 64
001: 128
010: 192
011: 256
Others: Reserved
7:2 / / /
TX_MD
Transmission Mode
1 R/W 0x0
0: TX starts after the TX DMA FIFO bytes is greater than the TX_TH
1: TX starts after the TX DMA FIFO is located a full frame
FLUSH_TX_FIFO
Flush the data in the TX FIFO
0 R/WAC 0x0
0: Enable
1: Disable
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9.12.6.7 0x001C EMAC Transmit Flow Control Register (Default Value: 0x0000_0000)
Offset: 0x001C Register Name: EMAC_TX_FLOW_CTL
Bit Read/Write Default/Hex Description
TX_FLOW_CTL_STA
This bit indicates a pause frame transmission is in progress. When
the configuration of flow control is ready, set this bit to transmit a
31 R/W 0x0 pause frame in full-duplex mode or activate the backpressure
function. After the transmission is completed, this bit will be
cleared automatically. Before writing TX_FLOW_CTRL register, this
bit must be read as 0.
30:22 / / /
TX_PAUSE_FRM_SLOT
The threshold of the pause timer at which the input flow control
21:20 R/W 0x0
signal is checked for automatic re-transmission of the pause frame.
The threshold values should be always less than PAUSE_TIME.
PAUSE_TIME
19:4 R/W 0x0
The pause time field in the transmitted control frame.
3:2 / / /
ZQP_FRM_EN
0: Disable
1 R/W 0x0 1: Enable
When set, enable the functionality to generate the Zero-Quanta
Pause control frame.
TX_FLOW_CTL_EN
TX Flow Control Enable
0: Disable
0 R/W 0x0 1: Enable
When set, enable flow control operation to transmit pause frames
in full-duplex mode, or enable the back-pressure operation in half-
duplex mode.
9.12.6.8 0x0020 EMAC Transmit DMA Descriptor List Address Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: EMAC_TX_DMA_LIST
Bit Read/Write Default/Hex Description
TX_DESC_LIST
31:0 R/W 0x0 The base address of the transmission descriptor list
It must be 32-bit aligned.
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9.12.6.9 0x0024 EMAC Receive Control Register0 (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: EMAC_RX_CTL0
Bit Read/Write Default/Hex Description
RX_EN
Enable Receiver
31 R/W 0x0
0: Disable receiver after current reception
1: Enable
RX_FRM_LEN_CTL
Frame Receive Length Control
0: Up to 2048 bytes (JUMBO_FRM_EN==0)
30 R/W 0x0
Up to 10240 bytes (JUMBO_FRM_EN==1)
1: Up to 16384 bytes
Any bytes after that is cut off.
JUMBO_FRM_EN
Jumbo Frame Enable
29 R/W 0x0
0: Disable
1: Enable Jumbo frames of 9018 bytes without reporting a giant
STRIP_FCS
28 R/W 0x0 When set, strip the Pad/FCS field on received frames only when
the length of field value is less than or equal to 1500 bytes.
CHECK_CRC
Check CRC Enable
27 R/W 0x0
0: Disable
1: Calculate CRC and check the IPv4 Header Checksum
26:18 / / /
RX_PAUSE_FRM_MD
0: Only detect multicast pause frame specified in the 802.3x
standard.
17 R/W 0x0 1: In addition to detect multicast pause frame specified in the
802.3x standard, also detect unicast pause frame with the address
specified in MAC Address 0 High Register and MAC address 0 Low
Register.
RX_FLOW_CTL_EN
When set, enable the functionality that decodes the received
16 R/W 0x0
pause frame and disable its transmitter for a specified time by
pause frame.
15:0 / / /
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9.12.6.10 0x0028 EMAC Receive Control Register1 (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: EMAC_RX_CTL1
Bit Read/Write Default/Hex Description
RX_DMA_START
31 R/W 0x0 When set, the RX DMA will work. It is cleared internally and always
read a 0.
RX_DMA_EN
Receive DMA Enable
30 R/W 0x0
0: Stop RX DMA after finishing the received current frame
1: Start and run RX DMA
29:25 / / /
RX_FIFO_FLOW_CTL
Receive FIFO Flow Control Enable
24 R/W 0x0 0: Disable
1: Enable, base on RX_FLOW_CTL_TH_DEACT and
RX_FLOW_CTL_TH_ACT
RX_FLOW_CTL_TH_DEACT
Threshold for Deactivating Flow Control
00: Full minus 1 KB
23:22 R/W 0x0 01: Full minus 2 KB
10: Full minus 3 KB
11: Full minus 4 KB
Valid in both half-duplex mode and full-duplex mode.
RX_FLOW_CTL_TH_ACT
Threshold for Activating Flow Control
00: Full minus 1 KB
21:20 R/W 0x0 01: Full minus 2 KB
10: Full minus 3 KB
11: Full minus 4 KB
Valid in both half-duplex mode and full-duplex mode.
19:6 / / /
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Offset: 0x0028 Register Name: EMAC_RX_CTL1
Bit Read/Write Default/Hex Description
RX_TH
Threshold for RX DMA FIFO Start
00: 64
01: 32
5:4 R/W 0x0
10: 96
11: 128
Only valid when RX_MD == 0, the full frames with a length less than
the threshold are transferred automatically.
RX_ERR_FRM
3 R/W 0x0 0: RX DMA drops frames with error
1: RX DMA forwards frames with error
RX_RUNT_FRM
2 R/W 0x0 When the bit is set to 1, it indicates forward undersized frames
with no error and length less than 64 bytes.
RX_MD
Receive Mode
1 R/W 0x0 0: RX starts to read after the RX DMA FIFO byte is greater than
RX_TH
1: RX starts to read after the RX DMA FIFO is located a full frame
FLUSH_RX_FRM
Flush Receive Frames
0 R/W 0x0
0: Enable when the receive descriptors/buffers are unavailable
1: Disable
9.12.6.11 0x0034 EMAC Receive DMA Descriptor List Address Register (Default Value: 0x0000_0000)
Offset: 0x0034 Register Name: EMAC_RX_DMA_LIST
Bit Read/Write Default/Hex Description
RX_DESC_LIST
31:0 R/W 0x0 The base address of the received descriptor list
It must be 32-bit aligned.
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9.12.6.12 0x0038 EMAC Receive Frame Filter Register (Default Value: 0x0000_0000)
Offset: 0x0038 Register Name: EMAC_RX_FRM_FLT
Bit Read/Write Default/Hex Description
DIS_ADDR_FILTER
Disable Address Filter
31 R/W 0x0
0: Enable
1: Disable
30:18 / / /
DIS_BROADCAST
Disable Receive Broadcast Frames
17 R/W 0x0
0: Receive
1: Drop
RX_ALL_MULTICAST
Receive All Multicast Frames Filter
16 R/W 0x0
0: Filter according to HASH_MULTICAST
1: Receive all
15:14 / / /
CTL_FRM_FILTER
Receive Control Frames Filter
00: Drop all control frames
13:12 R/W 0x0
01: Drop all control frames
10: Receive all control frames
11: Receive all control frames when passing the address filter
11:10 / / /
HASH_MULTICAST
Filter Multicast Frames Set
9 R/W 0x0
0: By comparing the DA field in DA MAC address registers
1: According to the hash table
HASH_UNICAST
Filter Unicast Frames Set
8 R/W 0x0
0: By comparing the DA field in DA MAC address registers
1: According to the hash table
7 / / /
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Offset: 0x0038 Register Name: EMAC_RX_FRM_FLT
Bit Read/Write Default/Hex Description
SA_FILTER_EN
Receive SA Filter Enable
0: Receive frames and update the result of SA filter
6 R/W 0x0
1: Update the result of the SA filter. In addition, if the SA field of
the received frame does not match the values in SA MAC address
registers, drop this frame.
SA_INV_FILTER
Receive SA Invert Filter Set
5 R/W 0x0 0: Pass frames whose SA field matches SA MAC address registers
1: Pass frames whose SA field does not match SA MAC address
registers
DA_INV_FILTER
0: Normal filtering of frames is performed
4 R/W 0x0
1: Filter both unicast and multicast frames by comparing DA field
in inverse filtering mode
3:2 / / /
FLT_MD
0: If the HASH_MULTICAST or HASH_UNICAST is set, the frame is
1 R/W 0x0 passed only when it matches the Hash filter
1: Receive the frame when it passes the address register filter or
the hash filter (set by HASH_MULTICAST or HASH_UNICAST)
RX_ALL
Receive All Frame
0 R/W 0x0 0: Receive the frames that pass the SA/DA address filter
1: Receive all frames and update the result of address filter (pass
or fail) in the receive status word
9.12.6.13 0x0040 EMAC Receive Hash Table Register0 (Default Value: 0x0000_0000)
Offset: 0x0040 Register Name: EMAC_RX_HASH0
Bit Read/Write Default/Hex Description
HASH_TAB0
31:0 R/W 0x0
The upper 32 bits of Hash table for the received frame filter.
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9.12.6.14 0x0044 EMAC Receive Hash Table Register1 (Default Value: 0x0000_0000)
Offset: 0x0044 Register Name: EMAC_RX_HASH1
Bit Read/Write Default/Hex Description
HASH_TAB1
31:0 R/W 0x0
The lower 32 bits of Hash table for the received frame filter.
9.12.6.15 0x0048 EMAC MII Command Register (Default Value: 0x0000_0000)
Offset: 0x0048 Register Name: EMAC_MII_CMD
Bit Read/Write Default/Hex Description
31:23 / / /
MDC_DIV_RATIO_M
MDC Clock Divider Ratio
The MDC Clock is divided from the AHB clock.
000: 16
22:20 R/W 0x0
001: 32
010: 64
011: 128
Others: Reserved
19:17 / / /
PHY_ADDR
16:12 R/W 0x0
PHY Address
11:9 / / /
PHY_REG_ADDR
8:4 R/W 0x0
PHY Register Address
3:2 / / /
MII_WR
MII Write and Read
1 R/W 0x0
0: Read
1: Write
MII_BUSY
MII Status
0: Writing 0 is no valid, and reading 0 indicates the read/write
0 R/WAC 0x0
operation is finished
1: Writing 1 starts the read/write operation, and reading 1
indicates busy.
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9.12.6.16 0x004C EMAC MII Data Register (Default Value: 0x0000_0000)
Offset: 0x004C Register Name: EMAC_MII_DATA
Bit Read/Write Default/Hex Description
31:16 / / /
MII_DATA
15:0 R/W 0x0
Write to or read from the register in the selected PHY.
9.12.6.17 0x0050 EMAC MAC Address High Register0 (Default Value: 0x0000_FFFF)
Offset: 0x0050 Register Name: EMAC_ADDR_HIGH0
Bit Read/Write Default/Hex Description
31:16 / / /
MAC_ADDR_HIGH0
15:0 R/W 0xFFFF
The upper 16 bits of the 1st MAC address.
9.12.6.18 0x0054 EMAC MAC Address Low Register0 (Default Value: 0xFFFF_FFFF)
Offset: 0x0054 Register Name: EMAC_ADDR_LOW0
Bit Read/Write Default/Hex Description
MAC_ADDR_LOW0
31:0 R/W 0xFFFFFFFF
The lower 32 bits of 1st MAC address.
9.12.6.19 0x0050+0x08*N EMAC MAC Address High Register N (Default Value: 0x0000_FFFF)
Offset: 0x0050+0x08*N (N=1~7) Register Name: EMAC_ADDR_HIGHN
Bit Read/Write Default/Hex Description
MAC_ADDR_CTL
MAC Address Valid
31 R/W 0x0
0: Not valid
1: Valid
MAC_ADDR_TYPE
MAC Address Type
0: Used to compare with the destination address of the received
30 R/W 0x0
frame
1: Used to compare with the source address of the received
frame
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Offset: 0x0050+0x08*N (N=1~7) Register Name: EMAC_ADDR_HIGHN
Bit Read/Write Default/Hex Description
MAC_ADDR_BYTE_CTL
MAC Address Byte Control Mask
29:24 R/W 0x0 The lower bit of mask controls the lower byte of the MAC
address. When the bit of mask is 1, do not compare the
corresponding byte.
23:16 / / /
MAC_ADDR_HIGH
15:0 R/W 0xFFFF
The upper 16 bits of the MAC address.
9.12.6.20 0x0054+0x08*N EMAC MAC Address Low Register N (Default Value: 0x0000_0000)
Offset: 0x0054+0x08*N (N=1~7) Register Name: EMAC_ADDR_LOWN
Bit Read/Write Default/Hex Description
MAC_ADDR_LOWN
31:0 R/W 0x0
The lower 32 bits of MAC address N (N: 1–7).
9.12.6.21 0x00B0 EMAC Transmit DMA Status Register (Default Value: 0x0000_0000)
Offset: 0x00B0 Register Name: EMAC_TX_DMA_STA
Bit Read/Write Default/Hex Description
31:3 / / /
TX_DMA_STA
The State of Transmit DMA FSM
000: STOP, when reset or disable TX DMA
001: RUN_FETCH_DESC, fetching TX DMA descriptor
010: RUN_WAIT_STA, waiting for the status of TX frame
011: RUN_TRANS_DATA, passing the frame from host memory to
2:0 R 0x0
TX DMA FIFO
100: Reserved
101: Reserved
111: RUN_CLOSE_DESC, closing TX descriptor
110: SUSPEND, TX descriptor is unavailable or TX DMA FIFO
underflow
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9.12.6.22 0x00B4 EMAC Transmit DMA Current Descriptor Register (Default Value: 0x0000_0000)
Offset: 0x00B4 Register Name: EMAC_TX_DMA_CUR_DESC
Bit Read/Write Default/Hex Description
TX_DMA_CUR_DESC
31:0 R 0x0
The address of current transmit descriptor.
9.12.6.23 0x00B8 EMAC Transmit DMA Current Buffer Address Register (Default Value: 0x0000_0000)
Offset: 0x00B8 Register Name: EMAC_TX_DMA_CUR_BUF
Bit Read/Write Default/Hex Description
TX_DMA_CUR_BUF
31:0 R 0x0
The address of current transmit DMA buffer.
9.12.6.24 0x00C0 EMAC Receive DMA Status Register (Default Value: 0x0000_0000)
Offset: 0x00C0 Register Name: EMAC_RX_DMA_STA
Bit Read/Write Default/Hex Description
31:3 / / /
RX_DMA_STA
The State of RX DMA FSM
000: STOP, when reset or disable RX DMA
001: RUN_FETCH_DESC, fetching RX DMA descriptor
010: Reserved
2:0 R 0x0 011: RUN_WAIT_FRM, waiting for the frame
100: SUSPEND, RX descriptor is unavailable
101: RUN_CLOSE_DESC, closing RX descriptor
110: Reserved
111: RUN_TRANS_DATA, passing the frame from host memory to
RX DMA FIFO
9.12.6.25 0x00C4 EMAC Receive DMA Current Descriptor Register (Default Value: 0x0000_0000)
Offset: 0x00C4 Register Name: EMAC_RX_DMA_CUR_DESC
Bit Read/Write Default/Hex Description
RX_DMA_CUR_DESC
31:0 R 0x0
The address of current receive descriptor
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9.12.6.26 0x00C8 EMAC Receive DMA Current Buffer Address Register (Default Value: 0x0000_0000)
Offset: 0x00C8 Register Name: EMAC_RX_DMA_CUR_BUF
Bit Read/Write Default/Hex Description
RX_DMA_CUR_BUF
31:0 R 0x0
The address of current receive DMA buffer
9.12.6.27 0x00D0 EMAC RGMII Status Register (Default Value: 0x0000_0000)
Offset: 0x00D0 Register Name: EMAC_RGMII_STA
Bit Read/Write Default/Hex Description
31:4 / / /
RGMII_LINK
The link status of the RGMII interface
3 R 0x0
0: Down
1: Up
RGMII_LINK_SPD
The link speed of the RGMII interface
00: 2.5 MHz
2:1 R 0x0
01: 25 MHz
10: 125 MHz
11: Reserved
RGMII_LINK_MD
The link mode of the RGMII interface
0 R 0x0
0: Half-Duplex
1: Full-Duplex
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9.13 CIR Receiver
9.13.1 Overview
The Consumer Infrared receiver (CIR_RX) captures pulse from the IR Receiver module and uses the Run-Length
Code (RLC) to encode the pulse.
The CIR receiver has the following features:
Supports CIR remote control receiver
Supports NEC IR protocol
64x8 bits RX FIFO for data buffer
Programmable RX FIFO thresholds
Supports interrupt
Sample clock up to 1 MHz
9.13.2 Block Diagram
Figure 9-106 CIR_RX Block Diagram
IRQ
APB
CIR_RX CIR_RX
REG FIFO
LOGIC
SCLK
The CIR_RX samples the input signal on the programmable frequency and records these samples into RX FIFO
when one CIR signal is found on the air. The CIR_RX uses Run-Length Code (RLC) to encode pulse width. The
encoded data is buffered in 64 levels and 8-bit width RX FIFO; the MSB bit is used to record the polarity of the
receiving CIR signal, the rest 7 bits are used for the length of RLC. The maximum length of the RLC is 128. If the
duration of one level (high or low level) is more than 128, another byte is used.
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9.13.3 Functional Description
9.13.3.1 External Signals
The following table describes the external signals of CIR_RX.
Table 9-40 CIR_RX External Signals
Signal Description Type
IR-RX Consumer Infrared Receiver I
9.13.3.2 Clock Sources
Figure 9-107 CIR_RX Clock System
IR_CIR[24, 1:0]
CCU
RTC_32K
div4 div2y CIR_RX_CLK SCS SAMPLE_CLK
MUX
clkgate
(1/2/4/8) (/1~32) (/1/64/128/512)
DCXO24M
9.13.3.3 Typical Application
Figure 9-108 CIR_RX Application Diagram
VCC
CIR_RX
CIR_RX
IR Receiver
GND
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9.13.3.4 NEC Protocol Format
Figure 9-109 NEC Protocol
ATHR ITHR
LSB MSB LSB MSB LSB MSB LSB MSB
9ms 4.5ms Address Address Command Command
The CIR_RX module is a timer with a capture function.
When CIR_RX signals satisfy the Active Threshold (ATHR), the CIR receiver can start to capture. In the process,
the signal is ignored if the pulse width of the signal is less than NTHR. When CIR_RX signals satisfy ITHR (Idle
Threshold), the capture process is stopped and the Receiver Packet End interrupt is generated, then the
Receiver Packet End Flag is asserted.
In a capture process, every effective pulse is buffered to FIFO in bytes according to the form of the Run-Length
Code. The MSB bit of a byte is the polarity of pulse, and the rest 7 bits is pulse width by taking Sample Clock as
a basic unit. This is the code form of the RLC-Byte. When the level changes or the pulse width counter overflows,
the RLC-Byte is buffered to FIFO. The CIR_RX module receives the infrared signals transmitted by the infrared
remote control, the software decodes the signals.
9.13.3.5 Operating Mode
Sample Clock
Figure 9-110 Logical ‘0’ and Logical ‘1’ of NEC Protocol
560us 560us
560us 1690us
Logical 0 Logical 1
For NEC protocol, a logical "1" takes 2.25 ms (560 us+1680 us) to transmit, while a logical "0" is only half of
that, being 1.12 ms (560 us+560 us).
For example, if the sample clock is 31.25 kHz, a sample cycle is 32 us, then 18 sample cycles are 560 us. So the
RLC of 560 us low level is 0x12 (b’00010010), the RLC of 560 us high level is 0x92 (b’10010010). Then a logical
“1” takes code 0x12 (b’00010010) and code 0xb5 (b’10110101) to transmit, a logical “0” takes code 0x12 and
code 0x92 to transmit.
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Active Threshold (ATHR)
When the CIR_RX is in Idle state, if the electrical level of the CIR_RX signal changes (positive jump or negative
jump), and the duration reaches this threshold, then the CIR_RX takes the starting of the signal as a lead code,
and the CIR_RX turns into an active state and starts to capture CIR_RX signals.
Figure 9-111 ATHR Definition
ATHR
LSB MSB
9ms 4.5ms Address
Idle Threshold (ITHR)
If the electrical level of CIR_RX signals has no change, and the duration reaches this threshold, then the CIR_RX
enters into Idle state and ends this capture.
Figure 9-112 ITHR Definition
ITHR
LSB MSB
Command
Noise Threshold (NTHR)
In the capture process, the pulse is ignored if the pulse width is less than the Noise Threshold.
Figure 9-113 NTHR Definition
a invalid short pulse
NTHR
LSB MSB
9ms 4.5ms Address
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Active Pulse Accept Mode (APAM)
The APAM is used to fit the type of lead code. If a pulse does not fit the type of lead code, it is not regarded as
a lead code even if the pulse width reaches ATHR.
Figure 9-114 APAM Definition
When APAM = 11b, a positive pulse is regarded as a valid leading code.
ATHR
LSB MSB
9ms 4.5ms Address
When APAM = 11b, a negative pulse is a invalid leading code and will be ignored.
ATHR
LSB
9ms 4.5ms Address
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9.13.4 Programming Guidelines
Figure 9-115 CIR Receiver Process
Start
Configure
Pin Multiplex
IR Gating pass, and
Reset de-assert
Set IR_CLK and
Sample Clock
Enable IRC
Set Idle Threshold,
Active Threshold,
Filter Threshold
Set Polarity Invert if
needed
Set FIFO Trigger
Level and Enable IRQ
Global Enable and
Receiver Block
Enable
RX FIFO No
Available?
Yes
Read data from FIFO
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9.13.5 Register List
Module Name Base Address
CIR_RX 0x07040000
Register Name Offset Description
CIR_CTL 0x0000 CIR Control Register
CIR_RXPCFG 0x0010 CIR Receiver Pulse Configure Register
CIR_RXFIFO 0x0020 CIR Receiver FIFO Register
CIR_RXINT 0x002C CIR Receiver Interrupt Control Register
CIR_RXSTA 0x0030 CIR Receiver Status Register
CIR_RXCFG 0x0034 CIR Receiver Configure Register
9.13.6 Register Description
9.13.6.1 0x0000 CIR Receiver Control Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: CIR_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
APAM
Active Pulse Accept Mode
00, 01: Both positive and negative pulses are valid as a leading
7:6 R/W 0x0
code
10: Only negative pulse is valid as a leading code
11: Only positive pulse is valid as a leading code
CIR ENABLE
5:4 R/W 0x0 00–10: Reserved
11: CIR mode enable
3:2 / / /
RXEN
Receiver Block Enable
1 R/W 0x0
0: Disable
1: Enable
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Offset: 0x0000 Register Name: CIR_CTL
Bit Read/Write Default/Hex Description
GEN
Global Enable
A disable on this bit overrides any other block or channel
0 R/W 0x0
enables and flushes all FIFOs.
0: Disable
1: Enable
9.13.6.2 0x0010 CIR Receiver Pulse Configure Register (Default Value: 0x0000_0004)
Offset: 0x0010 Register Name: CIR_RXPCFG
Bit Read/Write Default/Hex Description
31:3 / / /
RPPI
Receiver Pulse Polarity Invert
2 R/W 0x1
0: Do not invert receiver signal
1: Invert receiver signal
1:0 / / /
9.13.6.3 0x0020 CIR Receiver FIFO Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: CIR_RXFIFO
Bit Read/Write Default/Hex Description
31:8 / / /
RBF
7:0 R 0x0
Receiver Byte FIFO
9.13.6.4 0x002C CIR Receiver Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: CIR_RXINT
Bit Read/Write Default/Hex Description
31:14 / / /
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Offset: 0x002C Register Name: CIR_RXINT
Bit Read/Write Default/Hex Description
RAL
RX FIFO available received byte level for interrupt and DMA
13:8 R/W 0x0
request
TRIGGER_LEVEL = RAL + 1
DRQ_EN
RX FIFO DMA Enable
0: Disable
5 R/W 0x0
1: Enable
When it is set to ‘1’, the Receiver FIFO DRQ is asserted if
reaching RAL. The DRQ is de-asserted when the condition fails.
RAI_EN
RX FIFO Available Interrupt Enable
0: Disable
4 R/W 0x0
1: Enable
When it is set to ‘1’, the Receiver FIFO IRQ is asserted if reaching
RAL. The IRQ is de-asserted when the condition fails.
3:2 / / /
RPEI_EN
Receiver Packet End Interrupt Enable
1 R/W 0x0
0: Disable
1: Enable
ROI_EN
Receiver FIFO Overrun Interrupt Enable
0 R/W 0x0
0: Disable
1: Enable
9.13.6.5 0x0030 CIR Receiver Status Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: CIR_RXSTA
Bit Read/Write Default/Hex Description
31:15 / / /
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Offset: 0x0030 Register Name: CIR_RXSTA
Bit Read/Write Default/Hex Description
RAC
RX FIFO Available Counter
0: No available data in RX FIFO
14:8 R 0x0 1: 1-byte available data in RX FIFO
2: 2-bytes available data in RX FIFO
…
64: 64-bytes available data in RX FIFO
STAT
Status of CIR
7 R 0x0
0: Idle
1: Busy
6:5 / / /
RA
RX FIFO Available
4 R/W1C 0x0 0: RX FIFO not available according to its level
1: RX FIFO available according to its level
Writing 1 clears this bit.
3:2 / / /
RPE
Receiver Packet End Flag
0: STO was not detected. In CIR mode, one CIR symbol is
receiving or not detected.
1 R/W1C 0x0
1: STO field or packet abort symbol (7’b0000,000 and
8’b0000,0000 for MIR and FIR) is detected. In CIR mode, one CIR
symbol is received.
Writing 1 clears this bit.
ROI
Receiver FIFO Overrun
0 R/W1C 0x0 0: Receiver FIFO not overrun
1: Receiver FIFO overrun
Writing 1 clears this bit.
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9.13.6.6 0x0034 CIR Receiver Configure Register (Default Value: 0x0000_1828)
Offset: 0x0034 Register Name: CIR_RXCFG
Bit Read/Write Default/Hex Description
31:25 / / /
SCS2
24 R/W 0x0 Bit2 of Sample Clock Select for CIR
This bit is defined by SCS bits below.
ATHC
Active Threshold Control for CIR
23 R/W 0x0
0: ATHR in a unit of (Sample Clock)
1: ATHR in a unit of (128*Sample Clocks)
ATHR
Active Threshold for CIR
22:16 R/W 0x0 These bits control the duration of CIR from the idle to the active
state. The duration can be calculated by ((ATHR + 1)*(ATHC?
Sample Clock: 128*Sample Clock)).
ITHR
Idle Threshold for CIR
The Receiver uses it to decide whether the CIR command is
received. If there is no CIR signal on the air, the receiver is
staying in IDLE status. One active pulse will bring the receiver
from IDLE status to Receiving status. After the CIR receiver ends,
the inputting signal will keep the specified level (high or low
15:8 R/W 0x18
level) for a long time. The receiver can use this idle signal
duration to decide that it has received the CIR command. The
corresponding flag is asserted. If the corresponding interrupt is
enabled, the interrupt line is asserted to the CPU.
When the duration of the signal keeps one status (high or low
level) for the specified duration ((ITHR + 1)*128 sample_clk),
this means that the previous CIR command is finished.
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Offset: 0x0034 Register Name: CIR_RXCFG
Bit Read/Write Default/Hex Description
NTHR
Noise Threshold for CIR
When the duration of the signal pulse (high or low level) is less
than NTHR, the pulse is taken as noise and should be discarded
by hardware.
0: All samples are recorded into RX FIFO
7:2 R/W 0xA 1: If the signal is only one sample duration, it is taken as noise
and discarded.
2: If the signal is less than (<=) two sample duration, it is taken
as noise and discarded.
…
61: If the signal is less than (<=) sixty-one sample duration, it is
taken as noise and discarded.
SCS
Sample Clock Select for CIR
SCS2 SCS[1] SCS[0] Sample Clock
0 0 0 CIR_CLK/64
0 0 1 CIR_CLK/128
1:0 R/W 0x0 0 1 0 CIR_CLK/256
0 1 1 CIR_CLK/512
1 0 0 CIR_CLK
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
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9.14 CIR Transmitter
9.14.1 Overview
The CIR transmitter (CIR_TX) can transfer arbitrary waves which can be modulated with configurable carrier
waves such as 38 kHz.
The CIR_TX has the following features:
Supports CIR remote control transmitter
128 bytes FIFO for data buffer
Configurable carrier frequency
Supports Interrupt and DMA
Supports handshake mode and waiting mode of DMA
9.14.2 Block Diagram
The following figure shows a block diagram of the CIR_TX.
Figure 9-116 CIR_TX Block Diagram
cyc_str
tx_str
cyc_fin
tx_act_s
ASP
tx_act_p
idle_cnt_up_p
idle_cnt_up_s
idle_cnt
IR_TX
RFU ACU
Control Signals
wr rd
wdata rdata
tFIFO
wl wl
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9.14.3 Functional Description
9.14.3.1 External Signals
The following table describes the external signals of CIR_TX.
Table 9-41 CIR_TX External Signals
Signal Description Type
CIR-TX Consumer infrared transmitter O
9.14.3.2 Clock Sources
Figure 9-117 CIR_TX Clock System
CIR_TCR[3:1]
CCU
HOSC Reference
div4 div2y CIR_TX_CLK RCS
MUX
clkgate Clock
(1/2/4/8) (/1~16) (/1/2/4.../512)
PLL_PERI(1X)
9.14.3.3 Function Implementation
The CIR_TX is used to generate a waveform of arbitrary length, arbitrary shape, and no high-speed requirement,
and it can change the data into the high-/low-level sequence of a certain length. Every transmitting data is in
bytes, the Bit[7] of a byte means whether the level of a transmitting wave is high or low, the Bit[6:0] is the
length of this wave. If the current transmitting frequency-division is 1, 0x88 is a high level of 8 cycles, 0x08 is a
low level of 8 cycles. If the current transmitting frequency-division is 4, 0x88 is a high level of 32 cycles, 0x08 is
a low level of 32 cycles.
The CIR_TX has two transmission modes: non-cycle transmission, and cycle transmission.
The non-cycle transmission is to transmit all the data in TX_FIFO until the FIFO is empty.
The cycle transmission is to transmit all the data in TX_FIFO, after the transmission completion, wait for a
certain time to recover the data in TX_FIFO and then send it until a stop signal is detected. The data recovery
in FIFO is implemented by clearing the read pointer.
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9.14.3.4 Timing Diagram
The CIR remote control contains many protocols designed by different manufacturers. Here to NEC protocol as
an example, the CIR-TX module uses a variable pulse-width modulation technique to encompass the various
formats of infrared encoding for remote-control applications. A message is started by a 9 ms AGC burst, which
is used to set the gain of the earlier CIR receivers. This AGC burst is then followed by a 4.5 ms space, which is
then followed by the address and command.
Bit definition: the logical “1” takes 2.25 ms to transmit, while a logical “0” is only 1.12 ms.
Figure 9-118 Definitions of Logical “1” and Logical “0”
Timing for a message:
Figure 9-119 CIR Message Timing Diagram
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9.14.4 Programming Guidelines
Figure 9-120 CIR Transmitter Process
Start
Configure
Pin Multiplex
IR Gating pass, and
Reset de-assert
Set IR_CLK and
RFMC, RCS
Enable IRC
Set Polarity Invert if
needed
Set Transmitter
Threshold
Write TX FIFO
Reach No
Threshold?
Yes
Transmitting Data
Transmitting No
Complete?
Yes
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9.14.5 Register List
Module Name Base Address
CIR_TX 0x02003000
Register Name Offset Description
CIR_TGLR 0x0000 CIR Transmit Global Register
CIR_TMCR 0x0004 CIR Transmit Modulation Control Register
CIR_TCR 0x0008 CIR Transmit Control Register
CIR_IDC_H 0x000C CIR Transmit Idle Duration Threshold High Bit Register
CIR_IDC_L 0x0010 CIR Transmit Idle Duration Threshold Low Bit Register
CIR_TICR_H 0x0014 CIR Transmit Idle Counter High Bit Register
CIR_TICR_L 0x0018 CIR Transmit Idle Counter Low Bit Register
CIR_TEL 0x0020 CIR TX FIFO Empty Level Register
CIR_TXINT 0x0024 CIR Transmit Interrupt Control Register
CIR_TAC 0x0028 CIR Transmit FIFO Available Counter Register
CIR_TXSTA 0x002C CIR Transmit Status Register
CIR_TXT 0x0030 CIR Transmit Threshold Register
CIR_DMA 0x0034 CIR DMA Control Register
CIR_TXFIFO 0x0080 CIR Transmit FIFO Data Register
9.14.6 Register Description
9.14.6.1 0x0000 CIR Transmitter Global Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: CIR_TGLR
Bit Read/Write Default/Hex Description
31:8 / / /
IMS
Internal Modulation Select
7 R/W 0x0
0: The transmitting signal is not modulated
1: The transmitting signal is modulated internally
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Offset: 0x0000 Register Name: CIR_TGLR
Bit Read/Write Default/Hex Description
DRMC
Duty ratio of modulated carrier is high level/low level.
00: Low level is equal to high level
6:5 R/W 0x0
01: Low level is the double of high level
10: Low level is the triple of high level
11: Reserved
4:3 / / /
TPPI
Transmit Pulse Polarity Invert
2 R/W 0x0
0: Not invert transmit pulse
1: Invert transmit pulse
TR
Transmit Reset
When this bit is set, the transmitting is reset. The FIFO will be
1 R/W 0x0
flushed, the TIC filed and the CSS field will be cleared during
Transmit Reset. This field will automatically be cleared when the
Transmit Reset is finished, and the CIR transmitter will state Idle.
TXEN
Transmit Block Enable
0 R/W 0x0
0: Disable the CIR Transmitter
1: Enable the CIR Transmitter
9.14.6.2 0x0004 CIR Transmitter Modulation Control Register (Default Value: 0x0000_009E)
Offset: 0x0004 Register Name: CIR_TMCR
Bit Read/Write Default/Hex Description
31:8 / / /
RFMC
Reference Frequency of modulated carrier.
Reference Frequency of modulated carrier based on a division of
a fixed functional clock (FCLK). The range of the modulated
7:0 R/W 0x9E carrier is usually 30 kHz to 60 kHz. Most consumer electronics is
38 kHz.
The default modulated carrier is 38 kHz when FCLK is 12 MHz.
RFMC= FCLK/((N+1)*(DRMC+2)).
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9.14.6.3 0x0008 CIR Transmitter Control Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: CIR_TCR
Bit Read/Write Default/Hex Description
31:8 / / /
CSS
Cyclical Pulse Start/Stop Control
7 R/W 0x0 0: Stop when cleared to '0'. From start to stop, all data in FIFO
must be transmitted.
1: Start. Start to transmit when it is set to '1'.
6:4 / / /
RCS
Reference Clock Select for CIR Transmit
The data in TX_FIFO is used to describe the pulse in Run-Length
Code. The basic unit of pulse width is Reference Clock.
000: CIR Transmit reference clock is ir_clk
001: CIR Transmit reference clock is ir_clk/2
3:1 R/W 0x0
010: CIR Transmit reference clock is ir_clk/4
011: CIR Transmit reference clock is ir_clk/8
100: CIR Transmit reference clock is ir_clk/64
101: CIR Transmit reference clock is ir_clk/128
110: CIR Transmit reference clock is ir_clk/256
111: CIR Transmit reference clock is ir_clk/512
TTS
Type of the transmission signal
0 R/W 0x0
0: The transmitting wave is a single non-cyclical pulse.
1: The transmitting wave is a cyclical short-pulse.
9.14.6.4 0x000C CIR Transmitter Idle Duration Counter High Bit Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: CIR_IDC_H
Bit Read/Write Default/Hex Description
31:8 / / /
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Offset: 0x000C Register Name: CIR_IDC_H
Bit Read/Write Default/Hex Description
IDC_H
Idle Duration Counter Threshold (High 4 bits)
Idle Duration = 128*IDC*Ts (IDC = 0~4095)
3:0 R/W 0x0
It is used in cyclical transmission mode. When all the data in FIFO
is transmitted, the signals can be transmitted after a specific
time.
9.14.6.5 0x0010 CIR Transmitter Idle Duration Counter Low Bit Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: CIR_IDC_L
Bit Read/Write Default/Hex Description
31:8 / / /
IDC_L
Idle Duration Counter Threshold (Low 8 bits)
Idle Duration = 128*IDC*Ts (IDC = 0~4095)
3:0 R/W 0x0
It is used in cyclical transmission mode. When all the data in FIFO
is transmitted, the signals can be transmitted after a specific
time.
9.14.6.6 0x0014 CIR Transmitter Idle Counter High Bit Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: CIR_TICR_H
Bit Read/Write Default/Hex Description
31:8 / / /
TIC_H
Transmit Idle Counter_H (High 8 bits)
It is used to count the idle duration of CIR transmitter by
software.
7:0 R 0x0
Count in 128*Ts (Sample Duration, 1/Fs) when the transmitter is
idle, and it should be reset when the transmitter is active.
When this counter reaches the maximum value (0xFFFF), it will
stop automatically, and should not be cleared to zero.
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9.14.6.7 0x0018 CIR Transmitter Idle Counter Low Bit Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: CIR_TICR_L
Bit Read/Write Default/Hex Description
31:8 / / /
TIC_L
Transmit Idle Counter_L (Low 8 bits)
It is used to count the idle duration of CIR transmitter by
software.
7:0 R 0x0
Count in 128*Ts (Sample Duration, 1/Fs) when the transmitter is
idle, and it should be reset when the transmitter is active.
When this counter reaches the maximum value (0xFFFF), it will
stop automatically, and should not be cleared to zero.
9.14.6.8 0x0020 CIR Transmitter FIFO Empty Register (Default Value: 0x0000_0000)
Offset: 0x0020 Register Name: CIR_TEL
Bit Read/Write Default/Hex Description
31:8 / / /
TEL
7:0 R/W 0x0 TX FIFO empty Level for DRQ and IRQ.
TRIGGER_LEVEL = TEL + 1
9.14.6.9 0x0024 CIR Transmitter Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: CIR_TXINT
Bit Read/Write Default/Hex Description
31:3 / / /
DRQ_EN
TX FIFO DMA Enable
0: Disable
2 R/W 0x0 1: Enable
When it is set to ‘1’, the TX FIFO DRQ is asserted if the number
of the transmitting data in the FIFO is less than the RAL. The DRQ
is de-asserted when the condition fails.
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Offset: 0x0024 Register Name: CIR_TXINT
Bit Read/Write Default/Hex Description
TAI_EN
TX FIFO Available Interrupt Enable
1 R/W 0x0
0: Disable
1: Enable
TPEI_EN
Transmit Packet End Interrupt Enable for Cyclical Pulse
0: Disable
1: Enable
0 R/W 0x0
TUI_EN
Transmitter FIFO Underrun Interrupt Enable for Non-cyclical
Pulse
0: Disable
1: Enable
9.14.6.10 0x0028 CIR Transmitter FIFO Available Counter Register (Default Value: 0x0000_0080)
Offset: 0x0028 Register Name: CIR_TAC
Bit Read/Write Default/Hex Description
31:8 / / /
TAC
TX FIFO Available Space Counter
0x00: No available space in TX FIFO
7:0 R 0x80 0x01: 1 byte available space in TX FIFO
0x02: 2 bytes available space in TX FIFO
…
0x80: 128 bytes available space in TX FIFO
9.14.6.11 0x002C CIR Transmitter Status Register (Default Value: 0x0000_0002)
Offset: 0x002C Register Name: CIR_TXSTA
Bit Read/Write Default/Hex Description
31:4 / / /
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Offset: 0x002C Register Name: CIR_TXSTA
Bit Read/Write Default/Hex Description
STCT
Status of CIR Transmitter
0: Idle
1: Active
This bit will automatically set when the controller begins to
3 R 0x0 transmit the data in the FIFO. The “1” will last when the data in
the FIFO. It will automatically be cleared to “0” when all data in
the FIFO is transmitted.
The bit is for debugging.
The output Level of Idle state is determined by the level of the
last data output.
DRQ
DMA Request Flag
When set to ‘1’, the TX FIFO DRQ is asserted if the number of the
2 R 0x0
transmission data in the FIFO is less than the RAL. The DRQ is de-
asserted when the condition fails.
This bit is for debugging.
TAI
TX FIFO Available Interrupt Flag
1 R/W 0x1 0: TX FIFO not available by its level
1: TX FIFO available by its level
Writing 1 clears this bit.
TPE
Transmitter Packet End Flag for Cyclical Pulse
0: Transmissions of address, control and data fields not
completed
1: Transmissions of address, control and data fields completed
0 R/W 0x0
TUR
Transmitter FIFO Underrun Flag for Non-cyclical Pulse
0: No transmitter FIFO underrun
1: Transmitter FIFO underrun
Writing 1 clears this bit.
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9.14.6.12 0x0030 CIR Transmitter Threshold Register (Default Value: 0x0000_0000)
Offset: 0x0030 Register Name: CIR_TXT
Bit Read/Write Default/Hex Description
31:8 / / /
NCTT
Non-cyclical Pulse Transmit Threshold
7:0 R/W 0x0 The controller will trigger transmitting the data in the FIFO when
the data byte number has reached the Transmit Threshold set in
this field.
9.14.6.13 0x0034 CIR Transmitter DMA Control Register (Default Value: 0x0000_00A5)
Offset: 0x0034 Register Name: CIR_DMA_CTL
Bit Read/Write Default/Hex Description
31:8 / / /
DMA Handshake Configuration
7:0 R/W 0xA5 0xA5: DMA waiting cycle mode
0xEA: DMA handshake mode
9.14.6.14 0x0080 CIR Transmitter FIFO Data Register (Default Value: 0x0000_0000)
Offset: 0x0080 Register Name: CIR_TXFIFO
Bit Read/Write Default/Hex Description
31:8 / / /
TBF
Transmit Byte FIFO
7:0 W 0x0
When the transmission is triggered, the data in the FIFO will be
transmitted until the data number is transmitted completely.
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Contents
10 Security System ..................................................................................................................................................... 1280
10.1 Crypto Engine ................................................................................................................................................ 1280
10.1.1 Overview ........................................................................................................................................... 1280
10.1.2 Block Diagram ................................................................................................................................... 1281
10.1.3 Functional Descriptions..................................................................................................................... 1281
10.1.4 Programming Guidelines................................................................................................................... 1301
10.1.5 Register List ....................................................................................................................................... 1304
10.1.6 Register Description .......................................................................................................................... 1305
10.2 Security ID ..................................................................................................................................................... 1309
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Figures
Figure 10-1 CE Block Diagram ......................................................................................................................................... 1281
Figure 10-2 DES Encryption and Decryption ................................................................................................................... 1282
Figure 10-3 3DES Encryption and Decryption of a 3-key Operation and a 2-key Operation .......................................... 1283
Figure 10-4 ECB Mode Encryption and Decryption......................................................................................................... 1284
Figure 10-5 CBC Mode Encryption and Decryption ........................................................................................................ 1285
Figure 10-6 CTR Mode Encryption and Decryption......................................................................................................... 1286
Figure 10-7 CFB Mode Encryption and Decryption ......................................................................................................... 1287
Figure 10-8 OFB Mode Encryption and Decryption ........................................................................................................ 1288
Figure 10-9 CTS Mode Encryption and Decryption ......................................................................................................... 1289
Figure 10-10 Structure of Task Descriptor Chaining ....................................................................................................... 1290
Figure 10-11 Word Address of Message ......................................................................................................................... 1297
Figure 10-12 Byte Order.................................................................................................................................................. 1297
Figure 10-13 Bit Order .................................................................................................................................................... 1297
Figure 10-14 The Storage Method of 32-bit IV ............................................................................................................... 1298
Figure 10-15 The Storage Method of 64-bit IV ............................................................................................................... 1298
Figure 10-16 Task Request Process ................................................................................................................................. 1301
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10 Security System
10.1 Crypto Engine
10.1.1 Overview
The Crypto Engine (CE) module is one encryption/decryption algorithm accelerator. It supports kinds of
symmetric, asymmetric, Hash, and RNG algorithms.
The symmetric algorithm supports data encryption and decryption by following the data encryption standard
(DES), 3DES, or advanced encryption standard (AES) algorithms. It can encrypt or decrypt a large amount of
data effectively.
The Rivest-Shamir-Adleman (RSA) asymmetric algorithm is used for data encryption/decryption and digital
signature verification. It is a public key encryption/decryption algorithm implemented through the modular
exponentiation operation.
The Hash algorithm supports data integrity authentication and digital signature. The hash supports MD5, SHA1,
SHA224, SHA256, SHA384, SHA512, HMAC-SHA1, and HMAC-SHA256 algorithms.
The RNG algorithm can generate true-random numbers and pseudo-random numbers.
The software interface of the CE is simple, only setting interrupt control, task description address, and load tag.
The algorithm control information is written in memory by task descriptor, then the CE automatically reads it
when executing a request. It supports parallel execution of 4 channels and has an internal DMA controller to
transfer data between CE and memory.
The CE has the following features:
Symmetrical algorithm: AES, DES, 3DES
Hash algorithm: MD5, SHA1, SHA224, SHA256, SHA384, SHA512, HMAC-SHA1, HMAC-SHA256
Asymmetrical algorithm: RSA512/1024/2048-bit
160-bit hardware PRNG with 175-bit seed
256-bit hardware TRNG
Electronic codebook (ECB), cipher block chaining (CBC), counter (CTR), cipher text stealing (CTS), 128-
output feedback (OFB), 1-/8-/64-/128-cipher feedback (CFB) modes for AES algorithm
ECB, CBC, CTR modes for DES/3DES algorithm
128-, 192-, 256-bit key size for AES algorithms
16-, 32-, 64-, 128-bit wide size for AES CTR mode
16-, 32-, 64-bit wide size for DES/3DES CTR mode
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One or more blocks mode for MD5/SHA1/SHA224/SHA256/SHA384/SHA512
Internal DMA controller for data transfer with memory
10.1.2 Block Diagram
The following figure shows the block diagram of Crypto Engine.
Figure 10-1 CE Block Diagram
ce_ahb
cr
task_handle
ctrl:
aes,des,sha,
RSA
HMAC,prng、
trng...
mux
rx_fifo dma tx_fifo
ss_Mbus
10.1.3 Functional Description
10.1.3.1 DES Algorithm
Figure 10-2 shows the DES encryption and decryption operation.
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Figure 10-2 DES Encryption and Decryption
Plaintext Ciphertext
Input block Input block
Key Key
encryption decryption
Output block Output block
Ciphertext Plaintext
DES encryption DES decryption
10.1.3.2 3DES Algorithm
The 3DES algorithm supports both 3-key and 2-key operations. A 2-key operation can be regarded as a
simplified 3-key operation. To be specific, key 3 is represented by key 1 in a 2-key operation. Figure 10-3 shows
the 3DES encryption and decryption operation of a 3-key operation and a 2-key operation.
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Figure 10-3 3DES Encryption and Decryption of a 3-key Operation and a 2-key Operation
Plaintext
Input block Input block Input block
Key1 Key2 Key3 or Key1
encryption decryption encryption
Output block Output block Output block
Ciphertext
DES encryption
Ciphertext
Input block Input block Input block
Key3 or Key1 Key2 Key1
decryption encryption decryption
Output block Output block Output block
Plaintext
DES decryption
10.1.3.3 ECB Mode
The ECB mode is a confidentiality mode that features, for a given key, the assignment of a fixed ciphertext
block to each plaintext block, analogous to the assignment of code words in a codebook.
In ECB mode, encryption and decryption algorithms are directly applied to the block data. The operation of
each block is independent, so the plaintext encryption and ciphertext decryption can be performed
concurrently.
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Figure 10-4 ECB Mode Encryption and Decryption
Plaintext Ciphertext
Input block Input block
Key Key
encryption decryption
Output block Output block
Ciphertext Plaintext
ECB mode encryption ECB mode decryption
10.1.3.4 CBC Mode
The CBC mode is a confidentiality mode whose encryption process features the combining of the plaintext
blocks with the previous ciphertext blocks. The CBC mode requires an initialization vector (IV) to combine with
the first plaintext block. The encryption process of each plaintext block is related to the block processing result
of the previous ciphertext blocks, so encryption operations cannot be concurrently performed in CBC mode.
The decryption operation is independent of output plain text of the previous block, so decryption operations
can be performed concurrently.
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Figure 10-5 CBC Mode Encryption and Decryption
Initialization Plaintext 1 Plaintext 2 Plaintext n
vector
Input block 1 Input block 2 Input block n
Key Key Key
encryption encryption encryption
Output block 1 Output block 2 Output block n
Ciphertext 1 Ciphertext 2 Ciphertext n
CBC mode encryption
Ciphertext 1 Ciphertext 2 Ciphertext n
Input block 1 Input block 2 Input block n
Key Key Key
decryption decryption decryption
Output block 1 Output block 2 Output block n
Initialization
vector Plaintext 1 Plaintext 2 Plaintext n
CBC mode decryption
10.1.3.5 CTR Mode
The CTR mode is a confidentiality mode that features the application of the forward cipher to a set of input
blocks, called counters, to produce a sequence of output blocks that are exclusive-ORed with the plaintext to
produce the ciphertext, and vice versa. All of the counters must be distinct.
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Figure 10-6 CTR Mode Encryption and Decryption
Counter 1 Counter 2 Counter n
Input block 1 Input block 2 Input block n
Key Key Key
encryption encryption encryption
Output block 1 Output block 2 Output block n
Plaintext 1 Plaintext 2 Plaintext n
Ciphertext 1 Ciphertext 2 Ciphertext n
CTR mode encryption
Counter 1 Counter 2 Counter n
Input block 1 Input block 2 Input block n
Key Key Key
decryption decryption decryption
Output block 1 Output block 2 Output block n
Ciphertext 1 Ciphertext 2 Ciphertext n
Ciphertext 1 Ciphertext 2 Ciphertext n
CTR mode decryption
10.1.3.6 CFB Mode
The CFB mode is a confidentiality mode that features the feedback of successive ciphertext segments into the
input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to
produce the ciphertext, and vice versa. The CFB mode requires an IV as the initial input block, and the forward
cipher operation is applied to the IV to produce the first output block. The first ciphertext segment is produced
by exclusive-ORing the first plaintext segment with the s most significant bits of the first output block. The
value of s is 1 bit, 8 bits, 64 bits, or 128 bits.
The following figure shows the s-bit CFB mode of the AES algorithms.
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Figure 10-7 CFB Mode Encryption and Decryption
Initialization
vector
Input block 2 Input block n
Input block 1 s bits
(b-s) bits s bits (b-s) bits
Key Key Key
encryption encryption encryption
Output block 1 Output block 2 Output block n
Select Discard Select Discard Select Discard
s bits (b-s) bits s bits (b-s) bits s bits (b-s) bits
Plaintext 1 Plaintext 2 Plaintext n
s bits s bits s bits
Ciphertext 1 Ciphertext 2 Ciphertext n
s bits s bits s bits
CFB mode encryption
Initialization
vector
Input block 2 Input block n
Input block 1 s bits
(b-s) bits s bits (b-s) bits
Key Key Key
decryption decryption decryption
Output block 1 Output block 2 Output block n
Select Discard Select Discard Select Discard
s bits (b-s) bits s bits (b-s) bits s bits (b-s) bits
Ciphertext 1 Ciphertext 2 Ciphertext n
s bits s bits s bits
Plaintext 1 Plaintext 2 Plaintext n
s bits s bits s bits
CFB mode decryption
10.1.3.7 OFB Mode
The OFB mode is a confidentiality mode that features the iteration of the forward cipher on an IV to generate
a sequence of output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice
versa. If a same key is used, different IVs must be used to ensure operation security.
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Figure 10-8 OFB Mode Encryption and Decryption
Initialization
vector
Input block 1 Input block 2 Input block n
Key Key Key
encryption encryption encryption
Output block 1 Output block 2 Output block n
Plaintext 1 Plaintext 2 Plaintext n
Ciphertext 1 Ciphertext 2 Ciphertext n
OFB mode encryption
Initialization
vector
Input block 1 Input block 2 Input block n
Key Key Key
decryption decryption decryption
Output block 1 Output block 2 Output block n
Ciphertext 1 Ciphertext 2 Ciphertext n
Plaintext 1 Plaintext 2 Plaintext n
OFB mode decryption
10.1.3.8 CTS Mode
The CTS mode is a confidentiality mode that accepts any plaintext input whose bit length is greater than or
equal to the block size but not necessarily a multiple of the block size. Below are the diagrams for CTS
encryption and decryption.
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Figure 10-9 CTS Mode Encryption and Decryption
Initialization Plaintext 1 Plaintext 2 Plaintext n-1 Plaintext n
vector padding
Input block 1 Input block 2 Input block n-1 Input block n
Key Key Key
encryption Key encryption encryption encryption
Output block 1 Output block 2 Output block n-1 Output block n
Ciphertext 1 Ciphertext 2 Ciphertext n-1 Ciphertext n
CTS mode encryption
Ciphertext 1 Ciphertext 2 Ciphertext n-1 Ciphertext n
Input block n-1 Ciphertext n
Input block 1 Input block 2
Key Key decryption Key
decryption decryption Input block n
Initialization Output block n-1 Key
Output block 1 Output block 2 decryption
vector
Output block n
Plaintext 1 Plaintext 2
Plaintext n Plaintext n-1
CTS mode decryption
10.1.3.9 HASH Algorithm
The hash algorithms support MD5, SHA1, SHA224, SHA256, SHA384, SHA512, HMAC-SHA1, and HMAC-SHA256.
All algorithms are iterative, one-way hash functions that can process a message to produce a condensed
representation called a message digest. When a message is received, the message digest can be used to verify
whether the data has changed, that is, to verify its integrity.
The hash algorithm of the CE supports block-aligned total length of the input data (padded by software), that
is, a multiple of 64 bytes. The message length after padding by software is used as the configured data length
for the hash algorithm.
10.1.3.10 RSA Algorithm
The RSA is a public key encryption/decryption algorithm implemented through the modular exponentiation
operation.
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The ciphertext is obtained as follows: C = ME mod N. The plaintext is obtained as follows: M = CD mod N.
M indicates the plaintext, C indicates the ciphertext, (N, E) indicates the public key, and (N, D) indicates the
private key.
10.1.3.11 Task Descriptor
The software makes request through task descriptor, including algorithm type, algorithm mode, key address,
source/destination address and size, and so on. The structure of the task descriptor is as follows.
Figure 10-10 Structure of Task Descriptor Chaining
The bit definitions of the task descriptor are as follows.
Task ID
Bit Read/Write Default/Hex Description
31:4 / / /
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Bit Read/Write Default/Hex Description
CHN
Task channel ID
3:0 R/W 0x0
Indicates which channel the task is running on.
It supports 0 to 3.
Common Control
Bit Read/Write Default/Hex Description
Interrupt enable (IE) for the current task
0: disable interrupt
1: enable interrupt
Represents whether an interrupt signal is generated when the task
chain ends at the end of this task.
When the last task in a task chain ends, the operation of the task
chain will end normally; if a task fails in the middle, the task chain
31 R/W 0x0 will be aborted abnormally. And it is determined whether to
generate an interrupt signal according to the IE configuration of
the current task when the current task ends or aborts. Therefore,
if you want to use interrupts, it is recommended that not only the
IE of the last task of each task chain is configured to 1 to generate
the end interrupt of the task chain, but also the IEs of other tasks
in this task chain are also configured to 1. The purpose is to
generate an interrupt signal once an abnormal error occurs in
these tasks and the interrupt is aborted.
30:17 / / /
IV mode
IV mode for SHA1/SHA224/SHA256/SHA384/SHA512/MD5 or
16 R/W 0x0 constants
0: use initial constants defined in FIPS-180
1: use input iv
Last HMAC plaintext
15 R/W 0x0 0: not the last HMAC plaintext package
1: the last HMAC plaintext package
14:9 / / /
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Bit Read/Write Default/Hex Description
OP DIR
Algorithm Operation Direction
0: Encryption
8 R/W 0x0
1: Decryption
Configure according to the requirements of encryption or
decryption.
7 / / /
Algorithm Type
0x0: AES
0x1: DES
0x2: Triple DES (3DES)
0x10: MD5
0x11: SHA-1
0x12: SHA-224
0x13: SHA-256
6:0 R/W 0x0
0x14: SHA-384
0x15: SHA-512
0x16: HMAC-SHA1
0x17: HMAC-SHA256
0x20: RSA
0x30: TRNG
0x31: PRNG
Others: reserved
Symmetric Control
Bit Read/Write Default/Hex Description
31:24 / / /
KEY_SELECT
key select for AES
0000: Select input CE_KEYx (Normal Mode)
0001: Select {SSK}
23:20 R/W 0x0
0010: Select {HUK}
0011: Select {RSSK}
0100-0111: Reserved
1000-1111: Select internal Key n (n from 0 to 7)
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Bit Read/Write Default/Hex Description
CFB_WIDTH
AES-CFB width
00: CFB1
19:18 R/W 0x0
01: CFB8
10: CFB64
11: CFB128
PRNG_LD
Load new 15 bits key into linear feedback shift register (LFSR) for
PRNG.
When the algorithm type is PRNG, it is necessary to post-process
the random number output by PRNG through the linear shift
17 R/W 0x0
operation to generate the operand.
When the PRNG_LD is configured to 1, use iv_addr[14:0] as the
input number for linear shift operation, and do XOR operation
between the data and the random number output by PRNG to
generate the post-processing result of further operation.
CTS_LPKG
AES CTS last package flag
16 R/W 0x0
When set to ‘1’, it means this is the last package for AES-CTS mode
(the size of the last package is larger than 128 bits).
15:12 / / /
ALGORITHM_MODE
CE algorithm mode
0000: Electronic Code Book (ECB) mode
0001: Cipher Block Chaining (CBC) mode
11:8 R/W 0x0 0010: Counter (CTR) mode
0011: Cipher Text Stealing (CTS) mode
0100: Output Feedback (OFB) mode
0101: Cipher Feedback (CFB) mode
Other: reserved
7:4 / / /
CTR WIDTH
Counter width for CTR mode
00: 16-bit Counter
3:2 R/W 0x0
01: 32-bit Counter
10: 64-bit Counter
11: 128-bit Counter
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Bit Read/Write Default/Hex Description
AES KEY SIZE
00: 128-bit
1:0 R/W 0x0 01: 192-bit
10: 256-bit
11: Reserved
Asymmetric Control
Bit Read/Write Default/Hex Description
31 / / /
RSA Pubic Modulus Width
000: 512-bit
30:28 R/W 0x0 001: 1024-bit
010: 2048-bit
Other: reserved
27:19 / / /
RSA MODE
RSA algorithm mode.
For modular computation:
000: modular exponent(RSA)
18:16 R/W 0x0
001: modular div
010: modular mul
011: modular inv
others: reserved
15:0 / / /
Key Descriptor
Bit Read/Write Default/Hex Description
Key Address
31:0 R/W 0x0
The address of KEY that needs to be stored.
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IV Descriptor
Bit Read/Write Default/Hex Description
IV Address
31:0 R/W 0x0
The address of IV that needs to be stored.
Counter Descriptor
Bit Read/Write Default/Hex Description
CTR Data Output Address
31:0 R/W 0x0
The address of CTR data output that needs to be stored.
Data Length
Bit Read/Write Default/Hex Description
Data Length
Configure the data length of the corresponding segment. The data
length size needs to be consistent with dst_data_length
(destination data length 0 +... + destination data length 7).
The data length field in the task descriptor has different meanings
31:0 R/W 0x0 for different algorithms.
For AES-CTS, the data length field indicates byte numbers of source
data, for others indicate word numbers of source data.
For PRNG, the data length should be 5 words aligned.
For TRNG, it should be 8 words aligned.
Source Address 0~7
Bit Read/Write Default/Hex Description
Source Data Address
31:0 R/W 0x0
The address of the source data that needs to be stored.
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Source Data Length 0~7
Bit Read/Write Default/Hex Description
Source Data Length
31:0 R/W 0x0 The length of the source data.
Unit: byte
Destination Address 0~7
Bit Read/Write Default/Hex Description
Destination Data Address
31:0 R/W 0x0
The address of the destination data that needs to be stored.
Destination Data Length 0~7
Bit Read/Write Default/Hex Description
Destination Data Length
31:0 R/W 0x0 The length of the destination data.
Unit: byte
Next Descriptor Address
Bit Read/Write Default/Hex Description
Next Task Address
The address where the descriptor of the next task in a task-chain
31:0 R/W 0x0
is saved. If there is the only task or the last task of a task-chain, the
next task address must be 32’h0.
10.1.3.12 Storing Message
In the application, a message may not be stored contiguously in the memory, but divided into multiple
segments. Or a piece of continuously stored messages can be artificially split into multiple pieces as needs.
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Then each segment corresponds to a set of the source address and source length in the descriptor. Multiple
segments correspond to groups 0-7 source address/source length in sequence.
Each task supports up to 8 message segments, and the data volume of each message segment supports up to
4 GWord (AES-CTS is 1 GByte). The total amount of all segments in a task (that is a package) supports up to 4
GWord (AES-CTS is 1 GByte). If a message is divided into multiple packages, all others are required to be whole
words; when the last package of AES-CTS is less than one word, 0 needs to be padded, and those less than one
word are counted as one word. The following figure shows the address order structure.
Figure 10-11 Word Address of Message
W0 BASE_ADDR
W1 BASE_ADDR + 0x04
W2 BASE_ADDR + 0x08
W3 BASE_ADDR + 0x0C
W4 BASE_ADDR + 0x10
Byte order: low byte first, high byte last. When the data is less than one word, the low byte is filled first. The
following figure shows the byte order structure (blue means it is filled by the message).
Figure 10-12 Byte Order
B3 B2 B1 B0
Bit order: high bit first, low bit last. When the data is less than one Byte, the high bit is filled first. The following
figure shows the bit order structure.
Figure 10-13 Bit Order
31
Byte3 Byte1 Byte0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
10.1.3.13 Storing Key
The length of KEY must be an integer multiple of word, refer to section 10.1.3.15 “Algorithm Length Properties”.
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10.1.3.14 Storing IV
For different algorithms, the length of IV is different. But they are integer multiples of word. To keep the byte
order of IV and HASH digest output consistent, the byte order of IV is different from that of the message. For
the multi-packet operation, the first address of the digest output result of the previous HASH can be directly
configured to the first address of the next IV, and the software does not need to do any processing on the
digest.
The following figure shows the storage method of 32-bit IV value.
Figure 10-14 The Storage Method of 32-bit IV
IV0[31:0] BASE_ADDR
IV1[31:0] BASE_ADDR + 0x04
…… ……
IV7[31:0] BASE_ADDR + 0x1C
The following figure shows the storage method of 64-bit IV value.
Figure 10-15 The Storage Method of 64-bit IV
IV0[63:32] BASE_ADDR
IV0[31:00] BASE_ADDR + 0x04
IV1[63:32] BASE_ADDR + 0x08
IV1[31:00] BASE_ADDR + 0x0C
…… ……
IV7[63:32] BASE_ADDR
IV7[31:00] BASE_ADDR + 0x3C
10.1.3.15 Algorithm Length Properties
The algorithm length has different requirements for different algorithms.
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Table 10-1 Symmetric Algorithm Configuration Properties
Length Setting Software
Algorithm Alignment
Source Size Destination Size KEY IV Padding
AES-128: 4 Word
AES (except Word-
< 4 GWord < 4 GWord AES-192: 6 Word 4 Word need
CTS) aligned
AES 256: 8 Word
AES-128: 4 word
Word-
AES-CTS < 1 GByte < 1 GByte AES-192: 6 word 4 Word need
aligned
AES 256: 8 word
Word-
DES < 4 GWord < 4 GWord 2 Word 2 Word need
aligned
Word-
TDES < 4 GWord < 4 GWord 6 Word 2 Word need
aligned
Table 10-2 Hash Algorithm Configuration Properties
Length Setting Software
Algorithm Alignment
Source Size Destination Size KEY IV Padding
Word-
MD5 < 4 GWord 4 Word Fixed to 0 4 Word need
aligned
Word-
SHA-1 < 4 GWord 5 Word Fixed to 0 5 Word need
aligned
Word-
SHA-224 < 4 GWord 8 Word Fixed to 0 8 Word need
aligned
Word-
SHA-256 < 4 GWord 8 Word Fixed to 0 8 Word need
aligned
Word-
SHA-384 < 4 GWord 16 Word Fixed to 0 16 Word need
aligned
Word-
SHA-512 < 4 GWord 16 Word Fixed to 0 16 Word need
aligned
HMAC- Word-
< 4 GWord 5 Word 16 Word 5 Word need
SHA1 aligned
HMAC- Word-
< 4 GWord 8 Word 16 Word 8 Word need
SHA256 aligned
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Table 10-3 RNG Configuration Properties
Length Setting Software
Algorithm Alignment
Source Size Destination Size KEY IV Padding
Word-
TRNG < 4 GWord < 4 GWord Fixed to 0 4 Word need
aligned
Word-
PRNG < 4 GWord < 4 GWord 6 Word 4 Word need
aligned
Table 10-4 Asymmetric Algorithm Configuration Properties
Length Setting Software
Algorithm Alignment
Source Size Destination Size KEY IV Padding
Not use Word-
RSA512 16 Word 16 Word 16 Word need
IV aligned
Not use Word-
RSA1024 32 Word 32 Word 32 Word need
IV aligned
Not use Word-
RSA2048 64 Word 64 Word 64 Word need
IV aligned
10.1.3.16 Error Detection
The CE module includes error detection for task configuration, data computing error, and authentication invalid.
When the algorithm type in task descriptor is read into the CE module, the CE will check whether this type is
supported through checking algorithm type field in common control. If the type value is out of scope, the CE
will issue interrupt signal and set error state. Each type has certain input and output data size. After getting a
task descriptor, the input size and output size configuration will be checked to avoid size error. If the size
configuration is wrong, the CE will issue interrupt signal and set error state.
10.1.3.17 Clock Requirement
Clock Name Description Requirement
hclk AHB bus clock 24 MHz – 200 MHz
mclk MBUS clock 24 MHz – 400 MHz
ce_clk CE work clock 24 MHz – 400 MHz
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10.1.4 Programming Guidelines
10.1.4.1 Symmetrical/Asymmetrical/Hash/RNG Algorithm Operation Process
The following figure shows the process of an algorithm operation.
Figure 10-16 Task Request Process
Configure task
descriptor
Configure register
Enable the end
interrupt
Start task
Wait until the task
is complete
Read the hardware
calculation result
Clear the interrupt
Step 1 The software should configure a task descriptor in memory, including the related fields in the
descriptor. The channel id corresponds to one channel in CE. According to algorithm type, the software
should set the fields in common control, symmetric control, asymmetric control, then provide
key/iv/ctr address and the data length of this task. The source and destination address and size are set
based on the upper application. If there is another task concatenating after this task, then set its
descriptor address at the next descriptor field. For more details for task descriptor, see section 10.1.4.2,
section 10.1.4.3 and section 10.1.4.4.
Step 2 The software should set registers. Configure the first address of the task descriptor structure to CE
Task Descriptor Address Register. Configure the source/destination address to CE Current Source
Address Register/CE Current Destination Address Register.
Step 3 Enable the end interrupt of the corresponding task channel by setting CE Interrupt Control Register.
Step 4 The software reads CE Task Load Register to ensure that the bit0 is 0. If the bit0 is not read out to be
0, wait until it is 0, then configure the bit0 to be 1 to start task.
Step 5 Wait for interrupt status by reading CE Interrupt Status Register.
Step 6 Read the result from the destination address.
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Step 7 Clear the interrupt.
10.1.4.2 Configuring Task Descriptor of AES
Common control: Configure Common Control[6:0] to 0x0 to select AES algorithm type.
Symmetric control: According to the corresponding algorithm requirements, configure Symmetric Control
to select the key size, CTR width, CTS last package flag, CFB width, and AES algorithm mode, and so on.
Asymmetric control: The symmetric algorithm does not need to be configured for this field.
Key descriptor: Because the storage of the key requires word alignment, ensure that this descriptor is the
first address of the KEY (word address).
IV descriptor: In the task that requires the IV value, configure the first address of the storage space where
the IV is stored here. Because the storage of the IV requires word alignment, ensure that this descriptor
is the first address of the IV (word address).
Data length: Configure the data length of the corresponding segment. The data length size needs to be
consistent with dst_data_length (destination data length 0 +... + destination data length 7). When the
algorithm is CTS mode, the higher 30-bit of the data length is the word numbers of data volume; when
the data_length[1:0] is 0, the data length is the higher 30-bit, otherwise it is increased by 1. For AES CTS,
the data length indicates the byte numbers of the source data; for other algorithms, it indicates the word
numbers.
Source address: The first address of source data segments. Because the storage of the source data
requires word alignment, ensure that this descriptor is the first address (word address).
Source data length: The data volume of source data segments. The unit is word, and those less than one
word are counted as one word. Note that only the last word of the entire message is allowed to be non-
integer words, and the others must be integer words.
Destination address: The first address of destination data segments. Because the storage of the
destination data requires word alignment, ensure that this descriptor is the first address (word address).
Destination data length: The data volume of destination data segments. The unit is word, and those less
than one word are counted as one word. Note that only the last word of the entire message is allowed to
be non-integer words, and the others must be integer words.
Next descriptor: The first address of the next task descriptor. Because the storage of the descriptor
requires word alignment, ensure that this descriptor is the first address (word address).
Reserved: Configure to 0x0.
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10.1.4.3 Configuring Task Descriptor of HASH
Common control
Algorithm type: Configure Common Control[6:0] to select SHA or HMAC algorithm type.
Last HMAC plaintext: If the algorithm type is HMAC, and the task is the last package of the message
or if the message has only one package, then Common Control[15] needs to set to 1.
IV mode: The Common Control[16] (IV MODE) bit is only set to 1 in the following two scenarios,
except that the bit must be configured to 0. (1). When the message is split into multiple packages,
the Common Control[16] bit of other packages needs to be set to 1, except that the bit of the first
package needs to be cleared to 0. (2). In special applications, if you need to customize the IV value to
form the initial value of a certain HASH algorithm, you need to set the Common Control[16] bit of the
first (or only one) package to 1, and the first address of the storage space where the customized IV
value is stored in IV address.
Key descriptor: Because the storage of the key requires word alignment, ensure that this descriptor is the
first address of the KEY (word address).
IV descriptor: In the task that requires the IV value, configure the first address of the storage space where
the IV is stored here. Because the storage of the IV requires word alignment, ensure that this descriptor
is the first address of the IV (word address).
Data length: Configure the data length of the corresponding segment. The data length size needs to be
consistent with dst_data_length (destination data length 0 +... + destination data length 7).
Source address: The first address of source data segments. Because the storage of the source data
requires word alignment, ensure that this descriptor is the first address (word address).
Source data length: The data volume of source data segments. The unit is word, and those less than one
word are counted as one word. Note that only the last word of the entire message is allowed to be non-
integer words, and the others must be integer words.
Destination address: The first address of destination data segments. Because the storage of the
destination data requires word alignment, ensure that this descriptor is the first address (word address).
Destination data length: The data volume of destination data segments. The unit is word, and those less
than one word are counted as one word. Note that only the last word of the entire message is allowed to
be non-integer words, and the others must be integer words.
Next descriptor: The first address of the next task descriptor. Because the storage of the descriptor
requires word alignment, ensure that this descriptor is the first address (word address).
Reserved: Configure to 0x0.
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10.1.4.4 Configuring Task Descriptor of RSA
Common control: Configure Common Control[6:0] to 0x20 to select RSA algorithm type.
Asymmetric control: Configure Asymmetric Control[30:28] to select the RSA width.
Key descriptor: Because the storage of the key requires word alignment, ensure that this descriptor is the
first address of the KEY (word address).
Data length: Configure the data length of the corresponding segment. The data length size needs to be
consistent with dst_data_length (destination data length 0 +... + destination data length 7).
Source address: The first address of source data segments. Because the storage of the source data
requires word alignment, ensure that this descriptor is the first address (word address).
Source data length: The data volume of source data segments. The unit is word, and those less than one
word are counted as one word. Note that only the last word of the entire message is allowed to be non-
integer words, and the others must be integer words.
Destination address: The first address of destination data segments. Because the storage of the
destination data requires word alignment, ensure that this descriptor is the first address (word address).
Destination data length: The data volume of destination data segments. The unit is word, and those less
than one word are counted as one word. Note that only the last word of the entire message is allowed to
be non-integer words, and the others must be integer words.
Next descriptor: The first address of the next task descriptor. Because the storage of the descriptor
requires word alignment, ensure that this descriptor is the first address (word address).
Reserved: Configure to 0x0.
10.1.5 Register List
Module Name Base Address
CE_NS 0x03040000
Register Name Offset Description
CE_TDA 0x0000 Task Descriptor Address
CE_ICR 0x0008 Interrupt Control Register
CE_ISR 0x000C Interrupt Status Register
CE_TLR 0x0010 Task Load Register
CE_TSR 0x0014 Task Status Register
CE_ESR 0x0018 Error Status Register
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Register Name Offset Description
CE_CSA 0x0024 DMA Current Source Address
CE_CDA 0x0028 DMA Current Destination Address
CE_TPR 0x002C Throughput Register
10.1.6 Register Description
10.1.6.1 0x0000 CE Task Descriptor Address Register (Default Value: 0x0000_0000)
Offset: 0x0000 Register Name: CE_TDA
Bit Read/Write Default/Hex Description
Task Descriptor Address
31:0 R/W 0x0
Configure as the first address of the descriptor structure.
10.1.6.2 0x0008 CE Interrupt Control Register (Default Value: 0x0000_0000)
Offset: 0x0008 Register Name: CE_ICR
Bit Read/Write Default/Hex Description
31:4 / / /
Task Channel3~0 Interrupt Enable
3:0 R/W 0x0 0: Disable
1: Enable
10.1.6.3 0x000C CE Interrupt Status Register (Default Value: 0x0000_0000)
Offset: 0x000C Register Name: CE_ISR
Bit Read/Write Default/Hex Description
31:4 / / /
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Offset: 0x000C Register Name: CE_ISR
Bit Read/Write Default/Hex Description
Task Channel3~0 End Pending
0: Not finished
1: Finished
It indicates whether task is completed.
Write the corresponding channel bit of the register to clear the
end flag.
When the last task in the task chain ends, the operation of the
task chain will end normally. If the task fails in the middle, the
task chain will be aborted. The CE_ISR register will be
automatically updated when it ends normally or aborts
abnormally. And it is determined whether to generate an
3:0 R/W1C 0x0
interrupt signal according to the IE configuration (bit31) of
Common Control when the current task ends or aborts.
If using interrupt, after receiving the interrupt, read the
corresponding channel bit of CE_ISR to judge whether it ends
successfully or stops failure.
If not using interrupt, the CE_ISR status register can be
continuously queried for the channel bit until the successful end
flag is set or the failure stop flag is set. Write the corresponding
channel bit of the register to clear the end flag.
If it fails to stop, you can read the error code on the channel
corresponding to the CE_ESR register.
10.1.6.4 0x0010 CE Task Load Register (Default Value: 0x0000_0000)
Offset: 0x0010 Register Name: CE_TLR
Bit Read/Write Default/Hex Description
31:1 / / /
Task Load
0 R/W 0x0 When set, the CE can load the descriptor of task if the task FIFO
is not full.
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10.1.6.5 0x0014 CE Task Status Register (Default Value: 0x0000_0000)
Offset: 0x0014 Register Name: CE_TSR
Bit Read/Write Default/Hex Description
31:2 / / /
Running Channel Number
00: Task channel0
1:0 R 0x0 01: Task channel1
10: Task channel2
11: Task channel3
10.1.6.6 0x0018 CE Error Status Register (Default Value: 0x0000_0000)
Offset: 0x0018 Register Name: CE_ESR
Bit Read/Write Default/Hex Description
31:16 / / /
Task Channel3 Error Type
xxx1: Algorithm not support
15:12 R/W1C 0x0 xx1x: Data length error
x1xx: keysram access error for AES
1xxx: Reserved
Task Channel2 Error Type
xxx1: Algorithm not support
11:8 R/W1C 0x0 xx1x: Data length error
x1xx: keysram access error for AES
1xxx: Reserved
Task Channel1 Error Type
xxx1: Algorithm not support
7:4 R/W1C 0x0 xx1x: Data length error
x1xx: keysram access error for AES
1xxx: Reserved
Task Channel0 Error Type
xxx1: Algorithm not support
3:0 R/W1C 0x0 xx1x: Data length error
x1xx: keysram access error for AES
1xxx: Reserved
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10.1.6.7 0x0024 CE Current Source Address Register (Default Value: 0x0000_0000)
Offset: 0x0024 Register Name: CE_CSA
Bit Read/Write Default/Hex Description
CUR_SRC_ADDR
31:0 R 0x0
Current source address
10.1.6.8 0x0028 CE Current Destination Address Register (Default Value: 0x0000_0000)
Offset: 0x0028 Register Name: CE_CDA
Bit Read/Write Default/Hex Description
CUR_DST_ADDR
31:0 R 0x0
Current destination address
10.1.6.9 0x002C CE Throughput Register (Default Value: 0x0000_0000)
Offset: 0x002C Register Name: CE_TPR
Bit Read/Write Default/Hex Description
TP_NUM
31:0 R/WC 0x0 It indicates the throughput writing to this register at last time.
Writing to this register will clear it to 0.
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10.2 Security ID
The Security ID (SID) is used to program and read keys which include chip ID, thermal sensor, HASH code, and
so on.
The SID module has the following features:
2 Kbits electrical fuse (eFuse)
Backup eFuse information by using SID_SRAM
A fuse only can program one time
Burning the key to the SID
Reading the key use status in the SID
Loading the key to the CE
CAUTION
Before performing the burning operation, ensure that the power supply of the eFuse power pin is stable.
After the burning operation is completed, cancel the power supply of the eFuse power pin.
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Appendix: Glossary
The following table contains acronyms and abbreviations used in this document.
Term Meaning
A
ADC Analog-to-Digital Converter
AE Automatic Exposure
AEC Audio Echo Cancellation
AES Advanced Encryption Standard
AF Automatic Focus
AGC Automatic Gain Control
AHB AMBA High-Speed Bus
ALC Automatic Level Control
ANR Active Noise Reduction
APB Advanced Peripheral Bus
ARM Advanced RISC Machine
AVS Audio Video Synchronization
AWB Automatic White Balance
B
BROM Boot ROM
C
CIR Consumer Infrared
CMOS Complementary Metal-Oxide Semiconductor
CP15 Coprocessor 15
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CSI Camera Serial Interface
CVBS Composite Video Broadcast Signal
D
DDR Double Data Rate
DES Data Encryption Standard
DLL Delay-Locked Loop
DMA Direct Memory Access
DRC Dynamic Range Compression
DVFS Dynamic Voltage and Frequency Scaling
E
ECC Error Correction Code
eFuse Electrical Fuse, A one-time programmable memory
EHCI Enhanced Host Controller Interface
eMMC Embedded Multi-Media Card
ESD Electrostatic Discharge
F
FBGA Fine Pitch Ball Grid Array
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Term Meaning
FEL Fireware Exchange Launch
FIFO First In First Out
G
GPIO General Purpose Input Output
I
I2C Inter Integrated Circuit
I2S Inter IC Sound
ISP Image Signal Processor
J
JEDEC Joint Electron Device Engineering Council
JPEG Joint Photographic Experts Group
JTAG Joint Test Action Group
L
LCD Liquid-Crystal Display
LFBGA Low Profile Fine Pitch Ball Grid Array
LSB Least Significant Bit
LVDS Low Voltage Differential Signaling
M
MAC Media Access Control
MIC Microphone
MIPI Mobile Industry Processor Interface
MLC Multi-Level Cell
MMC Multimedia Card
MPEG Motion Pictures Expert Group
MSB Most Significant Bit
N
N/A Not Application
NMI Non Maskable Interrupt
NTSC National Television Standards Committee
NVM Non Volatile Storage Medium
O
OHCI Open Host Controller Interface
OTP One Time Programmable
OWA One Wire Audio
P
PAL Phase Alternating Line
PCM Pulse Code Modulation
PHY Physical Layer Controller
PID Packet Identifier
PLIC Platform-Level Interrupt Controller
PLL Phase-Locked Loop
POR Power-On Reset
PRCM Power Reset Clock Management
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Term Meaning
PWM Pulse Width Modulation
R
R Read only/non-Write
RGB Read Green Blue
RGMII Reduced Gigabit Media Independent Interface
RMII Reduced Media Independent Interface
ROM Read Only Memory
RSA Rivest-Shamir-Adleman
RTC Real Time Clock
S
SAR Successive Approximation Register
SD Secure Digital
SDIO Secure Digital Input Output
SDK Software Development Kit
SDRAM Synchronous Dynamic Random Access Memory
SDXC Secure Digital Extended Capacity
SLC Single-Level Cell
SoC System on Chip
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
T
TDES Triple Data Encryption Standard
TWI Two Wire Interface
U
UART Universal Asynchronous Receiver Transmitter
UDF Undefined
Transmitter
USB DRD Universal Serial Bus Dual Role Device
UTMI USB2.0 Transceiver Macrocell Interface
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Copyright© 2021 Allwinner Technology Co.,Ltd. All Rights Reserved.
This documentation is the original work and copyrighted property of Allwinner Technology Co.,Ltd (“Allwinner”). No part
of this document may be reproduced, modify, publish or transmitted in any form or by any means without prior written
consent of Allwinner.
Trademarks and Permissions
Allwinner and the Allwinner logo (incomplete enumeration) are trademarks of Allwinner Technology Co.,Ltd. All other
trademarks, trade names, product or service names mentioned in this document are the property of their respective
owners.
Important Notice and Disclaimer
The purchased products, services and features are stipulated by the contract made between Allwinner Technology
Co.,Ltd (“Allwinner”) and the customer. All or part of the products, services and features described in this document may
not be within the purchase scope or the usage scope. Please read the terms and conditions of the contract and relevant
instructions carefully before using, and follow the instructions in this documentation strictly. Allwinner assumes no
responsibility for the consequences of improper use (including but not limited to overvoltage, overclock, or excessive
temperature).
The information in this document is provided just as a reference or typical applications, and is subject to change without
notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents. Allwinner is
not responsible for any damage (including but not limited to indirect, incidental or special loss) or any infringement of
third party rights arising from the use of this document. All statements, information, and recommendations in this
document do not constitute a warranty or commitment of any kind, express or implied.
No license is granted by Allwinner herein express or implied or otherwise to any patent or intellectual property of
Allwinner. Third party licences may be required to implement the solution/product. Customers shall be solely responsible
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