BTS7002-1EPP

PROFET™+2 12V 1x 2.6 mΩ

Smart High-Side Power Switch

Package PG-TSDSO-14
Marking 7002-1P

1 Overview
Potential Applications
• Suitable for driving 21 A resistive, inductive and capacitive loads
• Replaces electromechanical relays, fuses and discrete circuits
• Suitable for driving glow plug, heating loads, DC motor and for power
distribution

VBAT
ZWIRE
Optional Optional

CVS CVSGND T1
Logic Supply
RGND

VDD GND VS
ROL

GPIO RIN IN

OUT
GPIO RDEN DEN

COUT0
RPD

PROFET™+2
ZWIRE

DZ2 CVS2 Microcontroller 12V

ADC RADC RIS_PROT IS

VSS
RSENSE

CSENSE DZ1
ZLOAD*

Logic GND

Power GND Optional

Chassis GND
*See Chapter 1 „Potential Applications“
App_1CH_INTDIO_CVG.emf

Figure 1 BTS7002-1EPP Application Diagram. Further information in Chapter 10

Data Sheet Rev. 1.04

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PROFET™+2 12V
Overview

Basic Features
• High-Side Switch with Diagnosis and Embedded Protection
• Part of PROFET™+2 12V Family
• ReverseON for low power dissipation in Reverse Polarity
• Green Product (RoHS compliant)

Protection Features
• Absolute and dynamic temperature limitation with controlled reactivation
• Overcurrent protection (tripping) with Intelligent Latch
• Undervoltage shutdown
• Overvoltage protection with external components (as shown in Figure 37)

Diagnostic Features
• Proportional load current sense
• Open Load in ON and OFF state
• Short circuit to ground and battery

Product Validation
Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.

Description
The BTS7002-1EPP is a Smart High-Side Power Switch, providing protection functions and diagnosis.

Table 1 Product Summary

Parameter Symbol Values
Minimum Operating voltage VS(OP) 4.1 V
Minimum Operating voltage (cranking) VS(UV) 3.1 V
Maximum Operating voltage VS 28 V
Minimum Overvoltage protection (TJ ≥ 25 °C) VDS(CLAMP)_25 35 V
Maximum current in OFF mode (TJ ≤ 85 °C) IVS(OFF)_85 0.9 µA
Maximum operative current IGND(ON_D) 3 mA
Typical ON-state resistance (TJ = 25 °C) RDS(ON)_25 2.6 mΩ
Maximum ON-state resistance (TJ = 150 °C) RDS(ON)_150 4.8 mΩ
Nominal load current (TA = 85 °C) IL(NOM) 21 A
Minimum overload detection current IL(OVL0)_-40 120 A
Typical current sense ratio at IL = IL(NOM) kILIS 22700

Data Sheet 2 Rev. 1.04

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Block Diagram and Terms

2 Block Diagram and Terms

2.1 Block Diagram

VS

Supply Voltage
Monitoring
Overvoltage
Protection
Channel
Internal Power Supply
Voltage Sensor
Intelligent Restart
Control T
Overtemperature Overvoltage
IS SENSE Output Clamping
Gate Control
+ Overcurrent
Driver Chargepump Protection
IN Logic
ReverseON OUT
ESD InverseON
Protection
+
DEN Load Current Sense
Input Logic

Output Voltage Limitation

Internal Reverse
Polarity Protection

GND Circuitry

GND Block_HE AT1ch.emf

Figure 2 Block Diagram of BTS7002-1EPP

Data Sheet 3 Rev. 1.04

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Block Diagram and Terms

2.2 Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.

IVS

VSIS VS
IIN VDS
IN

IDEN
DEN
IL
VS OUT

VIN
VDEN IIS
IS
VOUT
GND
VIS
IGND

Terms_1CH.emf

Figure 3 Voltage and Current Convention

Data Sheet 4 Rev. 1.04

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Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

GND 1 14 OUT
IN 2 13 OUT
DEN 3 12 OUT
IS 4 VS 11 n.c.
n.c. 5 10 OUT
n.c. 6 9 OUT
exposed pad (bottom)
n.c. 7 8 OUT

PinOut_PROF ET1ch_PDH.emf

Figure 4 Pin Configuration

Data Sheet 5 Rev. 1.04

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Pin Configuration

3.2 Pin Definitions and Functions

Table 2 Pin Definition

Pin Symbol Function
EP VS Supply Voltage
(exposed pad) Battery voltage
1 GND Ground
Signal ground
2 IN Input Channel
Digital signal to switch ON the channel (“high” active)
If not used: connect to GND pin or to module ground with resistor RIN = 4.7 kΩ
3 DEN Diagnostic Enable
Digital signal to enable device diagnosis (“high” active) and to clear the
protection latch of channel
If not used: connect to GND pin or to module ground with resistor RDEN = 4.7 kΩ
4 IS SENSE current output
Analog/digital signal for diagnosis
If not used: left open
5-7, 11 n.c. Not connected, internally not bonded
8-10, 12- OUT Output
14 Protected high-side power output channel1)
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow.

Data Sheet 6 Rev. 1.04

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General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings - General

Table 3 Absolute Maximum Ratings1)

TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Supply pins
Power Supply Voltage VS -0.3 – 28 V – P_4.1.0.1
Load Dump Voltage VBAT(LD) – – 35 V suppressed P_4.1.0.3
Load Dump
acc. to
ISO16750-2
(2010).
Ri = 2 Ω
Supply Voltage for Short Circuit VBAT(SC) 0 – 24 V Setup acc. to P_4.1.0.25
Protection AEC-Q100-012
Reverse Polarity Voltage -VBAT(REV) – – 16 V t ≤ 2 min P_4.1.0.5
TA = +25 °C
Setup as
described in
Chapter 10
Current through GND Pin IGND -50 – 50 mA RGND according P_4.1.0.9
to Chapter 10
Logic & control pins (Digital Input = DI)
DI = IN, DEN
2)
Current through DI Pin IDI -1 – 2 mA P_4.1.0.14

2)
Current through DI Pin IDI(REV) -1 – 10 mA P_4.1.0.36
Reverse Battery Condition t ≤ 2 min
IS pin
Voltage at IS Pin VIS -1.5 – VS V IIS = 10 μA P_4.1.0.16
Current through IS Pin IIS -25 – IIS(SAT),M mA – P_4.1.0.18
AX
Temperatures
Junction Temperature TJ -40 – 150 °C – P_4.1.0.19
Storage Temperature TSTG -55 – 150 °C – P_4.1.0.20

Data Sheet 7 Rev. 1.04

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General Product Characteristics

Table 3 Absolute Maximum Ratings1) (continued)

TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
ESD Susceptibility
ESD Susceptibility all Pins VESD(HBM) -2 – 2 kV HBM3) P_4.1.0.21
(HBM)
ESD Susceptibility OUT vs GND VESD(HBM)_OU -4 – 4 kV HBM3) P_4.1.0.22
and VS connected (HBM) T
ESD Susceptibility all Pins VESD(CDM) -500 – 500 V CDM4) P_4.1.0.23
(CDM)
ESD Susceptibility Corner Pins VESD(CDM)_CR -750 – 750 V CDM4) P_4.1.0.24
(CDM) N
(pins 1, 7, 8, 14)
1) Not subject to production test - specified by design.
2) Maximum VDI to be considered for Latch-Up tests: 5.5 V.
3) ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002.
4) ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011.

Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.

4.2 Absolute Maximum Ratings - Power Stages

4.2.1 Power Stage - 2 mΩ

Table 4 Absolute Maximum Ratings1)

TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Maximum Energy Dissipation EAS – – 315 mJ IL = 2*IL(NOM) P_4.2.10.1
Single Pulse TJ(0) = 150 °C
VS = 28 V

Data Sheet 8 Rev. 1.04

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General Product Characteristics

Table 4 Absolute Maximum Ratings1) (continued)

TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Maximum Energy Dissipation EAR – – 74 mJ IL = IL(NOM) P_4.2.10.2
Repetitive Pulse TJ(0) = 85 °C
VS = 13.5 V
1M cycles
Load Current |IL| – – IL(OVL0), A – P_4.2.10.3
MAX
1) Not subject to production test - specified by design.

4.3 Functional Range

Table 5 Functional Range - Supply Voltage and Temperature1)

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Supply Voltage Range for VS(NOR) 6 13.5 18 V – P_4.3.0.1
Normal Operation
2)3)
Lower Extended Supply VS(EXT,LOW) 3.1 – 6 V P_4.3.0.2
Voltage Range for Operation (parameter
deviations possible)
Supply Voltage Range VS(EXT,CVG) – – 3.1 V CVSGND is required P_4.3.0.7
reached after Overload when the Overload
Protection activation Protection is
leading to “Undervoltage on triggered (see
VS” condition Chapter 8.2) and
the observed
number of retries is
different from what
specified in
Chapter 8.3.1
3)
Upper Extended Supply VS(EXT,UP) 18 – 28 V P_4.3.0.3
Voltage Range for Operation (parameter
deviations possible)
Junction Temperature TJ -40 – 150 °C – P_4.3.0.5
1) Not subject to production test - specified by design.
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V.
3) Protection functions still operative.

Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
tables.

Data Sheet 9 Rev. 1.04

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General Product Characteristics

4.4 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.

Table 6 Thermal Resistance1)

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
2)
Thermal Characterization ΨJTOP – 3 5 K/W P_4.4.0.1
Parameter Junction-Top
2)
Thermal Resistance RthJC – 0.78 1.3 K/W P_4.4.0.2
Junction-to-Case simulated at
exposed pad
2)
Thermal Resistance RthJA – 30.7 – K/W P_4.4.0.3
Junction-to-Ambient
1) Not subject to production test - specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,
PDISSIPATION = 1 W.

4.4.1 PCB Setup

70 µm modeled (traces, cooling area)

1,5 mm

70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_1s0p.emf

Figure 5 1s0p PCB Cross Section

70 µm modeled (traces)
35 µm, 90% metalization*
1,5 mm

35 µm, 90% metalization*

70 µm, 5% metalization*

*: means percentual Cu metalization on each layer

PCB_Zth_2s2p.emf

Figure 6 2s2p PCB Cross Section

Data Sheet 10 Rev. 1.04

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General Product Characteristics

PCB 1s0p + 600 mm² cooling PCB 2s2p / 1s0p footprint

PCB_sim _setup_TSDSO14.emf

Figure 7 PCB setup for thermal simulations

PCB_2s2p_vias_TSDSO14.emf

Figure 8 Thermal vias on PCB for 2s2p PCB setup

Data Sheet 11 Rev. 1.04

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General Product Characteristics

4.4.2 Thermal Impedance

BTS7002-1EPx
100

10
ZthJA (K/W)
TA = 105°C

2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
0,1
0,0001 0,001 0,01 0,1 1 10 100 1000
Time (s)

Figure 9 Typical Thermal Impedance. PCB setup according Chapter 4.4.1

120
BTS7002-1EPx
1s0p - Ta = 105°C
110

100

90

80
RthJA (K/W)

70

60

50

40

30
0 100 200 300 400 500 600
Cooling area (mm²)

Figure 10 Thermal Resistance on 1s0p PCB with various cooling surfaces

Data Sheet 12 Rev. 1.04

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Logic Pins

5 Logic Pins
The device has 2 digital pins.

5.1 Input Pin (IN)

The input pin IN activates the output channel. The input circuitry is compatible with 3.3V and 5V
microcontroller (see Chapter 10 for the complete application setup overview). The electrical equivalent of the
input circuitry is shown in Figure 11. In case the pin is not used, it should be pulled to module GND or device
GND pin via RIN = 4.7 kΩ.

VS

IN

IDI VS(CLAMP)

ESD IDI

VDI(CLAMP)
VDI

GND

IGND
RGND

Input_IN_INTDIO.emf

Figure 11 Input circuitry

The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always
higher than the voltage needed to ensure a “low” state.

V DI

V DI(TH ),M AX
V DI(TH)
V DI(HYS)

V DI(TH ),M IN

t
Internal channel
0 x 1 x 0
activation signal
t
Input_VDITH_2.emf

Figure 12 Input Threshold voltages and hysteresis

Data Sheet 13 Rev. 1.04

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Logic Pins

5.2 Diagnosis Pin

The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and can be used to reset the latched protection
(Protection circuitry not disabled by DEN). When DEN pin is set to “high”, the diagnosis is enabled (see
Chapter 9.2 for more details). When it is set to “low”, the diagnosis is disabled (IS pin is set to high
impedance).
The transition from “high” to “low” of DEN pin clears the protection latch of the channel depending on the
logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal structure of
diagnosis pins is the same as the one of input pins. See Figure 11 for more details.

5.3 Electrical Characteristics Logic Pins

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Digital Input (DI) pins = IN, DEN

Table 7 Electrical Characteristics: Logic Pins - General

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Digital Input Voltage VDI(TH) 0.8 1.3 2 V See Figure 11 and P_5.4.0.1
Threshold Figure 12
1)
Digital Input Clamping VDI(CLAMP1) – 7 – V P_5.4.0.2
Voltage IDI = 1 mA
See Figure 11 and
Figure 12
Digital Input Clamping VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA P_5.4.0.3
Voltage See Figure 11 and
Figure 12
1)
Digital Input Hysteresis VDI(HYS) – 0.25 – V P_5.4.0.4
See Figure 11 and
Figure 12
Digital Input Current IDI(H) 2 10 25 µA VDI = 2 V P_5.4.0.5
(“high”) See Figure 11 and
Figure 12
Digital Input Current (“low”) IDI(L) 2 10 25 µA VDI = 0.8 V P_5.4.0.6
See Figure 11 and
Figure 12
1) Not subject to production test - specified by design.

Data Sheet 14 Rev. 1.04

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Power Supply

6 Power Supply
The BTS7002-1EPP is supplied by VS, which is used for the internal logic as well as supply for the power output
stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and
diagnosis in case the applied voltage is below the undervoltage threshold (VS < VS(OP)). During power up, the
internal power on signal is set when supply voltage (VS) exceeds the minimum operating voltage (VS > VS(OP)).

6.1 Operation Modes

BTS7002-1EPP has the following operation modes in case of VS > VS(OP):
• OFF mode
• ON mode
• Diagnosis in ON mode
• Diagnosis in OFF mode
• Fault
The transition between operation modes is determined according to these variables:
• Logic level at IN pin
• Logic level at DEN pin
• Internal latch
• Sense current IIS level
The truth table in case of VS > VS(OP) is shown in Table 8. The behavior of BTS7002-1EPP as well as some
parameters may change in dependence on the operation mode of the device.
There are three parameters describing each operation mode of BTS7002-1EPP:
• Status of the output channel
• Status of the diagnosis
• Current consumption at VS pin (measured by IVS in OFF mode, IGND in all other operative modes)

Table 8 Operation Mode truth table

IN DEN Internal IIS Operative Mode Comment
latch
L L L leakage OFF DMOS channel is OFF
L L H leakage OFF DMOS channel is OFF
L H L leakage OFF_DIAG Diagnostic in OFF-mode
open load Diagnostic in OFF-mode
L H H fault Diagnostic in OFF-mode
H L L leakage ON DMOS channel is ON, no diagnostic
H L H leakage fault DMOS channel is switched OFF due to
failure
H H L IIS ON_DIAG DMOS channel is ON and diagnostic
H H H fault fault DMOS channel is switched OFF due to
failure

Data Sheet 15 Rev. 1.04

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Power Supply

6.1.1 OFF mode

When BTS7002-1EPP is in OFF mode, the output channel is OFF. The current consumption is minimum (see
parameter IVS(OFF)). No Overtemperature, Overload protection mechanism and no diagnosis function is active
when the device is in OFF mode.

6.1.2 ON mode
ON (IN = High; DEN = Low) mode is the normal operation mode of BTS7002-1EPP. Device current consumption
is specified with IGND(ON_D) + IIS(OFF) (measured at GND pin because the current at VS pin includes the load
current). Overcurrent and Overtemperature protections are active. No diagnosis function is active.

6.1.3 OFF_Diag mode

The device is in OFF_Diag mode as long as DEN pin is set to “high” and IN pin is set to “low”. The output
channel is OFF. If an open load case happens, an Open Load in OFF current IIS(OLOFF) may be present at IS pin.
In such situation, the current consumption of the device is increased.

6.1.4 ON_Diag mode

The device is in normal ON mode with current sense function. IIS or IIS(FAULT) will be present at IS pin. Device
current consumption is specified with IGND(ON_D). Depending on the load condition, either a fault current
IIS(FAULT) or IIS current may be present at IS pin.

6.1.5 Fault mode

The device is in Fault mode as soon as a protection event happens which affects that the device switches off
due to its protection function. In Fault mode, a IIS(FAULT) signal is presenting at IS pin during the DEN signal is
"high".

6.2 Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in ON mode) and
the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output
channel.
As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is switched ON again. The
restart is delayed with a time tDELAY(UV) which protects the device in case the undervoltage condition is caused
by a short circuit event (according to AEC-Q100-012), as shown in Figure 13.
If the device is in OFF mode and the input is set to “high”, the channel will be switched ON if VS > VS(OP) without
waiting for tDELAY(UV).

Data Sheet 16 Rev. 1.04

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Power Supply

VS

VS(OP)
VS(HYS)
VS(UV)

t
Channel
activat ion signal
t

VOUT

tDELA Y(UV)

t
PowerSupply_UVRVS.emf

Figure 13 VS undervoltage behavior

Data Sheet 17 Rev. 1.04

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Power Supply

6.3 Electrical Characteristics Power Supply

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

Table 9 Electrical Characteristics: Power Supply - General

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
VS pin
Power Supply Undervoltage VS(UV) 1.8 2.3 3.1 V VS decreasing P_6.4.0.1
Shutdown IN = “high”
From VDS ≤ 0.5 V to
VDS = VS
See Figure 13
Power Supply Minimum VS(OP) 2.0 3.0 4.1 V VS increasing P_6.4.0.3
Operating Voltage IN = “high”
From VDS = VS to
VDS ≤ 0.5 V
See Figure 13
1)
Power Supply Undervoltage VS(HYS) – 0.7 – V P_6.4.0.6
Shutdown Hysteresis VS(OP) - VS(UV)
See Figure 13
Power Supply Undervoltage tDELAY(UV) 2.5 5 7.5 ms dVS/dt ≤ 0.5 V/µs P_6.4.0.7
Recovery Time VS ≥ -1 V
See Figure 13
1)
Breakdown Voltage -VS(REV) 16 – 30 V P_6.4.0.9
between GND and VS Pins in IGND(REV) = 7 mA
Reverse Battery TJ = 150 °C
1) Not subject to production test - specified by design.

Data Sheet 18 Rev. 1.04

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Power Supply

6.4 Electrical Characteristics Power Supply - Product Specific

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

6.4.1 BTS7002-1EPP

Table 10 Electrical Characteristics: Power Supply BTS7002-1EPP

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)
Supply Current IVS(OFF)_85 – 0.1 0.9 µA P_6.5.20.1
Consumption in OFF Mode VS = 18 V
with Loads VOUT = 0 V
IN = DEN = “low”
TJ ≤ 85 °C
Supply Current IVS(OFF)_150 – 1 27 µA VS = 18 V P_6.5.20.2
Consumption in OFF Mode VOUT = 0 V
with Loads IN = DEN = “low”
TJ = 150 °C
Operating Current in IGND(ON_D) – 2 3 mA VS = 18 V P_6.5.20.3
ON_Diag Mode (Channel IN = DEN = “high”
ON)
Operating Current in IGND(OFF_D) – 1.2 1.8 mA VS = 18 V P_6.5.20.5
OFF_Diag Mode IN = “low”;
DEN = “high”
1) Not subject to production test - specified by design.

Data Sheet 19 Rev. 1.04

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Power Stages

7 Power Stages
The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump.

7.1 Output ON-State Resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 14 shows the variation of
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150 °C.

RDS(ON) variation over TJ

2.20

Reference value:
2.00 "2" = RDS(ON),MAX @ 150 °C

1.80

1.60

1.40
RDS(ON) variation factor

1.20

1.00

0.80

0.60

0.40

0.20 Typical

0.00
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
Junction Temperature (°C)

Figure 14 RDS(ON) variation factor

The behavior in Reverse Polarity is described in Chapter 8.4.1.

7.2 Switching loads

7.2.1 Switching Resistive Loads

When switching resistive loads, the switching times and slew rates shown in Figure 15 can be considered. The
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF.

Data Sheet 20 Rev. 1.04

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Power Stages

IN
VIN(TH)
VIN(HYS)
t
VOUT
tON
90% of VS tOFF(DELAY)
70% of VS 70% of VS
-(dV/dt)OFF
(dV/dt)ON
30% of VS 30% of VS
tON(DELAY) tOFF
10% of VS t

PDMOS

EON EOFF
t

PowerStage_SwitchRes.emf

Figure 15 Switching a Resistive Load

7.2.2 Switching Inductive Loads

When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative
output voltage so that VDS = VDS(CLAMP). Figure 16 shows a concept drawing of the implementation. The
clamping structure is available in all operation modes listed in Chapter 6.1.

VS
High-side
Channel

VS VDS

VSIS(CLAMP)
VDS(CLAMP)

IS
IL
VS(CLAMP)
OUT VOUT
RSENSE

GND L,
IL
RL
RGND

PowerStage_Clamp_IN TDIO_1CH.emf

Figure 16 Output Clamp concept

Data Sheet 21 Rev. 1.04
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Power Stages

During demagnetization of inductive loads, energy has to be dissipated in BTS7002-1EPP. The energy can be
calculated with Equation (7.1):

V S – V DS ( CLAMP ) RL ⋅ IL L
E = V DS ( CLAMP ) ⋅ -------------------------------------------- ⋅ ln ⎛ 1 – -------------------------------------------
-⎞ + I L ⋅ ------ (7.1)
RL ⎝ V S – V DS ( CLAMP )⎠ RL

The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design
of the component. Please refer to Chapter 4.2 for the maximum allowed values of EAS (single pulse energy)
and EAR (repetitive energy).

7.2.3 Output Voltage Limitation

To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (DEN pin set to “high” - see Figure 17) bringing VDS equal or lower than VDS(SLC), the
output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for
very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently,
providing better kILIS accuracy for output current in the low range.

IN
t
DEN
t
IL

VDS t
VS
VDS(SLC)

t
PowerStage_GBR_diag_HEAT.emf

Figure 17 Output Voltage Limitation activation during diagnosis

7.3 Advanced Switching Characteristics

7.3.1 Inverse Current behavior

When VOUT > VS, a current IINV flows into the power output transistor (see Figure 18). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. If the channel is in ON state, RDS(INV) can be expected and
power dissipation in the output stage is comparable to normal operation in RDS(ON).
During Inverse Current condition, the channel remains in ON or OFF state as long as |-IL| < |-IL(INV)|.
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as |-IL| < |-IL(INV)|
(see Figure 19).

Data Sheet 22 Rev. 1.04

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Power Stages

VBAT

VS

Gate
Driver
VOUT > VS
Device INV -IL
Logic Comp. OUT

GND

RGND

PowerStage_Inverse_HE AT.emf

Figure 18 Inverse Current Circuitry

IN CASE 1 : Switch is ON IN CASE 2 : Switch is OFF

ON OFF
t t
IL IL

NORMAL NORMAL NORMAL NORMAL

t t
INVERSE INVERSE
DMOS state DMOS state

ON OFF
t t

CASE 3 : Switch ON into Inverse Current CASE 4 : Switch OFF into Inverse Current
IN IN

OFF ON ON OFF
t t
IL IL

NORMAL NORMAL NORMAL NORMAL

t t
INVERSE INVERSE
DMOS state DMOS state

OFF ON ON OFF
t t

PowerStage_InvCurr_INVON.emf

Figure 19 InverseON - Channel behavior in case of applied Inverse Current

Note: No protection mechanism like Overtemperature or Overload protection is active during applied
Inverse Currents.

Data Sheet 23 Rev. 1.04

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Power Stages

7.3.2 Cross Current robustness with H-Bridge configuration

When BTS7002-1EPP is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side
switch as shown in Figure 20), the maximum slew rate applied to the output by the low-side switch must be
lower than | dVOUT / dt |. Otherwise the output stage may turn ON in linear mode (not in RDS(ON)) while the low-
side switch is commutating. This creates an unprotected overheating for the DMOS due to the cross-
conduction current.

VBAT

R/L cable

HSS 1 HSS 2
VS VS
T T

ON (DC) IN IN OFF

OUT OUT | dVOUT / dt |

Cross
Current through Motor
Current

M
ON (PWM)
OFF

PowerStage_PassiveSlew_PROFET1Ch.emf

Figure 20 High-Side switch used in Bridge configuration

Data Sheet 24 Rev. 1.04

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Power Stages

7.4 Electrical Characteristics Power Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

Table 11 Electrical Characteristics: Power Stages - General

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Voltages
Drain to Source Clamping VDS(CLAMP)_-40 33 36.5 42 V IL = 5 mA P_7.4.0.1
Voltage at TJ = -40 °C TJ = -40°C
See Figure 16
1)
Drain to Source Clamping VDS(CLAMP)_25 35 38 44 V P_7.4.0.2
Voltage at TJ ≥ 25 °C IL = 5 mA
TJ ≥ 25°C
See Figure 16
1) Tested at TJ = 150°C.

7.4.1 Electrical Characteristics Power Stages

Table 12 Electrical Characteristics: Power Stages

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Timings
Switch-ON Delay tON(DELAY) 10 70 130 μs VS = 13.5 V P_7.4.5.1
VOUT = 10% VS
Switch-OFF Delay tOFF(DELAY) 10 50 160 μs VS = 13.5 V P_7.4.5.2
VOUT = 90% VS
Switch-ON Time tON 50 130 210 μs VS = 13.5 V P_7.4.5.3
VOUT = 90% VS
Switch-OFF Time tOFF 30 100 220 μs VS = 13.5 V P_7.4.5.4
VOUT = 10% VS
Switch-ON/OFF Matching ΔtSW -60 25 90 μs VS = 13.5 V P_7.4.5.5
tON - tOFF
Voltage Slope
Switch-ON Slew Rate (dV/dt)ON 0.16 0.27 0.39 V/μs VS = 13.5 V P_7.4.5.6
VOUT = 30% to 70%
of VS
Switch-OFF Slew Rate -(dV/dt)OFF 0.16 0.27 0.39 V/μs VS = 13.5 V P_7.4.5.7
VOUT = 70% to 30%
of VS

Data Sheet 25 Rev. 1.04

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Power Stages

Table 12 Electrical Characteristics: Power Stages (continued)

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Slew Rate Matching Δ(dV/dt)SW -0.15 0 +0.15 V/μs VS = 13.5 V P_7.4.5.8
(dV/dt)ON - (dV/dt)OFF
Voltages
1)
Output Voltage Drop VDS(SLC) 2 10 20 mV P_7.4.5.9
Limitation at Small Load IOUT = IOUT(OL) = 20
Currents mA
1) Not subject to production test - specified by design

7.5 Electrical Characteristics - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

7.5.1 Power Output Stage - 2 mΩ

Table 13 Electrical Characteristics: Power Stages - 2 mΩ

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Output characteristics
1)
ON-State Resistance at RDS(ON)_25 – 2.6 – mΩ P_7.5.10.1
TJ = 25 °C TJ = 25 °C
ON-State Resistance at RDS(ON)_150 – – 4.8 mΩ TJ = 150 °C P_7.5.10.2
TJ = 150 °C
ON-State Resistance in RDS(ON)_CRAN – – 6 mΩ TJ = 150 °C P_7.5.10.3
Cranking K VS = 3.1 V
1)
ON-State Resistance in RDS(INV)_25 – 2.7 – mΩ P_7.5.10.4
Inverse Current at TJ = 25 °C TJ = 25 °C
VS = 13.5 V
IL = -4 A
DEN = “low”
see Figure 18
ON-State Resistance in RDS(INV)_150 – – 6 mΩ TJ = 150 °C P_7.5.10.5
Inverse Current at TJ = 150 °C VS = 13.5 V
IL = -4 A
DEN = “low”
see Figure 18

Data Sheet 26 Rev. 1.04

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PROFET™+2 12V
Power Stages

Table 13 Electrical Characteristics: Power Stages - 2 mΩ (continued)

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)
ON-State Resistance in RDS(REV)_25 – 5.7 – mΩ P_7.5.10.6
Reverse Polarity at TJ = 25 °C TJ = 25 °C
VS = -13.5 V
IL = -4 A
see Figure 29
ON-State Resistance in RDS(REV)_150 – – 9.6 mΩ TJ = 150 °C P_7.5.10.7
Reverse Polarity at VS = -13.5 V
TJ = 150 °C IL = -4 A
1)
Nominal Load Current IL(NOM) – 21 – A P_7.5.10.8
TA = 85 °C
TJ ≤ 150 °C
1)
Output Leakage Current at IL(OFF)_85 – 0.1 0.9 μA P_7.5.10.9
TJ ≤ 85 °C VOUT = 0 V
VIN = “low”
TA ≤ 85 °C
Output Leakage Current at IL(OFF)_150 – – 27 μA VOUT = 0 V P_7.5.10.10
TJ = 150 °C VIN = “low”
TA = 150 °C
1)
Inverse Current Capability IL(INV) – -21 – A P_7.5.10.11
VS < VOUT
IN = “high”
see Figure 18
Voltage Slope
1)
Passive Slew Rate (e.g. for |dVOUT / dt| – – 10 V/μs P_7.5.10.12
Half Bridge Configuration) VS = 13.5 V
see Figure 20
Voltages
Drain Source Diode Voltage |VDS(DIODE)| – 550 700 mV IL = -190 mA P_7.5.10.13
TJ = 150 °C
Switching Energy
1)
Switch-ON Energy EON – 1.5 – mJ P_7.5.10.14
VS = 18 V
see Figure 15
1)
Switch-OFF Energy EOFF – 1.65 – mJ P_7.5.10.15
VS = 18 V
see Figure 15
1) Not subject to production test - specified by design.

Data Sheet 27 Rev. 1.04

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Protection

8 Protection
The BTS7002-1EPP is protected against Overtemperature, Overload, Reverse Battery (with ReverseON) and
Overvoltage. Overtemperature and Overload protections are working when the device is in ON or ON_Diag
mode but not during InverseON and ReverseON function. Overvoltage protection works in all operation
modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.

8.1 Overtemperature Protection

The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for
the channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN))
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until
junction temperature has reached the “Reactivation” condition described in Table 14. The behavior is shown
in Figure 21 (absolute Overtemperature Protection) and Figure 22 (dynamic Overtemperature Protection).
TJ(REF) is the reference temperature used for dynamic temperature protection.

IN

DEN

t
IL
IL(OVL 0)

I L(NOM)

t
TJ
TJ(ABS)

t
IIS
IIS = IL kILIS IIS( FAULT)

Internal
latch 0 1

Over_Temperature_Behaviour.emf

Figure 21 Overtemperature Protection (Absolute)

Data Sheet 28 Rev. 1.04

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Protection

IN

DEN

t
IL
IL ( OVL)

t
TJ
TJ( ABS)
TJ( D YN )

TJ(REF)
t
IIS
IL / k IL IS
IIS ( FAU L T)

Internal
Latch 0 1

Figure 22 Overtemperature Protection (Dynamic)

When the Overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent
Latch strategy described in Chapter 8.3 is followed.

8.2 Overload Protection

The BTS7002-1EPP is protected in case of Overload or short circuit to ground. Two Overload thresholds are
defined (see Figure 23) and selected automatically depending on the voltage VDS across the power DMOS:
• IL(OVL0) when VDS < 13 V
• IL(OVL1) when VDS > 22 V

Data Sheet 29 Rev. 1.04

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Protection

Figure 23 Overload Current Thresholds

In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low
temperature and decreases when TJ increases (see Figure 24). IL(OVL0) typical value remains constant up to a
junction temperature of +75 °C.

Figure 24 Overload Current Thresholds variation with TJ

Data Sheet 30 Rev. 1.04

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PROFET™+2 12V
Protection

Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 25.

I L(OVL )

IL(OVL_ JS)

V S(JS) VS
Protection_JS.emf

Figure 25 Overload Detection Current variation with VS voltage

When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1)) the channel is switched OFF. The channel is allowed to be reactivated
according to the intelligent latch strategy described in Chapter 8.3.

8.3 Protection and Diagnosis in case of Fault

Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:
• The channel switches OFF and the internal latch is set to “1”
• If the diagnosis is active for the channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2 for
further details)
The channel can be switched ON again if all the protection mechanisms fulfill the ”reactivation” conditions
described in Table 14. Furthermore, the device has the intelligent latch to protect itself against unwanted
repetitive reactivation in fault condition.

Table 14 Protection “Reactivation” Condition

Fault condition Switch OFF event “Reactivation” condition
Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)
(including hysteresis)
Overload IL ≥ IL(OVL) Device is OFF

8.3.1 Intelligent Latch Strategy

At normal condition, when IN is set to “high”, the channel is switched ON. In case of fault condition the output
stage latches OFF. There are two ways to de-latch the switch.
With IN pin:
It is necessary to set the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time) to de-latch
the channel. The channel can be allowed to restart only if the “latch” conditions for the protection
mechanisms are fulfilled (see Table 14 ).
Data Sheet 31 Rev. 1.04
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PROFET™+2 12V
Protection

During the “latch reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer
tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again.
The intelligent latch strategy is shown in Figure 28 (flowchart) and Figure 26 (timing diagram).
With DEN pin:
It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge
followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a
duration longer than tDEN(LR) to ensure a reset of the internal latch.
The timing is shown in Figure 27.

tDELAY (LR)
IN

Short circuit
to ground
t
IL

Internal
0 1 0 1
latch
t

DEN

t
ts IS(DIAG ) tON
IIS (FAULT) IIS (FAULT)
IIS

Protection_Latch_Timing.emf

Figure 26 Intelligent Latch Timing Diagram

Data Sheet 32 Rev. 1.04

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Protection

IN

t
Short circuit
to ground
t
IL

Internal
latch 0 1 0 1
t
t < t DEN(LR) t > tDEN(LR)

DEN

t
ts IS(DIAG ) t s IS(DIAG)
tsIS (DIAG)
IIS (FAULT) IIS (FAULT ) IIS (FAULT)
IIS

Protection_Latch_DENforce.emf

Figure 27 Intelligent Latch Timing Diagram with Forced Reset

Data Sheet 33 Rev. 1.04

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Protection

START

no
IN is "high"

yes

yes
Latch = 1

no

Reactivation
condition fulfilled
(TJ and / or ∆T / and / or
Overload) no

yes

Latch = 0 Switch channel ON

Yes

Fault
DEN pulse > tDEN(LR) (Overtemperature
no no
or Overload)

yes

Switch channel OFF

Wait until
DEN pulse > tDEN(LR) Latch = 1

Wait until IN is "low"

then start counting for
Set DEN to „high“ tDELAY(LR)

no
IN is "low"

yes

yes De-latching with

DEN

no
Continue latching for
tDELAY(LR)

tDELAY(LR) elapsed
no

yes

Latch = 0

Protection_PROFET_Flow_PDH.emf

Figure 28 Intelligent Latch Flowchart

Data Sheet 34 Rev. 1.04

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8.4 Additional protections

8.4.1 Reverse Polarity Protection

In Reverse Polarity condition (also known as Reverse Battery), the output stage is switched ON (see parameter
RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stage. Each ESD diode
of the logic contributes to total power dissipation. The reverse current through the output stage must be
limited by the connected load. The current through digital input pins has to be limited as well by an external
resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in
Chapter 10).
Figure 29 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND)
during Reverse Polarity condition is necessary to activate ReverseON, therefore a resistive path between
module ground and device GND pin must be present.

-VBAT(RE V)

High-side
Channel VS

IDI
Microcontroller
DO DI
RDI
ReverseON

OUT
-IL

GND IS GND
L, C, R
RSENSE

RGND

-IIS -IGND

Protection_RevBatt_HE AT.emf

Figure 29 Reverse Battery Protection (application example)

8.4.2 Overvoltage Protection

In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistor is still operational and
follows the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there
is a clamp mechanism available for Overvoltage protection for the logic circuit and the output channel,
monitoring the voltage between VS and GND pins (VS(CLAMP)).

Data Sheet 35 Rev. 1.04

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Protection

8.5 Protection against loss of connection

8.5.1 Loss of Battery and Loss of Load

The loss of connection to battery or to the load has no influence on device robustness when load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be
handled. PROFET™+2 12V devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In case
of applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor
diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide a well-
defined path to the load current.

8.5.2 Loss of Ground

In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin
and the microcontroller to ensure a channel switch OFF (as described in Chapter 10).

Note: In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground
path is available, which could keep the device operational during loss of device ground.

Data Sheet 36 Rev. 1.04

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Protection

8.6 Electrical Characteristics Protection

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

Table 15 Electrical Characteristics: Protection - General

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)2)
Thermal Shutdown TJ(ABS) 150 175 200 °C P_8.6.0.1
Temperature (Absolute) See Figure 21
3)
Thermal Shutdown THYS(ABS) – 30 – K P_8.6.0.2
Hysteresis (Absolute) See Figure 21
3)
Thermal Shutdown TJ(DYN) – 80 – K P_8.6.0.3
Temperature (Dynamic) See Figure 22
Power Supply Clamping VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA P_8.6.0.6
Voltage at TJ = -40 °C TJ = -40 °C
See Figure 16
2)
Power Supply Clamping VS(CLAMP)_25 35 38 44 V P_8.6.0.7
Voltage at TJ ≥ 25 °C IVS = 5 mA
TJ ≥ 25 °C
See Figure 16
3)
Power Supply Voltage VS(JS) 20.5 22.5 24.5 V P_8.6.0.8
Threshold for Overcurrent Setup acc. to AEC-
Threshold Reduction in case Q100-012
of Short Circuit
1) Functional test only.
2) Tested at TJ = 150°C only.
3) Not subject to production test - specified by design.

8.6.1 Electrical Characteristics Protection

Table 16 Electrical Characteristics: Protection

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)
Latch Reset Delay Time after tDELAY(LR) 40 70 100 ms P_8.6.4.1
Fault Condition
2)
Minimum DEN Pulse tDEN(LR) 50 100 150 µs P_8.6.4.2
Duration for Latch Reset
1) Functional test only.
2) Not subject to production test - specified by design.

Data Sheet 37 Rev. 1.04

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PROFET™+2 12V
Protection

8.7 Electrical Characteristics Protection - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

8.7.1 Protection Power Output Stage - 2 mΩ

Table 17 Electrical Characteristics: Protection - 2 mΩ

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)
Overload Detection Current IL(OVL0)_-40 120 135 158 A P_8.7.10.1
at TJ = -40 °C TJ = -40 °C
dI/dt = 0.4 A/µs
see Figure 23 and
Figure 24
2)
Overload Detection Current IL(OVL0)_25 116 133 150 A P_8.7.10.7
at TJ = 25 °C TJ = 25 °C
dI/dt = 0.4 A/µs
see Figure 23 and
Figure 24
2)
Overload Detection Current IL(OVL0)_150 100 115 130 A P_8.7.10.8
at TJ = 150 °C TJ = 150 °C
dI/dt = 0.4 A/µs
see Figure 23 and
Figure 24
2)
Overload Detection Current IL(OVL1) – 81 – A P_8.7.10.5
at High VDS dI/dt = 0.4 A/µs
see Figure 23
2)
Overload Detection Current IL(OVL_JS) – 81 – A P_8.7.10.6
Jump Start Condition VS > VS(JS)
dI/dt = 0.4 A/µs
see Figure 25
1) Functional test only.
2) Not subject to production test - specified by design.

Data Sheet 38 Rev. 1.04

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Diagnosis

9 Diagnosis
For diagnosis purpose, the BTS7002-1EPP provides a sense current signal (IIS) at pin IS. In case of disabled
diagnostic (DEN pin set to “low”), IS pin becomes high impedance.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS
pin to the sense current output of other devices, if they are supplied by a different battery feed.
See Figure 30 for details as an overview.

VS

Output Channel

Overtemperature

Latch IS Pin Control

Logic
OUT
IN
DEN IL / kILIS

IIS(FAULT) +V
DS(OLOFF)

IIS(OLOFF)

MUX

IS
RSENSE

Diag nosis_HEAT_1CH.emf

Figure 30 Diagnosis Block Diagram

Data Sheet 39 Rev. 1.04

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Diagnosis

9.1 Overview
Table 18 gives a quick reference to the state of the IS pin during BTS7002-1EPP operation.

Table 18 SENSE Signal, Function of Application Condition

Application Condition Input level DEN level VOUT Diagnostic Output
Normal operation “low” “high” ~ GND Z
IIS(FAULT) if latch ≠ 0
Short circuit to GND ~ GND Z
IIS(FAULT) if latch ≠ 0
Overtemperature Z IIS(FAULT)
Short circuit to VS VS IIS(OLOFF)
(IIS(FAULT) if latch ≠ 0)
Open Load < VS - VDS(OLOFF) Z
> VS - VDS(OLOFF)1) IIS(OLOFF)
(in both cases IIS(FAULT) if
latch ≠ 0)
Inverse current VOUT > VS IIS(OLOFF)
(IIS(FAULT) if latch ≠ 0)
Normal operation “high” ~ VS IIS = IL / kILIS
Overload < VS IIS(FAULT)
Short circuit to GND ~ GND IIS(FAULT)
Overtemperature Z IIS(FAULT)
Short circuit to VS VS IIS < IL / kILIS
2)
Open Load ~ VS IIS = IIS(EN)
3)
Under load (e.g. Output Voltage ~ VS IIS(EN) < IIS < IL(NOM) / kILIS
Limitation condition)
Inverse current VOUT > VS IIS = IIS(EN)
All conditions n.a. “low” n.a. Z
1) With additional pull-up resistor.
2) The output current has to be smaller than IL(OL).
3) The output current has to be higher than IL(OL).

9.2 Diagnosis in ON state

A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions
are fulfilled:
• The power output stage is switched ON with VDS < VDS(OLOFF)
• The diagnosis is enabled
• No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for
further details)
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.

Data Sheet 40 Rev. 1.04

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Diagnosis

9.2.1 Current Sense (kILIS)

The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in
Figure 32. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical
product.
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:
• A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by
ΔkILIS
The derating of kILIS after calibration is calculated using the formulas in Figure 31 and it is specified by ΔkILIS

Diagnosis_dKILIS.emf

Figure 31 ΔkILIS calculation formulas

The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H.

IIS

I IS(OL)

IIS(EN)

I L(OL) IL

Diagnosis_OLON_adv .emf

Figure 32 Current Sense Ratio in Open Load at ON condition

9.2.2 Fault Current (IIS(FAULT))

As soon as a protection event occurs, the value of the internal latch (see Chapter 8.3 for more details) is
changed from 0 to 1, a current IIS(FAULT) is provided by pin IS when DEN is set to “high” and the affected device
is switched OFF.

Data Sheet 41 Rev. 1.04

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BTS7002-1EPP
PROFET™+2 12V
Diagnosis

If internal latch is 1, and it is not reset, the current IIS(FAULT) is provided each time the device diagnosis is
activated by DEN=High.
Figure 33 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT).

IIS

IIS (SA T).max

IIS (SA T)

IIS (FA ULT).max

IIS (FA ULT)

IIS (SA T).min

IIS (FA ULT).min

IL / kILI S

IL(OV L).min IL(OV L).max IL

Diagnosis_HEAT_IISFAULT_IISSAT.emf

Figure 33 SENSE behavior - overview

9.3 Diagnosis in OFF state

When a power output stage is in OFF state, the BTS7002-1EPP can measure the drain-source voltage and
compare it with a threshold voltage. In this way, using some additional external components (a pull-down
resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a
short circuit to battery. If a Fault condition was detected by the device (if internal latch is 1, fault current is
provided by IS pin independent of drain-source or output voltage, as long as DEN=High) a current IIS(FAULT) is
provided by IS pin each time the channel diagnosis is checked also in OFF state. See Chapter 9.2.2 for further
details.

9.3.1 Open Load current (IIS(OLOFF))

In OFF state, when DEN pin is set to “high”, the VDS voltage is compared with a threshold voltage VDS(OLOFF). If
the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When
the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 34 shows the
relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents do not overlap making it always
possible to differentiate between Open Load in OFF and Fault condition.

Data Sheet 42 Rev. 1.04

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BTS7002-1EPP
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Diagnosis

IIS

IIS(FAUL T)

IIS(OLOFF)

VDS(OLOFF) VDS
Diagnosis_PROFET_IISOLOFF.emf

Figure 34 IIS in OFF State

It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 35 the timings for an Open
Load detection are shown - the load is always disconnected.

IN

t
DEN
tIS(OLOFF)_D t
VOUT ~ VS

VDS(OLOFF)

Load
conn ect ed

t
IIS
IIS(OLOFF)
IIS(OL)
t
Diagnosis_PROFET_OLOFF_time.emf

Figure 35 Open Load in OFF Timings - load disconnected

Data Sheet 43 Rev. 1.04

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Diagnosis

9.4 SENSE Timings

Figure 36 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load
change). As a proper signal cannot be established before the load current is stable (therefore before tON),
tsIS(DIAG) ≤ 3 × ( tON_max + tsIS(ON)_max ).

IN
OFF ON OFF
t

DEN

IL

tsIS (L C) tsIS (O FF) tsIS (ON) tsIS (O FF) t

tsIS (DI AG)
IIS

t
Diagnose_PROFET_SENSE_timings_Heat.emf

Figure 36 SENSE Settling / Disabling Timing

Data Sheet 44 Rev. 1.04

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BTS7002-1EPP
PROFET™+2 12V
Diagnosis

9.5 Electrical Characteristics Diagnosis

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

Table 19 Electrical Characteristics: Diagnosis - General

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
1)
SENSE Saturation Current IIS(SAT) 4.4 – 15 mA P_9.6.0.1
VSIS = VS - VIS ≥ 2 V
See Figure 33
SENSE Leakage Current IIS(OFF) – 0.01 0.5 µA DEN = “low” P_9.6.0.2
when Disabled VIS = 0 V
1)
SENSE Leakage Current IIS(EN)_85 – 0.2 1 µA P_9.6.0.3
when Enabled at TJ ≤ 85 °C TJ ≤ 85 °C
DEN = “high”
IL = 0 A
See Figure 32
SENSE Leakage Current IIS(EN)_150 – 0.2 1 µA TJ = 150 °C P_9.6.0.4
when Enabled at TJ = 150 °C DEN = “high”
IL = 0 A
See Figure 32
1)
SENSE Operative Range for VSIS_k – 0.5 1 V P_9.6.0.6
kILIS Operation VS = 6 V
(VS - VIS) IN = DEN = “high”
IL ≤ 2 * IL(NOM)
1)
SENSE Operative Range for VSIS_OL – 0.5 1 V P_9.6.0.7
Open Load at OFF Diagnosis VS = 6 V
(VS - VIS) IN = “low”
DEN = “high”
1)
SENSE Operative Range for VSIS_F – 0.5 1 V P_9.6.0.8
Fault Diagnosis VS = 6 V
(VS - VIS) IN = “low”
DEN = “high”
latch ≠ 0
Power Supply to IS Pin VSIS(CLAMP)_- 33 36.5 42 V IIS = 1 mA P_9.6.0.9
Clamping Voltage at 40 TJ = -40 °C
TJ = -40 °C See Figure 16
2)
Power Supply to IS Pin VSIS(CLAMP)_25 35 38 44 V P_9.6.0.10
Clamping Voltage at IIS = 1 mA
TJ ≥ 25 °C TJ ≥ 25 °C
See Figure 16
1) Not subject to production test - specified by design.
2) Tested at TJ = 150°C.

Data Sheet 45 Rev. 1.04

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PROFET™+2 12V
Diagnosis

9.5.1 Electrical Characteristics Diagnosis

Table 20 Electrical Characteristics: Diagnosis

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
SENSE Fault Current IIS(FAULT) 4.4 5.5 10 mA – P_9.6.4.1
SENSE Open Load in OFF IIS(OLOFF) 1.8 2.5 3.5 mA – P_9.6.4.2
Current
SENSE Open Load in OFF tIS(OLOFF)_D 70 185 300 µs VDS < VOL(OFF) P_9.6.4.4
Delay Time from IN falling
edge to VIS = RSENSE
* 0.9 * IIS(OLOFF),MIN
DEN = “high”
Open Load VDS Detection VDS(OLOFF) 1.3 1.8 2.3 V – P_9.6.4.5
Threshold in OFF State
SENSE Settling Time with tsIS(ON) – 5 40 µs IL = IL(NOM) P_9.6.4.6
Nominal Load Current DEN from “low” to
Stable “high”
1)
SENSE Disable Time tsIS(OFF) – 5 20 µs P_9.6.4.8
From DEN falling
edge to IIS = IIS(OFF)
See Figure 36
1)
SENSE Settling Time after tsIS(LC) – 5 20 µs P_9.6.4.3
Load Change from IL = IL19 to
IL = IL20
See Figure 36
1) Not subject to production test - specified by design.

Data Sheet 46 Rev. 1.04

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BTS7002-1EPP
PROFET™+2 12V
Diagnosis

9.6 Electrical Characteristics Diagnosis - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive load connected to the output for testing (unless otherwise specified):
RL = 2.1 Ω

9.6.1 Diagnosis Power Output Stage - 2 mΩ

Table 21 Electrical Characteristics: Diagnosis - 2 mΩ

Parameter Symbol Values Unit Note or Number
Min. Typ. Max. Test Condition
Open Load Output Current IL(OL)_4u 32 91 150 mA IIS = IIS(OL) = 4 µA P_9.7.10.1
at IIS = 4 µA see Figure 32
Current Sense Ratio at kILIS05 -65% 22700 +65% IL05 = 100 mA P_9.7.10.9
IL = IL05
Current Sense Ratio at kILIS09 -65% 22700 +65% IL09 = 450 mA P_9.7.10.13
IL = IL09
Current Sense Ratio at kILIS11 -55% 22700 +55% IL11 = 1 A P_9.7.10.15
IL = IL11
Current Sense Ratio at kILIS15 -40% 22700 +40% IL15 = 4 A P_9.7.10.19
IL = IL15
Current Sense Ratio at kILIS18 -24% 22700 +24% IL18 = 10 A P_9.7.10.22
IL = IL18
Current Sense Ratio at kILIS19 -8% 22700 +8% IL19 = 15 A P_9.7.10.23
IL = IL19
1)
Current Sense Ratio at kILIS20 -8% 22700 +8% P_9.7.10.24
IL = IL20 IL20 = 22 A
1)
SENSE Current Derating ΔkILIS(OL) -30 0 +30 % P_9.7.10.27
with Low Current IL(CAL) = IL09
Calibration IL(CAL)_H = IL11
IL(CAL)_L = IL05
TA(CAL) = 25 °C
1)
SENSE Current Derating ΔkILIS(NOM) -4 0 +4 % P_9.7.10.29
with Nominal Current IL(CAL) = IL19
Calibration IL(CAL)_H = IL20
IL(CAL)_L = IL18
TA(CAL) = 25 °C
1) Not subject to production test - specified by design.

Data Sheet 47 Rev. 1.04

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BTS7002-1EPP
PROFET™+2 12V
Application Information

10 Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.

10.1 Application setup

VBAT
ZWIRE
Optional Optional

CVS CVSGND T1
Logic Supply
RGND

VDD GND VS

ROL
GPIO RIN IN

OUT
GPIO RDEN DEN

COUT0

RPD
PROFET™+2

ZWIRE
DZ2 CVS2 Microcontroller 12V

ADC RADC RIS_PROT IS

VSS
RSENSE

CSENSE DZ1

ZLOAD*
Logic GND

Power GND Optional

Chassis GND
*See Chapter 1 „Potential Applications“
App_1CH_INTDIO_CVG.emf

Figure 37 BTS7002-1EPP Application Diagram

Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.

Data Sheet 48 Rev. 1.04

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BTS7002-1EPP
PROFET™+2 12V
Application Information

10.2 External Components

Table 22 Suggested Component values

Reference Value Purpose
RIN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity
Necessary to switch OFF BTS7002-1EPP output during Loss of Ground
RDEN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity
Necessary to switch OFF BTS7002-1EPP output during Loss of Ground
RPD 47 kΩ Output polarization (pull-down)
Ensures polarization of BTS7002-1EPP outputs to distinguish between
Open Load and Short to VS in OFF Diagnosis
ROL 1.5 kΩ Output polarization (pull-up)
Ensures polarization of BTS7002-1EPP output during Open Load in OFF
diagnosis
COUT 10 nF Protection of BTS7002-1EPP output during ESD events and BCI
T1 BC 807 Switch the battery voltage for Open Load in OFF diagnosis
CVS 100 nF Filtering of voltage spikes on the battery line
CVSGND 47 nF Buffer capacitor for fast transient
See Table 5 (P_4.3.0.7) for the boundary conditions
A placeholder on PCB layout is recommended
DZ2 33 V TVS Diode Transient Voltage Suppressor diode
Protection during Overvoltage and in case of Loss of Battery while driving
an inductive load
CVS2 – Filtering / buffer capacitor located at VBAT connector
RSENSE 1.2 kΩ SENSE resistor
RIS_PROT 4.7 kΩ Protection during Overvoltage, Reverse Polarity, Loss of Ground
Value to be tuned according to microcontroller specifications
DZ1 7 V Z-Diode Protection of microcontroller during Overvoltage
RADC 4.7 kΩ Protection of microcontroller ADC input during Overvoltage, Reverse
Polarity, Loss of Ground
Value to be tuned according to microcontroller specifications
CSENSE 220 pF Sense signal filtering
A time constant (RADC + RIS_PROT) * CSENSE longer than 1 µs is recommended
RGND 47 Ω Protection in case of Overvoltage and Loss of Battery while driving
inductive loads

10.3 Further Application Information

• Please contact us for information regarding the Pin FMEA

• For further information you may contact http://www.infineon.com/

Data Sheet 49 Rev. 1.04

2019-10-15
BTS7002-1EPP
PROFET™+2 12V
Package Outlines

11 Package Outlines

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Figure 38 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline

   
















 

FRSSHU VROGHU PDVN VWHQFLO DSHUWXUHV

$// ',0(16,216 $5( ,1 81,76 00

Figure 39 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil

Data Sheet 50 Rev. 1.04

2019-10-15
BTS7002-1EPP
PROFET™+2 12V
Package Outlines

Green product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

Data Sheet 51 Rev. 1.04

2019-10-15
BTS7002-1EPP
PROFET™+2 12V
Revision History

12 Revision History

Table 23 BTS7002-1EPP - List of changes

Revision Changes
1.04, 2019-10-15 P_6.5.20.1 updated (Typ.: 0.01 µA → 0.1 µA)
P_8.7.10.1, P_8.7.10.7, P_8.7.10.8 updated (added in Note or Test Condition: link to
Figure 24)
P_7.5.10.5 updated (added in Note or Test Condition: see Figure 18)
P_7.5.10.12 updated (added in Note or Test Condition: see Figure 20; deleted unnecessary
space in Symbol: |dVOUT / dt | → |dVOUT / dt|)
P_8.7.10.6 updated (added in Note or Test Condition: see Figure 25)
P_9.7.10.1 updated (added in Note or Test Condition: see Figure 32)
Figure 1, Figure 37 updated
P_4.3.0.7 added
Table 22 updated
Chapter 5.1 updated (added: see Chapter 10 for the complete application setup
overview)
Chapter 9.2 updated (2 V → VDS(OLOFF))
General: updated (ReverSave™ → ReverseON)
1.03, 2019-04-29 Chapter 1 updated ((inserted headline "Product Validation"), (Qualified in accordance
with AEC Q100 grade 1 → Qualified for automotive applications. Product validation
according to AEC-Q100 Grade 1.))
General: updated Product Name (High Current PROFET™ 12V → PROFET™+2 12V)
P_9.7.10.1 updated (Min./Typ./Max.: 62/-/138 mA → 32/91/150 mA)
1.02, 2019-02-05 Figure 9, Figure 10 updated
Page 1: updated (figure product)
Table 22 updated (punctuation)
Chapter 9.3, Chapter 9.3.1 updated (typo)
Page 1: updated (Package PG-TSDSO-14-22 → Package PG-TSDSO-14)
Figure 38 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package
Outline → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline)
Figure 39 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads
and stencil → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and
stencil)
Table 1 updated (Parameter: Minimum Overvoltage protection (TJ = 25 °C) → Minimum
Overvoltage protection (TJ ≥ 25 °C))
Table 1 updated (corrected typo in table Product Summary: IVS(OFF): 1 → 0.9 µA)
Table 1 updated (Symbol: IVS(OFF) → IVS(OFF)_85)
P_6.5.20.1 updated (Symbol: IVS(OFF) → IVS(OFF)_85)
P_6.5.20.2 updated (Symbol: IVS(OFF) → IVS(OFF)_150)
P_9.7.10.27, P_9.7.10.29 updated (Note or Test Condition: formatted physical symbols as
subscript)
1.01, 2018-06-14 Page numbering corrected
Figure Application Diagram, Figure 29, Figure 37 updated
1.00, 2018-05-23 Data Sheet available

Data Sheet 52 Rev. 1.04

2019-10-15
BTS7002-1EPP
PROFET™+2 12V

Table of Contents

Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.1 Power Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.1 PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.2 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Input Pin (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.1 OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.2 ON mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3 OFF_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.4 ON_Diag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.5 Fault mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.1 BTS7002-1EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2.1 Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2.2 Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.3 Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3.1 Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3.2 Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4.1 Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5.1 Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Sheet 53 Rev. 1.04

2019-10-15
BTS7002-1EPP
PROFET™+2 12V

Table of Contents

8 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3.1 Intelligent Latch Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.4 Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4.1 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4.2 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.5 Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.5.1 Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.5.2 Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.6 Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.6.1 Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.7 Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.7.1 Protection Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2 Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2.1 Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2.2 Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3 Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3.1 Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.4 SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.5 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.5.1 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.6 Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.6.1 Diagnosis Power Output Stage - 2 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1 Application setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.2 External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.3 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Data Sheet 54 Rev. 1.04

2019-10-15
Please read the Important Notice and Warnings at the end of this document

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