CS3351 - Digital Principles and Computer Organization

Course Objectives:

1.  CO1 – To make students understand the Combinational circuits.

2.  CO2 – To familiarize with implementation of sequentional logical circuits.
3.  CO3 – make students understand the basic structure and operation of digital computer .
4.  CO4 – To study the design of data path unit and control unit for processor.
5.  CO5 – To understand the concept of various memories and interfacing.

Course Outcomes:

On Completion of the course, the students will be able to:

1. Design combinational logical circuits.

2. .Understand the basics concepts of flipflop and register counter,
3. Understand the basics structure of computers, operations and instructions.
4. Understand pipelined execution and design control unit.
5. Understand the various memory systems and I/O communication.

Introduction:

Digital principles is about designing the combinational and sequential logical circuits.Computer Architecture is about designing and building specialized computers. A
computer system is composed of both hardware and software. It deals with the various memory organizations. The concepts of performance of a computer, Instruction set
types and formats are discussed in this subject.

Prerequisite:

 Knowledge about Binary Number System ,logic gates

 Knowledge about the Architecture and organisation
Learning Resources:

Text Books:

1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
References:

1. V. Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, ―Computer  Organization ― Fifth edition, Mc Graw-Hill Education   India Pvt Ltd, 2014.

2. William Stallings ―Computer Organization and Architecture‖, Seventh Edition, Pearson Education, 2006.

3. Govindarajalu  ― Computer Architecture and Organization, Design Principles and Applications, Second edition. McGraw-Hill Education India Pvt Ltd.2014

Lecture

No./ Topics to do Keywords Session outline Teaching Course Text and Page No. Proposed
Session No. methodology Outcomes Reference date
UNIT–I   COMBINATIONAL LOGIC 
1,2 Combinational Sum-carry-borrow Half, Full adder and subs Chalk and Talk, CO1 T1 135 18.08.22,
tractor PPT 19.08.22
Circuits
3 Karnaugh Map 2 variable-3 Boolean expression for SOP Chalk and Talk    CO1 T1 67 22.08.22
variable-4 variable AND POS
4 Analysis and Design Truth table-k map- Design the combinational Chalk and Talk CO1 T1 136 23.08.22
logical diagram circuits four steps
Procedures
5 Binary Adder, Full adder- LAC Parallel adder, serial adder, Chalk and Talk CO1 T1 155 24.08.22
adder look ahead carry adder
Subtractor
6 Decimal Adder BCD-octal BCD added, binary multiplier Chalk and Talk CO1 T1 160 25.08.22

7 Magnitude a>b, a<b, a=b 1 bit and 2 bit comparator Chalk and Talk CO1 T1 162 26.08.22
Comparator
8 Decoder, Encoder N input,2^n output 2:4 decoder,3:8 decoder and Chalk and Talk CO1 T1 164 27.08.22
and vice versa 4:2 encoder
9 Multiplexers , 1 input,2^n output ,n 8:1 Mux,1:8 mux Chalk and Talk CO1 T1 168 29.08.22
selection lines and
Demultiplexers
vice versa
 

Lecture                

No./Session                
No.
Topics to do Keywords Session outline Teaching Course Text and Page No. Proposed
methodology objectives Reference date
            UNIT II  SYNCHRONOUS SEQUENTIAL LOGIC 
10 Introduction to Clock signals Synchronous and Chalk and Talk CO2 T1 197 30.08.22
asynchronous circuits
Sequential Circuits

        11 Flip-Flops D,T,JK flipflop Operation and design of Chalk and Talk CO2 T1 199 31.08.22
D,T,JK flipflops
        12 operation and Excitation of all Characteristics of JK,T and D Chalk and Talk CO2 T1 199 01.09.22
flipflop FF
excitation tables
13 Triggering of FF EDGE-Level Positive and negative edge Chalk and Talk CO2 T1 203 02.09.22
trigger
14 Analysis and design Analysis-design Design of clocked sequential Chalk and Talk CO2 T1 210 05.09.22
circuits
of clocked
sequential circuits
15 Design Input-output Design moore and mealy Chalk and Talk CO2 T1 221 05.09.22
variation models
Moore/Mealy
models
     16,  17 state minimization, Redundancy state State minimized and assigned Chalk and Talk CO2 T1 233 06.09.22
diagram is designed
state assignment,
circuit
implementation
18 Registers , Counters Shift register- Design Chalk and Talk CO2 T1 253 07.09.22
up/down counter SISO,SIPO,PIPO,PISO and
synchronous counter

Lecture                

No./Session                
No.
Topics to do Keywords Session outline Teaching Course Text and Page No. Proposed
methodology objectives Reference date
                   UNIT III  COMPUTER ORGANIZATION  &  INSTRUCTIONS
19 Basics of a computer   CPU – Memory Components of a Computer Chalk and Talk CO3 T2 24 08.09.22
system Unit – Output Unit
20,21 Evolution,  Ideas, Generations – Different Generations of a Chalk and Talk CO3 T2 34 09.09.22
Technology Design Ideas Computer and Design Ideas
22 Performance, Power wall Execution Time Performance Equation of a Chalk and Talk CO3 T2 45 10.09.22
Computer  System

23 Uniprocessors  to Multiprocessors Advantages of  Chalk and Talk, CO3 T2 49 12.09.22
Multiprocessors Multiprocessor PPT
24 Addressing and addressing Register – Memory Different Addressing modes Chalk and Talk, CO3 T2 67  13.09.22
modes PPT

25 Instructions: Operations  Types of Various  types of Chalk and Talk CO3 T2 77 14.09.22 
and Operands Instructions Instructions including MIPS 
Instructions
26 Representing instructions Representation Representation of  various  Chalk and Talk CO3 T2 81 15.09.22
 types of  Instructions

27 Logical  Operations and Logical  Operators Types and uses of  Logical Chalk and Talk CO3 T2 86 16.09.22
Control Operations operations and Control
Operations

Lecture                

No./Session                
No.
Topics to do Keywords Session outline Teaching Course Text and Page No. Proposed
methodology objectives Reference date
             UNIT IV    THE PROCESSOR 
28 Introduction and  Logic Instruction Set, MIPS Instruction Set Chalk and Talk CO4 T2 121 19.09.22
Design Conventions  Architecture Architecture
20.09.22

        29 Building a Datapath Datapath, Designing the Datapath Chalk and Talk    CO4 T2 136 21.09.22
Functional Unit Elements
22.09.22

      30,  31 A Simple Implementation Implementation MIPS Implementation Chalk and Talk CO4 T2 140 23.09.22
scheme Scheme
24.09.22

32 An Overview of Pipelining Fetch, Decode, Pipelining and Hazards Chalk and Talk, CO4 T2 145 26.09.22
Execute, Store Overview PPT
 33 Pipelined Datapath and Control Pipelined Datapath and Chalk and Talk, CO4 T2 152 27.09.22
Control Control PPT

34 Data Hazards: Forwarding Data, Hazard, Stall Data Hazard and Data  Chalk and Talk CO4 T2 159 28.09.22
versus Stalling Hazard Handling Technique
 
35 Control Hazards Control, Instruction Control  Hazard and Control Chalk and Talk CO4 T2 165 29.09.22
Hazard Handling  Technique
 
36 Exceptions  and  Parallelism Error, Parallel Exceptions  and  Parallelism Chalk and Talk CO4 T2 183 30.09.22 
via Instructions

Lecture

No./ Topics to do Keywords Session outline Teaching Course Text and Page No. Proposed
Session No. methodology objectives Reference date

           UNIT V  MEMORY AND  I/O

37 Memory Hierarchy Primary, Secondary Various Memory  Levels Chalk and Talk CO5 R1  230 3.10.22

38 Memory Chip Organization  Storage, Cell Memory Chip Organization Chalk and Talk, CO5 R1 234 06.10.22
PPT
07.10.22

39.40 Cache Memory Mapping, Cache Cache Memory Types, Chalk and Talk CO5 R1 245 10.10.22
Mapping and Replacement
algorithm 11.10.22
 41 Virtual Memory Page, Address Concept of  Virtual Memory Chalk and Talk, CO5 R1 254 12.10.22
Translation and Address Translation PPT
13.10.22

42 Parallel Bus Architectures, Architecture, Bus Bus Architectures,  Internal Chalk and Talk, CO5 R1 270 14.10.22
Internal Communication Communication PPT
Methodologies Methodologies

43 Serial Bus Architectures Bus Arbitration, Serial Bus Architectures Chalk and Talk CO5 R1 278 17.10.22
Hand Shaking
44,45 Mass storage Tapes,  Disks Various Mass storage Chalk and Talk CO5 R1 321 18.10.22
Devices
19.10.22

CONTENT BEYOND SYLLABUS

46 Memory Hierarchy, Various Memory  Levels, Cache Memory, PPT CO6 Online Resources 20.10.22
Memory Chip Virtual Memory
Organization

Prepared By Approved By Principal