LEC # 10A

MEMORY INTERFACING
With 8088
Sec 10.1 , Sec 10.2 Reference Book

1 Microprocessor 2023 Raafat S Habeeb 11/12/2022

 Memory Terms
 Capacity
 Kbit, Mbit, Gbit ( BYTE or BIT )
 Organization
 Address lines
 Data lines
 Speed / Timing
 Access time
 Write ability
 ROM ( Read only Memory)
 RAM ( Random Access Memory)

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 RAM Variations
 SRAM -Volatile Type

 DRAM –Volatile Type

 NV-RAM

 SRAM – CMOS

 Internal lithium battery

 Control circuitry to monitor Vcc

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 ROM Variations
 Mask Rom

 PROM – OTP ( Programmable Read Only Memory )

 EPROM – UV_EPROM ( Erasable Programmable ROM)

 EEPROM ( Electrical Erasable Programmable ROM)

 Flash memory

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 Memory Chip
A0 I/O0
 8K SRAM A1 I/O1
A2 I/O2
 to be specific: A3 I/O3
A4 I/O4
 8Kx8 bits SRAM A5 I/O5
A6 I/O6
A7 I/O7
A8
A9 6264
A10
A11
A12

OE
WE
CS1
CS2

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 8088 Microprocessor: Minimum Mode
MN / MX AD0
AD1
READY AD2
CLK AD3
RESET AD4 Data bus
AD5
TEST AD6
AD7
HLDA
A8
HOLD A9
NMI A10
A11
Address bus
A12
A13
A14
8088 A15

A16 / S3
A17 / S4
A18 / S5
A19 / S6

SSO

DEN
DT / R
IO / M

RD
WR
ALE
INTR INTA

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 Control Pins: Minimum Mode
 CLK- Clock INPUT : The clock input provides the basic timing
for processor operation and bus control activity.
 MN/MX INPUT : The logic level at this pin decides whether
the processor is to operate in either minimum or maximum mode.
 M/IO – Memory/IO OUTPUT : When it is low, it indicates the
CPU is having an I/O operation, and when it is high, it indicates
that the CPU is having a memory operation. This line becomes
active high in the previous T4 and remains active till final T4 of the
current cycle.
 RD – Read OUTPUT : Active low signal indicates the
peripheral that the processor is performing memory or I/O read
operation.
 WR – Write OUTPUT : Active low indicating that Data on the
bus is being written to memory or I/O device.

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 Control Pins: Minimum Mode

 HOLD – Hold INPUT : Active high input from DMA controller.

Indicates that device requesting to control the local buses.
 HLDA – Hold Acknowledge OUTPUT : Active high o/p signal used
after HOLD. Indicate that CPU allows to the DMA to Use buses.
 DEN – Data Enable OUTPUT : Active low signal indicates the
availability of valid data over the address/data lines. It is used to enable
the transceivers ( bidirectional buffers ) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until
the middle of T4.
 DT/R – Data Transmit/Receive OUTPUT : This output is used to
decide the direction of data flow through the transceivers (bidirectional
buffers). When the processor sends out data, this signal is high and when
the processor is receiving data, this signal is low.

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 Control Pins: Minimum Mode

 ALE – Address Latch Enable OUTPUT : This output signal

indicates the availability of the valid address on the address/data
lines, and is connected to latch enable input of latches.
 INTR - Interrupt Request INPUT : This is a triggered input.
This is sampled during the last clock cycles of each instruction to
determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle.
 INTA – Interrupt Acknowledge OUTPUT : This signal is used as
a read strobe for interrupt acknowledge cycles. i.e. when it goes
low, the processor has accepted the interrupt.
 RESET - INPUT : This input provides a hardware means for
initializing the microprocessor.

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 8088 Microprocessor: Minimum Mode

DEN
DT / R

AD7 - AD0

A15 - A8

8088

A19/S6 - A16/S3

ALE

RD

IO / M

WR

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 8088 Microprocessor: Minimum Mode

DEN
DT / R

AD7 - AD0

A15 - A8

8088

A19/S6 - A16/S3
𝐼𝑂𝑅

ALE 𝐼𝑂𝑊
RD
𝑀𝐸𝑀𝑅
IO / M

WR
𝑀𝐸𝑀𝑊

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 Memory Read Cycle of the 8088

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 Memory Write Cycle of the 8088

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 Bus Demultiplexing
 Address Bus:
 To demultiplex the address from the AD pins, a latch
must be used
 74LS373 (Octal Transparent Latch) is commonly used to
grab the address, two purposes:
1. Latch the address from the 8088 and provide
address to the entire computer
2. To isolate the system address busses from
local address busses, so that other devices can
use system buses without disturbing CPU.

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Bus Demultiplexing
 The processor loads on the address bus (AD0 to AD7 and A8 to A19) the
address to be used, and sets the ALE. Thus the address signals A0 to A7
are latched on the 74LS373.
 On the next clock, AD0 to AD7 lines are used to carry data (D0 to D7).
The DEN enables the buffers of the 74LS245, while the DT/R specifies
the direction (read/write)

D0 Q0 A0 B0
D1 Q1 A1 B1
D2 Q2 A2 B2
D3 Q3 A3 B3
D4 Q4 A4 B4
D5 74LS373 Q5
A5
74LS245 B5
D6 Q6
A6 B6
D7 Q7
A7 B7

OE
E DIR
LE

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 Minimum Mode
A7 - A0 B7 - B0 D7 - D0

DEN E
DT / R DIR 74LS245

AD7 - AD0 D7 - D0 Q7 - Q0 A7 - A0
A15 - A8
GND OE A19 - A16
LE 74LS373

A15 - A8 D7 - D0 Q7 - Q0

GND OE MEMORY
8088 LE 74LS373

A19/S6 - A16/
D7 - D4 Q7 - Q4
S3
D3 - D0 Q3 - Q0

GND OE
ALE LE 74LS373
RD
RD

IO / M

WR
WR
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 Minimum Mode

D7 - D0 D7 - D0

A19 - A0 A19 - A0

Simplified
Drawing of
MEMORY
8088 Minimum
Mode

MEMR RD

MEMW WR
CS

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Interfacing a 1MB Memory to the 8088
Microprocessor

• What are the memory locations ( Address ) of a 1MB

(220 bytes) Memory?
• 00000 h– FFFFF

• In binary:

A19 A0
0000 0000 0000 0000 0000
1111 1111 1111 1111 1111
 Interfacing a 1MB Memory to the 8088 Microprocessor
00000
00001
A19-A0 A19-A0 00002
: :

D7-D0 D7-D0

: :

:
:

MEMR RD
MEMW WR

CS FFFFE
FFFFF

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 Interfacing 512KB Memory to 8088 Microprocessor

• What are the memory locations of a 512KB (219 bytes)

Memory?

• 00000 – 7FFFF

• In binary:

A18 A0
000 0000 0000 0000 0000
111 1111 1111 1111 1111

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 Interfacing a 512KB Memory to the 8088 Microprocessor
8088 What do we do with A19?
A19 00000
00001
A18-A0 A18-A0 00002
: :

D7-D0 D7-D0

MEMR RD : :
MEMW WR 7FFFE
7FFFF
CS

• What happened if A19 is not connected to CS?

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 Interfacing two 512KB Memory to the 8088 Microprocessor

• What are the memory locations of two consecutive 512KB (219

bytes) Memory?

Lower 0000 0000 0000 0000 0000

512 KB
0111 1111 1111 1111 1111
Upper 1000 0000 0000 0000 0000
512 KB
1111 1111 1111 1111 1111

• If A19 outputs a logic “0” the lower memory is enabled (and the upper
memory is disabled) and vice-versa.
 Interfacing two 512KB Memory to the 8088 Microprocessor
8088
A19 00000
00001
A18-A0 A18-A0 00002
: :

D7-D0 D7-D0

MEMR RD : :
MEMW WR 7FFFE
7FFFF
CS

00000
00001
A18-A0 00002
:
D7-D0

RD
WR
7FFFE
7FFFF
CS

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 Full and Partial Decoding

 Full Decoding
 When all of the “useful” address lines are
connected the memory/device to perform selection
 All previous examples are Full Decoding
 Partial Decoding
 When some of the “useful” address lines are
connected the memory/device to perform selection
 Using this type of decoding results into roll-over
addresses

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 Partial Decoding

8088
A19

A18-A0 A18-A0

D7-D0 D7-D0 512KB

MEMR RD
MEMW WR

CS

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 Partial Decoding

• In this example:
– The full decoding circuit has memory
physical address space 00000-7FFFF
– In partial decoding circuit, each location
of memory has two addresses.
Therefore, the physical address space is
00000-FFFFF

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 Interfacing four 256K Memory Chips to the 8088
Microprocessor
Memory addresses are mapped to:
XX00 0000 0000 0000 0000
XX11 1111 1111 1111 1111

Where XX is:
00 for chip #1 00000 h- 3FFFFh
01 for chip #2 40000 h- 7FFFFh
10 for chip #3 80000h- BFFFFh
11 for chip #4 C0000h- FFFFFh

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 Interfacing four 256K Memory Chips to the 8088
Microprocessor
A17-A0
A19
D7-D0
A18
RD 256 KB
A17-A0
WR #1
D7-D0 CS

A17-A0
8088 D7-D0
MEMR RD 256 KB
MEMW WR #2
CS

A17-A0
D7-D0
RD 256 KB
WR #3
CS

A17-A0
D7-D0
RD 256 KB
WR #4
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 Interfacing four 256K Memory Chips to the 8088
Microprocessor
A17-A0
A19
D7-D0
A18
RD 256 KB
A17-A0
WR #1
D7-D0 CS

A17-A0
8088 D7-D0
MEMR RD 256 KB
MEMW WR #2
CS

A17-A0
D7-D0
RD 256 KB
WR #3
CS

A17-A0
D7-D0
RD 256 KB
WR #4
CS

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 Interfacing four 256K Memory Chips to the 8088 Microprocessor
A 17 -A 0
A 19
D 7- D0
A 18
RD 256 KB
A 17 -A 0
WR #1

D 7-D 0 CS

A 17 -A 0
8088 D 7- D0

MEMR RD 256 KB
MEMW WR #2
CS

2x4 0 A 17 -A 0
Dec D 7- D0

RD 256 KB
1
WR #3
CS
I1
2
I0 A 17 -A 0
D 7- D0

RD 256 KB
3
WR #4

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 Interfacing 128
8K Memory Chips to
the 8088 P

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 Interfacing four 256K Memory Chips to the 8088
Microprocessor
A 17 -A 0
A 19
D 7- D0
A 18
RD 256 KB
A 17 -A 0
WR #1

D 7-D 0 CS

A 17 -A 0
8088 D 7- D0

MEMR RD 256 KB
MEMW WR #2
CS

2x4 A 17 -A 0
0
Dec D 7- D0

RD 256 KB
1
WR #3
CS
I1
2
I0 A 17 -A 0
D 7- D0

RD 256 KB
3
WR #4
CS
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Microprocessor 2023 Raafat S Habeeb
 A12
:
A0
A19 D7
8KB
A18 :

Interfacing 128 A17

A16
D0
RD
#128

A15 WR

8K Memory A14
A13
CS

A12
Chips to the :
A0
:
8088 P
D7
:
D0

8088
MEMR
MEMW :
Minimum
Mode
A12
:
A0
D7
:
8KB
D0 #2
RD
WR
CS

A12
:
A0
D7
:
8KB
D0 #1
RD
WR
CS

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 Problems

• Find the address of the following memory design

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 Problems

• Design a memory interface for the following

memory parts:
• 64 Kbyte RAM located in the beginning of
memory space.
• 32 Kbyte ROM located in the end of memory
space.

35 Microprocessor 2023 Raafat S Habeeb 11/12/2022

 Bus Buffering (Boosting)
 It is essential to examine the DC characteristics of any
devices involved in a microprocessor design, before
connecting anything on the microprocessors pins. Failure
to do so might result in malfunctions or even damages on
some components.

 Why Bus buffering (boosting)?

 When a pulse leaves an IC, it can lose source of its strength,
depending on how far away the receiving IC chip is located
 The more pins a signal is connected to, the stronger the signal must
be to drive them all
 Bus buffering is nothing more than boosting the signals traveling on
the busses. Commonly used 74LS244, 74LS245
 Signals provided by the CPU need boosting since 8086/88 is a
CMOS chip and MOS has a much lower driving capability than that of
TTL

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Bus Buffering
The 74LS373 and the 74LS245 are used to
demultiplex the AD0 to AD7 lines. They also
provide the necessary buffering for the A0 to
A7 and the D0 to D7 lines.

The rest of the address lines (A8 to A15) as

well as control lines (RD, WR, and IO/M) need
to be buffered using the 74LS244 octal buffer.

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