International Conference on Computer & Communication Technology (ICCCT)-2011

CORDIC Based Implementation of Fast

Fourier Transform
Pooja Choudhary Dr. Abhijit Karmakar
M.Tech, Banasthali University Scientist –EII (IC Design Group)
Banasthali, Tonk, India CEERI,Pilani-333031,India
Email :- [email protected] Email:- [email protected]

Abstract – CORDIC is an iterative arithmetic computing Cooley Tukey is most prominent in FFT and radix-2, radix-
algorithm capable of evaluating various elementary functions 4 are more use because of its simple structure based on
using a unified shift-and-add operations. Fast Fourier Transform butterfly and good use of periodicity and symmetry
processor based on CORDIC is implemented. The key ideas are property. There are two methods for computing FFT are
replacing the sine and cosine twiddle factors in conventional FFT when input sequence is broken into even and odd sequences
architecture by iterative CORDIC rotations which allow the called Decimation in Frequency.
reduction in read-only memory (ROM). The use of CORDIC in
FFT results in the elimination of multipliers, saves area, power
In FFT processor, butterfly is the basic unit and using
and cost CORDIC finds many applications as it providing a
simpler way of computing complex multiplications. It is proved single butterfly whole computation is done. So, main
that CORDIC is most suitable alternative. concern is on butterfly unit. It comprises of Twiddle factor
and complex addition and multiplication. FFT
Keywords - Butterfly, CORDIC, DFT, FFT, ROM, Twiddle requires   N computations. Using CORDIC in place of
factor. twiddle factor can solve the problem of complex
multiplication. It can also solve the problem of space
required on ROM and also time required to perform the
I. INTRODUCTION
operation.
With increasing use of technology in every field the need
for digital signal processing has increased. Nowadays, there In year 2009 CORDIC completed its 50 year of invention;
is more demand for reduced cost, area, power and increased by J.VOLDER [5]. This iterative process require only
speed; which motivated the development of more simple add and shift operation and can perform many
sophisticated DSP algorithms to enhance the performance. computing tasks such as trigonometry, logarithmic,
Discrete Fourier Transform is most power tool for exponential, hyperbolic, real and complex multiplication,
performing DSP. DFT decomposes a sequence into smaller eigen value estimation, square root, division, singular value
sequences and in this computation it requires   arithmetic decomposition and many more. With all these
operations. It has a slow and complex computation. computations it become unavoidable part of DSP and may
other systems. CORDIC is proposed by J. Volder [6] in

1965 and further generalizes by Walther [7] and refined by
() = ∑

 ()
Householder and many other [8] [9] [10][11][12]. It is the
fastest technique to perform these operations demanded
k = 0, 1, 2... ... N-1 (1) only add-and-shift, and attractive due to its efficient and

low cost implementation of large class of applications.
Where,
=  
In this paper, CORDIC is implemented using 2’s
() is the Discrete Fourier Transform and () is a complement signed fixed point representation. Using
sequence of samples
is called twiddle factor. Due to its CORDIC a specialized hardware FFT Processor is
complexity, Fast Fourier Transform has been proposed by implement using radix-2 DIT algorithm for 8 point. The
Cooley and Tukey [2]. Fast Fourier Transform is a cleaver detailed description and block diagram are given as well. It
trick for obtaining the same result as the DFT, using less shows that more efficient alternative has been considered
computation time. FFT decomposes the sequence, it follow for replacement of complex multiplier. Simulation results
the rule of divide and conquer. Plenty of work has been are shown for CORDIC.
done on FFT like radix-2, radix-4, split [3], Hybrid [4]. But

978-1-4577-1386-611$26.00©2011 IEEE 550

 International Conference on Computer & Communication Technology (ICCCT)-2011

The organization of the rest of paper is as follows. In

section II, an overview for FFT and derivation of radix-2
DIT. Followed by CORDIC computations and
implementation in section III. In section IV, there
description of CORDIC based twiddle factor in butterfly
unit. The design and implementation of 8-point radix-2
butterfly unit of FFT processor described in section V. At
last simulation results and conclusion are given in
sectionVI.

II. FAST FOURIER TRANSFORM Fig. 1 shows the basic Butterfly structure.

An efficient algorithm proposed by Cooley-Tukey is the Butterfly produces two complex outputs that become
fastest version of DFT. In this paper, implementation of butterfly inputs in the next stage. In each stage number of
radix-2 DIT algorithm for FFT computations is presented butterfly remains same (N/2), the number of input and
[13]. output remains the same from one stage to next. An “in-
place” implementation writes each butterfly output over the
A Discrete Fourier Transform X (k), 0 ≤ k ≤ N-1 is defined
next butterfly input. In an “in-place” implementation, the
in (1) can be computed using FFT. This N point DFT is
FFT results in same memory range as original inputs.
broken into two N/2 point DFT groups of even and odd.
Thus FFT uses a recursive algorithm. In this implementation the output is in normal sequence but
  input is bit reversed. 8-point radix-2 FFT is shown in fig. 2.
 
  In fig.3 radix-2 butterfly computation element diagram is
() ()
() =  ()
+  (2 + 1)
shown. It comprises of sine generator, multipliers, and
  addition/subtraction units. FFT require ROM and complex
multipliers for computation. Due to which FFT become
(2) more complex for computation [14].
 
 
 

() =  ()
 +
  (2 + 1)

 

(3)
 
   
() = ∑  ()
/ +
 ∑

(2 + 1)
/ (4)

() = !() +
 "() k=0,1........N/2 (5)

Thus, A(k) and B(k) are obtained by decimating x(n) by a

factor of 2, and resulting FFT algorithm is called a
decimation-in-time algorithm.
 is called the twiddle
factor. Fig 3 shows the butterfly computation block diagram.

$ $

 =  #$/
= %& − ' &*

Since A(k) and B(k) are periodic, with period N/2, then
A(k+ N/2) = A(k) and B(k + N/2) = B(k) and the factor

/

= −
 .

( + /2 ) = !() −

 "() k=0,1.......N/2 (6)

Basic computation of FFT is called Butterfly computation

shown in fig. 1.

Fig.2 8-point radix-2 DIT FFT.

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 International Conference on Computer & Communication Technology (ICCCT)-2011

From fig 3 we come to know that Butterfly unit require 85 = 95 − 65 arctan(2 5 ) (13)
multipliers, addition and subtraction unit for computation
and this acquire large area, cost and power. To cut down The generalized CORDIC algorithm for iteration can be
cost, area and power and to increase speed, use of CORDIC written as
in butterfly unit is an unavoidable demand of today. 5 = 5 − : 45 65 2 5
75 = 45 + 5 65 2 5
85 = 95 − 65 ;5 (14)

III.CORDIC – OVERVIEW
Where, the parameter : can assume one of the three values:
The CORDIC algorithm proposed in 1959 with an : =1 Circular rotations ;5 = <-12-i
objective to build a real-time navigational computer for use := 0 linear rotate ;5 =2-i
on aircrafts but later extended in 1971. CORDIC stands for := -1 hyperbolic rotation ;5 = <-12-i
CO-ordinate Rotation Digital Computer. The operations on
computer that are cheapest and fastest to perform are (A)
addition and subtraction, (B) comparing numbers to see −1; *A 9 < 0
di = ?
which is larger or smaller, (C) storing and retrieving +1; *A 9 ≥ 0
numbers from memory, and (D) shifting the binary point.
CORDIC, thus uses operations (A)–(D) to evaluate
functions. The heart of the algorithm is a series of cleverly
performed rotations. The CORDIC algorithm provides an IMPLEMENTATION OF CORDIC
efficient means of computing functions by rotating a vector
through some angle. There are two modes of operation There are number of ways to implement CORDIC. Here
rotation and vectoring. If vector v is rotated by an angle ∅ Iterative CORDIC structure is used. The hardware
as shown in fig.4 having coordinates (x, y) then a new implementation of CORDIC algorithm is shown in fig. 5 it
vector v ' can be obtained with coordinates (x', y') where x' requires x, y, z three registers, a look up table to store
and y' can be obtained using x, y and ∅ by the following values of ;5 , two shifter unit and add/subtract unit. The
method called rotation mode and in vectoring mode look up table is stored in ROM of memory.[16]
coordinate component of a vector are given [15].

 3 = %&∅ + 4&*∅ (7)

4 3 = &*∅ − 4%&∅ (8)

Fig. 5. Block diagram of CORDIC.

Fig. 4. Rotation of a vector by angle ∅.
Hardware implementation of this algorithm is based on data
path with adders, shifters, registers and Read Only Memory
Rearranging the equation (7) and (8) (containing a number of pre-computed constant factors).
Controller enables realization of all functions with the same
x' cos (∅)[x y. tan(∅  data path structure. The main computation algorithms
y' cos (∅)[ y x.tan∅)] (10) consist of a series of shift operations, and additions or
subtractions. At each clock cycle the controller determines
Putting tan (∅) 2i and ki cos (arc tan (2-i)) is the scaling by how many bits the shift operation should execute and
factor what operation (addition or subtraction) should take place.
5 = 5 [5 − 45 65 2 5 ] (11)
75 = 5 [45 + 5 65 2 5 ] (12) Initial conditions for computation of sine/cosine are:-
x0 = 1 / k y 0 = 0
di 
depends n the direction of each rotation and
angle accumulator

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 International Conference on Computer & Communication Technology (ICCCT)-2011

Where k =1.646760258 2. Low complexity scaling: when elementary angle is

Z= angle sufficiently small and rotation is in one direction
[5]
 
Hardware description language VHDL is used for  (5)
2 5 L H5 I
programming. RTL level programming is implemented and H 4 I = J K 1 5− 2 (5) 45

5M
2 1−2
it validates the architecture.
And wi+1 = wi – 2-i.
IV. CORDIC BASED BUTTERFLY UNIT
3. By using simple maths, rotating two CORDIC
In FFT processor CORDIC is used to simplify the twiddle module side by side one with angle (∅ + O) and
factor. One of the key advantages is the reduction of the second with angle (∅ − O) and O = cos-1(1/K).
twiddle factor memories. Having results for both the CORDIC module as
x1, y1 for first and x2, y2 for second.
$ $ X= (x1 + x2)/2

=  #$/
= %& − ' &*


Y= (y1 +y2)/2. This compensates the factor.
4. Compensated CORDIC algorithm proposed by
Let, Q be a complex number
Despain [18].
Q = bR + jbI (15)
Xi+1 = xi + bixi2-i+1+ai yi.2-i+1
When Q multiplied by twiddle factor, we get Yi+1= yi + biyi2-i+1+ai xi.2-i+1
Zi+1 = zi – ai ctn-1 [bi +ai]
Q
 = (bR+jbI) x (%&
$
− ' &*
$
) (16) The advantage of this is that it requires 2-i+1 twice but


computed only once.
$ $
Q
 = (bR cos E F +bI sin ( )) + IMPLEMENTATION

$ $
j (bI cos ( ) − bR sin ( )) (17) FFT is consists of processing unit and the routing unit.

Processing unit is for computation of equations and this

implementation of FFT includes complex multiplication
By comparing the equation (7) and (8) and equation and ROM for storage of twiddle factor. For large point FFT
(18).We came to know that the real and imaginary part of ROM is large and consumes a lot of power. So, we replace
equation (17) represents circular rotation operation by this processing unit with CORDIC and few post processing
angle2G/. The CORDIC is well known for performing steps. Routing unit is for data recirculation and
such rotations. We can write management purpose [17].
$ $
Xi = (bR cos E F +bI sin ( ) (18) Our main emphasis will be on processing unit in this paper.

$ $
Yi = (bI cos ( ) − bR sin ( ) (19) In CORDIC processor the real and imaginary parts of X (k)

Where one is real part and another is imaginary part. is taken as the initial values for x and y.
The CORDIC equations can be written for radix-2 is:-

5 = 5 − : 45 65 2 5
75 = 45 + 5 65 2 5
85 = 95 − 65 ;5 (20)

Initial conditions set are:-

X0 = a
Y0 = b
Z0 = 2πkn/N
Scaling factor K is independent and compensated. In radix-
2 it is constant K= 1.6475.

Compensation techniques:- Fig.6 Processing unit-detailed diagram.

1. The most direct one is multiplying the final output By the help of CORDIC algorithm the exponential factor is
with 1/K. K-1 is constant for radix-2. realized by sine and cosine operations.
$ $
X = (bR cos E F +bI sin ( )

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 International Conference on Computer & Communication Technology (ICCCT)-2011

$ $
Y = (bI cos ( ) − bR sin ( )

A further processing is required to compute butterfly as

shown in fig 4.
aI’ = a I + X bI ’ = a I – X (21)
aR’ = a R + Y bR ’ = a R – Y

In order to expand the range of the processor from 0 to G

then at initial stage rotate the angle by G/2 whose
associated rotation is greater. The expression will be

bR’ = -bI
bI’ = bR

In FFT implementation angles are known before than there

is no need of evaluating the z, the angles can be stored in
ROM [19].

By, using CORDIC we can implement n point FFT. For

simplicity, in this paper only 8 point radix-2 FFT is
considered shown in fig. 7 and by help of simple maths
FFT Processor is modified and simulated. Table 1 FPGA utilization report.

Fig 7. 8 point radix-2 FFT based on CORDIC.

V. CONCLUSION AND SIMULATION RESULTS Fig.9 the simulation result for CORDIC based FFT processor

Simulation results:

Fig.10 the two character printed on hyperterminal through UART

Fig.8 the simulation results of CORDIC.

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 International Conference on Computer & Communication Technology (ICCCT)-2011

Conclusion [12] J. Duprat and J.M. Muller, “The CORDIC Algorithm:

In this paper, described the method to efficiently compute New results for fast VLSI implementation,” IEEE Trans.
CORDIC algorithm and its implementation using hardware Computers, vol.42, no. 2, pp.168-178, feb 1993.
description language and on Spartan 3E kit through UART. [13] Alan Oppenheim, Schafer, Buck Discrete-Time Signal
CORDIC is used to implement FFT, DCT, DHT, DIF. Then Processing, second edition, Prentice Hall, 2000.
derived FFT with the help of a Specialized Hardware [14] Steven M.Currie, “Implementation of a single
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for FFT and proved boon to the technology. Programmable Gate Arrays (FPGA’98), pp191-200,
February 1998.
Acknowledgment [17] Roberto Sarmiento, Valentin de Armas, Roberto Espr-
Chain, Jose F. Lopez, “A CORDIC processor for FFT
This work is carried out at Centre Electronics Engineering Computation and its Implementation Using Gallium
and Research Institute, Pilani and would like to thank all Arsenide Technology”, IEEE Trans.onn very large scale
the members of IC Design Group. integration (VLSI) systems, vol. 6, pp.18-29, march 1998.
[18] Despain. A.M., “Fourier transform computers using
CORDIC iterations”, IEEE Trans. On computers, volc-23,
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