Low Power, Low Area and High Efficiency

Full Adder Using XOR-XNOR Cell

Badri Sai Hemanth,
MTech(Microelectronics)
220942029
Under the guidance of Dr M Sathish Kumar

Department of Electronics & Communications

MIT, Manipal
Contents
1) Introduction
2) Literature Survey & research gap.
3) Problem Statement
4) Objective
5) Methodologies
6) Existing Design.
7) Tools required.
8) References.
Introduction
• The Adder is a fundamental unit of most used arithmetic units such as multipliers
which are the major building blocks of the data and control paths.
• Since these units controls one third of microprocessors performances. The
optimisation of some of circuit parameters such as power delay, performance of
the adder can result in high performance of the processors.
• This Project mainly focus on optimisation of the below circuit parameters.
1. Power delay product (PDP) which provides the efficiency and power
consumption of the system.
2. Total number of transistors used to build the system provides area
optimization.
Literature Survey
J. Kandpal, A. Tomar, M. Agarwal and K. K. Sharma, "High-Speed Hybrid-
Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell," in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6,
pp. 1413-1422, June 2020:
This paper proposed the building of the basic digital circuits such as full adders and
cascade adders using full swing XOR-XNOR cells. The paper discusses on the
various types of logics available in the existing systems and plotted the differences
such as area and efficiency. The proposed design of XOR-XNOR logic will help in
removing the dependency of inverters in pass transistor and transmission gates
logic. The proposed XOR-XNOR logic was implemented to develop 4 types of full
adders and calculated efficiency in cascaded stage.
Research Gap: The Proposed design has more transistors near to 20 so the Power
Delay Product will be more and so the power consumption.
Proposal: The proposed design can be further improved by reducing the number of
transistors to get more performance and area optimization.
Literature Survey
M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam, "Design of a
Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation," in IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 8, pp.
1464-1468, Aug. 2020.:
This paper proposed a 1-bit full adder design with XOR gate using hybrid of pass
transistor, transmission gate and CCMOS logic. The Carry generation unit was
designed using And-Or gates with pass transistors and transmission gate logic. The
sum generation unit was designed using a CCMOS and pass transistor logic. This
paper also discusses the results obtained for various voltages tested in cadence
virtuoso tool which can be helpful for research.
Research Gap: The Proposed full adder circuit uses 19 transistors and 3 inverters,
which has comparatively more area compared to any other models discussed above.
Proposal: Instead of XOR and CCMOS we can use XOR-XNOR gate combinations
with pass transistor logic which will help in reducing area.
Literature Survey
H. Naseri and S. Timarchi, "Low-Power and Fast Full Adder by Exploring New XOR
and XNOR Gates," in IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 26, no. 8, pp. 1481-1493, Aug. 2018:
This paper proposed the implementation of full adder circuits using non full swing XOR-
XNOR gates. The Paper mainly concentrated on designing low power circuit using pass
transistor and transmission gate logics. The proposed full adder circuit is a 6-transistor
circuit which has low power delay product (PDP). The number of transistors was less
compared to referred circuits hence overall power consumption was reduced and the overall
propagation delay between the gates was less and hence PDP will be reduced. Though the
circuit provides the low power and less area with respect to transistors, the circuit uses a
NOT gate which was large compared to MOS transistors.
Research Gap: Due to the large NOT gate the overall area of the full adder was more and
hence less efficient.
Proposal: The circuit can be modified such that the NOT gate can be replaced with
transistors.
Literature Survey
U. P. Anagha and P. Pramod, "Power and area efficient carry select
adder," 2015 IEEE Recent Advances in Intelligent Computational Systems
(RAICS), 2015, pp. 17-20:
This paper proposed carry select look ahead adder with a better area optimized way.
The paper calculated area based on And-Or-Inverter (AOI) implementation. The
Paper discussed the existing carry look ahead adder and its blocks and methodology.
The Proposed methodology reduces the usage of one carry generator by directly
operating carry select block based on carry in. Since one carry generator was
reduced 2 And – 1 Or – 2 Inverters are reduced and so area was reduced.
Research Gap: Even though overall area of proposed model was less compared to
existing carry look ahead select adder it was using larger gates such as inverters,
And gates.
Proposal: The implementation of Half adder and carry generators using optimized
XOR gates of pass transistor logic will even help in area optimization.
Literature Survey
P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat,
"Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder
Circuit," in IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 23, no. 10, pp. 2001-2008, Oct. 2015:
This paper proposed the 1-bit full adder design using hybrid CMOS and
transmission gate logic. The Paper also discuss about various logics such as pass
transistor logic, transmission gate logic and their transistor counts, power delay
products. The area of the proposed design was reduced by implementing a hybrid
XNOR logic with CMOS and transmission gates. The carry generation module area
was reduced by using the transmission gate logic with 8 transistors. Since the sum
and carry generator modules area was optimized overall area was optimized and so,
PDP factor.
Literature Survey
Research Gap: A buffer was added in between the inputs and sum and carry
modules to improve the delay which increases power and area.
Proposal: Instead of XNOR gate logic alone we can use XNOR-XOR logic will
help in reducing the use of buffer and delay and efficiency.
Literature Survey
I. Obridko and R. Ginosar, "Minimal Energy Asynchronous Dynamic Adders,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14,
no. 9, pp. 1043-1047, Sept. 2006:
This paper has proposed design of an adder based on the dynamic MOS transistors
and pass transistor logic. When the input of the dynamic was low the adder will do
the sum operation and when it is high adder will work as carry generator. The
Dynamic logic will provide less power dissipation and energy conservation.
Literature Survey
Research Gap: The Proposed Dynamic logic suffers from many issues like charge
sharing, leakage, cascading issues. To overcome the issues the transistor counts will
be increased rapidly and have many inverters. Due to this the area will be more and
has more delay factor.
Proposal: Even though the Dynamic logic have good power dissipation, the other
parameters such as area and delay were more compared to static adders. The static
MOS will help in overcoming the issues.
Literature Survey
S.no Author Summary Research gap Proposal
1 J. Kandpal, A. Design of Full adder The number of transistors The number of
Tomar, M. Agarwal using Full Swing XOR- on input and output path transistors can be
and K. K. Sharma XNOR Cells was more. Total number of further reduced.
(2020) transistors is 20.

2 M. Hasan, M. J. Design of Full adder Only XOR logic is used and The use of XOR-
Hossein, M. using XOR and CCMOS number of transistors is 25. XNOR logic can
Hossain, H. U. logic reduce the use of
Zaman and S. Islam inverters.
(2020)
3 H. Naseri and S. Design of full adder The Circuit uses several The NOT gates can
Timarchi (2018) using XOR-XNOR inverters gates which are be replaced with
without Full Swing. large compared to MOS. appropriate design
changes
Literature Survey
S.no Author Summary Research gap Proposal
4 U. P. Anagha and P. Design of Less area carry The circuit consists of many Use of proposed 1
Pramod (2015) look ahead(CLA) adder basic gates like AND, OR, bit adder can help in
by reducing a carry NOT which consumes more achieving high
generator area speed CLA.

5 P. Bhattacharyya, B. Design of low power full The circuit uses buffers to The use of XOR-
Kundu, S. Ghosh, V. adder using CCMOS and improve delay which XNOR logic will
Kumar and A. transmission gate logic increases area and power. eliminate buffer
Dandapat (2015) requirement.
6 I. Obridko and R. Design of Low power The Dynamic logic itself Use of any static
Ginosar (2006) Full adder using dynamic suffers from many CMOS logic of pass
CMOS Logic disadvantages so the transistor logic.
modifications to overcome
them increases the delay of
circuit
Problem Statement
To propose a design to optimize the system or circuit parameters such as power,
area, speed, and efficiency for better results over the existing designs. Implementing
the proposed algorithm to the existing modules/ systems and compare the results for
better optimization results.
Objective
• The proposed design focus on reducing the number of transistors of the circuit
compared to existing circuit and validate the results.

• Minimizing the Transistor along the input and output path which will reduce the
delay between the signal transmission and output which will reduce the effect of
signal lost.

• If the circuit has less transistors and nets the power dissipation will be reduced and
so power delay product.

• The power delay product reduction results in high efficiency.

Methodology
The adder was divided in to three modules.

1) XOR-XNOR cell: The transistors are placed and sized to achieve required
optimised parameters.

2) Sum Generator: The number of transistors was reduced from 6 to 2 using pass
transistor logic with approximate passing of control and input signals.

3) Carry Generator: The number of transistors was reduced from 4 to 3 using

CMOS logic.
Existing Design
The Existing Design was implemented using complementary Pass Transistor Logic
for XOR-XNOR cells. Using the XOR-XNOR Cells the full adder was created with
transmission gate logic.
Existing Circuit Parameters
Power consumption and delay for full adder circuits of existing design.
Full Adder Circuits No: of Transistors Delay(ps) Power(uW) PDP

J. Kandpal (2020) [I] 20 41.45 25.8 1070.7

Hossein, M [2] 22 65.7 11.35 737.7

H. Naseri [3] 22 55.8 26.7 1489.86

P. Bhattacharyya [5] 16 65.59 22.6 1482.23

Tools/ Applications required
• Cadence – Virtuoso (90 nm technology)
References
[1]. J. Kandpal, A. Tomar, M. Agarwal and K. K. Sharma, "High-Speed Hybrid-
Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell," in IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp.
1413-1422, June 2020.
[2]. M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam, "Design of a
Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation," in IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 8, pp. 1464-
1468, Aug. 2020
[3]. H. Naseri and S. Timarchi, "Low-Power and Fast Full Adder by Exploring New
XOR and XNOR Gates," in IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol. 26, no. 8, pp. 1481-1493, Aug. 2018.
[4]. U. P. Anagha and P. Pramod, "Power and area efficient carry select adder," 2015
IEEE Recent Advances in Intelligent Computational Systems (RAICS), 2015, pp.
17-20
References
[5]. P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat,
"Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder
Circuit," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.
23, no. 10, pp. 2001-2008, Oct. 2015.
[6]. I. Obridko and R. Ginosar, "Minimal Energy Asynchronous Dynamic Adders,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no.
9, pp. 1043-1047, Sept. 2006.
Thank you