A Novel High Integration-Density TFT-CMOS Inverter with Vertical Structure

for Low Power Application

Min-Yan Lin*, Jyi-Tsong Lin, and You-Ren Lu

Department of Electrical Engineering, National Sun Yat-Sen University

70 Lien-Hai Rd., Kaohsiung 80424, Taiwan, R.O.C.
[email protected]

Abstract was deposited and planarized by chemical mechanical polishing

(CMP), and SiN (50 nm) deposition were formed as hard mask,
In this paper, a novel vertical-like TFT-CMOS inverter which are shown in Fig. 2(c).
with simple process and high integration density is
proposed, which is composed of a pseudo-planar CMOS.
Two compared devices are also designed for comparison,
namely, the vertical complementary metal-oxide-
semiconductor (VCMOS) and planar complementary
metal-oxide-semiconductor (PCMOS). According to
simulation results, the source overlap region is used to
obtain a high drain saturation current, the drain underlap
region is used to obtain a low Ioff, and the BOI is used to
reduce the drain off-state current. we find out that the
proposed approach achieves a 59.5% area reduction and
signicant shortening of wiring distance between the active
devices when compared with existing planar CMOS
technology.

1. Introduction
(a)
The conventional planar complementary
metal–oxide–semiconductor (CMOS) scaling has reached its
scaling limits; therefore, new device architectures are needed to
continue/maintain the performance gain of the CMOS. A
vertical MOSFETs exploit the vertical channel to achieve the
higher performances compared with the conventional planar
MOSFETs [1], [2]. Owing to its importance in the nano scale
regime and challenges in developing technologies, there is a
strong need for evaluating circuit performance with a realistic
VCMOS architecture including the effects of layout, and device
design. In this paper, the scaling performance (of area, speed,
and power efciency) and the behavioral analysis of a VCMOS
platform are carried out using SILVACO TCAD simulation,
including parasitic effects, and being benchmarked with planar
[3] technologies for the same technology node. The results (b)
show that the new VCMOS offers signicant performance
gains and is a viable solution for future CMOS technologies. Fig. 1. The two schematic structures of (a) new VCMOS
In this paper, we demonstrate a new VCMOS inverter as inverter and (b) PCMOS inverter.
shown in Fig. 1(a), and we compare its preliminary
characteristics with those of the conventional PCMOS inverter In order to form the vertical channel scheme, the SiN and
by using SILVACO TCAD. polysilicon were etched as shown in Fig. 2(d). Third, the silicon
dioxide was deposited, and dry etched to form the oxide spacer
2. Device Structure and Fabrication for protecting the channel regions, After dening the S/D pads
and channel regions, n-type S/D doping was then performed
A new VCMOS inverter processes were simulated by using with arsenic at a tilt angle of 45, whereas p-type S/D doping
SILVACO TCAD. The starting substrates were wafers capped was performed with boron at a tilt angle of 45, respectively,
with a thick oxide layer for this work as shown in Fig. 2(a). as shown in Fig. 2(e). And then, we used the SiN hard mask to
First, the buried oxides (BOI) layer was patterned and etched define the vertical island by continuing anisotropic etching,
(40 nm), as shown in Fig. 2(b). Second, a thick poly-Si layer then, the gate oxide was thermally grown for the vertical

393
sidewall structure. Next, an in situ 40 nm thick poly-Si film was
doped and deposited simultaneously to form p + poly-Si gate
and then patterned by plasma etching technology, as shown in
Fig. 2(f). Finally, the contact formation is performed to form
the connection layer.

Fig. 3. Simulated Id-Vg characteristics of VCMOS inverter and

PCMOS inverter.

(a)

Fig. 2. The main fabrication process of a new VCMOS inverter.

(a) wafers capped with a thick oxide layer, (b) etch oxide, (c)
poly-Si deposition, CMP, and SiN deposition, (d) etch SiN and
poly-Si, (e) S/D formation and (f) gate formation.

3. Results and Discussion

Fig. 3 shows the Id-Vg characteristics of the two CMOS

inverters. It shows the Id-Vg curves of the two CMOS inverters.
It can be observed that the Ioff and Subthreshold Swing (S.S.) of
the VCMOS inverter are improved due to the drain underlap (b)
regions, when compared with the PCMOS inverter.
Fig. 4 shows the transfer curves and the static current of the Fig. 4. (a) transfer curves and (b) static current transfer
two CMOS inverters. We note that the VCMOS output voltage characteristics for the inverters of the new VCMOS inverter and
can reach the full swing. Also, it can be observed that the static conventional PCMOS inerter.
power of the VCMOS inverter is lower than that of the PCMOS
inverter. Fig. 5 compares the tpLH and the tpHL of the two CMOS
technologies. The average delay time of the VCMOS exhibits
36% improved compared with a PCMOS. The extracted static
power, tpLH and tpHL of them are also shown in Table 1.

394
 (a)
Fig. 6. VTC of a new VCMOS inverter at different VDD ranging
from 0.3 to 1 V.

Fig. 7 shows the excellent noise margins of a new VCMOS

inverter which is extracted from the graphical illustration, e.g.,
NML = 0.42 V and NMH = 0.41 V for 1 V of supply voltage. To
rene the analysis, by using the maximum product criterion
(MPC) [5] to evaluate the static noise margins. The maximum
area of the rectangles can be embedded within the VTC loops
of the cross-coupled inverters.

(b)
Fig. 5. Comparison of (a) the tpLH and (b) the tpHL between the
VCMOS and PCMOS inverters.

Table 1. Summary of the characteristics of the inverters.

PCMOS VCMOS
Static Power (μW) 46.4 22.9
tPHL (ps) 2.14 1.07
tPLH (ps) 1.8 1.3
tP (ps) 1.97 1.185
FOM (aJ) 91.4 27 Fig. 7. Transfer static characteristics of the new VCMOS
inverter at three different VDD (0.3, 0.5, and 1 V) by plotting Vin
Note: The tP is calculated as, (tPHL + tPLH )/2, where tPLH and and Vout interchangeably to evaluate the noise margins.
tPHL are propagation delay value of each kind of inverters which
are shown in Fig. 5. Note: The Figure of Merit (FOM) is Fig. 8 shows the transfer curves and the static current of the
calculated from tP and static power product. VCMOS inverter with different LG. We note that the LG = 35
nm of the VCMOS output voltage can reach the full swing.
Fig. 6 shows the voltage transfer characteristics (VTC) for Also, it can be observed that the static power of the LG = 35 nm
an inverter featuring 40-nm-long transistors. Several VDD values is lower than that of the LG = 12 nm.
are considered ranging from 0.3 to 1 V. For each supply voltage
condition, well-behaved VTC is obtained with a low-to-high
output dynamic that reach rail-to-rail supply voltage range.
Also, it does not degrade the high and low logic states due to
the subthreshold leakage currents of both transistors are
sufciently low.

395
 (a) (a)

(b) (b)
Fig. 8. (a) transfer curves and (b) static current transfer Fig. 9. (a) transfer curves and (b) static current transfer
characteristics for the inverters of the new VCMOS inverter characteristics for the inverters of the new VCMOS inverter
with different LG. with different WOX.

Fig. 5 compares the tpLH and the tpHL of the two CMOS Fig. 5 compares the tpLH and the tpHL of the two CMOS
technologies. The average delay time of the VCMOS exhibits technologies. The average delay time of the VCMOS exhibits
36% improved compared with a PCMOS. The extracted static 36% improved compared with a PCMOS. The extracted static
power, tpLH and tpHL of them are also shown in Table 2. power, tpLH and tpHL of them are also shown in Table 3.

Table 2. Summary of the characteristics of the VCMOS Table 3. Summary of the characteristics of the VCMOS
inverter. inverter.
LG (nm) LG = 12 LG = 22 LG = 35 WOX (nm) WOX = 12 WOX = 22 WOX = 28
Static Power (μW) 110 45.4 13.5 Static Power (μW) 9.5 12 13.5
tP (ps) 0.63 0.8 1.475 tP (ps) 16 16.5 1.475
FOM (aJ) 69.3 36.32 19.9 FOM (aJ) 1.5675 19.2 19.9

Fig. 9 shows the transfer curves and the static current of the Fig. 8 shows the layout of the conventional CMOS inverter
VCMOS inverter with different WOX. We note that the different and the new VCMOS inverter which have a shared output
WOX of the VCMOS output voltage can reach the full swing. contact and without gate width modulation. It can effectively
Also, it can be observed that the static power of the WOX = 12 reduce the area about 59.5%. Thus, a low cost, extra-high
nm is lower than that of the WOX = 28 nm. due to the drain on-off speed, and high packing density VCMOS inverter
underlap regions small, when compared with the WOX = 28 nm technology can be easily achieved and applied for use in the
of VCMOS inverter. future ULSI design.

396
 5. Acknowledgement

The authors would like to thank the company- SILVACO.

The authors would also like to thank the National Center for
High-performance Computing (NCHC, Taiwan) for computer
time and facilities.

6. References

[1]. Thomas Schulz, Wolfgang Rösner, Lothar Risch, Adam

Korbel, and Ulrich Langmann, “Short-Channel Vertical
Sidewall MOSFETs”, IEEE Trans. Electron Devices, vol.
48, pp. 1783-1788, Aug. 2001.
[2]. M. Kittler, F. Schwierz and D. Schipanski, “Scaling of
Vertical and lateral MOSFETS in the deep submicrometer
range”, in Proc. IEEE Int. ICCDCS Conf., pp.
D58/1-D58/6, Mar. 2000.
[3]. T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, H. Tigelaar,
M. Van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A.
Shickova, R. Mitsuhashi,I. Satoru, M. Niwa, A.
Rothschild, B. Froment, J. Ramos, A. Nack-aerts, M.
Rosmeulen, S. Brus, C. Vrancken, P. P. Absil, M.
Jurczak, S. Biesemans, and J. A. Kittl, “Ni-based FUSI
Fig. 8. Comparison of the area penalty of (a) a conventional
Gates: CMOS Integration for 45 nm Node and Beyond,”
CMOS inverter and (b) the new VCMOS inverter which have
in IEDM Tech. Dig., pp. 269–273, 2006.
shared output node.
[4]. Y.-C. Eng, J.-T. Lin, and S.-S. Kang, “Anʳ SOI-based
Self-aligned Quasi-SOI MOSFET with -shaped ʳ ʳ ʳ ʳ
4. Conclusions Semiconductor Conductive Layer,” in Proc. IEEE Int. ʳ ʳ ʳ
Conf. Integr. Circuit Des. Technol., pp. 75-78, 2008.
In this paper, we have presented a simulation study for ULSI [5]. J. R. Hauser, “Noise margin criteria for digital logic
applications of a new VCMOS inverter. According to the circuits,” IEEE Trans.Educ., vol. 36, no. 4, pp. 363-368,
simulations, the VCMOS inverter shows better electrical Nov. 1993.
performance than its conventional counterpart. Besides, the
new VCMOS shows the excellent noise margins deduced from
the graphical illustration. Thus, it is believed that the new
VCMOS inverter can become a low power application for high
integration density ULSI applications.

397