Multiplexers

& Demultiplexers
Digital Design. M. Morris Mano
Prof. Imane Aly Saroit Ismail 1 Logic Design
Multiplexers
The multiplexer (also known as Data Selector) is a
combinational circuit that a device that allows one of
several analog or digital input signals to be selected and
directs this input into a single output.
It has 2n data inputs, n selection lines and single output
line. One of these data inputs will be connected to the
output based on the values of selection lines.

Prof. Imane Aly Saroit Ismail 2 Logic Design

Multiplexers
The output depends on the minterms of the Select Lines.

Block Diagram

Prof. Imane Aly Saroit Ismail 3 Logic Design

2x1 Multiplexer
S Y
0 I0
Two inputs: I0, I1
1 I1
One Selector S
Function Table
One Output: Y
S 𝟎 𝟏 Y
0 𝟎 0 I0 If (S=0) Y= 𝟎
1 0 𝟏 I1 If (S=1) Y= 𝟏

Prof. Imane Aly Saroit Ismail 4 Logic Design

2x1 Multiplexer

Block Diagram
Logic Diagram

Prof. Imane Aly Saroit Ismail 5 Logic Design

4x1 Multiplexer
S1 S0 Y
Four inputs: I0, I1, I2, I3
0 0 I0
Two Selectors: S0, S1
0 1 I1
One Output: Y 1 0 I2
1 1 I3
Function Table

Prof. Imane Aly Saroit Ismail 6 Logic Design

4x1 Multiplexer

S1 S0 𝟏 𝟎 𝟎 𝟏 𝟎 𝟏 𝟏 𝟎 𝟐 𝟏 𝟎 𝟑 Y
0 0 𝟎 0 0 0 I0 If ( 𝟏 𝟎 =00) Y= 𝟎
0 1 0 𝟏 0 0 I1 If ( 𝟏 𝟎 =01) Y= 𝟏
1 0 0 0 𝟐 0 I2 If ( 𝟏 𝟎 =01) Y= 𝟐
1 1 0 0 0 𝟑 I3 If ( 𝟏 𝟎 =11) Y= 𝟑

Function Table

Prof. Imane Aly Saroit Ismail 7 Logic Design

4x1 Multiplexer

Block Diagram Logic Diagram

Prof. Imane Aly Saroit Ismail 8 Logic Design

Multiplexer with enable
A multiplexer can have an additional input signal called
the enable which enables or disables the generated
output. So a multiplexer with enable has 2n data inputs,
an enable, n selection lines and a single output line.
In general (active high enable):
If enable=0, all the outputs=0.
If enable=1, the output chooses one of the inputs
according to the select lines.
Prof. Imane Aly Saroit Ismail 9 Logic Design
Multiplexer with enable

Block Diagram

Prof. Imane Aly Saroit Ismail 10 Logic Design

4x1 Multiplexer with enable
E S1 S0 Y
Four inputs: I0, I1, I2, I3 0 x x 0
Two Selectors: S0, S1 1 0 0 I0
Enable Input: E 1 0 1 I1
One Output: Y 1 1 0 I2
1 1 1 I3
Function Table

Prof. Imane Aly Saroit Ismail 11 Logic Design

4x1 Multiplexer
with enable

Block Diagram
Logic Diagram

Prof. Imane Aly Saroit Ismail 12 Logic Design

Multiplexers with three state gates
Another type of multiplexer with enable, is by using
three state buffer.
In general (active high enable):
If enable=0, all the outputs=high impedance.
If enable=1, the output chooses one of the inputs
according to the select lines.

Prof. Imane Aly Saroit Ismail 13 Logic Design

4x1 Multiplexer
with three
state gates

Prof. Imane Aly Saroit Ismail 14 Logic Design

 1
1
1
1
0
0
0
0
E
The first Mux is The first Mux
not working is working
Its enable=0
Its enable=1.
Comparing with

Prof. Imane Aly Saroit Ismail

Comparing with
First MUX
S2, so E =S2’
S2, so E =S2’

The Second Mux The Second Mux

is working is not working

Its enable=1. Its enable=0

Comparing with Comparing with

15
Multiplexers with enable
Second MUX

S2, so E =S2 S2, so E =S2

1
1
1
1
0
0
0
0
S2

1
1
1
1

0
0
0
0
S1

1
1
1
1
0
0

0
0
S0
Building a 8x1 Multiplexer using two 4x1

Logic Design
I1

I7
I6
I5
I4
I3
I2
I0
Building a 8x1 Multiplexer using two 4x1
Multiplexers with enable

Prof. Imane Aly Saroit Ismail 16 Logic Design

Building a 8x1 Multiplexer using two 4x1
Multiplexers and one 2x1 Mux

Prof. Imane Aly Saroit Ismail 17 Logic Design

Building a 8x1 Multiplexer using two 4x1
Multiplexers and one 2x1 Mux
2x1 MUX
First 4x1 MUX Second 4x1 MUX
Inputs are the
Inputs are Inputs are
O/P of the 4x1
I0, I1, I2, I3 I4, I5, I6, I7
S2 S1 S0 MUXs
Select
Selectors Selectors O/P
or
O/P O/P
S1 S0 S1 S0 S2
0 0 0 0 0 I0 0 0 I4 0 I0

O/p of the O/p of the

2nd MUX 1st MUX
0 0 1 0 1 I1 0 1 I5 0 I1
0 1 0 1 0 I2 1 0 I6 0 I2
0 1 1 1 1 I3 1 1 I7 0 I3
1 0 0 0 0 I0 0 0 I4 1 I4
1 0 1 0 1 I1 0 1 I5 1 I5
1 1 0 1 0 I2 1 0 I6 1 I6
1 1 1 1 1 I3 1 1 I7 1 I7
Prof. Imane Aly Saroit Ismail 18 Logic Design
Quadruple Multiplexers
• Many multiplexer circuits can be combined with common
selection inputs to provide multiple-bit(s) selection logic.
• A quadruple (Quad) multiplexer is actually four
multiplexers, with common selectors.

Prof. Imane Aly Saroit Ismail 19 Logic Design

Quad 2x1 Multiplexers
If (Select=0)
Y=A (Yi=Ai)
(Y3=A3, Y2=A2,
Y1=A1, Y0=A0)
If (Select=1)
Y=B (Yi=Bi)
(Y3=B3, Y2=B2,
Y1=B1, Y0=B0)

Prof. Imane Aly Saroit Ismail 20 Logic Design

Using a Multiplexer to build a function
Using a multiplexer, the minterms of a function can be
generated by the selection lines and inputs.
In order to build a function of n inputs: the simplest but
not the best way, is by using a multiplexer with n selection
lines; and 2n data inputs.
The selection lines are the function’ variables. The
multiplexer inputs are either 0 or 1 according to the value
of the function according to the selectors values (in order).
Prof. Imane Aly Saroit Ismail 21 Logic Design
Using a Multiplexer to build a function
Example 1:
Build F(A,B,C,D)=m (1,2,3,8,10,12,13,14,15) using a
16x1 multiplexer.

Prof. Imane Aly Saroit Ismail 22 Logic Design

 A B C D F F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
0 0 0 0 0 0
1

2
Using a Multiplexer to build a function
0 0 0 1 1
0 0 1 0 1
3 0 0 1 1 1
4
Example
0 1 0 3: 0 0
5 0 1 0 1 0
6 Build
0 1 F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
1 0 0 using a 4x1
7
multiplexer.
0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 Note
1 0 1 1 0
that some simple gate(s) may be used in addition
12 to1 this
1 multiplexer.
0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
23
15 1 Prof.1 Imane
1 Aly1Saroit1 Ismail Logic Design
Using a Multiplexer Selectors
A B C D F
to build a function 0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Prof. Imane Aly Saroit Ismail 24 Logic Design

Using a Multiplexer to build a function
Usually, the optimal method to build a function of n inputs,
is by using a multiplexer with n-1 selection lines, and 2n-
1 data inputs.

The selection lines are chosen from the functions’ variables

(usually the first n-1 variables).
The remaining variable is used in the multiplexer input
data: for each combination of the selection variables, the
output is evaluated as a function of the remaining variable.
Prof. Imane Aly Saroit Ismail 25 Logic Design
Using a Multiplexer to build a function
So each data input to the multiplexer either is 0 or 1 or
the remaining variable or the complement of the
remaining variable.
Example 2:
Build F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15) using a 8x1
multiplexer.
Note that only NoT(s) may be used in addition to this
multiplexer.
Prof. Imane Aly Saroit Ismail 26 Logic Design
 A B C D F F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
0 0 0 0 0 0
1

2
Using a Multiplexer to build a function
0 0 0 1 1
0 0 1 0 1
3 0 0 1 1 1
4
Example
0 1 0 3: 0 0
5 0 1 0 1 0
6 Build
0 1 F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
1 0 0 using a 4x1
7
multiplexer.
0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 Note
1 0 1 1 0
that some simple gate(s) may be used in addition
12 to1 this
1 multiplexer.
0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
27
15 1 Prof.1 Imane
1 Aly1Saroit1 Ismail Logic Design
Using a Multiplexer

Used in
Inputs
Selectors
to build a function A B C
0 0 0
D
0
F
0
F=D
0 0 0 1 1
0 0 1 0 1
F=1
0 0 1 1 1
0 1 0 0 0
F=0
0 1 0 1 0
0 1 1 0 0
F=0
0 1 1 1 0
1 0 0 0 1
F=𝐃
1 0 0 1 0
1 0 1 0 1
F=𝐃
1 0 1 1 0
1 1 0 0 1
F=1
1 1 0 1 1
1 1 1 0 1
F=1
1 1 1 1 1

Prof. Imane Aly Saroit Ismail 28 Logic Design

Using a Multiplexer to build a function
In some cases, it is needed to build the function using a
multiplexer with a smaller size than the optimal one.
Some of the function’ variables (usually the first ones)
are used as the selection variables of the multiplexer.
The remaining variables are used in the multiplexer
input data: for each combination of the selection
variables, the output is evaluated as a function of the
remaining variables.
Prof. Imane Aly Saroit Ismail 29 Logic Design
Using a Multiplexer to build a function
Example 3:
Build F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15) using a 4x1
multiplexer.

Note that some simple gate(s) may be used in addition

to this multiplexer.

Prof. Imane Aly Saroit Ismail 30 Logic Design

 A B C D F F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
0 0 0 0 0 0
1

2
Using a Multiplexer to build a function
0 0 0 1 1
0 0 1 0 1
3 0 0 1 1 1
4
Example
0 1 0 3: 0 0
5 0 1 0 1 0
6 Build
0 1 F(A,B,C,D)=m(1,2,3,8,10,12,13,14,15)
1 0 0 using a 4x1
7
multiplexer.
0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 0
10 1 0 1 0 1
11 Note
1 0 1 1 0
that some simple gate(s) may be used in addition
12 to1 this
1 multiplexer.
0 0 1
13 1 1 0 1 1
14 1 1 1 0 1
31
15 1 Prof.1 Imane
1 Aly1Saroit1 Ismail Logic Design
 Used in
Using a Multiplexer Selectors Inputs
A B C D F
to build a function 0 0 0 0 0 D
0 0 0 1 1 C 0 1
F=C+D
0 0 1 0 1 0 1
0 0 1 1 1 1 1 1
0 1 0 0 0
0 1 0 1 0
F=0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
F=𝐃
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
F=1
1 1 1 0 1
1 1 1 1 1

Prof. Imane Aly Saroit Ismail 32 Logic Design

 Example 4:
Having two input A and B, build the following function using
a multiplexer with the optimal size and any other gates you
may need: If (A≠B) then F=0 else F=1.
First method:

Prof. Imane Aly Saroit Ismail 33 Logic Design

Example 4:
Second method:
If (A≠B) then F=0 else F=1.

Prof. Imane Aly Saroit Ismail 34 Logic Design

Example 5:
Having a number of four bits ABCD,
build the following function using a
multiplexer with the optimal size and
any other gates you may need:
If (ABCD is an odd number) then
F=0 else F=1.

Prof. Imane Aly Saroit Ismail 35 Logic Design

Example 6:
A combinational circuit consists of two inputs A,B, two
select lines S1S0 (=S) and an output F defined as follows:
• If (S=0) then
• If (S=1) then F=A+B (Addition)
• If (S=2) then F=A-B
• If (S=3) then
Build F using: a full adder, a 4x1 multiplexer, an XOR and
an inverter.

Prof. Imane Aly Saroit Ismail 36 Logic Design

 37

Prof. Imane Aly Saroit Ismail

Example 6:

Prof. Imane Aly Saroit Ismail 38 Logic Design

Demultiplexers
The demultiplexer is a combinational circuit that
performs the inverse operation of a multiplexer. It has
one input, n selection lines and 2n data outputs.
Based on the values of selection lines, the input is
directed (transmitted) into a single output.

Prof. Imane Aly Saroit Ismail 39 Logic Design

Demultiplexers

Block Diagram

Prof. Imane Aly Saroit Ismail 40 Logic Design

1x4 Demultiplexer
One Input: E S1 S0 D0 D1 D2 D3
0 0 E 0 0 0
Four outputs: D0, D1, D2, D3
0 1 0 E 0 0
Two Selectors: S0, S1 1 0 0 0 E 0
1 1 0 0 0 E

𝟏 𝟎 𝟏 𝟎 Function Table
𝟏 𝟎 𝟏 𝟎

Prof. Imane Aly Saroit Ismail 41 Logic Design

1x 4 Demultiplexer

Block Diagram
Logic Diagram

Prof. Imane Aly Saroit Ismail 42 Logic Design

1x 4 Demultiplexer
It is clear that the logic diagram of the 1x4 Demultiplexer
resembles that of a 2x4 decoder with enable.
2x4 decoder with enable: 2x4 decoder 1x4
Two inputs, Four outputs, with enable demultiplexer

Enable. 2 Inputs 2 Selection

Lines
1x4 demultiplexer: 4 Outputs 4 Outputs
One input, Two Selectors, 1 Enable 1 Input
Four outputs.
Prof. Imane Aly Saroit Ismail 43 Logic Design
Demultiplexers
In general a 1x2n demultiplexer is equivalent to nx2n decoder
with enable.

nx2n decoder with enable 1x2n demultiplexer

n Inputs n Selection Lines
2n Outputs 2nOutputs
1 Enable 1 Input

Prof. Imane Aly Saroit Ismail 44 Logic Design