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Ch02P6 Gate Delays

This document section discusses propagation delay in combinational logic circuits. It defines propagation delay as the time for a change on an input to propagate to the output of a gate. Propagation delay can be different for high-to-low and low-to-high transitions. Real gates have delays that cause transient incorrect output values. Delay models like transport and inertial delay are introduced to model circuit behavior. Fan-out and the number of loads on a gate output affect its propagation delay. Timing diagrams are used to analyze signal timing in logic circuits.

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105 views10 pages

Ch02P6 Gate Delays

This document section discusses propagation delay in combinational logic circuits. It defines propagation delay as the time for a change on an input to propagate to the output of a gate. Propagation delay can be different for high-to-low and low-to-high transitions. Real gates have delays that cause transient incorrect output values. Delay models like transport and inertial delay are introduced to model circuit behavior. Fan-out and the number of loads on a gate output affect its propagation delay. Timing diagrams are used to analyze signal timing in logic circuits.

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خالد الرومي
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Logic and Computer Design

Fundamentals
Chapter 2 – Combinational

Logic Circuits
Part 1 – Gate Circuits and Boolean Equations
2-7 Gate Propagation Delay
 Propagation delay is the time for a change on an
input of a gate to propagate to the output.
 Delay is usually measured at the 50% point with
respect to the H and L output voltage levels.
 High-to-low (tPHL) and low-to-high (tPLH) output
signal changes may have different propagation
delays.
 High-to-low (HL) and low-to-high (LH) transitions
are defined with respect to the output, not the
input.
 An HL input transition causes:
• an LH output transition if the gate inverts and
• an HL output transition if the gate does not invert.
Propagation delay example
 Real gates have real delays
 Example: A' • A = 0?











 Delays cause transient F=1
Chapter 2 - Part 1
Transitions is slow (Fuzzy
edges)







 Propagation delays measured at the
midpoint between the L and H values
Delay Models
 Transport delay - a change in the output in
response to a change on the inputs occurs
after a fixed specified delay
 Inertial delay - similar to transport delay,
except that if the input changes such that
the output is to change twice in a time
interval less than the rejection time, the
output changes do not occur. Models typical
electronic circuit behavior, namely, rejects
narrow “pulses” on the outputs
Delay Model Example
A

B
A B:
No Delay
(ND) a b c d e
Transport
Delay (TD)
Inertial
Delay (ID)

0 2 4 6 8 10 12 14 16 Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns
Fan-out and Delay
 The fan-out loading (a gate’s
gate’s propagation delay output) affects the
 The propagation
following: delay in general effected by the
• fixed inherent delay
• Number of standard loads driven by the output (SL)
• delay per standard load
 Ais simple formula to calculate the propagation delay
• tpd = fixed_delay + delay_per_SL * SL
 Ifcircuit
this effect
takes is
on considered,
different the
values delay of
dependinga gate
on in
the a
circuit load on its output.

Fan-out and Delay
 Example 6-1:( page 324)
• A 4-input NAND gate (with fixed delay = 0.7 and delay per
SL =
with 0.021)
the attached
given numberto the
of inputs
standard of the
loads following gates
representing their
inputs:
 4-input NOR gate—0.8 standard load
 3-input NAND gate—1.0 standard load
Inverter—1.0 standard load
• One realistic equation for tpd for a NAND gate with 4 inputs

is:
tpd = 0.07 + 0.021× SL ns
• For SL = 0.8+1+1, tpd = 0.129 ns,
 How

about wiring delay?
 Assuming that NOT and OR gates
have a delay of 50ps while XOR gates
have a delay of 100ps, complete the
following timing diagram from time 0
to 450ps. Assume the inputs have
been constant for a long time before
0ps.

Chapter 2 - Part 1
Timing diagrams

Chapter 2 - Part 1

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