HB211

PROGRAMMING THE
6800 MICROPROCESSOR
- Bob Southern -
Algonquin College
Ottawa Ont. Canada

A self-instructional workbook
for assembly language and machine code programming
01 the 6800 family of microprocessors and peripherals

Chapter 1 - Binary and Hex Numbers

2- Accumulator Operations

3- Symbolic Addressing

4- Index Register

5- Branching - Assembly Language

6- Branching - Machine Code

7- ACIA - Asynchronous Communications

Interface Adapter

8- PIA - Peripheral Interface Adapter

9- Subroutines

10 - Stack Operations

11 - Interrupt

AppendICes
A ._. . Hex Codes G _._. . C)laraeter Set
B .... ASCII Codes H .._ . Common losll\lctJons
el, C2 Instruction Set ~ ".." Glossary
D . .. Machme Code J 1, J2 Assembler Error Codes
E1. E2 . .. ACIA K OM Instruction
F1. F2 . .. PIA

® MOTOROLA Semiconductor Products 100.

Acknowledgments

- Many people helped make this workbook possible. I would like to thank Peter
Booler, Brian Bradley, Michel Brule and Bill Foster of Algonquin College, and
Don Lindsay of Dynalogic Limited for their advice and comments. I also would
like to thank Lynne Hall who formatted and typed this book. Lastly, I would like
to thank Richard Leir, John Oldfield and John Quarterman for their time in
testing the final version of this book.
- The program on the front cover was written by Don Lindsay of Dynalogic
Limited, Ottawa.
Bob Southern

Disclaimer

- The information contained in this workbook has been carefully checked and is
believed to be correct. However the author and publisher cannot assume
responsibility for errors or omissions or liability for any damages or
consequential damages arising from the use of this workbook.

Copyright © 1977 R.W. Southern

All rights reserved

This book or parts thereof may not

be reproduced in any form without
the permission of the copyright
holder.

9 8 7 6
Printed in Canada
 PROGRAMMING THE 6800 MICROPROCESSOR

ABOUT THIS WORKBOOK

This workbook has one purpose only, to help you to
learn the fundamentals of assembly language and machine code
programming of the 6800 microprocessor and its peripheral
devices. Considerable coverage is given to programming of
input/output devices, an essential part of microprocessor
applications. The ACIA and PIA, each with their various modes
of operations, are explored in detail in both non-interrupt
and interrupt modes. Program design and documentation is
emphasized, enabling others to understand the purpose and
operational details of your programs. Programming hints and
aids are included along with the answers.

FOR WHOM
This workbook was designed primarily for use by students
at the community college level, although it has been successfully
used by at least one capable high school student. Previous
programming experience is not necessary •. Early high school
mathematics is adequate, although mathematical competence beyond
this level is a good predictor of success.

THIS WORKBOOK IS
AVAILABLE FROM

Motorola Semiconductor Products Inc.

Literature Distribution Center
P.O. Box 20924
Phoenix, AZ 85036

Copyright ~ 1977 R. W. Southern.

HOW TO USE THIS WORKBOOK
The programmed notes in this workbook are for your
use at your own pace. Take your time, proceeding to the next
frame when you are satisfied with your answer, after
comparison with the answer given.

To use these notes effectively.

(a) Cover the given answer shown below the
horizontal line following each question.
A data card is very convenient for this.
(b) Read the text material given in the frame.
(c) Write your answer to the question asked.
( d) Compare your answer with the answer given and
when you fully understand any differences, if
any, proceed to the next paragraph.
For practice attempt the following question, after
covering the answer below the line. Write your answer here.

"After answering the question what should the student do?"

_ _------1/
Answers The student should compare his/her answer with the one
given in the workbook and, when satisfied with any
\ .
d1fferences, move on to the next paragraph.
I
 BINARY AND HEX NUMBERS

Before starting please read the left page to get the

most benefit from this programmed instruction workbook.

PRE-TEST

If you are familiar with binary and hexadecimal

arithmetic operations, try the test below. If this is not
familiar to you, turn the page and start the instruction in
frame 1-1.
(a) Calculate 75 - 41, after first converting each decimal
number to its hexadecimal value, then performing the
subtraction. Verify by converting your answer back to
decimal. Write your answer on this page.
(b) Repeat (a) in binary rather than hexa~ecimal. Solutions
are on the next page.

Contd •••
 PRE-TEST
Contd.
(a) Solutions 75 - 41 = 34 (decimal)
2 W 1001011
--.,.-~
2 W 101001
"--w-' "-v-'
2 L1Z
+ 1 4 B 2 ~+ 1 2 9
2 ill + 1 2 L1Q
+ 0
2 U+ 0 2 U+ 0
2 U+ 1 2 U+ 1
2 U+ 0 2 L! + 0
2 L! + 0 o + 1
o+ 1
Calculate -29 then add 75. all in hex.
FF
-~
D6
+-1
D7
+4B
22 hex
o
~::: 16 = 2} "
16 1 = )2
)4 decimal

----------------------------~-------------------------
------

75
= 01001011 (as an 8 bit number)
41 = 00101001
one's complement of 41 = 11010110
+ 1 ---~

two's complement of 41 = 11010111

plus 75 01001011
1 00100010
1
~~
overflow J x 2 = 2
x 25 = E
34 decimal

If your answers are correct skip over to Chapter 2,

otherwise start Chapter 1 instruction on the opposite page.
 1-1
---
The number system most familiar to us is the decimal one,
in which a character has ten possible states, 0 to 9. Adding 1
to 9 results in 10, that is "0" with "1 to carry" or simply
"0 with a carry".
A decimal number 527 means I 7 units = 7
plus 2 tens = 20
plus 5 hundreds = 500
Total = 527
Another decimal concept to note is that 10 3 = 10 x 10 x 10 = 1000.
Similarly 10 2 = 10 x 10, 10 1 = 10 and 10 0 = 1. In fact any value,
raised to the power of zero, equals 1.
The decimal number 527 may then be expressed as,

527 ~10 used with decimal numbers.

~~
~'572 xx1001 = 7 x 1 =
10 = 2 x 10 = 20
7

x 10 2 = 5 x 100 = 500
527
Computers use the binary or two-state number system, that
is each "binary digit" or IJbit" has only two states,' 0 or 1.
Adding 1 to 1 results in 0 with a carry.
The first 3 numbers in the binary number system are 0, 1
and 10. This is seen by adding 0 1
+1 then +1
=1 =10 = 2 (decimal)
In binary add 2 + 1. Your answer should be written above
this line. Then check your answer.

_ _ _--J/
10
+ 1
=11 = 3 (decimal) 11 (binary) : J (decimal)
 --
1-2
Now calculate the binary values for 4, 5 and 6, starting
from the binary equivalent of 3.

11 =J 100 = 4
-----/
101 = 5
U U U
100 =4 101 =5 110 = 6

~ 1
1
+
+
1 =0
c~rry
+ carry
= 0 + carry.

In summary the binary equivalents of 0 to 6 are.

Decimal 0 1 2 3 4 5 6
Binary 0 1 10 11 100 101 110
Leading zeros could be used with the above binary numbers, if
desired, e.g., 110 = 0110 if a 4 bit number is required.
A subscript will be used from now on to denote the number
system, e.g., 1102 is the binary number 110, while 110 10 is the
decimal number 110. When the number system is obvious the
subscript may be omitted.

Interpretation of the binary number 101 iSI

101 ~ 2 used with binarl numbers
x 20 = 1

~: x 21 = 0
x 22 =..2t...
5
 Determine the binary value for 8 and 9. ---
1-3

_ _ _--J/
8 = 1000 To verify 110 =6 110 = 6
9 = 1001 ~ +10 = 2
111 =7 1000 = 8
+ 1
OR + 1
1000 = 8 1001 = 9
~
1001 =9
The second solution is more direct and also demonstrates binary
addition with a carry.

1-4
In the binary number 101, the ri"ght bit carries the
least weight and is therefore called the Least Significant
-
Bit or LSB. The left bit carries the most weight (2 2 in this
case) and is the Most Significant Bit or MSB.
In binary, calculate 6 + 4. Verify by converting
your answer to decimal.

6 = 110
---~/
+4 = 100
10 1010

~l- ~ ~~
= 0
: : = 2
2
a x 2 =0
1 x 23 = 8
10 10 Yes! It works.
 Calculate 8 + 7 in binary. Verify your answer by
....
1-5

converting it back to decimal.

1000 = 8 1111
/
+0111 = 7 20 = 1

lS::
x
1111 = 15 1
x 2 = 2
x 22 = 4
1 x 23 =...L
15
In summary the binary equivalents for a to 15 are:
0000 = a 0100 = 4 1000 = 8 1100 = 12
0001 = 1 0101 = 5 1001 = 9 1101 = lJ
0010 = 2 0110 = 6 1010 = 10 1110 = 14
0011 = 3 0111 = 7 1011 = 11 1111 = 15

1-6
Each bit of a binary number is assigned a bit number
which is the same as its binary exponent as shown below.
--
1011

"t:~~ :~
~(:bit #2
' - bit #J
What is another name for bit #J in this binary number lOll?

MSB or Most Significant Bit.

---_/
The bit number is also useful in determining the weight of each
bit in a binary number, e.g.,

.--bit #@,
110110 5)~same.
~1 x 2~
 1-7
. -
Let's look at a method to convert from decimal to binary.
This method involves successive division of the decimal number
by 2, noting the remainder at each stage. Conversion of 19 10 to
binary is illustrated.
2 l.!2 .---- remainder
r
2 l2+ 1
2 IJ!.+ 1 10011. This is obtained by reading
2 13. + 0 the remainders, bottom to top.
2 l!.+ 0
o+1
To verifyc 10011
0

LS~:
2 = 1
1
2 2=
1 x 2 4 = 16
19 10
Now calculate the binary equivalent of 69 and verify your answer.

2 l§2 1000101 To verify

/
2 (l!±+ 1 ~ :11 xx 22°2 == 1
2 lJ2+ 0 4
2 l§.+ 1 1 x 2 6 = 64
2 ~+ 0 69 10
2 ~+ 0
2 l!.+ 0
o + 1
 Convert 117 10 to binary and verify your answer by
reconverting to decimal.
---
1-8

2 111 7 1110101
20

~:
2 ~+ 1 x = 1
2 (29 + 0 x 22 = 4
2 (14 + 1 x 24 = 16
25
\......,
2 11. + 0 ~ 1 x = 32
2 f1.+ 1 1 x 26 = 64
2 L!.+ 1 117 10
o+ 1 117 10 = 1110101 2
If you are satisfied with your progress proceed to the
next frame. If not, try another number of your own choice now.

Let's look at binary addition now. Add 6 +

and verify your answer by converting it to decimal.
-1-9
7 in binary

-----------------
~ Note that here 1 1 plus
/ +
111 =7 a carry =1 plus a carry.
1101 = 1)10
~'-
------1..~ 1
:~ ~~:
x 23 = ~
=
=
1
4

13 10 13 10 = 1101 2
 1-10
Calculate 5 + 7 in binary and convert your answer to
decimal to verify it.

5 = 101
_ _ _----J/
Z = 111
1210 = 110°2

~~
x 22 = 4 )
) ...... 12 10 = 110°2
x 23 = 8 )

1-11
Values less than 1 can be expressed in binary as in the
example below
1010 binary point
The 1 on the right side of the binary point carries the weighting
of 2- 1 (or 0.5 10 ); since the binary exponent continues to decrease
by 1 for each move to the right. The decimal value is then
x 22 = 4

~1
x 2
x 2°
1
=
=
°1
-1
x 2 = ~
101.1
5·5
Express 110.11 in decimal.

-------'/

The weight of each bit of a binary number can be summarized by.

11111 111
4 ~J ~~;I ~ \,,~
Bina:yexponent -1 -2 -)
orB~t# ~
Binary Value • 24 23 22 21 2° 2- 1 2-2 2-)
Decimal - -.... 16 8 4 2 1 1/2 1/4 1/8
Equivalent
 1-12
We'll return to the binary number system later. Mean-
while let's look at another way to express binary numbers, in
hexadecimal form (hex for short) meaning 16 possible states.
A 4 bit binary number has 16 possible states, 0000 to
1111. Expressing each of the first ten values as a single
character is quite familiar now.
0000 = a 0101 = 5
0001 = 1 0110 = 6
0010 = 2 0111 = 7
0011 = J 1000 = 8
0100 = 4 1001 = 9
The problem now is that we need 6 more characters to
express the next values, 1010 to 1111. Arbitrarily the letters
A to F are assigned to express the missing values, that iSI
A = 1010
B = 1011
C = 1100 The even values, A, C and E can be
D = 1101 remembered by the word "ACE"
E = 1110 Appendix A summarizes the binary
F = 1111
equivalents of the hex values, 0 to F.
Without looking in Appendix A, what is the decimal equivalent of
hex code E?

---_/
 1-13
By breaking up longer binary numbers into groups of 4
bits each we can express them in their hex equivalents e.g.,
the 8 bit binary number
10011010 can be grouped as
1001
"'-y--'
1010
.~

9 A or 9A as the hex equivalent.

Each of the 2 characters can then be a number (0 - 9) or a letter
(A - F). Express 11000011 in hex and mark bit #6 of this
binary number.

,
_ _ _-1/
-bit #6
C3 ~ ~ ---iJ' 11000011
C 3 76543210 4-bit #
Hex codes are very popular with 8 bit microprocessors,
such as the 6800, with 2 hex characters equalling 8 bits or
1 byte. If for some reason only 7 bits are used in a binary
number, a leading zero may be added to fill out the 8 bits, e.g.,
1011101 = ~~!l~
5 D

1-14
Express each of the following binary numbers in hexi
11000101 1111000 111011

_ _ _--.J/
11000101 ~1~10~
~-v--'----.....'
~
C 5 7 8
With a base of 16 the hex number 78 equals,
78 ,-;:- 16 used here for ~ numbers.
l'- : 8 x 16° =
7 x 16
1
= 112
8

120
10
The hex number 78 can be expressed as 78 16 to avoid confusion
with the decimal number 78 10 , a different value.
 1-15
Express each of the following hex numbers in binary
and in decimal.
D4
39
6A

D4 = ~91~ D4
\ ~D4 x= 16
D 4 0
= 4 '1. 212 10
'-. 13 13 x 16 1 = 208)

39=~~
3 9
48
9} 57 10

6A = W10!Q,
6 A 10 10 x 16° = 10} 106
.... 6 x 16 1 = 96 10

1-16
Addition in hex can be challenging, although the problem
does not exist for computers since they work in binary. Hex is
for our convenience in expressing binary numbers.
One solution is to convert to binary, add the numbers
and convert the answer back to hex, possible but not the fastest
way. If we had 8 toes on each foot we could count on our toes
to add. Did you ever consider why our number system has a base
of ten?
The solution proposed is the use of the number line.
until you become more familiar with hex addition.
For example. 9 + 3 = C
start here~"';",--count J to the right to get "C II

o 1 2 J 4 5 678 9 ABC D E F 0 1 2 345 6 7 8 9 ABC D E F

Going beyond F produces a carry
e.g., D + 5 = 12 16 , that is 2 plus a carry.
start~

o 1 2 J 4 5 6 7 8 9 ABC D E Ff F1 2 J 4 5 6 7 8 9 ABC D EF

to o. Contd .•.
 1-16
Contd-
Using this principle show that A + 9 = 13 16-

start
--_--.J/
1 2 3 4 5 6 7 8 9 To verifyl
8 9 ABC DEFt 0 1 2 J 4 A = 1010
9 = 1001
' - carry produced 1 0011
~
in going from 1 3 = 13 16
F to o.

1-17
Now add C + 9 and verify your answer by adding the
decimal equivalents.

start·
_ _ _---..J/
1 2 3 4 5 6 7 8 9~~------5 plus carry = 15 16
ABC D E F 0 1 2 345 6 7
C = 12 10
9 = -2..-
21 10
~---- agrees
 1-18
Now add 7 + D and verify your answer by adding in
decimal.

start 1 2 J 4 5 678 9 ABC D

,~

7 8 9 ABC D E FlO 1 2 3 4 5 6 7 8
~4 plus carry = 14 16
To verify 14 16
,,-~4 x 16° = 4 7 =7
1 x 16 1 = 16 D = 13 10
2010 2010
....... agrees ~
It would have been easier to add 7 to D rather than D to 7.
The answer still is 14 16 •

1-19
Add the hex numbers C and D. Verify your answer.

start
c

c =
D=
4-- agrees ~
 1-20
To add 2 column hex numbers each column is added
separately, as in decimal. If the right column produces a
carry it is added to the left column
e.g.. 2F
ill
42
(: : F ++ J +== 2 plus carry
- ~ 2 1 carry = 4
Add the hex numbers JE + 27.

JE
_ _ _---.J/
+27
65
l: :E + 7 = 5 plus carry
J + 2 + carry
.... = 6

1-21
Add the hex numbers 4D and 25.

72 16 4D
--_----.1/
~
72 16
~. :: D + 5 = 2 plus carry
4 + 2 + carry = 7
To verify we'll convert all data to decimal
4D 16 = 4 x 16 1 + 1J x 16° = 64 + 1) = 77 10 77
25 16 = 2 x 16 1 + 5 x 16 0 = )2 + 5 = J7 10 !-12
1 0
72 16 = 7 x 16 + 2 x 16 = 112 + 2 = 114 10 ~1f~------~"~ 114 10
agrees
 1-22
Subtraction involves moving to the left on the number
line, e.g., D - 5 = 8 as seen below
54 ) 2 1 start
~
o 1 2 ) 4 5 6 7 8 9 ABC D
For the moment we will avoid "borrow" operations.
Calculate B - 7.

4 7 6 5 4 )
---~/ start
o 1 2 ) 4 5 678 9 A B

1-2)

If we are to handle subtraction we have to recognize

negative numbers since 9 - ) is actually 9 + ( - ) . Consider the
number line for an 8 bit binary number. Expressed in hex it
extends from 00 to FF (0 to 255 10 )

t
00 01 02 - - - - - - FD FE FF
However, if 1 is added to FF the result, still using 2 hex
characters (8 bits), is FF
+01
1 00
carry---1{
or 00, the carry being lost as an overflow, outside the 8 bit
limit. The question now asked is "What number, when 1 is
added to it, becomes O?" The answer is -1. By definition
therefore FF = -1. We now reconstruct our number line
-1 0 +1 +2
I I I
,
---- FD FE FF 00 01 02 - -------
What is the value of FD based on this number line?

_ _ _-J/
-) Since FD + ) = 00 (carry is outside the 8 bit limit)
This new number line is called a signed number line since it
permits both positive and negative values.
 1-24
Continuing with the signed number line if the leading
bit (MSB) of the 8 bit number = 1, that is 8 or more for the
first hex character, the number by definition is negative. The
extent of this signed number line is shown below in decimal,
hex and binary.

-..............
~ ~
-127 ~ ~--.......
..- ......--.. __ -... +127
10 10
-128 10 ~ -) -::2 -:'1 - - - + 1 - +2 - +) +12~10 ~
~• II I I l II 1- I
80 81 FD FE FF 00 01 02 OJ 7E 7F
\..10000000 2 01111111
2
J
The extent of this signed number line is then -128 10
to +12710, Based on this number line which of the following
hex values are negative,
7A 94 F2 00 8E CA

-----'/
All except 7A and 00 are negative. having a leading hex
character 8 or larger. If converted to binary all except 7A and
00 would have 1 as a leading bit.
If a larger range is needed for the signed number line
16 bits (2 bytes) could be used, again providing negative
values if the leading bit equals 1. This is sometimes referred
to as a double precision value.
 1-25
To determine the negative value for the hex number 31
is more difficult. A procedure shown below is based on the 2's
complement arithmetic used in binary subtraction.
The procedure then iSI
- Start with the largest possible hex value
(ignoring the sign) -----I...... FF
- then subtract the number .::1! F-1~
using the number line approach CE ABCDEF
~,

- then add 1 F -3 = c
OF now equals -3116 CF
To prove it the sum of OF and 31 should be zero in 2 character
hex format. Prove it.

CF
_ _ _---J/
ill
100
~ =
F + 1 = 0 + carry
C + 3 + carry = 0 + carry
carry, which is ignored as an overflow
CF = -3 116
1-26
Determine the hex value for -5D and prove that it is
correct by adding +5D to it.

/
FF DC B A 9 8 ? 6 5 4 3 2 1 start
-5D 2 J 4 5 678 9 ABC D E F
A2 ~start
.:!:....! In the top row a more direct subtraction
AJ = -5D is seen in that F and D are separated by
2, hence F -D = 2.
To check AJ
+.2Q
carry~
1 00
 1-27
Now calculate -6C and verify it.

-6c = 94 FF
------/ To checkl
-6C ~start 4

U
93

94
9ABCDEF
~start
carry)
E 6c
100

1-28
The "two hex character" value of -) is FD. If 4
characters are used to express -3. prove that -3 = FFFD.

FFFD
----'/
.:..-..J Similarly a 6 character representation would be
1 0000 FFFFFD.
~ carry.
To determine the value of _.) using 4 hex characters, the
procedure is FFFF FFFFFF
=---1 3
FFFC Using 6 hex characters FFFFFC
~ -) equals + 1
= FFFD FFFFFD
Almost all our work will employ 2 hex characters only.
For 6 hex characters () bytes) the signed number line would
extend from 800000 16 (most negative) to 7FFFFF16 (most positive) ..
 1-29
We now have the capability to subtract in hex since
72 -JD is actually 72 +(-JD). Once -3D has been calculated the
hex addition will produce the answer. Try it.

_ _ _ _-----J/'
FF largest hex value To checkl
-JQ If 72 -)D = 35 then 35 + 3D = 72
C2 35
+ 1 plus 1 +3D
CJ = -3D 72
+1£ now add the 72
1 J5 answer
~overflow ignored

Iro verify further we will convert all data to decimal.

72 = 7 x 16 1 + 2 x 16
0
= 112 + 2 = 11410~
0 114 10 -61 10 = 5)10
3D = 3 x 16 1 + 13 x 16 = 48 + 13 = 61 10 ~
1 0 ~agrees
35 = 3 x 16 + 5 x 16 = 48 + 5 = 53 10
 1-;0
Let's try one more subtraction. Calculate E; -DC.

FF
-----/
E; is already a negative number FF
-DC -E3
2; Ej = -lD 16 = -29 10 1C
.!...1 .!...1
24 = -DC 1D
+E3 DC is already a negative number too FF
07 -DC
DC = -24 16
Therefore -DC = 24 16 = 36 10 2;
.!...1
24
To verify. EJ - DC = 07
OR -29 - (-j6) = 7
This shows that subtraction is valid with positive negative or
mixed numbers. Errors will occur if the result goes beyond the
range of -128 10 to 12710, the limit of an 8 bit signed number.
 1-31
Now calculate 57 -2C and verify your answer in decimal.

FF To check 57 16 = 5 x 16 1 + 7 x 16 0 = 80 + 7 = 87 10
/
-2C 2C =2 x 16 1 + 12 x 16 0 = 32 + 12 = 44 10
D3
Total 43 10
U
D4 2B =2 x 16 1 + 11 x 16 0 = 32 + 11 = 43 10
ill
1 2B

1-32
As a variation, let's reverse the data in the last
question. Calculate 2C -57.

D5 or -2B FF
- _ _--J/
.:.i'Z
A8
U
A9
+2C
D5
But D5 is a negative number. To find its positive equivalent.
FF
-D5
2A
.!.J.
-2B
Therefore D5 = -2B, the same answer but the opposite sign,
compared to the previous question, since the data was reversed.
 1-))
To complete this section let's review it all within
several questions. Given two decimal numbers, 47 and 7),
calculate the sum by converting to hex, adding, then converting
back to decimal. Verify by decimal addition.

2 I 47 101111
--_-----.J/ 2 17)
1001001
2 I 2) +1
= 00101111 2 l.1£ +1
= '---v--
01001001
2 l!! +1
=
~~
2 F 2 W +0
= 4
.-....--'
9
2 U +1 2 L...2 +0
2U +1 2 L2t +1
2 L! +0 2 U +0
o +1 2 L...! +0
o +1
2F
+49 start 1 2 J 4 56 7 8 9
~-v--.""~I"~V~
78 F 0 1 2 J 4 5 678
l~ 8 0
:7 x 16 1 = 8
x 16 = ill
120 10
 1-34
Now perform the following decimal subtraction 83 -52
by converting to hex, subtracting, then converting to decimal.
Verify in decimal.

_ _ _-----J/
2W 2 L2£
2 I 41 +1
1010011 110100
2 ; 26 +0
2 I 20 +1 = 53 16 2 W +0
= )4 16
\.
2 L1Q +0 2U +1
2U +0 2U +0 FF )
2 U +1 2 L.! +1 ~/
2 L.!. +0 o +1 CB
a +1 .:!:..-!
CC = -)4 16
ill
1 1F

1
1F =1 x 16 + 15 x 16° = 3110 At last! It agrees.
 1-35
Binary subtraction is not essential if you can subtract
in hex. However it is included to complete the arithmetic
operations in both formats. From a previous hex example,
D -5 = 8
D = 13 = 1101 1101
5 = 5 = 0101 -0101
1000
As in hex subtraction start with the number to be subtracted,
0101 in this example. Complement it , that is each 0 becomes 1
and each 1 becomes o. Then add 1. This will produce the neg-
ative value of the original number (-5 = 1011 below).
0101
becomes 1010
plus 1 .:!:..-!
= 1011 =-5
Now add the +1101 ill
minuend 1101 1 1000 = 8
{overflow or carry is ignored.
This subtraction is limited to 4 bits as shown above.
Now calculate 12 10 - 7 10 in binary.

12 10 = 1100 -7 = 1000
--------'/
1100 = 12
710 = 0111 + 1 ~+1001 = =2.
1001.-J 1 0101 = 5

Perform the following 8 bit subtraction &

11010111 (215 decimal)
-10110100 (180 decimal)

--_/ Contd ...

 1-36
Contd.

10110100 = 180 10
complemented = 01001011
plus 1 + 1
01001100 = -180 10
+11010111 + 21 510
1 00100011
( overflow 35 10
If your data is in hex form already it is more direct
to subtract in hex. If the data is in decimal and conversion
has to be made to binary first, it is your choice whether you
subtract in binary or hex. If the answer is needed in hex, then
hex is preferred.

1-37
Here is the last question for this chapter. Calculate
in binary.
10110100
-11010111

11011101 which equals -35 10 •

-------/
This is the previous question with the order reversed.
e.g., 180 10 - 21 510 = -35 10
Details are. 11010111 ( 21 510 )
00101000 (complemented)
+ 1
00101001 (two'S complement) = ~21510
+10110100 (+18°10)
11011101 (which is a negative answer)
To calculate its positive value.
11011101
00100010
+ 1
00100011 = 35 10
Therefore the answer 11011101 2 = -35 10
 ACCUMULATOR OPERATIONS -2-1

The 6800 microcomputer is capable of a simple task such as

the addition of two numbers or a complex task such as the control
of a piece of electronic equipment. In both cases the task is
defined by a series of instructions to the computer, usually
referred to as a program.
Many program formats exist, the most fundamental being
machine code in which a series of 8 bit words are entered in the
computer via switches on the front panel of the computer.
The next level up is the expression of each instruction as
2, 4 or 6 hex characters, permitting entry via a keypad which ha~
one key for each hex character. This still is a form of machine code.
For longer programs it is very tedious to generate hex
codes for each machine language instruction. The solution is
to write the program in assembly language, in which each
instruction is in an abbreviated English format. The computer
itself then converts this assembly language program to machine
code, using a ready-made program called an assembler.
Higher still in the hierarchy of program format~. are
languages like BASI~, oriented to mathematical calculations in which
algebraic-like statements, including trigonometric functions, are
interpreted into many bytes of machine code for execution by the
computer.
Our interest in this workbook is in assembly language and
machine code programs which link the computer to keyboards, printers,
displays, communication devices and external electronic instruments.
Within the 6800 microprocessor (computer without memory or
interfaces to external equipment) there are two "accumulators", A
and B. Within each accumulator 8 bits of data can be added, sub-
tracted or modified via many different arithmetical and logical
operations.
 2-1
Contd.
One of the simplest assembly language instruction is
"CLR A", formed from "CLeaR accumulator A', meaning "put a zero in
each of the 8 bits of accumulator A." The machine code for CLR A,
expressed in hex, is 4F. (You don't have to remember the machine
code. )
Write what you think is the assembly language instruction
to clear accumulator B.

-------'/
CLR B, which in machine code is 5F. This instruction
can be written CLRB, omitting the space. Similarly CLR A can be
written CLRA. Machine codes for all assembly language instructions
are provided in Appendix C, at the end of this workbook. Instruc-
tions involving accumulators are on the first page of Appendix C.

--
2-2
If a hex value such as 2C is to be loaded into accumulator
A the instruction is
LDA A #$2C (LDA A = LoaD Accumulator A) •
The # symbol denotes that data follows immediately within the
instruction. The $ symbol denotes that the data is in hex format.
After this instruction is executed, the contents of ACC·A is

---' '-- C .7

since the LDA A instruction overwrites any previous contents of

ACC A.
The instruction LDA A #$2C is formed of 2 parts.
LDA A (called the operator)which tells
what happens (loading of ACC A),
#$2C (called the operand) which provides
the data to be loaded.

Contd. • •
 2-2
Contd .
•
Such an instruction requires 2 bytes of machine code.
LDA A, when followed by the # symbol is known as an immediate
mode instruction; its machine code, 86, is found under the
"IMMED" column, opposite LDAA in Appendix C. The second byte
of the instruction contains the data to be loaded, 2C. Hence
86 2C = LDA A #$2C. Write the assembly language instruction
and machine code to load ACC B with the hex value 7D.

LDA B #$7D C6 7D
---~/
Appendix G summarizes the use of special symbols such as # and $.

2-)
Write the instruction to load ACC A with the hex value
4D. Also write the machine code.

LDA A #$4D 86 4D
--_--....../
t 86, the machine code for the "operator" part of
the instruction is also known as an operation code, commonly
called the "op code".
The operand value, 4D, is also the code for the letter 00,
based on the ASCII (American Standard Code for Information
Interchange) code, listed in Appendix B at the back of this
workbook.
For practice use this table now to confirm that the
ASCII code for Z is 5A, under column 5 opposite row A.

A spare copy of the Instruction Set is provided at the

end of this workbook. It may be convenient to cut out this
sheet, for use with each problem, instead of continually looking
in the appendices.
 -
2-4
Write the assembly language instruction and machine code
to load ACC A with the ASCII code for the number 8. See Appendix B.

LDA A #$38 86 38
~from Appendix B -ASCII codes.
The ASCII codes for the numbers 0 to 9 are easy to remember,
being 30 + N where N = 0 to 9.

Another form of the immediate instruction to load an

ASCII code is seen in
LDA A #'Z (note the apostrophe)
in which the apostrophe denotes that the ASCII code for the letter
Z is to be loaded. Hence the computer on assembling (converting to
machine code) the above instruction automatically provides the
desired ASCII code for the second byte of the machine code instruc-
tion. The resultant machine code is still 86 SA since this is still
an immediate mode instruction. Such an instruction in which the
computer provides the appropriate code for the desired character is
often referred to as a "literal" instruction.
Write the literal instruction and the resultant machine code
to load ACC B with the ASCII code for the number 7.

LDA B #'7 c6 37
' - opposi te LDAB under Il'fiMED in Appendix C
 2-6
.--.
Now write two instructions, the first to load ACC A with
the hex value OF, the second to load ACe B with the ASCII code
for the letter F (using a literal). For each instruction provide
the machine code on the left side of the assembly language
instructions.

_ _ _----.J/
86 0F LCtA A #$0F
C6 46 LCtA B #"'F
The first instruction loads a hex value, OF, into Ace A.
The second loads an ASCII code for the letter F into Aec B. If
the difference is not clear, please reread the question and answer.
If the above two instructions were executed in the order
listed ACe A would take on a value, OF, and ACC B a value of 46.
This example although trivial shows the beginning of a program,
a series of instructions executed by the computer which modifies
the contents of an accumulator or a memory location (discussed
later).

.....
2-7
Write the assembly language instructions to load ACC A
with the ASCII code for A and load ACC B with the hex value OA.
For each provide the machine code.

86 41. LCtA A #'''A

LCtA E: #$0A
_-----J/
OF.: LDA A #$41.
C6 0A

Again note the distinction between a hex value and an ASCII code.
The above machi~e code and instructions are part of an
assembler listing, the printout produced by the assembler when
converting assembly language instructions to machine code.
 The addition of 2 hex values, JF and 27,
........
2-8
in ACC A can be
performed by

4F elf;,: A
E:B 3F ADD A #$3F'" (Adds JF + 0 = )F in ACe A)
88 27 ADD A #$27 - (JF + 27 = 66 16 in ACC A)
\....Y-' .~

machine assembly
code language
instructions
Rewrite the. above, using 2 rather than J instructions, again
providing the machine code.

86 3:F LOA A #$3:F

-----~/
This method is preferable to the one
88 27 ADD A #$27
above since it is shorter.

~
2-9
The memory of a computer, where data is stored, can be
envisaged as a series of mail boxes, each with a 4 character hex
address, e.g. l4D5, and the capability to store one byte of data.
'rhe instruction
LDA A $12B7 (no # this time)
loads ACC A with the 8 bit contents of address 12B7, without
destroying the contents of 12B7. Such an instruction is known as
an EXTENDED mode instruction, requiring one byte for the operator
(LDA A) and 2 bytes for the operand ($12B7). Hence LDA A $12B7
becomes B6 12B7. The B6 is found under the EXTND heading, opposite
the LDAA instruction in Appendix C. The total number of bytes
required {J} is found two columns to the right of B6, under
the # column.

Contd •.•
 2-9
Contd.
Write the assembly language instructions and machine code
to load accumulator B with the contents of address 06E4.

F6 06E4 LDA B $e6E4

-------.1./
If address 06E4 contains JF then ACe B will contain )F after
execution of this instruction. In the above instruction
LDA B is the operator while 06E4 is the operand, denoting
the data source.

2-10
Write the assembly language instructions to add the
contents of memory addresses lCOO, lCOl and lC02, the answer
residing in ACC B. ...Provide the machine code •

F6 1.cee
FB 1.C01.
LDA B
ADD B
$1.C~10
$1.CI2I1.
-------'/
FB 1.C"32 ADD B $1.Ce2

2-11
The accumulators are used for many purposes within a
program. Data, after being processed in an accumulator, usually
is stored in a memory location, e:',g.,
STA A $064c
which stores the contents of ACC A in address 0640 but does not
destroy the contents of ACC A. This instruction, referencing a
4 character hex address, also is "extended" mode. Write the
machine code for the above instruction.

87 12164(:
_ _ _--J/
·l.. address
·'
STA A (extended mode)
 2-12
Write the assembly language instructions and machine code
to add the hex contents of addresses 14no and 14D1. then store
the sum in address 14D2. without using ACC A.
If 14no contains JE (14DO/JE) and 14Dl contains B5 (14Dl!BS) ,
what will the hex value in address 14D2 be when this program is
executed?

_ _ _--J/
F6 1.400 LOA B $14De (ACe B/JE)
FB :1.40:1. ADD B $1.4D1. )E + B5 = F)
F7 1402 STA B $1.4D:2 14D2/FJ (ACC B still contains F3)

JE
+B5
start 1 2
FJ
BeD E FlO
start-~4

2-1J
To place a particular value in a particular memory address
it is first necessary to set it into Aee A or B. With this in mind
write the assembly language instructions and machine code to put
the hex value JB in address 12EJ.

_ _ _--J/
86 3B LDA A #$38 }_ assuming use of ACC A.
87 1.2E3 STA A $1.2E3
Such a procedure is known as initializatio~, providing a particular
memory address with an initial value, for use during a program.
 2-14
Write the assembly language instructions and machine code
to initialize address 0439 with the ASCII code for the letter G,
with the computer providing the ASCII code.

86 47 LDA A # ..013
---~/
87 (1439 STA A $0439
Again it is not necessary to memorize the machine code for the
instructions. However, the 86 and B7 values will soon become
quite familiar.

2-15
The instruction SUB A $1524 subtracts from accumulator A
the contents of address 1524. Write the assembly language
instructions and machine code tOI
(a) ADD the contents of addresses 13C4 and 13C8
(b) then SUBTRACT from this the contents of address 13CA
(c) then STORE the result in address 1)CC.

B6 :1.3C4 Lr..A A $1.3C4

_------..1/
BB 1.3C8 Ar..[) A $:1. -"-'8 )
:-~~ ) -assuming use of ACC A
Be 1.3CA SUB A $1.J:I_oA )
87 :1.3CC STA A $13CC
 2-16
An instruction which will produce the negative value of
the contents of ACC A is
NEG A (NEGate accumulator A).
If ACC A contained 04 before execution of NEG A it would contain
FC (-04) after execution. The machine code or operation
code (op code) is 40 as seen in Appendix C opposite the
2's complement (Negate) instruction.
Like the CLR A instruction NEG is under the
INHERent column, being complete within itself; that is it
does not require another byte for the operand.
Write the assembly language instructions and machine code
to store the value -JC in address 095A.

#$3C
_ _ _-----J/
86 3C LDA A
40 NEG A
87 1!:195A STA A $t195A

Address 095A now contains 04 (-JC)

2-17
Memory addresses referenced in an instruction normally
require 2 bytes (4 hex characters) to describe them, e.g.,
LOA A $12A6, requiring an EXTENDed mode instruction. Memory
addresses below 100 16 require only 1 byte to describe them, as
is seen in a DIRECT mode instruction, e.g.,
LDA A $4A
which loads ACC A from address 004A. The machine codes for
DIRECT mode instructions are in Appendix C. For the above
instruction the machine code is
96 4A
'-v-' "-v-'
address 004A
L LDA A (DIREC'! mode)

Contd ..•
 2-17
Contd .
•

Write the instruction to store ACC B in address 66 using a

DIRECT mode instruction. Write its machine code.

STA E: $66
---_/
Aside from requiring fewer memory locations to stor~ the
instruction a DIRECT mode instruction requires fewer machine
cycles to execute as seen in Appendix C. Large programs often
use addresses below 100 as a "scratch pad" storage area, e.g.,
for storage of counter values, or temporary storage of a byte
of data. Use of this area of memory saves memory bytes and
reduces execution time.

2-18
The instruction TAB transfers the contents of ACC A to
ACC B. Similarly TBA provides the reverse transfer. Using as
few instructions as possible, swap the contents of the two
accumulators. Memory addresses below 100 16 are available (use
DIRECT mode only). Write the assembly language instructions
and machine code.

97 50 STA A $50
---_/
(or your choice of address)
1.7 TBA
[)6 5~3 LDA E: $5~ (or your choice of address)

Q) 50~
A/ B
4Q)
Counter-clockwise execution of the above flow diagram would
utilize TAB (op code 16).
 2-19
Accumulator A can be incremented (1 is added to it) via
the instruction
INC A (INCrement accumulator A)
for which the op code is 4C.
Similarly DEC A (DECrement accumulator A) will decrease
its contents by 1. Its op code is 4A. Accumulator B also can
be incremented or decremented.
Calculate the contents of each accumulator after the
following instructions are executed.
CLR A
CLR B
INC B
ADD A #$2C
ADD A #$16
TAB
NEG A
INC A

Ace A Ace E:
/
ClF.: A fl
ACC A/BF ClF.: E: 0 f,1
ACC B/42 INC E: f:t i
ADD A #$2C 2C :1
ADD A #$16 42 1
FF TAB 4'-'
.::. 42
NEG A BE 4'-:'
0::..
-42 INC A ElF 4'::-
..-
BD
.±-!
BE
Therefore -42 = BE
 2-20
Sometimes it is necessary to clear (force to 0) or set
(force to 1) specific bits of an accumulator, without disturbing
the other bits of the accumulator. This is accomplished via the
AND and ORA operating on the accumulator. The AND instruction
clears specific bits while the ORA instruction sets specific
bits. The instruction
AND A #i5A (machine code 84 SA)
performs the "logical AND" operation (not addition) bit by bit
with ACC A and the data SA being inputs and ACC A holding the
result.
In the "logical AND" operation each bit of the result
will be 1, if and only if both the corresponding inputs are 1.
Looking first at bit #7, below, one of the two inputs has a zero.
Therefore bit #7 of the result is zero. Complete the bottom line
showing the contents of ACC A after the AND A #$5A instruction is
executed ~
bit #7 J r11 1 1 0 1 1 0 0 - ACC A (before)
0 1 0 1 1 0 1 0 -5A
0 ,- ACC A (after)

---~/
1 1 1 0 1 1 0 0
0 1 0 1 1 0 1 0
0 1 0 0 1 0 0 0

~
"'---
\. \. \,,, 1.. at
~_.;z-..-_ _--a._-.a_~
result
leas is 0 since
t one of the
inputs is o.
 2-21
If address 14A2 contains 70, what will ACC A contain
after execution of
LDA A $ 14A2
AND A #$BF

JC
7 6 543
----/
2 1 o ...-bit II
7C = 0 1 1 1 1 1 0 0 L{Contents of 14A2
BF = 1 0 1 1 1 1 1 1 to ACC A
0 0 1 1 1 1 0 0 = 3C
Bit #6 is guaranteed to be zero regardless of the contents
of address 14A2 since the "mask word", BF contains a zero in bit #6.
The result can be shown as
XOXXXXXX
where X denotes the original data in ACC A before the AND
operation. If the purpose of this operation was to clear bit #6
of the data in address 14A2, the modified data would then be stored
back in address 14A2 by another instruction, STA A $14A2.

2-22
Write the assembly language instructions and machine code
to clear bit #3 of the contents of address 1256.

-------'/ Contd •••

 2-22
Contd.

86 :1256 L[:IA A $:1256 7 4 3 2 1 o ...bit #

84 F7 AND A #$F7 x Contents
87 1.256 5TA A $1.256 of 1256
1

~I---X-=---~~~-T--~
~ contents

X represents undisturbed data

· # = 0
B1t3 .
S1nce X"-• 0 = 0 could be 0 or 1
" X
symbol for
logical AND
J If X = 0, then 0.0 = 0
If X = 1, then 1.0 = 0
Therefore X.O = 0
All other bits are unchanged since
X.l = X If X = 1, then 1.1 = 1
If X = 0, then 0.1 = 0
Therefore X.l =,X ~

same as before

2-23
Similarly all bits, except a specific bit, of a
particular. address can be cleared by the appropriate "mask word".
Write the assembly language instructions and machine code to clear
all bits, except bit #6, of address 065E.

86 f165E
84 40
LOA A
AND A
$065E
#$40
---_/ iii bit #6
87 t165E 5TA A $~~165E (40 = 01000000)
Since only bit #6 of the mask word = 1, then only bit #6
of the original contents of 065E will be retained. All other bits
of the result will be zero. This technique will be used extensively
later in this workbook.
The above AND instruction could be rewritten in terms of the
binary value of the mask word e.g.,
AND A #%01000000
The % symbol indicates that a binary value will follow. This form
is often useful to both the programmer and the user in quickly
determining which bits are cleared.
 ----
2-24
An ASCII code, produced by an external device, such as
a keyboard requires only 7 bits to describe it. The 8th bit
(bit #7) may be 1 or 0 depending on the particular data source.
Assume that an ASCII code is now in ACC A. Write the assembly
language and machine code instruction to clear bit #7 of the
ASCII data. Use the binary version of the mask word in your
answer.

84 7F AND A
_ _ _----J/
#~0~11~~1~

Note that the machine code instruction is still expressed in hex

even though the assembly language instruction uses a binary mask
word.
In summary a 0 is used in the mask word of an AND
operation for each bit that is to be cleared. All other bits of
the mask word are 1.

2-25
We have seen how to clear specific bits. Let's look at
a method to set specific bits. For this purpose the "logical
OR" operation is used (sometimes called INCLUSIVE OR). Given 2
bits as inputs the logical OR output will be 1 if either the
first input OR the second input OR both inputs are 1. Stated in
logical form ~z ~C + D ~
output 'one tlOgical other
input OR input
symbol
(not addition)
The instruction ORA A #$08 will perform the logical OR operation
with ACC A contents and the mask word, 08, as inputs. The result
will reside in ACC A. If 144A contains $CA, what will be the
result after execution of
B6 144A IDA A $144A
8A 5C ORA A #$5C

Contd •..
 2-25
Contd.

Ace A/DE 7 6 5 4 3 2 1 O~bit #

CA = 1 1 0 0 1 0 1 0
5C 0 1 0 1 1 1 0 0
1 1 0 1 1 1 1 0 = DE

The mask word 5C (01011100) with a 1 in bits #2, J, 4 and 6

ensures that these bits are set, regardless of the original
data in address 144A. All other bits remain the same.

2-26
Write the assembly language instruction and machine
code to set bits #2 and #7 of the data in address o6A4, without
changing the other bits of this data. Use binary format for
the mask word.

$€16A4
----_/
86 06A4 LDA A
E:A E:4 OF.:A A #~'-;::t ~~1 ~j~~UZ1:t (10
87 €16A4 STA A $06A4

In summary a 1 is used in the mask word of an ORA operation for

each bit that is to be set. All other bits in the mask word are O.
 2-27
Now set bit #3 and clear bit #5 of address 16n6. Use
binary format for the mask words.

86 1.6D6
E:A 08
LDA A $1.6D6
#:..~00001.000
----'/ set bit #3
OF.~A
A
84 DF AND A #~·~:11.0:11.:111 clear bi t #5
87 16D6 5TA A $:16D6

Ix [ X 10 I X 11 I X I X I xl
X = unchanged bit

2-28
Once more now! Set bits #7, 6 and 2 of address lA42
and clear bits #1 and 4. Assume that each bit controls the
lights for one room in an 8 room house. Provide both assembly
language and machine code instructions.

86 1.A42
:3A C4
LDA A
OF.: A A
$:lA42
#~'~110~~n~1100
------'/ (Set 7, 6 and 2)
f=:~+ ED AND A # ~.~ 1 :11€1:11 ~~11. (Clear 4 and 1)
6''7
.'1 :1A42 5TA A $:1A42

Although this is the end of the "Accumulator Operations"

chapter several other accumulator operations will be introduced
at a more appropriate place, later in this workbook. You are
probably ready for a change from "bit bashing". Time for a coffee!
 SYMBOLIC ADDRESSING ---
)-1

So far we have used absolute addresses e.g., 1A42 for

storage of data. When writing in assembly language this is not
desirable for several reasonsl
- until the program is assembled the addresses available
for data storage may not be known.
- if many addresses are used for different purposes it
becomes difficult to remember the purpose of each
address while preparing the program.
- if a program is later modified certain addresses now
used for data storage may not be available, requiring
re-assignment of storage addresses.
The solution is the" use of a "symbolic address" rather
than an absolute address e.g.,
STA A COUNTR
which stores ACe A contents in an address carrying the symbolic
address eOUNTR. ~e absolute address will be determined when the
instructions are assembled into machine code and printed on the
resultant listing. Meanwhile the programmer can continue to use
the symbolic address as if it were an absolute address.
To present an everyday analogy one might suggest meeting
for lunch at "Dan's Place" (a symbolic address), whereas Dan's
Place might be at 146J Main Street (the absolute address).
Write the assembly language instructions to initialize
the symbolic address COUNTR with the hex value JC.

LDA A
STA A
#$3C
COUNT~:
------.;/
 3-2
......
Symbolic addresses generated by the programmer can be
up to 6 characters long, the first character being a letter and
all subsequent characters being a letter or a number. It is
good practice to choose a symbolic address which describes the
function, COUNTR perhaps being a counter to keep track of the
number of events that take place when the program is executed.
The only illegal symbolic addresses are A, B and X, the first two
being previously assigned to accumulators. Single letters for
symbolic addresses are almost meaningless and should be avoided.
Write the assembly language instructions to set bit #5
of STATUS, without changing any other bits.

LDA A STATUS
ORA A #~0010e000
STA A STATUS

Only after the above instructions are assembled into machine code
will we know the absolute address for STATUS.
 When the computer assembles an assembly language -
)-)

program, it needs to know at what address to start. in assigning

each byte of machine code to a memory address. The ORG (origin)
directive to the assembler, in the example below, designates the
starting address. e.g .•
O~:G $0200
LOA A #$3C
STA A COUNTR

This will cause the following address assignments for the

resultant machine code, assuming that COUNTR corresponds to
address 024)
0200/86
}- LDA A #$JC
0201/;C
0202!B7
0203/02 } - STA A COUNTR
0204/4)
To minimize the amount of paper, produced by the assembler. the
address printed is for the first byte of each instruction. e.g.,
0200 :36 3C LOA A #$3C
02~12 87 0243 STA A COUNTR

Write the assembly language instructions and machine code

to clear bit #4 of STATUS, which corresponds to address 124E.
Start the instructions at address 1200. Show the addresses.

_ _ _----J/
ORG $1200
:1.200 86 124E LOA A STATUS
1.2~13 84 EF AND A #~~1.1.1.011.11.
1.205 87 1.24E STA A STATUS

A very common error is omission of the $ symbol. which

causes the assembler to interpret 1200 as a decimal number
in the above example.
 To reserve a memory byte for a specific symbolic
......
3-4

address, the assembler MUST be directed to do so. In this

program
0200 ORG $0200
0200 86 3C LDA A #$3C
0202 87 0243
,
STA A COUNTR

J
I
I
0243 0001 COUNTR RM8 1

The last line, COUNTR RMB 1 (Reserve Memory Byte - 1 only)

causes one byte (address 0243) to be reserved and recognized as
the symbolic address COUNTR.
This symbolic address, COUNTR, contains data and must not
be embedded in the middle of a group of instructions where its
contents would be interpreted as an instruction, rather than data.
Such an error is seen in this examples

0200 ORG $0200

0200 86 4F LOA A #$4F
0202 87 0205 STA A COUNTR
0205 COUNTR RM8 1

Here COUNTR (address 0205) contains 4F after the first two

instructions are executed. The next instruction would then be
from the next address, 0205, whose contents is now 4F, a CLR A
instruction. It is the execution of the program which determines
whether the contents of a memory address is treated as an
instruction or data.
To avoid the above p~oblems the symbolic address
COUNTR is located outside the group of instructions forming this
part of the program, as in the first example.

No answer is required in this frame

 3-5
~

Write the instructions to initialize DATA5 with the

value A4. Start this program at address 0400 and show a complete
listing, noting" that DATA5 corresponds to address 0462.

040f1 OF.:Ci
_ _ _-----.J/
$t:.::140~Z1
t14~~1t1 86 A4 LDA A #$A4
13402 E:7 ~3462 STA A [)ATA5

13462 0130:1. DATA5 F.:MB :1.

" • " , ""...,I" .. J

Label Operator Operand Comment

Field Field Field Field
The 4 fields of an assembly language program are seen above.
The operator and operand have been discussed previously. In
the bottom line we see DATA5. a "label". that is a "symbolic
address in the label field". In preparing assembly language
programs. labels start in the first column of the line, while
operators (LDA etc.) start in the 8th column. It is only
necessary to space over 1 column rather than 7 to start the
operator (LDA etc.) since the assembler, on noting the absence
of a label. will automatically print the operator in the 8th
column. Similarly short labels (less than 6 characters) need
only to be terminated by one space; the assembler again will
start the operator in the 8th column. A sample source program
before assembly is shown below.

NAt'1 CiENPF.:O
ind"ented one OPT 0 .. 5
space to start OF~Ci $12~n3
in the Operator LDA A STATUS
Field. AND A #;'~:1:1.:t€11.1:t1
STA A STATUS
for Label Field r
start first column : It is legal to
, ORG $:t24E .-:..-.-
have more than
'~STATUS FeE: $FF one ORG directive
END
within a program.

t
1
st
column
 The comment field, mentioned on the previous page,
permits entry of comments to improve the readability of a
---
3-6

program. e.g.,
L.DA A #$2£1 INITIALIZE NUVALU
STA A NU'·.. ALU WITH :2£1 (DECIMAL
.... Commenf Field
Such comments are ignored by the assembler but printed on the
resultant listing. One space is all that is needed to separate
such a comment from the operand field.
A good program should begin with a brief description of
its purpose and perhaps some of its internal details. Whole
lines of comments are legal if the * symbol appears in column 1
of each comment line. These too are ignored by the assembler
but printed on the listing. Both examples are seen below.
:+:
:+: PROGRAM TO OUTPUT TEN CHARACTERS
:+: TO THE LINE PRINTER.
:+: VERSION 38 77/11/12 RWS
:+:
LDA A #$£1A INITIALIZE COUNTER
STA A COUNTR WITH 0A (1£1 DECIMAL)

One assumption to make when programming is that someone

else without your help will have to modify your program several
years from now. For this, documentation in the form of good
comments is essential. To put it more bluntly. if it is not
worth documenting it is not worth doing. There will be lots
of opportunity to practice this in the next chapter. No answer
is required in this frame.
 ~
3-7
Three other directives are needed to form a complete
program. These plus the ORG directive are illustrated below.

NAM HEXCHK
OPT 0. 5
ORG $04013

•I
I
I
Program
Instructions

END

The entry following NAM, up to 6 characters long, is a program

name, generate. by the programmer. It will be reproduced at the
top of each page of the assembler's listing, aiding in program
recognition.
The OPT (option) directive has many possible entries.
The 0, above, requests an object (machine code) file to be
produced. Depending on the computer system this file may be
stored on paper tape, cassette, diskette or some other medium.
The S entry requests a symbol table, a list of all symbolic
addresses along with the corresponding absolute addresses, at
the end of the listing.
The last directive is END which terminates the assembly
language program. Without looking up, try to list the 4
necessary directives for a program.

NAM OPT ORG and END.

- _ _---J/
 To practice use of these directives write a program
called CLRALL, starting at address 0400, to clear both
---
3-8

accumulators. Yes, it is a ridiculous program.

NAt1 Cl~:ALl
_ _-----...1'/
OPT 0., S
OF.:G
:+:
:+:ClRALl. . . CLEARS 80TH ACCUMULATORS.
:+:
1214121121 4F ClR A A TRIVIAL PROGRAM
121401 5F ClR 8
END
To save space in this workbook the directives will not normally
be shown in the listing, but will be assumed.
Note that END only tells the assembler that this is the end
of the program. It does not halt the program, when it is
later executed.
)-9
~

NAM PROG68 In this listing

OPT 0 .. S the assembler has noted
01121121 OF.:G $1211121121
:+: ERROR 209 for the
:+: F'3:-9 instruction LDA #$4A.
:+:
12Ij,0~3 4F ClF.: A Can you find the error?
e1~:::11 5F elF.: E:
EF~ROR 2~39
12111212 ~:::1€1 0£1€1€1 lOA #$4A
€11~35 87 £1427 STA A $~3427
:+:
END

The instruction should be LDA A #$4A or LDA B #$4A.

Assembler Error Codes, such as ERROR 209. are explained in
Appendices Jl and J2.
 4-1
INDEX REGISTER
Each accumulator is capable of holding 1 byte, represented
by 2 hex characters. If 2 bytes are to be referenced we use the
Index Register which holds 16 bits (2 bytes or 4 hex characters).
The instruction

LDX #$lF2D (an Il~~Diate mode instruction)

loads the Index Register with the hex value lF2D.
The instruction sequence
021Z10 CE 1.F2D LC'::-:: #$:1.F2D
0203 FF 131.6C ST:x: $016C

initializes 2 bytes of memory with iF and 2D via the Index

Register. Address 016c receives 1F while address 016n
receives 2D, as shown below.

I I
016B 0160 016D ~memory address
Machine codes for Index Register instructions are on the second
page of Appendix C.
Write the instruction sequence to initialize 2 bytes of
memory, 14C4 and 14C5, with the hex value 0640. Include the
corresponding machine code.

1!:11.0~3 CE ~:::164€1 LD:X:

---~/
#$1Z164f.1
1Z11.03: FF 1.4C4 sr::< $1.4C4
 4-2 ~

Initialize 2 bytes of memory, lC80 and lC81, with the

hex value 2C40. Include the m~chine code.

----/
CE 2C4e LDX #$2C4121
FF 1.C8£1 ST>:: $1.C8121

The result iSI 1C80/2C (lC80 contains 2C)

1C'81/40 (lC81 contains 40)

~
A symbolic rather than an absolute address may be used
to store the value, e.g.,

CE 1.5D6 LDX #$1.5D6

FF 1211.6121 STX LISTOP
f
•
1211211212 LISTOP •
RMB 2

(a) Why does the above example use RMB 2 rather than RMB 11
(b) Initialize a symbolic address POINTR with the hex value
1C60. Omit machine code this time.

_ _ _---J/
(a) 2 bytes are necessary to store the 2 byte value 1506.
(b)
LD>:: #$1.C6£1 (an lOOMED instruction)
,
ST>~ POI NT F.: (an EXfND instruction)
I
POINTR F.:t18 2

le goes into POINTR

60 goes into the next address above POINTR.
 4-4
The instruction STX POINTR+l stores the contents of
the Index Register in the next address above POINTR. Write an
--
instruction to store the Index Register contents in memory, 3
addresses below CONREG.

FF 14A2 5r::·:: CONREG-3

--~/
If CONREG correponds to address 14A5, the Index Register contents
are stored in address 14A5 - 3 = 14A2, as is seen in the machine
code of this listing.

This could be accomplished, one byte at a time, via

accumulator operations; however the above approach is preferred
because of its simplicity.

Another use of the index register is seen in

-4-5
LD::-:: #t1E55ACi
5T::·:: PO I NTFt~

which stores the address, not the contents of MESSAG in the

2 byte address, headed by POINTR. If MESSAG corresponds to
address lBJ4, what will be the contents of POlNTR after
execution ofl
LD~< #t1ES5AG-1
5T::-:: PO I NT F.:

Write the machine code for these two instructions assuming

POINTR corresponds to address lB6A.

lB3J
-----------"/
Since MESSAG corresponds to address lB34, then
MESSAG-l corresponds to address lBJJ.
132130 CE 1833 LDX #MESSAG-1 ~ lMMED MODE (USES #)
121203 FF 186A STX POINTR
 4-6 ~

If TOPBLK corresponds to address lAOO and contains 0)

while TOPBLK+l contains 80, what is the 2 byte contents of
U~MPNT (and MEMPNT+l) for each example below?

#TOPE:LJ(-:1 LD>~ TOPE:LK

t'lEt'1PNT ST>:: t1Et'1PNT
I I
,
I I
t
t'1Et'1PNT F.:t1E: 2 t'1Et'1PNT F.:t1E: 2

19FF
_ _ _---i/0)80
lAOO -1 = 19FF, one The 2 byte contents of
address below lAOO, TOPBLK and TOPBLK+l is
now stored in MEMPNT 0)80, now stored in
and MEMPNT+ 1. MEMPNT and MEMPNT+l.

4-7
~

The instruction
CLR :3,X
is interpreted as "Calculate a new address which is the sum of
the Index Register contents and the offset, :3 in this example,
then clear that memory address." The above instruction could
be written as
CLR $3,X
although the $ is redundant for values of 7 or less.
If the Index Register contains l)E4, what address has
its contents cleared by CLR :3,X?

_ _ _---.-.1,/
l)E7 X/ 1)E4
+ 3
IJE7 = address operated upon by CLR ),X

This mode of instruction is known as Index Mode. The

instruction CLR X is also an Index Mode instruction, being
a legal contraction of CLR O,X. If X contains 2400, the
instruction CLR X will clear the contents of address 2400.
Similarly LDA A X is a contraction of LDA A O,X loading
ACe A with the contents of the address now in X.
 -4-8
Write the assembly language instruction to store the
contents of ACC A in address 24C0 when the Index Register
contains 24AO.

STA A $20.. >~

--_/
24Co
-24AO
20
Offsets are positive only, 00 to FF, the offset FF producing a
new address 255 10 above the address contained in X. Symbolic
offsets, e. g. ,
LDA A OFFSET,X
are valid, the value of OFFSET being determined at assembly time.
If OFFSET equals $14 via the assembler directive
OFFSET EQU $14
the result would be the same as execution of LDA A $14,X.
Assembler directives are normally located at the top of a
program, to improve readability

4-9
..--
Machine code for Index mode instructions are found
under the INDEX column in Appendix C. Note that
LDA A 3,X (op code A6)
requires 2 bytes as seen by the 2 under the # column, 2 columns
to the right of A6. What does the second byte denote? Take
a guess. Attempt to encode the above instruction in machine
code.

--------/
The second byte contains the offset value, 03 in this case,
e.g., ~~~
LDA A offset
(Index Mo de)
 4-10
The 2 byte contents of the Index Register can be
incremented (1 is added to it) via the instruction
INX INcrement indeX register (08)
Similarly, DEX DEcrement indeX register (09)
will decrement it.
Write the assembly language instructions to increment
the contents of MEMPNT which now contains the hex value 19FF.
What will its new contents (2 bytes) be after the above
incrementing?

_ _ _---J/
LD>!. t'1EMPNT
INX
STX t'1EMPNT
t
I
I
MEMPNT RMB 2 (If not already present in
the rest of' ·the program.)
This J line sequence will be used many times in this workbook to
increment a 2 byte value in memory. Note that the Index Register
(X) still contains the incremented value, 1A00 in the above
example, after STX MEMPNT is executed.

Another application of Index Mode is seen in code

conversion, such as ASCII to Baudot, where each ASCII value
is separated in memory from its Baudot value by 80 16 addresses.
Once the address of the ASCII value is known, the corresponding
Baudot value is obtained by the instruction LDA A $80,X
 4-11
To store a message such as "START CARD READER" in
memory, it is not necessary to load and store each ASCII
character of the message. The sequence below will store each
required ASCII code and terminate the message with a null (00).
MESSAG FCC ISTART CARD READERI
FeB ~3

FCC (Form Constant Character) is a directive to the assembler.

ordering the storing of the appropriate ASCII codes. Two
identical characters are required to define the boundaries of
the message. The slash (/) is popular for this since it is
not usually used within a message.
FCB (Form Constant Byte) directs the storage of a hex value.
00 in this example, to denote the end of the message. Note
the difference between null (00) and the ASCII code for
zero (JO).
Such message entries generate a lot of unnecessary
printing at assembly time as each ASCII character of the
message is listed. The OPT directive NOG (NO Generate)
eliminates the ASCII code listings but includes the printed
message. e.g., OPT O.S,NOG (at ~he top of the program).

Noting the above message, intialize POINTR with the

address one below the start of the message.

LD>c:
STX
#MESSACi-1.
POIr'~T~:
-----/
I
I
I
POINTR Rt1B 2
 4-12
Store the message "ENTER DATA" in memory headed by the
label MESS04, and terminated by a null. Initialize MESPNT with
the address one below the start of this message.

LDX #MESS(14-:1.
-----/
ST>!' t'1ESPNT
I
I
I
t1ESF'NT F.:t1B 2
t'lESS04 FCC /ENTEF.: DATA/
FCE: ~~1

One other assembler directive, available but not required above

is FDB (Form Double Byte) e.g.,
FDB $1433,$7
which in this case stores 14 and 33 in 2 bytes, then 00 and 07
in the next 2 bytes. This directive stores an open ended
string of 4 character data, each separated by a comma.

4-13
What will be the contents of ACe A after execution of
the instructions shown below?
LDX #MESS04-1 INITIALIZE POINTER WITH
STX POINTR ADDRESS MESS04-1
LD::'!, PO I NTF.:
I~~i::
ST::< PO I NTF.:
>!, GET CHAR VIA :;.~
LDA A
~
i
POI NT F.: Rt1B .-..::.
MESS(14 FCC .·...ENTER DATA/
FCE: ~3

---_/ Contd ...

 4-1:3
Contd.

45, the ASCII code for E in the message ENTER DATA.

POINTR initially contains the address MEsso4-1. After
the second STX POINTR is executed, both POINTR and X contain
the address corresponding to MESSo4. Hence E (ASCII code 45)
is the first data retrieved via LDA A X.
The above sequence, with additions, will be used many
times in this workbook. The advantage of starting with
MEsso4-1 rather than MESSo4 is that X points to the start of
the message when LDA A X is executed the first time.

4-14
If address 12A6 contains C4 (12A6 / c4) the instruction
LDA A $12A6
loads ACC A with C4, the contents of address 12A6.
If address 14AS and the next address contain l2A6
(14A5 / 12 and l4A6 / A6) then
LD::·:: $:14A5 X.·...:12A6
LDA A ::.~ A,.··C4
also places e4 in ACe A, this time via an "indirect" manner,
with X containing the address of the data, 12A6, after execution
of LDX $14A5. Hence this is commonly known as an "indirect" or
"deferred" memory reference.
This process can be extended further. Given the
following initial conditionsl
lCSO / l4A5
14A5 / 12A6
l2A6 / C4
the instructions
LDX $lC50
LDX X
LDA A X

will also place C4 in ACC A via a "double deferred" memory

reference. Before execution of LDX X, X contains 14A5t This
instruction, LDX X, loads X with the contents of the address
now in X, that is with l2A6 the contents of l4A5. The last
instruction then loads C4, the contents of 12A6, into ACC A.
 --
4-15
The main point of this chapter probably needs review again.
If X / 13C4 where is the data stored when STA A X is executed?

----....,,/
in address 13C4. The best way to interpret this instruction is
"store the data in Accumulator A via X". that is X points to the
destination •

4-16
~

If X / 02AE and 02AE / B5 what will ACe B contain after the

instruction LDA B X is executed?

---_/
B5 Accumulator B is loaded via X, that is from the address
now in X. This time X points to the source of the data.

If X / 267E what is compared when the instruction eMP A X

.....
4-17

is executed?

----/
The contents of Accumulator A is compared with the contents
of address 267E.
 BRANCHING - ASSEMBLY LANGUAGE -5-1

Computer programs in which instructions are executed in

a simple linear manner are almost non-existent. In fact many
decisions are made by computers, in executing a typical program,
to determine what to do next. A program with decisions in it is
described as follows.
The computer may be required to determine if the ASCII
code, now in Ace A corresponds to a valid hex chal'acter t
e.g., 30 to 39 for 0 to 9 or 41 to 46 for A to F. Invalid
characters are to be rejected. Valid ASCII codes are to be
converted to their corresponding hex value, e.g., 39 becomes 9
or 46 becomes OF.
In eliminating invalid ASCII codes the computer must
first eliminate all values below 30. The instructions
COOP A #$2F (CoMPare acc A to 2F)
BLS BADHEX (Branch if Lower or Same to BADHEX)
will do this. If the value in Ace A is lower than 2F or the
same as 2F, the program will branch to BADHEXa that is the
next instruction executed will be the one carrying the label
BADHEX.
If the value in ACC A is JO, the ASCII code for 0,
what will happen "after execution of the above 2 instructions?
Take a guess if necessary.

---~/
No branching will take place. The next instruction executed
will be the one following BLS BADHEX.
 -5-2
If the first test was passed (no branch since the ASCII
value was 30 or greater), the next test is to check for values
greater than 39, the ASCII code for 9. If the value is 39 or
lower, the program should branch to NUMOK. otherwise it should
continue. Write the instructions to ·do this noting the avail-
ability of the instructions I
BLS - Branch if Lower than or Same
BHI - Branch if HIgher than
BRA - BRAnch unconditionally.

Ct'1F' A #$39
---_/
BLS NUt10K o TO 9. VALID HEX

The conditional branch instructions BLS and BHI treat

the ACe A contents as an unsigned number, that is all values,
00 to FF are considered positive.
By having available both BLS and BHI (opposite instructions)
the programmer can either choose to branch or not to branch when a
specific condition is met.
So far the program is.
HEXCHK CMP A #$2F
8LS 8ADHEX MUST BE BELOW 30
Cr·1P A #$39
BLS NUMOK MUST BE 30-39
••
•
Nur'10K,
I
BAD HE}!,
 For ASCII codes )0 - 39 we want the hex values 0 - 9 in
ACC A. What instruction, starting at the label NUMOK will do
-
5-)

this, e.g., when key 5 on a keyboard is struck the final contents

of ACe A will be 5, not 35. The program should go to GOODHX when
the correct value is in ACC A. Again assume that the ASCII
code is already in Ace A when the program starts. Show only
the program additions.

NUt10.::: SUE: A #$3:~3

--_----.J/
E:F.: A 1100DH~-::

or
NUt'10K SUB A #···0
BF.:A GOODH::<
We now have a
HEXCHK Ct1P A #$2F
E:LS E:ADHE:X: t'lUST BE E:ELOl,~ 3:(1
Cr'1P A #$3S1
E:LS NUr'10k: NUST BE 3:~~1-3:9

GOO[)H:X:
I
I
I
NUNOK SUE: A #$30
BRA GOODH:X:
BADHE>::
 Now scree n for valu es A to F. Vali d char acte rs in this
grou p shou ld be conv erted from thei r ASCII code to thei
---
5-4

r true
hex valu e, e.g. , OA when A is struc k. For valid char acte
rs
cont inue to GOODHX, the next line, afte r this conv ersio
n. For
inva lid char acte rs branc h to BADHEX.

_ - - - - .. J /
cr'lP A #$40
BLS BA[)HE >~ t1UST BE 3:A-4~3
Ct1F' A #$46
BHI BADHE>:: MUST BE GREATER THAN 46
SUE: A #$37 41-46 NOt,J 0A-~3F
END OF ROUT I NE.

The ASCII code for A is 41, for whic h the hex value is
OA. The ~i:ference is 37, whic h when subt racte d from 41
give s
us OA. S~m~larly when F is struc k, 46 - 37 = OF. Calc
ulati ons
are shown below .
FF 41 When A is struc k 41 ASCII for "A"
-OA .+F6 +C9 (-37)

U
F5

F6
j
= -OA
1 37 1 OA
~ hex code for A
 HEXCHK) iss
The fina l versi on of this routi ne (let 's call it -
5-5

HEXCHK. .. CHECKS IF CHAR NOW IN ACC A

IS VALID HEX CHAR~ THAT IS 121-9 OR A-F.
ENTER WITH ASCI I CHAR IN ACC A.
RETURNS WITH 4 BIT EQUIVALENT HEX IN ACe A IF VALID

HE::-::CHK C\"'lP A #$2F

BLS BADHE~ ':: t'lUST BE BELOl.oJ 3:f~
Ct'lP A #$3:9
BLS NUt'10K t'lUST BE 3:€1-3:9
Ct1P A #$4~3
BLS BADHE::·:: t'lUST BE 3:A-4~ 3
Ct'1P A #$46
BHI BADHE>:: t'lUST BE CiF:EATEF~ THAr·~ 46
SUE: A #$3:7 4:1-4 6 NOf..J f1A-0F
CiOODH::·::
,
I END OF ROUT INE.
I
l
NUt10K SUB A #$3:121
BF.:A CiOODH~'::
BADHE::·:: ,
I
I
BADt1ES IFCC lNOT I",'ALID HE::·::..···
FCB ~3
END

What would happ en if the firs t line was CMP A #$301

---_/
When 0 is struc k on the keyb oard the ASCII code 30 woul
d resu lt.
The firs t 2 line s would then cause a bran ch to BADHEX (norm
ally
reser ved for inva lid char acte rs), since BLS BADHEX reco
gniz es
that the code prod uced is the same as 30. Such an erro
r where
a bran ch instr uctio n is inco rrect for one valu e, is very
common.
Hence a progr amm er shou ld manu ally check for boun dary valu
es,
0, 9, A and F in the abov e progr am.

The labe l GOODHX could prov ide an instr uctio n JMP NEXT,
jump ing to the next progr am segm ent. The BADHEX secti on
could
be temp orari ly term inate d by the instr uctio n BADHEX BRA
BADHEX,
an instr uctio n whic h loop s back to itse lf, prev entin g exec
ution
of "lef t over " code in that memory addr ess.
 Modify this HEXCHK program to include the necessary --
.5-6

assembler directives, this time calling the program HEX2C and

starting it at address 1E40. Show only the first and last
lines of the program.

NAr'1 HE::-::2C
-------'/
OPT 0 .. 5
OF.:G $1E4€1
HE;<:CHI< Cr'1P A #$;~:F
i
I
BADHE>::
END
Note that all 4 directives appear in the operator field. The
first label of the program does not have to agree with that
used with NAM. The latter usually designates which version is
listed, e.g., version 2C in this example. Updating the version
number when changes are made is a very effective way of denoting
which listing is the latest, an absolute essential as programs
evolve.

~
.5-7
To understand better how the branch instructions
operate one must be aware of the Condition Code Register (CCR)
in which each of the 6 assigned bits may be set or cleared
according to each instruction executed.

5 4 :3 2 1
'I""----::'-~---+----r-__+-__r-
°....-Condition
__- _ _ r
bit #
Code
Register
For example bit #0 is the CARRY or C bit which will be set if an
8 bit addition produces an overflow, the C bit behaving as the
9th bit. The C bit can be set under other conditions, seen later.
Bit #1, the oVerflow or V bit, is set if a 2's complement
(signed number) arithmetic operation produces an answer exceeding
the range of -128 10 (8016) to +127 10 (7F16)' the available range
using an 8 bit signed number.
Contd •••
 5-7
Contd.
b

The Z or Zero bit (bit #2) is set when a zero is produced

in a memory or accumulator operation, e.g., CLR A or CLR MEMPNT.
The N or Negative bit (#3) is set when a resultant
leading bit = 1, implying a negative value in the accumulator or
memory.
The I bit will be treated in the Interrupt chapter.
The H bit is used internally by the DAA instruction for
BCD arithmetic operations. (Details in Appendix K )

Each instruction executed affects the CCR bits as noted

in the right column of Appendix C where the state of each CCR
bit, after the execution of each instruction, is shown. For
example, CLR A will clear or reset (R) the N, V and C bits and
set (5) the Z bit. The dot implies no change. The vertical
arrows for the eMP instruction imply conditional setting or
clearing of these bits. For example, CMP A #$72 produces a
subtraction (ACC A minus 72) which sets the Z bit if the result
is zero or sets the N bit if the answer is negati~e an~or sets
the V bit if a two's complement overflow took place_
Detection of the Z bit status is achieved via
BEQ - Branch if EQual (Equal to Zero if no other
. reference named)
or BNE - Branch if Not Equal
as seen in
DEC A
BEQ ALLDUN
which branches to ALLDUN if ACC A = 0- Similarly BNE branches
on non-zero results when
LDA A SUBTOT
AND A #$C2
BNE t'1ATCH
is executed. Will branching occur assuming SUBTOT/JE? What is
the Z bit state,

_ _ _-.--J/
Yes branching will occur since C2-3E = 2 (not equal to zero),
clearing the Z bit and causing a branch via BNE MATCH.
 ~
Will the following instructions cause a branch to HIT
if KEDATA contains 291
LDA A I<E[:.ATA
AND A #$D6
E:NE HIT

NO KEDATA
---_/
= 00101001
D6 = 11010110
LOGICAL AND = 00000000
Since the result is zero the BNE instruction (Branch if not
equal to zero) will not cause a branch to HIT. The Z bit will
be set.

.5-9
.-
The instructions I
LDA A CONTF.:O
E: I T A #$4~~1
E:NE HIE:IT
perform the logical AND on CONTRO and 40, without modifying
ACC A. The CCR bits are affected and branching to HIBIT will
occur if bit #6 of CONTRO = 1 (not equal to zero).
XXXXXXXX CONTRO
01000000 40
t
Bit #6 is only bit of CONTRO tested.
Since the BIT instruction does not destroy the original
contents of ACC A, several bits can be individually tested,
permitting multiple branches.
Write the instructions to branch to RECEIV if bit #0 of
SERCSR is set or to TRANS if bit #1 of SERCSR is set; otherwise
continue.

---_/ Contd •••

 5-9
Contd.
LDA A SEf;,:CSf;,:
BIT A #$0:1
BNE F.:ECEIV
BIT A #$(12
BNE TRANS
,
I

,
J

5-10
Write the instructions to test bits #2 and 3 of SPEED,
branching to LSPEED if bit #2 is set, to HSPEED if bit #3 is
set or to STOPIT if both bits are cleared. Assume that both
bits will not be set at the same time.

LDA
BIT
A
A
SPEED
#t::€1000:1:1~3(1
--------'/
CHECK FOR 00
BEQ STOPIT
BIT A #~"~€10~3(1(11€1€1 CHECK FOF.: BIT #2=:1
BNE LSPEED
BIT A #~";:€100€1:1~300 CHECK FOF~ BIT #3:=:1
BNE HSPEED
I
I
I

Note that all bits of ACC A, "viewed" via the mask word, must
be zero to set the Z bit of the CCR. Hence both bits #2 and #3
of SPEED must be zero to branch to STOPIT via the above test.
The above instructions could be part of a speed control routine
for a machine, the individual bits of SPEED being controlled by
the machine's push buttons, connected to the computer.
 5-11
....-
Further branching operations will.be seen in a program
to clear a group of memory locations. In the program below,
what is the initial contents of MEMADD? What address will be
first to be cleared?
~3200 CE 23FF LOX #$240£1-:1.
0203 FF (12613 STX t'1Et'1A[:. 0
132136 FE ~326e t'10F.:CLF.: L.D:X: t'1Et1ADO
132139 08 INX
e;;:~eA FF 02613 STX MEt'1AOD
132(10 6F 00 elF.: :=-!.

020F 2(1 F5 E:RA t'10F~CLR

132613 OF.~J3 $02613

.~

0260 01302 t1Et1AorJ Rt1E: .:!.

Initially MEMADD contains 2JFF (2400 - 1 = 2JFF).

--_-----:/
INX will increment X to 2400, the first address to be cleared
via CLR X.

5-12
What address will be cleared when CLR X is executed the
second time? Explain, starting at MORCLR (second time through
here). When does this clearing operation cease?

Address 2401
-----/
When MORCLR LDX MEMADD is executed the second time X contains
2400. After INX, X contains 2401 which is stored via STX ME~~DD.
CLR X then clears address 2401.
This clearing operation will continue until the above
program is partially overwritten (cleared) by its own operation.
We need a method to break out of this loop after a specific
address is cleared. If the suspense is killing you, check the
next page!
 5-13
The CPX (ComPare indeX register) instruction compares
. t er con t ent s t 0 some 2 byte reference value, e.g.,
the Index Reg1s
CPX #$24C7
or CPX HIVALU
Only 2 branch instructions are valid after CPX, BEQ or BNE.
Modify the previous program to exit from the loop after
address 240F is cleared.

---~/
02(U~1 CE 23FF LD::< *$240~1-1 THIS F'F.~OGf;.:At'1 CLEAF~S
€1203 FF ~1260 ST:X: t'lEt'lAD(:t AND LOOPS BACK
(12~~16 FE €1260 t'10RCLF.: LDX t1Et'lA[)(:l UNTIL t1Et10F~'T' A(:l(:tF~ESS
€1209 ~j8 IN>:: 240F Ie-' CLEAF.:ED
020A FF ~3260 ST::< t1Et1ADD AFTEF~ I.oJHICH E~,::IT
1!:12~3D 6F e0 CLF.: X TAKES PLACE
0;;::0F E:C 240F CF'>~ #$240F
0:.:!::1.2 26 F2 E:NE t10RCLR
:+:
026~3 OF.:G $~1260
~3260 ~~U~102 t1Et1ADD F.:t1B 2
END

While it is true that the Index Register could remain the pointer
throughout this program, without using MEMADD, we are looking
ahead to programs where the Index Register is used for several
purposes inside one loop, requiring retrieval and storage of
each memory address pointer each time it is used.
 How many memory locations will be cleared by the
previous program?
---
5-14

10 16 or 16 10
---_/
After CLR X is executed JL Hof addresses cleared
1st time 2400 1
2nd time 2401 2
Jrd time 2402 3

15th time 240E OF 16 (1510)

16th time 240F 1016 (16 10 )
Tables like this are useful to ensure that the exit from a loop
takes place at the correct point, not one loop too soon or late.
For example, if the problem was to clear 2016 locations such a
table ensures that 241F is the correct reference address for the
exit.

Modify the previous program to clear 100 10 memory

addresses, starting at address 2400. Show only the changes.
-
5-15

CPX #$2463 is the only change.

-----"/
10010 = 64 16
Memory Address # of addresses cleared
2400 1
2401 2

2462
2463
 5-16
....-
What would be the effeci~ if the label MORCLR appeared
opposite the first instruction, e.g.,
MORCLR LDX #$2400-1
rather than in its present location? Refer back several frames
for the program.

---_/
The program would be re-initialized after each loop, hence it
would clear address 2400 each time in a continuous loop. This
is a fundamental error which ev~ybody makes at least once,
including you and me. The only question is when. More important
though is to be aware of this potential problem. The solution
can be summarized by
LOOPBACK IS ALWAYS BELOW INITIALIZATION
Initialization in the previous program sets up MEMADD with 2;FF,
its initial value. The program loops back to MORCLR, below the
initialization in the original program.
 5-17
Good programming requires good planning. While many
planning methods are advocated today, one of the simplest and
most effective is the flow chart, shown below.

Note that a flow

\N'T'AL.lZE
A t>t>ResS chart depicts
POIWTE'R
functions, not
specific instructions.
PO, NTEs:l-r X
INCPo..EMENT
ANI>
SToRE

CLEAR
MEMORY
IU)I>R£SS
HAMEl> v,~ X

Here operations such as initialization, clearing,

storing, etc., are shown inside rectangles. Decisions are
depicted by diamonds which have multiple exits, the chosen
path depending on the decision made.
A good flow chart represents the major effort in
preparing a program. Converting it to instructions, once you
are familiar with the instruction set, should take less time
than flow charting. A flow chart is also useful in documenting
a program for use by future users.
No answer is required in this frame.
 5-18
The program to clear 64 16 locations could be handled by
using a counter, with an initial value of 64 16 , which is
decremented after each address is cleared. Exit would then take
place when the counter is zero. Flow chart such a program.

---------/
IN'T"'L.12G
- COUNTE'I\
- ADI>P.'ESS

><.= UPDATE E>

At>OR6SS

CLEAR MSM
AOl>RESS
DECReME'NT
COU~Te~

To next part of longer program.

 5-19
Now write the program to clear 100 10 (64 16 ) locations,
starting at address 1200. The program itself is called MEMCLR
and should start at address 0800. Include the necessary
assembler directives. The instructions INC or DEC may be
~

useful to you.

--_-----..1/
NAt'1 t1Et·1CLF.:
OPT 0 .. S
1218121121 OF.:G

MEMCLR... CLEARS 1121121 (DECIMAL) MEMORY LOCATIONS

STARTING AT 12121121. USES X.

1!:18f1f1 B6 64 t1Et'1CLR LOA A #$64 OR LDA A #:1.(1121

121:=:1212 87 12126121 STA A COUNT INIT COUNTEF.:
f18~35 CE 1iFF LD>:: #$12e~3-1
0:=:1218 FF 121261 ST::·~ t1Et'1ADD SET UP ADDF.:ESS PO I NTEF.:.
(1E:eB FE 121;;;:61 t'10F~CLR LO::-:: t1Et'1AOD
eE:eE 1-3:::: IN::~
0E:I-3F FF 0261 ST>~ r1Et'1A[:'D GET ADDF.:ESS
1!:1812 6F e~3 CLF.: ::.~ AND CLEAF.: IT
1218:14 7A 12126(1 DEC COUNT LAST ADDF.:ES5?
1218:17 26 F2 8NE t10F.:CLF.: NO. TF.:'T' AGAIN
f
t
1!:126~3 ORG $12126(1
12126121 01211211 COUNT Rt1E: :1
0:;~61. 00~:::12 t'1Et1ADD F.:t1B 2
END

COUNT could have been incremented from 0, exit taking place when
count equals 64. Down counting is preferred since it is easier
to detect zero than a specific value (CMP A #$64). Both,
however. are valid.
 5-20
In the previous program the task was to clear an
address. In the next program the task is to count the number
of addresses, 0900 to 09FF inclusive, which contain zero. This
time the task itself will contain a decision, to count or not
to count. First flow chart, then write the program.

C\.1:AR COUNTeR.
".'T f\DDRESS 0200 7F 0262 ZCOUNT CLR
---~/BLANt< EMPTY COUNTER
POIMTSR 0203 CE 0::::FF LD:~ #$1219£1£1-:1
1212"~6 FF ~126121 ST::-:: t'1Et'1PNT INIT ADDRESS POINTER
0209 FE €126£1 t'10~:CHK LD;:':: t1Et'lPNT
020C £1:::: IN:>::
X =UPbATE.D £12£1(:1 FF 026121 ST::-:: t'lEt1PNT GET NEXT ADDRESS
ADDRESS "32:1£1 A6 "3121 LDA A X GET ITS CONTENTS
£12:12 26 ..3 3 BNE SKIPIT NOT ZEF~O
1212:14 7C 121262 INC BLANK GOT ONE
02:17 E:C e9FF SI<IPIT '::F·::.:: #$"~19FF LAST ADDFi:ESS?
02:1.A 26 ED BNE t10RCHK NO. BACK AGAIN
I
•
13260 OFi:G $0260
f126"~1
1210132 t'1Et'1F'NT ~:t'1E: 2
0262 00€1:1. BLANK Rt'18 :1.
END

ACC B, if available. could

have been used as the counter.
 5-21
When the possible count exceeds 255 10 (FF 16 ) two bytes
will be necessary to contain the number of bits. A problem in
incrementing a 16 bit (two byte) counter exists when the low
byte overflows to zero, at which point the high byte must be
incremented, e.g., ~
~ Least Significant
Before ~ 00000010 11111111 Byte
After
Incrementing~ ~ . .oooo~oo~
Count Count +1
Modify the previous program to count the number of addresses
containing zero in the address range 0900 to 10FF inclusive.
Show program changes only.

Before
---~/ After

ZCOUNT C:LF~ BLANK ZCOU~~T CL~~ BLANK

I CL~~ 8LANt<+1.
I •I
I INC BLANI<+1.
I BHE SKIPIT
INC BLANK INC BLANK
S~(IPIT CPX #$09FF S~(IPIT CP:X: #$:10FF
I
,
I

BLANK Rt1B :1- BLANK Rt18 2

·rhis process can be extended

to a J byte counter.
 5-22
The Index Register also can be used to increment a
2 byte counter. What changes would you make from the previously
modified program to use the Index Register to increment BLANK?
Again show only the program changes.

Before
---_/ After
INC BLANK+i LDX BLANk:
BNE SKIF'IT IN>~
INC BLANK STX BLANK
SKIPIT SKIPIT

If BLANK is to be tested or compared later. the Index Register

will be needed... for that operation. Hence the second solution,
using the Index Register. is preferred.
The second solution shows how the Index Register can be
used for many tasks within a program since the updated value
(after INX) is immediately stored in memory. releasing the Index
Register for another task.
 5-23
Assume that the instruction JSR GETCHR, a subroutine
call which we'll examine in detail in a later chapter, puts the
ASCII code for the key, struck on a keyboard, into ACC A. Use
this instruction within a looping type program to store in memory
the ASCII codes for the keys struck. Start storing data at
address 1200. When the! key is struck. exit from the loop
without storing this terminator character. First flow chart
your program.

\NIT
_ _ _-----01'/
GETCH~: EG~U $~F00
"1)1)RESS
PO'"T&~
STOASC... STORES ASCII CODES FROM KEYBOARD
IN SUCCESIVE MEM ADDR STARTING AT ~200.
! TERMINATES PROGRAM.
CALLS GETCHR. USES A AND X.
GET CHAR
STOASC L[:'~: #$1.2f10-1.
5T:)~ ADDRES INIT POINTER
GETt'10F.: JSF.: GETCHR GET ASCII CODE
Ct'1F' A # .., !
BEG! ALLDUN MUST BE !
LD::"~ A[:'D~:ES
IN::·::
ST::< ADDRES UP[:'ATE ADDF.:ESS
.....
STA A .... AND STORE ASCII CODE
x: UPoA,eo BRA GETt10~: AN [:a BACK AGA I N.
PO'HTER ALLDLIN
STORE CH"~
ADDF.:ES Rt1B 2
Here the test takes place before
the task, to avoid storing the !
character.
 5-24
Branching instructions recogn~z~ng signed (~) values area
BGE - Branch if Greater or Equal
BGT - Branch if Greater Than
BLE - Branch if Less than or Equal
BLT - Branch if Less Than
BPL - Branch if PLus
BMI - Branch if MInus
Flow chart a program to count the number of
occurrences of values between! 26 16 inclusive, within the
memory range 0800 - OBFF inclusive. Manually check your program
for proper branching for values of !26 and ±27.

---_/
SET up L'M'TS
I N I" ADOk POINT
CLEAR COUNTER

)(: UPDATED
ADDRESS
GET CONTE"'TS
 5-25
From your flow chart on the previous page, write the
program.

_ _ _..----.J/
MEMCHK. . . COUNTS OCCURRENCES OF +26 TO -26 HEX
IN MEM ADDR 0800-0BFF INCLUSIVE

02121121 86 26 t1Et'1CHK LDA A #$26

£12~32 87 £1271 STA A HILIt1 SET UPPER CHECK VALUE
0205 4~3 NEG A
021216 E:7 02;~0 STA A LOLIt'l SET LOI.a~EF.: CHECt< '·.·'ALUE
02~39 7F 1-3274 eLF.: HIT
1-320C "("F &::1275 CL~: HIT+:t
t!.120F CE 07FF L.D>:: #$080121-1
~:::1212 FF 0272 ST~-.:: t'1Et'1PNT INIT PO I NTEF.:
121215 FE 0272 GET8'T'T L[:IX t'lEt1PNT
"32:18 fiE: IN>-~
~3219 FF ..:::12?2 ST~<: t1Et'lPNT GET NE>::T ADDF.:E5S
021C A6
t12:tE 8:t
&::10
£1271
LDA A
Ct1P A
>~
HILIt'1 .... ..
GET CHAF.:
_... - -....
~t.:. 'f

£1221 2E ~:::1C BGT NOHIT IF SO IGNOF.:E IT

£1223: 8i "32(?~:::1 eMP A LOLIt'1 <26?
~1;;;::26 2(:' €1~::' BLT NOHIT IF SO IGNOF.:E IT
..:::122:=: FE €1274 LD::< HIT
"3228 121' ='
- t_, IN~<:
€122C FF £1274 ST~"t, HIT ADD i TO HIT
"::1~:2F FE (127:2 NOHIT LD:~ t'1Et1PNT
0232 8C €1BFF CF'>~ #$0E:FF
k1;;::3:5 ~:6 DE BNE GETBIT'T NO.. BACI< AGAIN

£12';:'0
02710 '3(11.::11 LOLIt.., F~t"'B 1
10271 121001. HILIt1 F.:t·lB :1
0272 a;:n3f12
0274 ~:::n3f12
t1Et'lPNT Rt1B
HIT F.:~18
.-.2
~
 5-26
Previously we saw how to store a message in memory. It
is time to print such a message. For now, assume that the
instruction JSR PRINT, a subroutine call, prints the contents of
ACC A as one ASCII character on a printer. Assume that the
label MESSAG heads a stored message, in ASCII format, terminated
by a null. Flow chart and write a program to print this message,
using the JSR PRINT instruction. If you are stuck, look at the
first two instructions of the solution

IN'T POINTER
------J/
MESSPR... PRINTS MESSAGE THAT IS STORED IN MEMORY.
CALLS PRINT SUBROUTINE FOR EACH CHARACTER PRINTED.
TO MESSAGE
USES A AND X PLUS PRINT SUBROUTINE.
Lei?::
t1ESSPF.~ #t1ESSAG-:1.
ST:X: POI~TR INIT MEM POINTER
MORPRT LD>:: POINTF.:
x= UPDATED INX
PO\NTER ST>:: POINTF~ GET ADDRESS OF CHAR
GeT CHAR. LDA A '.J
...., GET ASC I I CHAF.: INA.
BEG! ALLDUN
.JSF.: PF.:I NT PF.: I NT IT
BF.:A t'10F.~PF.:T BACI< FOF~ MOF~E
ALLDUN
I
I
POINTF.~ ~:t1B 2
t1ESSAG FCC . . . FILENAME?...1
FeB o
PR'NT CHAR Note the test before printing
to avoid trying to type a null
which cannot be printed.
 5-27
Data stored on a diskette, a magnetic mass storage
device, is usually written in blocks of 80 16 characters at a
time from a buffer. which is a specific block of memory. In
such an operation the X register must be used both for
retrieving data from the "source" memory address and for storing
it in the "destination" address. For this 2 pointers must be
initialized. For each byte moved. each pointer must then be
updated for use by X. With this in mind, flow chart and write
a program to move the memory block 0600 - o6FF to 0800 - 08FF.

, N\T SOURCE t'10VEIT LDX

---~/
#$(160(1-1.
ANO DESTIN. ST:X: SOURCE INIT SOURCE ADDRESS
POINTER.S
L[:.:>:: #$~~1:30€1-:1
ST::-:: OEST INIT DESTINATION ADDRESS
t'l0 1",1 E:'T1T L[:e::-:: SOUF.:CE
UPPATE
SourtcE IN::-::
P01NTER ST::-:: SOURCE GET NEXT SOURCE ADDRESS
G-Ei 8YTE LOA A X GET A BYTE
LD;·:: DEST
IN::·::
UPDATE ST::-~ DEST GET DESTINATION ADDRESS
DES-rlWAT lOti STA A AND STOF.:E 8'T' TE
POIr.'TE~
CP::·:: #$"~1:3FF LAST B'r'TE?
STORE 8'C'TE BNE t10VB'r'T NO. AROUN[) AGA I N
I
,
I

I
SOUF~CE F.:t·lE: 2
DEST Rt'lE: 2
END
 Earlier we saw how to increment a 2 byte counter
-5-28
without using the X Register. Similarly a 2 byte counter can
be decremented without using the X Register. A special
condition, shown below, exists when the least significant byte
is zero, before decrementing, since both bytes will have to be
decremented this time. Least Significant Byte
.~
Before Decrementing 00111011 00000000
After Decrementing ~ ,111~111.1
Count Count +1
Write the instructions to decrement the two byte counter COUNT,
recognizing the special condition above. The instruction TST
(TeST or "compare to zero") is useful here.

--_----.J/
TST COUNT+1. CHECK LEAST SIG BYTE FOR ZERO
BNE DECLOW IF NOT e IGNORE MOST SIG BYTE
r.. EC COUNT IF LEAST SIG BYTE e DEC MOST
DECLOW DEC COUNT+1 ALWAYS DEC LEAST SIG BYTE

This sequence of instructions is most useful if a 2 byte counter

must be decremented when the Index Register is not available to
do it. This process also can be extended to a 3 byte counter.
 5-29
The program listed below is a slightly shorter version
of HEXCHK, developed earlier in this chapter. This one uses
signed branch instructions which had not been discussed when
the original program was developed.

HE>::CH~( SUB A #$30

BMI BADHE>:: BELOleJ 313
Ct-1F' A #$09
BLE ENDHE>:: BELOI.oJ -. -
-::.3. ABO.....E 313
SUB A #$137
Ct-1P A #$0F
BHI BADHE~-:: 46-30-7=€1F. ABO.....E F
Cr-1p A #$09
BLE BADHE>( 4:1-30=0A 8ELOl.oJ A

ENDHE:x:
BAC'HE::·(

Since either 30 or 37 had" to be subtracted to convert

to hex, )0 was subtracted immediately. Branching on a minus
value is now possible, eliminating a COOP instruction. While
the purpose of this workbook is to help you learn fundamentals
rather than write "tight" programs, the above listing is
included to point out that the shortest programs are not
necessarily the most readable and vice versa.
Time for a break. This was a long chapter.
 BRANCHING - MACHINE CODE
Even when writing very short machine code programs it
is highly desirable to start with assembly language instructions
and then assemble them into machine code. Manual assembly of a
program raises a problem in that the address for MEMADD in the
instruction STX MEMAOO is often not known until MEMADO RNIB 2 is
encountered, perhaps many instructions later. The solution
proposed is the one used by the computer when it assembles a
program, that of processing the assembly language program twice.
When the assembly language program is read the first time, an
absolute address is assigned to each label (symbolic address in
label field). During the second reading, machine code is
produced for each instruction.
To assign absolute addresses to labels requires knowing
how many bytes each instruction requires. This data is available
in Appendices C1 and C2, under the # column, for each mode avail-
able. Assuming Extended Mode for the instruction LDX MEMPNT, we
see J in the # column for the "EXTNO" mode opposite the LDX
instruction.
For the program below assign the appropriate addresses,
starting at 0618. Addresses already are assigned to the first
2 instructions.
06:18 INIT LOA A #$1.7
(161A STA A END VAL
L.[:,~< #$€16D7
ST>~ t1Et1ADD
RTS

/
ENDVAL F~t'1B :t
tolEt'1ADD Rt1B 2

0618 INIT l.DA A #$17

061A STA A END'·lAL
061.0 LO~'~ #$0607
062€1 ST:X: t1Et1ADD
0623 RTS
0624 END...·'AL F~t18 :t
0625 t'lEt'lADD ~:t'1B 2
 Now that all addresses are known, complete the assembly -
6-2

operation by assigning the machine code for each instruction.

No entry is required for the labels ENDVAL and MEMADD at the
end of this program.
06:L:=: INIT LDA A #$1.7

ti6iA STA A EN[:IVAL

":361D L())·:: #$06D7

"~1620 STX t1Et'1A[)[:'

103623 ~~TS

0624 EN[:IVAL Rt1B :1

0625 t,otEtil AD[:r Rt1B 2

/
0618 86 17 INIT LDA A #$17
:+:
e61.A B7 0624 STA A ENDVAL
:+:
1o:::161.D CE €16D7 LDX #$06()7
:+:
e620 FF 121625 ST::-:: t'lEt1ADD
:+:
€i623 39 ~:TS
:+:
0624 ":300:1 EN[)VAL Rt18 1
:+:
1216~~5 01211212 t1Et1A[:t[:' Rt18 2
 6-3
...-
In general it is easy to work with the machine code for
the 6800 microcomputer. Only one area, that of encoding branch
instructions, requires extra care. In the instruction sequence.

:186F 8C 1.A7F CPX ISTART

1.872 26 1.36 BNE STORTN
1874 CE 1.E:78 L[:'X #8IGSOR
1877 8D 1.F0C .JSR OUTt'1ES
:t:=:7A 39 STOF.:TN F.~TS

the code for BNE is 26. The next byte, 06, is a forward
reference to STORTN, 6 bytes beyond the byte following 06.
Better read that again! When the microprocessor has fetched
06 from memory and is processing it, to determine the address
to which to branch, the program counter (PC) contains the
address of the next byte, 1874. It is 6 bytes (hence the 06)
from 1874, the PC contents, to 187A, the address of STORTN.
2 4 5.-~ 6
1873 1874 1876 1878 1879 187A
06
t
while proCeSSing" PC. points
t
address of
this byte :J here STORTN
If STORTN is at address 187E instead of 187A, while the
BNE instruction remains at the same address, what value is in
address 1873, the forward reference to STORTN for the BNE
instruction?

OA
--_---..J/
187E - 1874 = OA ~ branch offset
target address~ addtess following branch offset
 -
6-4
Backward branching is somewhat more challenging. e.g ••

1.A8aa 86 7FF6 t10RTES LDA A SEF~CSf;.:

:1.A83 84 ~~11. AND A #$131
iA85 27 F9 8E(;J. t'10RTES
1.A87 86 7FF7 LDA A SERBUF

While processing the branch offset F9 (address lAS6) the PC

contains lAS? the address of the next byte. The target
address is lASO, ? bytes backward from the PC value. Hence
F9 (-7) is the branch offset.
To determine this value, F9. the most direct method is
to calculate lA80 - lAS? resulting in FFF9 as a 2 byte negative
value which contracts to F9 as a one byte negative value (refer
to the first chapter for 2 versus 1 byte negative numbers).
For short backward branches the number of bytes can be deter-
mined by counting from lASO to lAS7. e.g ••
@ CD®
iA8aa 86 7FF6

:tA83: :3fjJ t1fY

iA85
® @
27 _
CD
iAB? 86 7FF7

Since the separation is 7 bytes then -7 can be converted to F9.

The missing value above then becomes F9. For more than a dozen
bytes this may become tedious. For short branches, however, it
is simple and quick.
No answer is required in this frame.
 With more experience in using machine code, you may
prefer to count the number of bytes backwards instead of forward
-
6-5

to obtain the branch offset directly. Using the previous program

this would bea
~~l@
1.A80 ~ 7FFt'
1.A83 &?fi>
1.A85
@@
2( -- .. F9 then follows the 27
1.A87 ~...)
Using the above technique determine the machine code for
the backward branch below. The address for LOOPNO is lA60.

02013 7A :1A60 NOTYET DEC lOOPNO

02133 27 BEQ NOTYET
(12£15 4F ClF.: A

/
G>~e
02013 7H :1 60 NOTl.r'ET (:.EC lOOPNO
02€13 @~
2,· F: * BEQ NOT'r'ET
02~35
4(i):J * ClF.: A
*
 NEXCHR JSR GETCHR Manually assemble the program
(opposite) using both the first
-6-6

LDX MEt1A[)D
and last methods to determine
IN>::
each branch offset. Machine
STX t1Et1ADD code for JSR GETCHR is BD tFOO
LDA A X and for JSR OUTERM is BD lFOJ.
Start at address 0740.
CMF' A #$00

BEQ ENDLIN

.JSR OUTERt1

BRA NEXCH(;:

ENDLIN RTS

MEMADO Rt'1B 2
/
a.3f1 FF FE 12:1740 BD :1Fa.~n~1 NEXCHF.: .JSR GETCHF.:
*=
FD Fe FE: 12:1743: FE 0756 L[:a>:: t1Et'1ADD
:+:
FA 0746 1.38 IN>~
:+:
F9 F8 F7 (1747 FF 121756 ST>:: t1Et1AD[:a
:+:
'.}
F6 F5 (174A A6 0(1 LDA A .'.,
:+:
F4 F3 1-~174C :=::1 a.3D C~1P A #$&;:1[:1
:+:
F2 F:1 074E 27 1-35 BEG~ ENDLIN

F0 EF EE (1750 B ~
f :1~..z,~.
@* JSR OUTEF.:t'1
:+:
Q) ®
ED EC (1753 20 EB
:+:
EE: (1755 RTS

\ ,/ 0756 0002 Rt'1B 2

V 0740 FFFF
~~ END
+
Backward
i t
address machine
-.Q.Z.5..2 ~ -.Q.Z.5..2
=F8AA
branch code
counting +---1
(last 0755 F8AB
method)
-.Q.ZjQ +0740
5 ~FFEB
(forward reference) ~

but FFEB (in 2 byte format) becomes EB in 1 byte format (see

Chapter 1). Normally JMP NEXCHR rather than BRA NEXCHR would
be used to avoid offset calculations.
 Branch instructions use a one byte signed offset,
limiting the branching range to !127 (decimal) addresses.
-
6-7

Attempted branches beyond this range produce an error at assembly

time. Sometimes programs which were previously error-free now
will cause a branching error when new instructions, inserted
between the branch instruction and the target address, now
produce too great an offset. One solution is to branch to the
end of the present routine, or some other appropriate place
where a ~~P (JuMP) instruction, which can jump anywhere, jumps
to the target address.
Such a solution is also one way to avoid backward
branching in machine code, a pragmatic if not aesthetic solution.
Similarly BSR should be replaced by JSR when writing in machine
code unless memory locations are scarce.
Assume that NUCHAR, at address 0608 is beyond branching
range of BEQ NUCHAR, below. Modify the program to reach NUCHAR.
Show your changes in machine code.

~:)2~Je~ E:1 ~~1A Ct'1P A #:f.~]A

:+:
1;:,2t!~~:: '-,-:0
.:::.,' BEG! r·JUCHAF.:
:+:
~12~34 BCI iA64 .JSF.: STOF.:E
:+:
Cl2~:f?

02~~1'j
3:9

E:1 ~~1A
F.:TS
/
~+.

213(,27 134) ..
11:1 BEG! .JUr'lPNU Changed lines
:+:
02~Z14 BD :1A64 .JSF.: STOF.:E
are circled.

F.:TS

.Jt1P NUCHAF.:
 --
6-8
A problem often encountered in writing machine code
programs is the need to insert a few instructions in the middle
of a program. This results in new addresses for all labels
below the insert (on the listing) requiring re-encoding of the
program.
To prevent or minimize such problems it is desirable to
leave memory address gaps between subroutines or program segments,
typically 1/4 the length of the code written. Where instructions
follow one another continuously for more than ten lines, insert
several Nap (No OPeration) instructions (OP CODE 01) which do
absolutely nothing except to occupy memory locations. These are
easily removed when extra addresses are required for later
changes. The only cost is the extra memory used and slower
execution.
When re-assembly is undesirable or impossible a PATCH is
recommended. This involves a jump to some external address,
where the extra instructi"Ons are placed, followed by a "jump back"
to the address just below the first "jump out". The cost is
usually 6 bytes (2 jumps) plus the inserted code. In the program
below a CLR COUNT instruction is needed just after STX ~mMADD.
Modify the program below to patch in the extra instruction
assuming that COUNT is address OOFF and that addresses 0680 - o68F
are available. Write both .the assembly language instructions and
the machine code for the patch.
1361313 CE i34E LOX #$i34E
0603 FF 136213 STX MEMAOO
13606 FE 0620 LOX MEMAOO
06139 08 INX
0620 t'lEt1ADD EG~U $0620
/
0600
0603
0606
0609
0680
0680
CE i34E
7E 0680
FE 062€1
08

FF 136213 PATCH
r
.
LDX
, ~Tt1P
LDX
IN>::
ORG
STX
l$i~4E
PATCH ,
MEt1ADO

$06813
t'lEt1ADD
13683 7F e0FF CLR COUNT
13686 7E 0606 .JMP $0606
 The problem below presents a condition where memory -6-9

locations for a patch are very limited. Assume that 5 bytes

are available (0470 - 0474). The instruction CLR B is now needed
between the first 2 instructions. In your solution show assembly
language and machine code for changes made. If you are stuck,
look at the hint in the first line of the answer.

£14£10 8D 1.F0(1 .JSF.~ TEF.~t1 IN

134133: 84 5F ANCI A *$5F
0405 :=::1 4C Ct1P A *··-L

---~/
Hint. Use branch rather than jump instructions.
Calculations
(1) 0470 - 0405
FFFF
-0405 €14~]f1 BD l.F~::10 JSF.: TEF.:t'l I N
04~(:t ~;~~~~ 68 BF.:A
FBFA PATCH
~14~15 ::::t BACK Ct'lF' A #'·L
+__1 £14-;::'121 OF.~G $047~3
~14?t1 5F PATCH
FBFB CLR 8
0471 84 AND A #$5F
+0470 121473: E:F.~A BACK
006B
(2) 0405 - 0475
FFFF
-~
FB8A
+ __1
FBBB
+0405 Since only 5 locations are available
FF90 . 90 branch instructions (2 bytes per branch)
would just fit. Such situations are quite
common when modifying old programs,
particularly if source listings are
unavailable.
 The previous example shows how the program counter
.......
6-10

contents, when added to the branch offset, produces the address

of the next instruction to be executed, e.g.,
0405 = PC
+ 6B = branch offset
0470 = new address (where PATCH begins)
Reverse branching calculation is slightly different. Since 90
is a negative value, its 2 byte equivalent is then FF90
0475 = PC
+FF90 = branch offset (2 byte format)
0405 = new address (BACK)
Given the following machine code, convert it to assembly
language producing absolute rather than symbolic addresses.
Appendix D gives the instruction for each operation code.
:iF49 81 ~:;'4
1F48 27 (14
1F4D 8D (19
1F4F 2(1 EC

_ _ _----.J/ lF4D
lF49 :::1 (14 Cr'1P A #$04 +~ lF4F
1F48 27 1-:;'4
lF4D 8D (19
8EG'~
8SF.~ $1F58
$1F3D
-...,,"f"---lF51 _lF58
$:1F5:1 ~~~- +~

lF4F 2(1 EC E:~~A

") lF51
Only negative values must be ~+FFEC note Ee becomes FFEC
preceded by FF in 2 byte IF)D in 2 byte format.
format.
If more practice is needed, there are lots of listings
in the last half of this workbook.
 - ACIA - ---7-1

ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER

A computer, to perform any useful function, must be able
to communicate with the "outside world", that is to and from
external devices such as keyboards, printers, teletypes, remote
computers, etc. Two forms of information transfer are available,
serial and parallel. Parallel format, in which 8 bits are
transferred at one time, requires 8 external data lines, plus
control lines. For transmission of data beyond several hundred
feet the large number of wires in a cable makes this parallel
transmission impractical. In such cases serial transmission is
preferable. For data transmission over a telephone line serial
format is essential, since only one channel is available.
In serial format data is transmitted at a predetermined
data rate, one bit after another. Each character or byte
(usually 8 bits) is self contained, preceded by a start bit
(always 0) and terminated by one or two stop bits (always 1).
In between successive characters the signal remains in the 1
state, if there is a pause. A typical character is seen below.

rime ---... r,(l is also known as MARK, 0 as SPACE)

'ol~~-LiJ STAll ,-Si\ "', "'1.. .. ~ "'t tl5 q.~ ~7 St'oP ~,\-(iP
a,r P.uT '~,1

The ACIA acts as the interface between the serial device

and the computer, communicating with the serial device in serial
format and with the computer in parallel format.
Associated with the ACIA are 2 consecutive memory
addresses, the lower one (even) controlling and indicating the
status of the ACIA and the higher one (odd address) containing
data transmitted or received by the ACIA. The actual addresses
are usually in the top half of memory and are assigned by the
hardware designer.

Contd.
 7-1
Contd.
Let's look at the Data Buffer first, assuming an address
of 7FF5 for the ACIA Data Buffer "SERBUF". This single buffer
services 2 internal buffers, receiving data from the "read only"
RECEIVE BUFFER. and transmitting data to the "write only"
TRANSMIT BUFFER. The same address is used for both buffers
(see below). Hence the instruction LDA A SERBUF automatically
gets its data from the RECEIVE BUFFER. while STA A SERBUF
automatically passes its data to the TRANSMIT BUFFER.

RECe\ve ~\JFFe~
( i).EA 0 ONL.'()

TRA NSM IT B"Fi=E.R

ACtA
D"7A BUFF i:R..
l ~4cl~e~~ "IFF S \>~\c)",,)
~V'Clns ~;11 eeA set ..o.l dc:..tCc
"itAIVS~11 '""N'e

Write an instruction which sends data, now in ACC A to

the ACIA where it will be automatically put into serial form
and transmitted to some external device.

STA A $7FF5
----'/
All that for one instruction!
Symbolic addresses are preferable when working with the ACIA.
lrhe statement
SERBUF EQU $7FF5
directs the assembler to substitute 7FF5 for the symbolic
address SERBUF. To improve readability of programs it is
usual practice to place all "EQU" assembler directives at
the beginning of a program.
Address 7FF4 is known as the Control and Status Register,
described in detail later in this chapter. Arbitrarily it is
called SERCSR (SERial Control and Status Register).
 7-2
Write an instruction to read serial data from the ACIA
into Ace B. Assume previous symbolic definition of the Data
Buffer.

LDA B SERBUF
----'/
Note that if STA A SERBUF
LDA A SERBUF
is executed, the data in ACC A will normally change since data
is stored in the TRANSMIT buffer but loaded from the RECEIVE
buffer, even though both carry the same symbolic address SERBUF.

-----
If serial data is being received by the ACIA, some
7-)

method is necessary to inform the computer when parallel data

is ready. If data is read too soon it would be erroneous; if
too late it could be lost, since the ACIA has only one 8 bit
RECEIVE buffer where parallel data is stored after being
formed from the incoming serial bit stream. At high serial
data rates, e.g. 9600 bits/sec, the "lifetime" of data in the
RECEIVE buffer is approximately 1 millisecond, after which it
is overwritten by the next byte.
When an incoming data byte is ready, bit #0 of the
Status Register (7FF4) automatically changes from 0 to 1. The
AND or BIT instructions permit us to examine this bit #0, or
"READY" bit, of the ACIA Receiver. It is normal practice to
to test this bit in a looping manner, exit from the loop
taking place when bit #0 = 1, that is when data is ready.
Write the instructions to examine bit #0 of the Status
Register. (No branching yet.)

LDA A SE~:CSR
----.-,,/
AND A #$121:1
 7-4
.....-.
Now add instructions to cause continuous testing of
bit #0 until data is ready, whereupon the data is to be
transferred to ACC A.

---~/
INLOOP LDA A SEF.:CSF.:
AND A #$0:1
BEG! INLOOP
L.DA A SE~:E:UF
lJ)51) .,
-DATA READY.
Reading of the data from the RECEIVE buffer, SERBUF, clears the
READY bit, sometimes referred to as a READY FLAG or DONE FLAG.
A timing diagram of these events is shown here.
few if repeated in a looping
RECEIVER
READY
BIT
bit#
1 ---
microseconds

fJ
~~

n
type program
,...,-__--.A.------..
~

o { 1/ -_........ ---
Goes to 1'\ ~utomatically Data'\ \Data is read
when dat~} cleared when READY into ACC A
is READY data is read, (LDA A SERBUF)
in Data e . g. ,
Buffer. LDA A SERBUF.
Although the rate of transmitting and receiving data bits is fixed
ther~ may be long time gaps between successive characters. Hence
the term "asynchronous" in the ACIA, meaning no specified number
of characters per second.
 7-5
. -
Data to be transmitted in serial form by the ACIA should
not be transferred to the ACIA's TRANSMIT data buffer until this
buffer is empty and therefore ready to accept a new byte. Bit #1
of the Status Register is the transmitter's READY bit. When in
the 1 state, it denotes this READY condition.
Write a short program to put the byte now in ACC A into
the TRANSMIT buffer when the transmi·~ter is READY. Warning.
Don't destroy data now in ACC A while testing for the READY
condition.

OLOOP LDA B SEF::CSR

-----'/ I
ANCI B #$02 T~< F::EAD'r ?
SEQ OLOOF'
STA A SER8UF OUT TO TX
E~~Ca

The use of ACC ~ preserves the data in ACC A

printing time, based on
predetermined data rate

Transmi tter READY '; of ~t:'CIA ~ I

bit normally 1
while waiting for
data.
j _
t
,
0
READY bit goes to 1
STA A SERBUF when transmission of
character is complete.
Note that the transmitter, while dormant, is normally READY,
waiting for data from the computer. In contrast, the receiver
in the dormant state is normally not READY, since it is waiting
for new serial data from the external device.
 7-6
Now write a s~ries of instructions to echo serial data
from the ACIA RECEIVE line out on the ACIA's TRANSMIT line.

--------/
$132013
:+:
:+:
:+:
7FF4 SEF.:CSF.: EG!U $7FF4
7FF5 SEF.:BUF EfJ.U $7FF5
:+:
020f~ 86 7FF4 INLOOP LCJA A SEF.:CSF~
13203 84 €Ii. AND A #$131. R:ECE I VEF.: F.:EAD'-r'?
€12€15 27 F9 BEQ INLOOP
1212137 86 7FF5 LDA A SEF~E:UF GET CHAR IN A
020A F6 7FF4 OLOOP LDA B SEF.:CSF.:
020() C4 02 AND 8 #$f:l2 T:xi F.:EADY?
02€1F 27 F9 BEG! OLOOP
12121:1 87 7FF5 STA A SEF.:BUF OUT TO T·"J.
....
END

This is often known as an ECHO routine, permitting data which

is entered on the keyboard to be viewed by the user.

To make this program more readable, the instruction

AND A #$01 could be replaced by AND A #RXREDY, if
RXREDY EQU $01 is included in the above definitions. Similarly
AND B #$02 could be replaced by AND B #TXREDY.
 Sometimes data, received by the ACIA must be stored, --
7-7

byte by byte, in memory. Flow chart and write a program to do

this, the first byte going into address 1000. For now assume
no end to this looping type program.

I N'T'A~'%E
----'/
ADDRess L[):)'~ #$1.000-1.
pOIN1'eR
5TX MEMADD SET UP ADDF.:ESS POINTEF.:
t10F.:TES LDA A SERCSF~
AND A #$~31. F~:X: DATA REAr..y?
8EQ MOF.:TE5
LI)A A 5ERE:UF GET CHAF~
NO LD~·!.
OUTER t'1Et1ADD
~OOP IN::-::
5TX t'1Et1A [:1 D AND NEI.oJ ADDF~ESS
STA A >~ AND STORE CHAF.:
BRA t10F.:TES BACt< FOR r·10F.:E
SToRe IT
RME: 2
IN END
HE t.-r AODRESS

Here we see an inner loop testing the READY bit and an outer loop
storing data. 'fhis is known as a "nested" loop format.
 .ll
Modify your program such that receipt of 5A will cause
storage of this byte, then exit from the loop. Show changes only.

Before
---_./
After
BRA MORTES cr1P A 1$5A IS IT Z?
BNE t"10RTES

If your modification looked like thisl

CMP A 1$5A IS IT Z?
BEQ NEXT
BRA MORTES

note that a conditional branch (BEQ NEXT) followed by an

unconditional branch (BRA) can usually be replaced by a
single branch instruction (BNE MORTES) of the opposite sense
(BNE vs BEQ).
Although the ASCII code for Z is 5A some terminals
produce "mark parity", that is the leading bit is always set,
resulting in DA rather than 5A. Other terminals may produce
"space parity" (leading bit is zero) or odd or even parity,
discussed a few pages later.
 The computer when connected via the ACIA to some output --
7-9

device such as a printer or CRT terminal could send a specific

message to the computer operator.
Flow chart and write a program to output the message
BAD HEX CHAR to such an output device via the ACIA. Terminate
the message with a null.

7FF4 SERCSR EQU

----"/ $7FF4
7FF5 SERBUF EI~U $7FF5
IN IT'''L''Z.&
ADI>RESS * LOX #t1ESBAD-1
POINT&R
ST:>:: MEMPNT INIT MESS POINT
P~:Tt'10R LD>:: MEMF'NT
IN>~
GET HE",. STX t1Et1PNT GET POINT ADDRESS
BYT~ F5\OM
l1eMORY
L(:IA A x GET CHAR FROM MEM
BEQ ALL[:IUN G~UIT IF NULL
OUTEST LDA E: SERCS~:
AND B #$02 OUTPUT DEVICE READY?
:0
BEQ OUTEST NOT 'TIET
STR A SERBUF YES OUTPUT IT
BRA PRTt10F.:
t1Et1PNT Rt1B
MESBAD FCC . . . BAD HE:>:: CHAR.. .
FeE: &3
ALLDUN
 7-10
To operate the ACIA correctly the data rate at the
receiving end must be within 1 or ~; (5% would produce errors)
of the transmitted data rate. Hence the frequency of external
oscillator which determines the basic data rate for each ACIA
is usually crystal-controlled. as in modern electronic watches.
Selection of data rates and control operations are
possible via the Control Register. a "WRITE ONLY"
register which shares the same address as the
"READ ONLY" Status Register. The diagram at the
left depicts these registers. assuming 7FF4 as the
assigned address. Hence LDA A $7FF4 reads from
7FF't the Status Register, while STA A $7FF4 stores in
\" ~iS
exaDlplt the Control Register. The common symbolic address
in previous examples has been SERCSR.

The data rate of the ACIA is determined by dividing

the external oscillator's frequency by 64, 16 or 1, under
control of bits #0 and 1 of the Control Register (see App. E1).
For example, if bit #1 is 0 and bit #0 is 1 (i16 mode) an
oscillator frequency of 9600 bps would produce a data rate
of 9600/16 = 600 bps.
Assuming that all other control bits are correctly set
ensure that the ACIA will operate at a data rate of JOO bps
when the oscillator frequency is 19200 Hz (cycles/sec).
Since the Control Register cannot be read to be modified. assume
that it is updated from ACIACR. a symbolic address in memory.

_ _ _----J/
GET ORIGINAL STATUS
01.1313 B6 738E LDA A ACIAC~~
131.03: 84 FE AND A CLEAR BIT 0
#~:11.:1:1:11.:10
0:1'.::15 SA 02 ORA A #~~000000:10 SET BIT :1
131.1217 87 738E STA A ACIACR UPDATE OF~IGINAL
01.0A 87 7FF4 STA A SERCSF~

19200/300 = 64
Therefore bit #1 = 1 ) See
bit #0 = 0 )- Appendix
in the Control Register} E.
If both bits are 1 RESET takes place. This is necessary when
power is first turned on, before changing speed, parity, etc.
 7-11
Bits 2, 3 and 4 (see Appendix E) determine the number
of data bits and stop bits of the data format. It also
determines the parity options for the data. Parity control
determines whether each transmitted data byte carries an even,
odd or unspecified number of ones, bit #7 of the data being
modified to produce odd or even parity.
The number of data bits and stop bits, plus parity
options must be agreed upon for both ends of the data link.
Although programmable, they are not usually changed once a
data link is set up.
Without disturbing unspecified Cpntrol Register bits,
set the ACIA for 1200 bps operation using a 19200 bps oscillator.
The data formed is to be 7 data bits plus l' odd parity bi t plus
1 stop bit. Again use ACIACR as the original for the Control
Register.

121:1.013 86 738E LOA A

---_/
ACIACR GET ORIGINAL STATUS
0:1.03 84 ED AND A #~~:1.1e1:1.01CLEAR BITS :1. AND 4
&Z1:1.05 8A e[) OF.:A A #%01210e1101 SET BITS 0~2 AND 3
01.07 B7 738E STA A ACIACR UPDATE ORIGINAL
0:1.0A 87 7FF4 STA A SERCSR CHANGE CONTROL REGISTER
7 6 5 4 3 2 1 0 1 - bi t /I
I X X X 0 110 1[
'--v-' "v-'"

7 data -:16
odd
1 stop
For your first few programs, which are not part of a larger
program, simply place the desired value in the Control
Register e.g. LDA A #%00001101
STA A SERCSR
 7-12
Serial data processed by the ACIA essentially follows
the RS-232-C Specifications of the Electronic Industries
Association (EIA). Voltage levels, source and load resistances,
connector type and pin assignments for data and control signals
are contained within this specification. Some of these control
signals are produced by the ACIA for the serial device. Others
are produced by the serial device for the ACIA.
One control signal is RTS (Request To Send)t which is
produced by the ACIA when requesting permission of the serial
device, a printer perhaps, to send data to it. This signal
is active when low hence is called RTS, the bar over RTS
indicating inversion, that is when RTS = 1, RTS = 0. RTS
is determined by Control Register bits #6 and 5.
The usual response by a serial device (printer) upon
°
receiving RTS = is to activate a control line to the ACIA
called CTS (Clear To Send), also active when low.
This exchange of control signals, usually preceding data
transmission, is often called "hand shaking" and can be used to
permit data transfer only when a device is turned on and
operational. The RTS line can alternately be used as a control
line without feedback (CTS is ignored), perhaps controlling a
function in an external device.
Control Register bits #7! 6 and 5 remain to be discussed.
Bit #7 controls receiver "Interrupt" operations (Chapter 11) and
is assumed to be 0 for now. Similarly bit #5 is assumed to be 0
since it controls transmitter "Interrupt" and "Break" operations.
°
With bit #5 = 0, bit #6 controls the RTS line; RTS = when
bit #6 = 0, and 1 when bit #6 = 1. See Appendix E for details.

The following program is to.

(a) initialize the ACIA for operation with.
- 7 data bits, even parity and 1 stop bit.
- data rate of 600 bps when the oscillator
frequency is 38400 bps.
(b) set RTS = o.
(c) send the ASCII code ACK (acknowledge) after the
external device (printer) clears eTS.
Contd.
 7-12
Contd.

7FF4 SEF.:CSF.~EG!U $~::'FF4

7FF5 SEF.:E:UF EG!U $7FF5
73::=:E ACIACF.: EG!U $73:=:E
:+:
J.)1J3t1 E:6 -;:'3::=:E LDA A ACIACF.:
(1:1J.~f3: :=:4 :::A AND A #;'~1 (1J.~10:10 1 0
01t15 :=:A (1A OF.:A A #;·~(10t1J.~11 (1:1 J.~1
10311217 E'"'?'I 73::=:E STA A ACIACF.: UPDATE OF.: I Ci I NAL
J.~11(1A Eo"' 'I ? 7FF4 STA A SEF.:CSF.:
J.~1:1J.~1D F6 7FF4 NOT.,.IET LDA E: SEr.:CSF.:
t1:1:1J.3 C4 0A AND E: #~~ t1J.~1 t1J.~11 (11(1
103:1:12 C:1 J.~12 Ct'1F' E: #i~ 0J.~1(1J.:10t1:1 t1
1211:14 .-,.-
c..t.:. F7 BNE NOTITIET
(11.1.6 :=:6 (16 LDA A #$(16
1211.:1:=: E:7 7FF5 STA A SEF.:E:UF

Explain the function of the 4 instructions starting

with LDA B SERCSR

--------.",/
7 6 5 4 J 2 1 0 ~bi t #
10 -..,-
0 0 0
~
1 0 1 0
"~
I Control
Register
LDA B SERCSR and
AND B #~~000010 10 expose"
_
RTS = 0
I
7 data.
r I II

Status Register bits #3 & 1.

even .;.64
parity. CdlP B i;~ooooOO 10 tests for
1 stop bit. o in bit #3 (CfS=O) and
1 in bit #1 (Tx READY).
Ix XXX 0 X 1 01 Status
"=C=T=S-=0-J-- - -- Register BNE NOTYET branches back if
j 4
either condition is not met.
or "fTransmitter
CTS=l lREADY
 7-1J
Returning to the Status Register, other bits not yet
discussed are,
- Bit #2 - Data Carrier Detect or DCD an input to the ACIA from
a "modem" used to transmit serial data over a telephone
line. DCD = 1 if loss of tone occurs on the telephone line.
- Bit #4 - Framing Error goes to 1 when a stop bit is missing,
usually due to an erroneous start bit.
- Bit #5 - Receiver Overrun - goes to 1 when data is lost due to
too slow reading of the Data Buffer. It is cleared by reading
the Data Buffer.
- Bit #6 - Parity error,goes to 1 when the parity of the
received data differs from that expected, based on the Control
Register contents.
- Bit #7 - Interrupt Request state (Chapter 11).

Write a few instructions to ensure that the Framing Error,

Receiver Overrun and Parity Error bits are all normal (zero). If
one or more is wrong, branch to ERROR.

7FF4
7FF5
EQU
SE~:CSF.: $7FF4
---_/
SERBUF EQU $7FF5
86 7FF4 * LDA A SE~:CSF~
:=:4 70 ANI) A #t~~111100~30 CHEC.< FOF~ 3 T',..PES OF ERROR
26 59 BNE EF.:~:OF.:

7 6 5 4 :3 2 1 0 ... bi t #
1X 0 0 0 X X X
t I I
xl
P 0 F
 - PIA - ---8-1

PERIPHERAL INTERFACE ADAPTER

In the previous chapter we worked with the ACIA which
transmits and receives serial data in a fixed format at a
predetermined rate. This chapter involves the Peripheral
Interface Adapter (PIA), a device which transmits and receives
data in parallel form at an unspecified data rate.
The PIA is comprised of 2 almost identical sections,
A and B, each capable of transmitting or receiving 8 bits of
data. A block diagram of the "An half of the PIA is shown
below. For each section there is a Control Register (CR) and
a Data Buffer, both having similar functions to those in the
ACIA, plus a Data Direction Register (DDR) which determines
which bits of the Data Buffer are inputs and which are outputs.
Both the Data Buffer and the Data Direction Register share the
same official memory address, the selection between the two
depending on the state of bit #2 of the Control Register.
Assume address 7FFO for the DDR and Data Buffer for the
A half of the PIA. Automatically its Control Register address
would be 7FF1. For the "B" half of the PIA the addresses would
be 7FF2 and 7FFJ (Data Buffer and DDR = 7FF2, CR = 7FFJ).

~ CONT~OL
iFFO
I
7Ffl ~_ _~
)
R1:G\S'TER

-4.-----------B~it\#2 of Oontrol Register

determines if DDR or Data
Buffer is served via 7FFO.
(Bit #2 = 0 --serve DDR)
(Bit #2 = 1 --serve Data Buffer)
Let's assign symbolic addresses to these two memory
addresses, PIABFA being the nA" half Data Buffer (and DDR too)
at address 7FFO. Similarly PIACRA would be the "A" half of
Control Register at 7FF1. For the "B n half the corresponding
symbolic addresses would be PIABFB (Data Buffer and DDR) at 7FF2,
and PIACRB (Control Register) at 7FFJ.
Contd •.•
 8-1
Contd.
As noted in the previous diagram, if bit #2 of
PIACRA = 0, then data destined for PIABFA goes to the "A"
Data Direction Register. If this bit #2 = 1, the data will go
to the "A" Data Buffer.
The Data Direction Register stores 8 bits, each bit
independently controlling the data direction for the
corresponding bit of the Data Buffer; 1 = output, 0 = input.
Write the instructions to ensure that all PIA data
lines for the itA" half of the PIA will be input lines. Note
that the first task is to address the Data Direction Register,
via bit #2 of the Control Register.

7FF0 *
F'IABFA EI)U
-------/
$7FFe
7FF:1 PIACF~A EG~U $7FF1

0:1€n3 B6 7FF:1. * LDA A PIACRA

01€(s 84 FB AND A #~1111101:1. CLEAR BIT 2 TO ACCESS DDR
13:1135 B7 7FF1. STA A PIACRA
01138 7F 7FF0 CLF~ PIABFA SET A HALF FOR INPUT
 The routine in the previous frame would normally be
8-2
-
found within a RESET program which is automatically executed
when the microprocessor power is first applied or when the
RESET button is depressed. More details on such initializing
operations are contained in the Interrupt Chapter.
Write the instructions for a RESET routine to set up
the "A" half of the PIA for input and the "B" half for output.
This routine should leave the PIA ready to load and store data.

/
7FF0 *PIA8FA EG'~U $7FF0
7FF1 PIACRA EQU $7FF1
7FF2 PIABFB EI~U $7FF2
7FF3 PIACRE: EG'~U $7FF3
:+:
01(10 86 7FF1 AHALF LDA A PIACF~A
0103 84 FE: --,
AND A #~~1.1111011 CLEAR BIT .:!. TO ACCESS DDR
01.05 87 7FF1 STA A PIACRA
01.0S 7F 7FF0 CLR PIABFA SET A HALF FOR INPUT
01.£18 SA 04 OF::A A #~'-;:00£10£110£1 BIT 2 = 1 FOR DATA
e1£1D 87 7FF1 STA A PIACRA
0110 F6 7FF3 BHALF LDA A PIACRE:
01.13 84 FE: AND A # %111.11 ~31. 1 CLEAR BIT 2 TO ACCESS DDR
0115 B7 7FF3 STA A PIACRB
01.:1.8 86 FF LDA A # ~.~ 1.:1.1.:1.1.1.1.:1.
01.:1.A
87 7FF2 STA A PIABFB SET 8 DCIF~ FOR OUTPUT
01.1.086 7FF3 LDA A PIACF~E: GET CR AGAIN
01213 8A 134 ORA A #;-;:(113000100 BIT 2 = 1 FOR DATA
01.22 B7 7FF3 STA A PIACRB
 Assuming that the B half of the PIA is already
initialized for output (see previous frame), set bit #5 and
clear bit #J of Data Buffer B, without disturbing other Data
Buffer bits. From now on assume PIA Register definition
(PIABFA EQU $7FFO etc.), unless otherwise requested.

----_/
LDA A PIABFB
ORA A #:Y.001.00000 SET BIT 5
AND A #~1111e111 CLEAR BIT 3
STA A PIABFB
The PIA could be controlling a machine tool, with the changes
in bits #J and #5 representing control signals for the next
machine process.

What is the state of bit #2 of PIACRB during the -

8-4

previous frame?

---~/
Bit #2 of PIACRB = 1 permitting communication with the Data
Buffer rather than the Data Direction Register.

..§.;.l
The PIA could be used with a 6800 microcomputer in an
automobile sensor and alarm system. Assume INDATA as Data
Buffer A, at address 7FFO. Also assume the following bit
assignments for INDATA.

Contd •. ·
 8-5
Contd.
The input Buffer, INDATA, has the following bit
assignments.
Bit # Function Status if 0 Status if 1
o Seat Belt Monitor disconnected fastened
1 Door Monitor closed opened
2 Oil Pressure Monitor low normal
J Ignition Monitor ignition off ignition on
4 Gear Shift Monitor park/neutral all others
5 Engine Monitor not running running
6 Day/Night Monitor night day
7 Headlight Monitor lights off lights on
The output Buffer, OUTDAT, has the following bit
assignments.
Bit # Function Status if 0 Status if 1
o Buzzer off on
1 Bell off on
2 Panel Alarm Light off on
3 Starter Control starting starting
disabled enabled
Flow chart and write the in~tructions to ring the bell
if the ignition is off and the headlights are on. (I wish
that I had that on my car.) Assume previous initialization of
the PIA for input on Buffer A and output on Buffer B.

_ _ _--J/
€1:100 B6 7FF0 CARCHK * LDA A INDATA
~1:1.03 85 0'-' c' BIT A #%01300:11210121 IGN?
0:105 .-,.-
oe:.t.:. 49 BNE NOBELL
€1:1.07 85 8~:::1 BIT A #:"'~:1.0€100000 LIGHT?
~1:109 27 45 SEQ NOBELL
0:1.0B 86 7FF2 LDA A OUTDAT
0:1.€1E E:A €12 OF.:A A #::-~0~3000e1.€1 BELL?
1211.:1.0 87 7FF2 STA A OUTDAT RING BELL
*
ExaT R'WG BELL 01.50 *
NOBELL
 -8-6
This time permit the car to be started if and only ife
(a) seat belt is fastened and
(b) gear shift is in Park or Neutral and
(c) door is closed.
otherwise turn on the buzzer.
First flow chart your solution.

_ _ _-.1/
Your order of checking
the functions may correctly
be different. The order
shown here leads to
slightly easier testing
O"fHe~S ( l '
as seen in answer in the
next frame.

OPE" (I)
 Now write the program, preferably using the flow chart -8-7
shown in the previous frame.

0:1.22
01.25
86 7FF0
85 01.
TESCA~:LDA
BIT
A
A
---------/
IN[)ATA
#%000000€11. BELT ON?
01.27 27 1214 8EQ BUZZ
01.29 85 :1.2 BIT A #%12100:1.00:1.et GEAR SHIFT AND DOOR?
0:1.28 27 etA BEQ OKTOGO
0:1.20 86 7FF2 BUZZ LDA A OUTDAT
0:1.313 8A (11. ORA A #~~000000(11
0132 87 7FF2 STA A OUTDAT BUZZ
0135 20 08 BRA [)ONE
0:1.37 B6 7FF2 OKTOGO LDA A OUTDAT
013A 8A 138 ORA A #"~0(1e01.000 OK TO START
0:1.3(: 87 7FF2 STA A OUT[)AT
0:1.3F 20 E:1. DONE
7 6 .5 4 J 2 1 0 bit #
o ijBelt on
I~ IX X X 0 X X
L-Door
1 closed
Park or Neutral
OVT 3 ;J. 0

\J Istart ILight Bell I Buzz I

By grouping the Gear Shift and Door checks together the single
instruction BIT A #$00010010 will cause a branch via BEQ OKTOGO
if and only if both bits are o.
 -8-8
Transfer of data between the PIA and an external device
takes place at an unspecified rate; hence control lines are
needed between the PIA and the external device to indicate to
the PIA when the data is ready and to the external device when
the data has been read. This provides a "hand shaking" linkage
similar to that possible via RTS and CTS in the ACIA.
For the A half of the PIA two control lines, CAl (input
to the PIA) and CA2 (input or output) are available. CAl could
inform the PIA, acting as a
CAt
( --... data receiver, that data is
?lA now available. When this
D" ,A E"Xi'cftt1AL
BVrFER data is read by the PIA, CA2
bcV'':E
A could inform the external
\... - ~
device that data has been read;
CA1..
therefore another byte could be
placed on the data lines. GBl and CB2 could perform similar
functions for the B half. Both CAl and CA2 are controlled by
specific bits of Control Register A as shown below.
#
CAl
CONTROL
CAl READY Bit
goes to 1 when
CAl goes ACTIVE -------~----
~

If 1 CA1 goes ACTIVE in going HIGH.

If 0 CA1 goes ACTIVE in going LOW.
The J bits associated with CA1 are shown above. We are
not using interrupt at this time; hence bit #0 = o. Bit #1
determines whether CAl sets the READY bit (#7) when CAl goes
LOW (if bit #1 = Q) or HIGH (if bit #1 = 1). The CAl READY
bit (also called IRQAl in Motorola literature) indicates, when
going to the 1 state, that CAl has gone ACTIVE.
If bi t #1 ~H'G" If bi t #1
,~\~"
=0
in the
CAi LOw
=
in the
1 cA1 __
I
,I.D~

Control 'Batt.,. Control

~
W
eM •
Register ~~A01 Reg1ster _ _ 6_1t_ _l_ _....I1. "
_ <:1\\ il-=AO'1'
- -..... 0 ""i',t\G~
Contd •••
 8-8
Contd.
The PIA READY bi t (similar to the ACIA ',' READY bit)
It It II

will be cleared automatically when data is read from the Data

Buffer, e.g. LDA A PIABFA. Bit #7 of the Control Register
is a READ ONLY bit, and therefore cannot be set or cleared
by a STA A PIACRA instruction.
Initialize Control Register A so that CAl's READY bit
is set when CAl goes HIGH. Do not disturb the other Control
Register bits.

xXXXXX1 X
t ~ Assume 0
Set (no interrupt)

01.£10 B6 7FF1 LDA A PIACF.:A

0::1..1213: BH (1:2 OJ;.:A A #~.~ (n30£1€,n:;:110 SET E:IT 2
~~~t~Z15 B? '?FFl STA A PI ACF.:A

Note that it is the transition (LOW to HIGH or HIGH to LOW)

which causes the input Control Lines to become ACTIVE, rather
than the final level of these lines
 When bit #5 of Control Register A = 0, CA2 also acts --
8-9

as an input line similar to CAl. Bit assignments for PIACRA

are as follows.
654 J

t lo
for "no interrupt"
(0 = CA2 ACTIVE in going LOW
(1 = CA2 ACTIVE in gOillf..~ HIGH
o for input operation of CA2
CA2 READY bit (read only) 1 = REAux
Bit #5 for input. =0 Bits #4 and J behave the same as bits #1
and 0 for CAl.

Assume that both CAl and CA2 are to be in~ut Gontrol

lines, CAl being ACl'IVE in going LOW and CA2 being AC'I'IVE in
going HIGH. Write the instructions to produce this. Also
set up the A Data Buffer for input operation.

---~/
xx° ° 1 0 x 0 ctf-Control Reg. A

tt \..CAl no Interrupt
CAl ACTIVE LOW
o to set direction
{ then 1
CA2 no Interrupt
$'?FF ~.:~
CA2 ACTIVE HIGH
?FF~3 PIABFA EOU
?FFl P I ACF.~A EG!U $?F F:.I.. CA2 Input
?FF:;:~ F'IAE:FE: EG!U $7'FF;;::
7FF3: P I ACF.~E: EOU $?FF3:
~11.~:::1~:3 E:6 7FF:l LDA A F'IACF.:A
t1:1.ff::' ::::4 D~:::1 AND A # :'.~:1 :1. ~:1:1 ~] ~:::10 ~:::1
~:3:tf15B7 7FF:l STA A PIACRA SET FOR DDR
(11.(18 '?F 7FF~3 eLf;,: F'IABFA INPUTS FOR A HALF
0:1t1E: ::::A :1.4 OPA A #%00010100 DATA 8UF NQW
~~:1.~~[) E:~:O ·?FF1. :::;TA A PIACRA
 8-10
There are J possible modes for CA2, acting as an output
(bit #5 = 1). The first is seen when bit #4 = 1. CA2 will now
act as an output line whose state will be determined by bit #3,
(0 produces LOW, 1 produces HIGH).
7 6 4 J 2 1 0
1

Assume that to communicate with some external device CA2

is to go to the HIGH state for 1 millisecond, then go LOW.
Also assume that the instruction JSR MILSEC (subroutines will be
covered in the next chapter) will cause a delay of 1.0 milli-
seconds. Write the necessary instructions assuming that CA2 is
presen"tly LOW.

7FF~3 F'IABFA EGHJ

--------'/
$7FF0
'?FF:1 PIACF.:A EG!U $7FF:1
7FF2 PIABFB Et:;"~'-' $7FF2
7FF3 PIACF.:8 EG!U $7FF3
~31~~10 86 7FF:1 LOA A PIACRA
(1:103: :3A 3:=' OF.:A A #~'~~Z1€1:111 €n3~3 SET 8ITS 5 .. 4 AND 7
..>.

0:1~35 87 7FF:1 STA A PIACF.:A NO~o.I

CA2=1
€11J3:::: 8D ~3113 .JSF.: t'1ILSEC ONE t'1ILLISEC DELA'r'
131.08 E"- ·b 7FF1 L[)A A PIACF.:A t1ILSEC t1AY USE ACe A
~310E 84 F7 AND A #~";1:11:101.1.:t CLEAF.~ BIT '3
~:::11.1.~3 87 7FF:1 STA A PIACF.:A CA2=~3

Such an output control signal on CA2 could be produced after

data reception on the A half of the PIA to order the data
source to change mode of operation. For lack of a better name
let's call this the PROGRAMMED mode, since the state of CA2 is
determined by program control.
 8-11
CA2 may be used as an output control line in a "hand
shaking" mode when bit #5 = 1 and bits 4 and J = o. In this
mode the A half acts as a data receiver. CA2 will go HIGH
automatically when CAl goes ACTIVE (HIGH in this example) and
will go LOW automatically when Data Buffer A is read.

_C_A_l__ n:::'
L-Data Ready p
CAt

~
~

DAtA
k'<r"] 1
A
~I."""J'I
....., 8 '-,..,&S
OF DATA
SOURCE
\.O~_

CA2 follows
CAl state.
J '---nata Read.
Therefore CA2 " -.
is LOW.
When CA2 goes LOW the external device will know that new data
may be put on the data lines.
Flow chart and write the instructions to read the data
from the external source via the PIA (A half) when CAl goes HIGH,
automatically indicating via CA2 that the data has been read.
Store the data starting at 0800. terminating data storage
after FF has been read and stored.

-----1/ Contd •••

 8-11
Contd.
*
F'IAHAN LDX #$0800-1.
IH\T PtA ST;>:: t1Et'lPNT INIT POINTER
LDA R F'IRCF~A
AND A #:Y.1.1.1.0001.0 BITS 4.. 3.. 2.. 0 = 0
STA A PIACRA
CLF.: F'IABFA INPUT t10DE NOIo~
OF.:A A #~·~e01.001.1.0 SET ElITS 5.. 2 AND 1.
STA A PIACRA DATA ElUF NOlo!
INl·JAIT LDA A F'IACRA
E:F'L INl·~AIT WAIT FOR F.:EAD1T1 FLAG
STORE IT LOA A PIABFA GET DATA
LOX t'lEt'1F'NT
IN~'~
ST}:: t1Et'lPNT GET STOF.:E AD[)F.:ESS
STR A >~ AND STOF~E DATA
Ct'lF' A #$FF
BNE INWAIT NOT LAST DATA
Hp~ Bp~A HR ALL DONE SPIN FOREVER
t1Er1F'NT Rt18 2
8-12
In the same hand shaking mode (bit #5 = 1, bits
#4 and 3 = .0), the B half of the PIA acts as a transmitter.
Here CB2 will go HIGH when CBl goes ACTIVE (HIGH in this example)
and will go LOW when data is written out (stored) in Data Buffer B.
Sketch timing diagrams for CBl and CB2 indicating the
reason or significance of each change. When working this out
think of what information the PIA (transmitter) and the external
device (e.g., printer) need to know to transmit data without
loss of data or loss of time.

_ _ _-1/
CB 1 (in) nf..;.~.~':-------
\ data received by printer, therefore new data
can be put on data lines by PIA
CB2
(out)"
I I1-----------
CB2' ~new data now available in
follows PIA, therefore CB2 goes LOW
OBl state
Again the hand shaking operation permits optimum data
flow. Although the printer would not normally store more than
132 characters for one complete line of text, the data rate within
this line could be as high as 50 000 characters/second, limited
by the computer's clock and the number of instructions per loop.
 8-13
One last mode, the STROBE mode is available when
bit #5 = 1, bit #4 = 0, and bit #3 = 1. It is similar to the
previous HANDSHAKE mode in that CA2 goes low when data is read
(LDA A PIABFA) into the A Data Buffer. It differs in that CA2
automatically returns to the 1 state several microseconds (one
instruction) later. Similarly, in the B half of the PIA, CB2
goes low when a write operation (STA A PIABFB) takes place and
returns to the 1 state automatically, several microseconds
later. This mode of operation releases CAl and CBl for other
tasks, but assumes that data is always ready for the "A" half
and that the external device is always ready to receive data
from the "B half. A summary of control line operations is
II

shown below.

CAl (CB 1)
(input only)
7 6 543 2 1 0

CAl (CB1)
READY BIT
(read only)
I

"'O=DDR access ~
via Data Buff
! l L
(0 =
(
°CAlfor (CB1)
going LOW
no interrupt
ACTIVE in
l=Data Buffer (1 = CAl (CD1) ACTIVE in
access (going HIGH

CA2 (CB2) I
bit #5

7 6 5
,..-__...._---".,A..---
o=
4 3°
input

2 1
I 1 = output
_ ,
bit #4
=1.&...._ _-_0..........
~I/] /Id/h). 10)~1 '?///} ,...,.. - "
..
~ >~'(, I a;;1;/t-r i~PI/l PROGRAMMED mode I
~ t CA2 (CB2) bit #3
1~~2)
READY
j 0 1
f I 0 for no
interrupt
fO_l_IO_W_S_b_i_t_II_3
_
=_o_l= 1
+
r

BIT ~.,
,
r
CA2 (CB2) ACTIVEJ HANDSHAKE mode STROBE mode
~~~nfci~~~ 'ACTIVE CA2 (CB2) goes HIGH CA2 goes LOvl
momentarily after
• I following CAl (CB1).
go~ng HIGH CA2 goes LOW after READ from A Buffer.
READ from A BUFFER. CB2 goes LO~l1
CB2 goes LOW after momentarily after
WRITE to B BUFFER. ~RlrE to B Buffer.

No answer is required in this frame.

 8-14
Here is an application of the PIA to
detect which of the 4 keys, A. B. C or
D was depressed. CA2 provides logic 0
o ~.-- -t- A
.....- +- & to all 4 intersections, the depressed
1 ~_-a-+--w-«; key passing on this 0 state to the
Pt f\ 3 P
appropriate input. The symbol at the
top of the diagram is an ~
"inverted input OR gate" ~,.
whose output goes to the 1 state if
one or more of the inputs go to o.
PIA lines 4 to 7 are not needed.
Write the initialization instructions for the PIA to
set up CAl as an input (ACTIVE high) and CA2 as an output.
following bit #3. The Data Buffer should be set up as an input.

--_---..J/ XXllo'M'10
~ '-v-J
CA2 CAl
output" input
= bit #3 active
hi.gh
:+: PIA PROG FOR FOUR KEY KEYBOARD.
* CA2 IS OUTPUT TO SWITCHES. CAi IS
:+: INPUT TO PIA. DATA GOES TO LOW 4 BITS.
:+:
~:::11.~::'1f1 86 7FFi KE1TIPIA LOA A PIACRA
~:::1:l03: :=~·4 F;;'-:: AND A ~* ~,~ :t 1 :1 :1 ~:1 ~~11 ~:::1
~~1:t~~15 E:~:t ~;:OFF1. STA A PIACRA ACCESS DDR
0:t~?1S ?F 7FFf1 CLF.~ PIA8FA DATA INPUT MODE
~:::11J1E: SA 3:6 OF.~A A #~'~~?1~3:1.1~';):1 i~:::1
(1:1(1[) E'?'I 7FF:t STA A PIACRA DATA MODE NOW
 8-15
Now flow chart and write the instructions to branch to
KEYA, KEYB, KEYC, or KEYD, corresponding to a depression of
keys A, B, C or D.

-----"/
TR'T'AGN LDA A PIACF.:A
BPL Tf;,:'T'ACiN CA1. r'~OT UP 'r'ET
LDA A PIABFA UP r-.low
AND A #$~)F LOl.oJER 4 BITS ONL'T'
BIT A #$f1::L KElT' A HIT?
SEQ KE'r'A 'T'ES.
BIT A #$02 KElT' B HIT'f'
BEGJ. KE'T'S
BIT A #$04 I<E'r' C HIT?
BEI;J, I<E'r'(:
BIT A #$(1E: KE'T' D HIT?
BEG! I<E'T'[)

For short tests this "brute force" method is acceptable. For

longer checks, data table lookups should be used.
 8-16
Whenever mechanical devices such as switches are used
there exists a problem of contact bounce, that is the contacts
may close, open; then close, several times within a few milli-
seconds of the first contact before settling down to a "closed"
or ON condition. Data or signals from such a switch are highly
unpredictable during this transient period, hence a timing loop
of perhaps ten milliseconds should be introduced after the
first contact detection, via CAlor CA2 before the PIA Data
Buffer is read.
Assuming a lMHz (10 6 cycles/sec.) clock in the 6800
microprocessor, the number of microseconds per instruction
executed can be determined from Appendix C under the ~ column
denoting the number of machine cycles per instruction.
LDX #$0400
an immediate mode instruction, requires J cycles or J micro-
seconds.
What is the execution time per loop ina
r'10ReaEX DEX
BNE t'10RDE>::

t'10F.:DE>:: DE:X:
BNE t'10RDE>~
4 CYCLES
4 C'r'CLES
------"'/
:+:
:+: 8 CYCLES TOTAL
 8-17
To get 10 msec., then the # of loops required =
10 / ~6
10 3 10
= 125010 loops

Initialize the counter for this value and write the

complete delay routine.

NAt1
-----/
PF.:OG68
OPT 0.. S
OF.:G $~j1.€nj
:+:
:+: P8-1.7
:+:
CE 04E2 TIMER LDX #1.25~] 4-- No $ silZll for decimal #.
09 MORDEX DEX 4 C'T'CLES
26 FD BNE MORDEX 4 CYCLES
:+:
:+: 1::1 C'T'CLES TOTAL

This routine would then be executed when CAl first detects

a key hit, which would occur when the key is depressed, and
probably upon release, which also produces transient pulses. Hence
the state of CAl should be checked after the delay. If CAl is still
1 it is a legal key hit. If 0, it is probably due to "bounce" upon
key release, which could then be ignored by the program.
 8-18
A stepping motor is another application of a PIA.
Imagine 3 electromagnets or coils, A, B and C, placed at equal
angles around a magnet which is free to turn.

A:~

~;:e~
Each of electromagnets At B and C are directly under control
of a PIA Data Buffer bit, as shown in the diagram below.
A magnet is ON when the appropriate bit is in the 1 state,
and OFF when the bit is o. Energizing magnet C causes the
North pole of the central magnet to rotate to the South pole
at c.

[
C B
[I
A
PIA Data Buffer B

Set up the PIA to cause the central magnet's North pole

to point to A. Assume that PIABFB is already initialized for
output. Also assume that the South pole of each energized
electromagnet is the closest pole to the magnet, as in electro-
magnet C.

_ _ _...---J/
0~00 86 ~1 MAGA LDA A #:$:~~1~
0:1€12 87 7FF0 STA A F'IABFB
Bit #0 (electromagnet A) is ON.
 8-19
How would you suggest having the N pole of the central
magnet point to a half way between A and B? Write the
instructions.

------/
€1:10E: 86 ~:1:$ t'lAGA8 LDA A #$03
0:10A 87 7FF0 STA A PIA8FB

Both A and B are ON and equally attracting the N pole, causing

it to point between the two electromagnets, at about the 2
o'clock position.
 8-20
~

Write the instructions to cause the central magnet to

move clockwise continuously, starting at A. Assume a delay
subroutine call JSR DELAY, which introduces a delay between
each change to slow down the computer changes to acceptable
rotational rates.

---_/
Data Buffer
01.1313 86 (11. MAGA LDA A #$131.
01.132 B-:O
,( 7FF2 STA A PIABFB
01.135 80 €11.32 JSF.: C'ELAY
131.08 86 0-"
..=:. t1AGA8 LOA A #$03
..31.eA E'"?
'I 7FF2 STA A PIAE:FE:
(11.0D 8D 13:1.32 J5R DELA'T'
(1:11.(1 86 02 MAGE: LOA A #$02
(11.1.2 B7 7FF2 STA A PIABFB
13:1:1.5 BC' 0132 .J5~: DELA'T'
€I1.18 86 (16 t1AGBC LOA A #$06
13:1.1A 87 7FF2 STH A PIABFB
0:1.:1.D BD (11.32 JS~: DELA'T'
..::t120 86 04 t1AGC LDA A #$134
"~tl22 E'?
'I ?FF2 5TFt A PIABFB
~~1125 BD (11.32 .J5~: DELA..,'
0:1.28 E:6 &.35 t'1AGCA L[:eA A #$135
'.
€1:12A E''? 7FF2
e:12D BD 0:1.32
STA A
.JSR
PIABFE:
DELAY
13:130 2€1 CE BRA MAGA
 How would you modify the angular velocity for this
--8-21

stepping motor, under program control?

---_/
The constant used for the delay could be entered via a keyboard
e.g., using the keys 1 - 9, each producing a different constant
and therefore a different angular velocity. The smaller
constant would then be down-counted sooner, producing a shorter
delay, hence a higher speed.
Modern stepping motors usually have many (dozens) of
coils around 'the circumference I alternating between A, B and C
groups, each group being driven by one specific line, hence
PIA bit. An output of the sequence 001, then 010, then 100
would represent one cycle, usually a few degrees. Reversing
the order would reverse rotational direction.
 SUBROUTINES
.......
9-1

In previous chapters we have used subroutine calls

e.g., JSR GETCHR which caused the ASCII code, for the key struck
on keyboard, to appear in Ace A. Such a subroutine call causes
execution of a group of instructions, headed by the label GETCHR
and terminated by
RTS - ReTurn from Subroutine.
After this subroutine has been executed, the next instruction
executed is that following the subroutine call, e.g •
.JSF.: CiETCHF.:
STA A KE'T'[:tAT

A program can be made up of a series of subroutine calls,

each causing execution of a particular subroutine, ito carry out a
specific task. Each subroutine should have only one entry point
and one exit point. Entry and exit conditions should be well
documented in the accompanying comments, e.g., IIEnter with X
pointing to the head of a message, and exit when the message has
been printed, with Ace A and Ace B contents being overwritten."
Each subroutine can be individually tested and then used with
confidence when called within the main program.
Program planning should be in IItop-down format, with
ll

overall tasks being defined first, and from these tasks the sub-
tasks defined. Each task can then be assigned to a subroutine
which in turn can call lower level subroutines to carry out the
sub-tasks. Subroutine calls can be many levels deep, if
necessary, those at the lowest level being responsible for the
simplest tasks, like checking a READY bit in an ACIA or a
control line in a PIA. The overall result is a hierarchical or
pyramidical structure, the top levels being general or "global",
the lowest levels looking after detail.

Contd •••
 9-1
Contd.
A typical subroutine. properly documented, is
shown here,
* GETCHR... SUBROUTINE WHICH RETURNS WITH
* ASCII CHAR IN ACC A. X AND B NOT CHANGED.
7FF4 *
SEF.:CSF.: EG!L1 $7FF4
7FF5 SEF.:E:UF EG!U $7FF5
:+:
(11(17 86 7FF4 J3ETCHf;.: LDA A SEF.:CSR
~310A :=:4 01 AN[) A #$1211 [:tATA F.:EA[:tIT'?
(110C 27 F9 BEG! CiETCHF.: NOT 'TIET.
~Z11(1E 86 7FF5 LDA A SERBUF 'TIES. GET DATA
(1:1.11. 39 F.:TS AND E::·::1T.

Such a subroutine can be called from anywhere within a program,

avoiding duplication of the above instructions.
A subroutine call JSR ECHO is to cause the character,
struck on the keyboard, to be printed or displayed on the
terminal used. ECHO itself could call 2 other subroutines.
Based on this information write the subroutine ECHO, using only
3 instructions. A subroutine called PRINT is available, to
print the ASCII character in ACC A.

--------/
* ECHO... SUBROUTINE TO ACCEPT ASCI CODE FROM ACIA
* RECEIVER AND ECHO IT ON THE ACIA TRANSMITTER.
* CALLS GETCHR AND PRINT SUBS..
~31.~3~Z1
SD 01.07
*ECHO .JSF.: GETCHF~ GETS INPUT
€1:103 SD 1-3:1:12 JSF.: PF.:INT Ar·~D OUTPUTS IT.
e1.e6 39 RTS AND RETURNS

At this point the details of GETCHR and PRINT are not necessary
except that they both use ACe A.
 ~
Assuming co.mrnunication to the printing device via the
ACIA, convert the instructions shown below to a well documented
subroutine called PRINT.
PF.:INT LDA B SERCSF.:
AND B #$02 READY TO PF.: I NT""!'
E:Ef~ PRINT NOT 'TIET.
STA A SEF.:E:UF PRINT CHAF.:.

___-------J/
* PRINT... SUBROUTINE TO PRINT ASCII CONTENTS
* OF ACC A ON ACIA OUTPUT DEVICE. USES A AND B.

0112 F6 7FF4
*
PF~INT LDA B SEF.:CSF.:
0:115 C4 02 AND E: . #$1212 F.:EAD'TI TO PF.: I NT?
0:1:17 27 F9 BEt] PF.: I NT NOT 'T'ET.
0:1:19 87 7FF5 STA A SERBUF PF.: I NT CHAR.
0:1:1C 39 F~TS AND F~ETUF~N.

The documentation is just as important as the instructions

written. Fight off the sometimes overwhelming urge to write
undocumented programs, which usually end up in the waste basket.
six months later.
We could depict the subroutine hierarchy ass

ECHO
GETCHR~ PRINT "
implying that ECHO calls both GETCHR and PRINT. For lack of a
better name let's call this a "subroutine tree".
 Imagine a system where the computer is to receive -- 9-)

inputs from 2 ACIA's. It would not be feasible to have the

computer wait in a loop for ACIA #1 since it could lose data
from ACIA #2. The computer could alternately check ACIA #1,
#2, #1 etc., receiving data from an ACIA that is ready. (The
Chapter on "Interrupt" presents another solution.) A
subroutine to check the READY status of ACIA #1, without
reading data, is shown here.

01€10 86 7FF4 I NCHK1. LDA A SEFC:CSl

0103 84 01. AND A #$01 DATA FC:EAD',..?
01.05 27 02 BEG'J. NODATA
01.07 0D SEC GOES HERE IF DATA READY
e1.08 39 SE1RTN RTS
01.09 0(: NO[)ATA CLC GOES HERE IF NOT READY
010A 20 FC E:F~A SE1RTN

Upon exit from this subroutine what is different, when data is

ready, compared to when data is not ready?

-----/
The C bit is set when data is ready, and cleared when data is
not ready.
 ~
In Appendix C find 2 instructions, each of which branch
conditionally, depending on the state of the C bit. Use one of
them in the main program below, upon return from the subroutine
INCHKl to determine whether or not to store data, MEMADl being
the pointer. If that is not too difficult repeat for ACIA #2,
where MEMAD2 is the pointer within INCHK2, which similarly checks
if ACIA #2 is ready.

BCC - Branch if Carry CHECK:.1. JSR I NCHK1. ACIA #:.1. READY?

/
bit Cleared BCC CHEC.:::2 NO DATA HERE
or BCS - Branch if Carry LOX t'1Et1AD:.1.
bit Set INX
STX t'1Et1ADi GET POINTER
LOA A SEF~BF1. GET I~~PUT DATA
STA A >~ AND STOF~E IT.
CHECK2 ,JSF.: I NCHI<2 ACIA #--,o:!- F.:EAO'T'?
BCC CHECK1. NO r,lATA HERE
LO~: t'1EMAC'2
IN>::
ST>:: t'lEt'lAD2 GET POINTER
LDA A SEF.:BF2 GET DATA FROt1 #2
STA A X AND STORE IT.
BRA CHECK1.

The use of the C bit permits decisions' to be made within

a subroutine, without violation of the requirement for a single
return to the mainline program, via one RTS instruction. The RTS
should be the only means of exiting from a subroutine. To violate
this rule, e.g., via a branch instruction, destroys the modular
design of your program and makes de-bugging a nightmare.
 Let's look at a subroutine HEXADD which expects 4 hex
keys to be struck. and stores the corresponding 4 character
-
9-5

hex value in 2 consecutive bytes of memory. For example if

keys 2. 3. C and 5 are struck. the 2 bytes of memory would look
like this.
r 1 byte "' r 1 byte ,
10 1 0 11 I 0 I 0 1 0 1 1 I 1 I1 I 1 I 0 I 0 1 0 1 1 I 0 I1I
'-- 2

Approaching this from a "top-down" direction. assume that we have

a subroutine INBYTE which would return with 23 16 in ACC A when
two keys. 2 and 3. are struck. Write the subroutine HEXADD which
calls INBYTE and produces the 16 bit binary contents in the two
memory locations. ADORES and ADDRES+1.

_ _--c/
:+: HEXADO. . . STORES 2 BYTES IN MEf1 AT LABEL ADDRES
=+: CALLS INBYTE TWICE. USES ACC A.
=+:
£1101'21 BC' 01.13 HEXAr..D JSR INB'r'TE GET 8 BITS IN ACC A.
1'21103 87 1-31.130 STA A ADORES AND STORE THEt-1.
01£16 SD e113 JSR INBYTE 8 t10RE BITS
131£19 87 e10E STA A AD[:'~~ES+1. INTO NE~"~T ADDRESS.
010C 39 RTS
e:1.eD 0£102 Ar)DRES Rt1B 2
=+:
13113 INB'T'TE EQU $0:1.13

This "top-down" approach assumes that we could write the INBYTE

subroutine, if it is not already available.
 .2=.2.
Now also assume that INBYTE returns with the C bit set
if an invalid hex key was struck; otherwise C is cleared.
Modify the HEXADD subroutine to check for this abnormal condition,
restarting the HEXADD subroutine when such an error is detected.
Modify the documentation accordingly.

:+:
---~/
HEXADD... STORES 2 BYTES IN MEM AT LABEL ADORES
:+: CALLS INBYTE TWICE, CHECKING FOR ERROR WITHIN BYTE
:+: SUB VIA SET C BIT. ACe A USED.
:+:
:+:
0::1-£1£1 BD ~]:1:13 HE:~-::ADD ..TSR INB'T'TE GET 8 E:ITS IN Ace A.
~3:1~~13 25 FE: BCS HEXADD RESTART IF ERROF.:.
~1:1~~15 87 '.:11.:1:1 STR A ADDRES ELSE STOF.:E THEt1.
£11.£18 BD '.:1:11.3 .JSR INB'T'TE 8 t10F.:E BITS
€1:1(1B c:..._1 F3
.-.~
BCS HE>::ADD RESTART IF ERROR
f1:10D 87 €1:1.:1.2 STA A ADDF.~ES+:1 ELSE STORE IN NEXT ADDRESS.
~J:t:1€1 39 RTS
!::11.:1:1 1-~1(1f12 ADDF.~ES F.~t1B 2

A better solution would be to print the message BAD HEX before

restarting HEXADD. This improves communcation between the
computer and the user, an important consideration in program
design.
 j;;J.
A subroutine HEXCHR is now available to acquire an ASCII
character in ACC A, when a key is struck, and to convert it to
its 4 bit hex equivalent, e.g., OB results when B is struck.
This 4 bit result will be right-justified (against the right edge
or as far right as possible) in ACC A. Is this where you
ultimately want the first 4 bits inside ACC A when the INBYTE
subroutine, which receives two such characters, is executed?

---..----.-1/
No. If 5 is the first of two keys struck, the 0101 result
must be moved to the left half of ACC A, to make room for
the next 4 bits, which go in the right half when the second
key is struck.

~
Write the first half of the INBYTE subroutine to place
the first 4 bits in the left half of ACC B. Useful instructions
might be ASL A and TAB. Why is ACC B needed? The HEXCHR
subroutine is still available and returns with the C bit set if
an invalid hex key was struck. Such a condition should cause
an immediate return from INBYTE to HEXADD, with the C bit still
set.

~3:t1~~: BO ~Z11.25 INBIT'TE .JSF.:

---------.1/
HE::·::CHF.: GET 4 BITS
~Z1:t.16 25 1~1C Be::; BITITF.:TN BRD HEX. RETURN NOW.
01:1::: 4':'
'-' ASL A
0119 4':'
'-' ASl.. A
~::11.:1A 4':'
'-' ASL A
0:118 4':'
'-' ASL A SHIFT 4 BITS LEFT.
(111C 16 TAB STOF.:E IN B

Ace B is used to store the first 4 bits when HEXCHR, which uses
ACC A, is called to get the second 4 bits. RTS passes the C bit,
undisturbed, to the calling subroutine HEXADD.
 Now finish the INBYTE subroutine including documentation. ---
9-9

The instruction ABA may be useful to you.

The complete INBYTE subroutine might bes

_ _ _-J/
* INBYTE... PRODUCES 8 BITS IN ACC A CORRESPONDING
* TO TWO 4 BIT HEX VALUES} EACH PRODUCED BY
* HEXCHR SUB} WHICH IS CALLED TWICE. USES A AND B
€1113: BD 13125 IN8YTE JSR HEXCHR GET 4 BITS
13:11.6 .::.,._1 ec
'-,e:'
BCS BYTRTN BAD HEX. RETURN NOW.
e:1.:t8 4:=: ASL A
1!:1:1:t9 4'-' .=. ASL A
e11A 4:=: ASL A
1!:111.B 40::''-' ASL A SHIFT 4 BITS LEFT.
€1::t:1C 16 TAB STOF.:E IN B
1!:111D BC' 01.25 JSR HEXCHR GET 4 t10F.:E BITS.
~~112J.3 25 02 BCS BYTRTN IF BAD HE>::
"~1:122 :1B ABA MERGE BOTH 4 BIT SETS OF DATA
0:123 1!:1t:: CLC TELL THEM ITS GOOD DATA
13124 39 E:'T'TF.:TN F.~TS

ACC A 0 0 0 0 1 1 1 0 After the first JSR HEXCHR if E

was struck.
A"""
vv B 1 1 1 0 0 0 0 0 After therAB instruction.
Ace A 0 0 0 0 1 0 0 1 After the second JSR HEXCHrl if 9
was struck.
ACe A 1 1 1 0 1 0 0 1 After ABA. ACe B is added to
ACe A to merge both 4 bit codes.
So far we have HEXADD calling INBYTE twice.
 9-10
The HEXCHR subroutine could be formed from the hex
checking program shown early in the Branching Chapter. Write
this subroutine including the following changes I
(a) At the beginning of the subroutine get the ASCII code for
the struck key into ACC A.
(b) Set the C bit if an invalid hex key is struck; otherwise
clear the C bit and return from the subroutine with the
4 bit hex code in ACC A.
Refer to the Branching Chapter for the original hex checking
program. Assume that the GETCHR subroutine i~ available
to receive an ASCII code in ACC A. when a key is struck.

*= HE:X:CHR.
---~/
RECEIVES ASCII eODE IN Ace A VIA GETCHR
*= CONVEF.:TS TO 4 BIT HEX EQUIVALENT IF VALID
AND CLEARS C BIT. ELSE RETURNS WITH C SET.
**=
121125 BD 0143 HE>~CHF~ .J5F.: GETCH~~ (ECHO WOULD BE BETTER STILL)
13128 81 2F #$2F
eMF' A
012A .-,-.. 14
oe:.~ BLS BADHEX BEL.OW 3121, NOT HEX
012C 81 39 cr'1P A #$39
0:12E 23 fi(: BL.S NUt10K 121 TO 9. VALID HEX
121:13121 E::1 4121 er'1P A #$40
€1:t32 23 ec BLS BADHE::-:: 3A TO 4121. ILL.EGAL
0134 :::1 46 Ct1F' A #$46
01.36 22 138 BHI BADHEX ABOVE 46. ILLEGAL
£1138 8~1 37 SUB A #$37 A TO F IN 4 BIT FORMAT
0:t3A 0C GOODH:X: CLC TELL THEM IT/5 GOOD
013B ::~9 HE>!'F.~Tr·~ F.~TS
et13C 80 3=121 NUt10K SUB A #$3€1 121 TO 9 IN 4 BIT FORMAT.
~313E 2~3 FA BRA GOO[:IH>::
0::1.4~3 €1D E:ADHE:)~ SEC BAD NEWS. WRONG KEY.
~1:14:1 ;;::€i F:::: BF.:A HE::<RTN
 9-11
The GETCHR subroutine is essentially the same as before
except for 2 changes.
(a) Bit #7, the parity bit must be cleared for all data.
(b) Lower case alphabetic characters a to z, must be forced to
upper case by clearing bit #5. Write the GETCHR subroutine.
Both of the above are required to make the data independent of the
type of terminal (some produce parity bit set, others cleared)
and to eliminate having to hold the SHIFT key down when entering
alphabetic characters.

------"/
* GETCHR... SUBROUTINE TO GET ASCII CODE FROM ACIA RX.
*_BIT #7 (PARITY BIT) CLEARED. UPPER CASE IS FORCED.
7FF4 *SERCSREQU $7FF4
7FF5 SERBUF EQU $7FF5
0:143 B6 *
7FF4 GETCHR LDA A SERCSR
0:146 84 01. AND A #$01. DATA READY?
01.48 27 F9 BEQ GETCHR NOT YET.
014A 86 7FF5 LDA A SERBUF YES. GET DATA
0140 84 7F AND A #$7F CLEAR PARITY BIT.
014F 81. 60 CMP A #$60
01.51 23 06 BLS GETRTN BELOW "SMALL All
01.53 81. 7A Cf1P A #$7A
01.55 22 02 BHI GETRTN ABOVE "SMALL ZU
0:157 84 DF AND A #$DF UPPER CASE ALPHA CHAR
01.59 39 GETRTN RTS AND EXIT.
 9-12
Describe the sequence of events when a non-hex key is
struck. Sketch the "subroutine tree" in your answer.

HEXADD
---~/
•
INBYTE
~
HEXCHR

/
• "-.
ECHO
GETCHR PRINT

·When HEXCHR detects an invalid hex character the C bit is

set and HEXCHR returns to INBYTE. INBYTE immediately checks the
C bit and. noting that the C bit is set, returns immediately to
HEXADD, which also checks the C bit. HEXADD, on noting that the
C bit is set, immediately restarts .. In summary, a wrong key
immediately restarts HEXADD, preferably after a printed message
such as BAD HEX.
Further use of the C bit is seen in a program where a
task, assigned to a subroutine, results in the C bit being cleared
if the task is completed normally. If the result is abnormal
the C bit is set and ACe A contains the erroneous result, which
can be printed as an error message.
 9-13
Here is a new problem, to write a subroutine called
PAGE which prints one page of data. the first address of the
data being in the X Register when PAGE is called. The format
is as follows I
- one PAGE comprises 16 10 lines.
- one LINE comprises a Carriage Return and Line Feed (to start
a new line) followed by 8 words, each separated by a space.
- one WORD comprises 4 bytes, from memory, each byte being
printed as 2 ASCII characters, e.g., 00111101 in memory would
cause 3D to be printed.
Use a "top-down" approach to this problem in flow charting and
writing the subroutine PAGE. Assume that the subroutine LINE
is available to print one LINE.

---------//
* PAGE... SUBROUTINE TO PRINT ONE PAGE (16 LINES)
* OF DATA FROM MEMORY. ENTER WITH X POINTING TO
STORE
PO'NTER-I * FIRST CHAR TO BE PRINTED. CALLS LINE SUB.
COUNT: "10 *PAGE DE:>:: ONE BELOW FIRST CHAR ADDR
STX MEt1PNT INIT POINTER.
LDA A #1.6
STA A LINCNT SET UP COUNTER.
NULINE JSR LINE PF.:INT LINE
DEC LINCNT LAST LINE?
BNE NULINE NO. PRINT ANOTHER
RTS LAST ONE.
\ \ LINCNT Rt18 1
'---........- - - MEt'1PNT Rt1B 2
Note the double vertical bar here
"-- indicating a subroutine.

The address for the first memory address could be produced by

the previous subroutine HEXADD.
 9-14
The next task, working downward, is to write the
subroutine LINE, which prints 8 words, each comprising the
contents of 4 addresses. Flow chart and write the subroutine
LINE, assuming that 2 subroutines are available as follows.
- ~ORD, to print one word.
- CRLF, to produce a Carriage Return ~~d Line Feed, to start
the next character on a new line.

_____---J/
* LINE... SUBROUTINE TO PRINT 64 (DECIMAL) CHAR
:+: FROM 32 MEMORY ADDRESSES. CALLS WORD. USES A.
SET UP :+:
,""OR.O c.o~N'TER START NEW LINE
LINE .JSR C~:LF
LDA A #$~Z1:=:
STA A l·JF~DNUt·1 SET UP COUNTER
.JSF~ L·JORD
DEC L·JF.~DNUt'1 LAST laJORD?
BNE NULaJORD NO. BACK AGAIN.
RTS LAST ONE.
l·JF.:DNUt·1 Rt1B :1.
*
 9-15
~henext subroutine proceeding downward is WORD, which
prints the contents of 4 memory locations, then skips one space.
The subroutine OBYTE, to print the contents of ACe A as 2 ASCII
.
characters is available. SPA~E, a~other subroutine will pr~n" .
(or skip over) one space. Flow chart and write the NORD
subroutine.

---------J/
~ WORD... SUBROUTINE TO PRINT CONTENTS OF 4 MEM
* ADRESSES AS 8 HEX CHAR. CALLS OBYTE AND SPACE.
:+: USES ACe A.
:+:
l.oJO F.: D LDA A #$~:::14
STA R B'T'TeNT INIT COUNTER
.JSP OB'T'TE PPINT 1 BYTE AS 2 CHAF.:.
DEC B'T'Te~·~T
E:NE NUB'T'TE NOT LAST B'T'TE
JS~: SPACE 'T'ES. LAST B'T'TE. ONE SPACE.
F.:TS DONE
B'T'TCNT F.:t18 :1.

RETURN
 9-16
The OBYTE subroutine is next. It gets one byte from
memory via the pointer MEMPNT and calls HEXPRT twice to print
it as 2 ASCII characters. HEXPRT is entered with 4 bits
right-justified in ACC A. Flow chart and write the OBYTE
subroutine.

* DBYTE... SUBROUTINE
* ADDRESS AS 2 ASCII
--------/ TO PRINT CONTENTS OF ONE MEM
CHAR. CALLS HEXPRT. USES A JX.
* ENTER WITH ADDRESS IN MEMPNT.
*OBYTE LD~':: MEMPNT
IN>-~
STX MEMPNT GET ADDRESS
LDA A >:: GET BYTE
STA A TEMP SA.. . E COP'T'.
ASF.: A F.:IGHT
ASF.: A .JUSTIF'T'
ASF.: A LEFT
ASR A HALF
ANC' A #$(1F ZAP LEFT HALF
.JSF.: HE>::PF.:T PF.:INT IT
Le'A A TEt'1P GET CLEAN COP'T'
AND A #$0F ZAP LEFT HALF
.JSF.: HE~·::PF.:T PF.:INT IT
RTS DONE
TEMP RMB 1

Re"'URN
Note the use of TEW~ rather than ACC B. It is not good practice
to tie up an accumulator, when calling a subroutine which may
need the accumulator.
 9-11
HEXPRT is entered with 4 bits right-justified in Ace A.
It prints the corresponding ASCII character. Flow chart and
write this subroutine noting that PRINT is available to print
the ASCII contents of ACC A.

*
_----J/
HEXPRT... SUB TO PRINT ASCII CHAR. CALLS PRINT SUB.
~oo 30 TO * ENTER WITH 4 BITS RIGHT JUSTIFIED IN ACC A.
ACt " CON'Tetm
HE>::PF.~T ADD A #$3~3 CONVEF.~T TO ASC I I
Cf1P A #$]:9 NUt1BEF.~?
BLS OUTPUT
ADD A #$07 LETTEF.~. A[:ID 7 t'10RE.
OUTPUT JSR PRINT OUT IT GOES.
RTS

PR\NT CHRIl.

Check this routine by testing it first with values 0 and 9.

then with values A and F. plus the 4 values just outside these
legal values.
 9-18 ..
Next we need the PRINT subroutine. The printer, via
the CTS control line back to the ACIA, will inform the computer
to stop transmitting while Carriage Return and Line Feed
functions take place. Flow chart and write the subroutine to
transmit data via the ACIA when CTS = 1 (CTS = 0).

*
----..1/
PRINT... SUBROUTINE TO PRINT CHAR IF DEVICE
* IS ON LINE VIA CTS=~ CCTS NOT=0). USES ACC A AND B
* ENTER WITH ASSCII CODE IN Ace A.
SERCSR EQU $7FF4
SERBUF EQU $7FF5
*PRINT LDA B SERCSR
BIT 8 #$08 CTS NOT=0?
BHE PRINT NO. TRY AGAIN.
BIT 8 #$02 READY?
PIUNT CHAR BEQ PRINT
STA A SERBUF PRINT IT
F.~TS
RETURN

Loopback for the second test is to the top to ensure that CTS
has not gone to 1, while waiting for the printer to become READY.
 9-19
SPACE and CRLF now remain. A problem exists in using
the ACIA with the printer in that the ACIA will transmit the
last character in its TRANSMIT Buffer even though the printer
requests a halt to more data by clearing CTS (Clear To Send).
eTS is normally cleared during a Carriage Return or Line Feed
operation or when the printer is not ready to print data. The
above problem results in the loss of the last transmitted
character. The solution is to send a 2 nulls (ae) to the ACIA
after both the CR and LF characters. ;rhe nulls are then
"sacrificed" to preserve the next legal character printed.
With this in mind, write the CRLF and SPACE subroutines. Flow
charts are not necessary for these.

*
--_---J/
SPACE... SUBROUTINE TO OUTPUT ONE SPACE CHAR.
:+: CALLS PRINT SUB. USES ACC A.
*
SPACE LDA A #$20 ASCII FOR SPACE
.JSF.: I::'R I NT
~:TS

* CRLF... SUBROUTINE TO OUTPUT CARRIAGE RETURN

* AND LINE FEED CHAR TO PRINTING DEVICE. PADS EACH
:+: WITH 2 NULLS CHAR. CALLS PRINT SUB. USES ACC A.
:+:
CRLF LDA A #$eD C~:
.JSF.: PF.:INT
CLR A
.JSR PRINT OUTPUT NULL
.JSR PF.:INT
LDA A #$~3A LF
. T. SR PRINT
CLR A
,JSR PF.:INT NULL
,JSF~ PF.:INT
RTS
 9-20
To complete the subroutine PAGE, draw the "subroutine
tree" to show the subroutine's hierarchy.

PAGE
---------/
~
LINE

/ "CRLF
WORD

/ "SPACE
OBYTE
In only a few words, the
overview of PAGE is depicted

HE~p0 here.

PRINT

A program could call both the HEXADD and PAGE

sUbroutines, the former to define the starting address and the
latter to print the page of data.
 9-21
Near the end of the PIA chapter is a program in which
a delay is used to "de-bounce" a switch before its state is
read by the PIA. This delay could be achieved more easily if
subroutine format was used.

Flow chart and write a subroutine which produces a

delay of N milliseconds, where N is the binary contents of
ACC A. This subroutine should call a subroutine MILSEC which
produces a delay of 1 millisecond each time it is called.
Write the ruILSEC subroutine, assuming 1 microsecond per MPU
cycle. If necessary refer to the PIA chapter for the previous
delay routine.

----~/
* DELAY... SUBROUTINE TO PRODUCE DELAY
tHaT cou,,"ER * OF N MILLISECONDS~ WHERE N= BINARY
* CONTENTS OF ACC A ON ENTRY. CALLS MILSEC.
10:1130 B7 ~1:10C *DELA'T' STA A COUNT STO~~ES N

'.0 M\LLlSEC ~3:103 BD e:113D t10~:t'1 I L .JSF.: t1ILSEC ONE t1ILLISEC

t>E~"Y
0:1~16 7A e:113C DEC COUNT
0:1~39 26 F8 BNE t10Rt1IL NOT LAST YET
0:10E: 39 RTS
0:113C ~~10e:1 COUNT Rt'1B :1
*=
* MILSEC... SUB TO P~:O""'IDE
* ONE MILLISECOND DELA'T'.
e:10D 86 64 *t1 I LSEC LDA A #:113121
13:113F 87 ~1:1:1.8 STA A t'1ILCNT
~1:1:12 7A ~~1:1:1.::: t'10RDEC DEC t'1ILCNT
~:1:15 26 FB BNE t10RDEC
0:1:17 39 ~:TS
10:1:18 131313:1 t1 I LCNT RME: :1
The 2 loop instructions DEG ~ILCNr and BNE MORDEe take 6 + 4 = 10 10
MPU cycles or 10 microseconds. Therefore 100 10 or 64 16 loops
provide a delay of 1000 microseconds or one millisecond.
 9-22k&
I

In the previous frame MIIJCNT could have been given an

initial value of 64 16 sim~ly via
MILCNT FeB $64
eliminating the need for the 2 lines of initialization at the
start of the MILSEC subroutine. Would this be acceptable? Why?

------/
No! The subroutine would execute properly the first time it is
called, MILCNT being decremented from 64 to o. The second time
(and all subsequent times) that it is called MILCNT would start
at FF, after first being decremented from 0 by DEC MILCNT. This
subroutine MILSEC would then go through 25610 loops to reach zero,
instead of 100 10 loops, producing an incorrect delay. Self-
initialization is required within the subroutine to reset MILCNT
to 64 every time the subroutine is called. Lack of self-
initialization is a common catastrophic error when coverting a
program, which runs correctly once, into a subroutine which is
called many times within a larger program.
This concept should be ext~nded to all programs, as well
as subroutines enabling faulty programs to be restarted during
de-bugging without the necessity of being reassembled or reloaded.
Enough said for now about subroutines!
 10-1
STACK OPERATIONS
Previously we have seen data storage in which the Index
Register was used as a pointer. Another 16 bit register. the
Stack Pointer (Sp) is also used to store and retrieve data.
employing a user-defined block of memory, called the stack, for
the storage operations. 'rhe Stack Pointer may be initialized
to point to the address lC40 ·J'ia
LDS #$lC40 (LoaD the Stack pointer)
Another instruction
PSH A (PuSH accumulator A)
performs a "push" operation, that is it stores the contents of
ACC A in the address now contained in the Stack Pointer. The
Stack Pointer is automatically decremented after the storage
operation.
"PuSH" is an appropriate description, similar to the
"pushing" of individual serviettes into a metal holder, each
new serviette now being on the top of the stack.
Initialize the Stack Pointer to lAFF, then store the
contents of Ace A and Ace B on the stack in that order.

01.00 8E 1.AFF LDS

---_/
#$:1.AFF
01.03 36 PSH A
0104 37 PSH B
Stack Status Diagr~ns

lAF r: lAr' " " ' ) - - - - - f lAF.,·~_...... 3P

lAF E lAF -""---'11 lAF-,:.=._.=--::::ot
lAF F ~SP lAF· lAF
~~.;.;;lI ~~~

Before P3H A After PSH A After PSH B

SP/lAFF
 10-2
Data can be retrived from the top of the stack via
PUL A
which "pulls" the data off the stack into ACC A. 'rhis is
similar to retrieving a stored serviette from the holder, the
last one in being the first one out. In the PUL operation the
stack pointer is incremented automatically, before each byte is
retrieved. Assuming the 2 PSH operations in the previous fr~~e
the instructionsl
PUL B
32 PUL A
first transfers the data, stored in lAFE, into Ace B, then
transfers the data from lAFF into Ace A. Note that the PUL
operations are in the reverse order to the PSH operations,
respecting the "Last In First Out" (LIFO) sequence.
Use of the stack permits temporary storage of data without
the need for a symbolic address or an accumulator usage. Modify
this now familiar subroutine to operate without ACe B. Assume
previous stack pointer initialization.
PF.:INT L.DA E: SEF.:C5 F.:
AND E: #$(12 TO PF.: I t·JT?
F~ERDITI
BEG! PF.:INT NOT 'T'ET.
5TA A SEPBUF PP I NT CHAF.:.
F.:TS AND PETUF.:N.

7FF4 SEF.:C5R EI~~U

------------------
:t?FF4
/
7FF5 SEF.:E:UF EG!U $7FF5
:+:
..:1:1tUj3:6 PF.:I NT
PSH A
t11J::'1!E"-
'I::, 7FF4 NOT'T'ET LDA A SEF.:CSF.:
\.31\.34 :::4 \.32 AN[:t A #$02
":1:1":1627 F9 BEG! NOT'T'ET
01.0::: 3:2 PUL A
\.3:t(19 E'-;:O
'I '7FF5 5TA A SEF.:E:UF
1~1~l(1C 39 F.:T5
WARNINGs For every PSH there must be a corresponding PUL to
restore the stack pointer to its original state.
 10-)
Assume that the main line program which calls this
PRINT subroutine iSI

07C3: 8[) :1.3:5E: .JSR PF.:INT

07C6 FE 077E LDX t1Et1PNT

If the stack pointer contains lAFF just before JSR PRINT

is executed, the address of the next main line instruction, 07C6
in this example, is stored on the stack. The low byte (C6) goes
into lAFF and the high byte (07) goes into lAFE. The stack
status at this point is depicted by this diagram.
The RTS instruction at the end of the subroutine
automatically performs two PUL operations,
restoring the 07C6 value in the Program Counter.
lAFO ~SP The next instruction executed is then from 07C6,
lAFE 07 the LOX MEMPNT instruction following the
lAFF c6 subroutine call.
Assume that the first byte of JSR PRINT resides in 0426,
and that the stack pointer contents is 13CB just before JSR PRINT
is executed. Draw the stack diagram showing stack contents and
SP value for each stack change, starting just before JSR PRINT is
executed and finishing when LOX MEMPNT is executed. The PRINT
subroutine is the one given in the answer of the previous frame.

--_/ the next PSH

r--...,
overwrites 29 1

13C5 ~SP
. lJC 6 ...SP ~CC A SP
13C 7 04 04
lJC 8 ....SP 13C 8 29 13C8 29 lJe
before just after after after after
JSR PRINT JSR PRIN'r PSH A PUL A RTS
 -
10-4
Examination of data stored on the stack is achieved vial
TSX - Transfer Stack pointer to indeX register.
which transfers the Stack Pointer to the Index Register, then
increments the. Index Register. In this way the Index Register
points at the last byte stored on the stack. This permits
direct access to the data, storea l)n the stack, wi thout
disturbing the Stack Pointer. Wri tl~ the instructions to print
the value of the last byte, stored on the stack. The sub-
routine OBY'l'E is available.

-------..;l'/
0203 30 TSX
0204 A6 0€1 LDA A X
02€16 E:D €1142 .JSR OBYTE

10-5
Assume' that 4 bytes have been stored on the stack. It
is now desired to increment the first of these 4 bytes without
disturbing the stack pointer or other data on the stack. Write
the necessary instructions.

_ _ _----.II
~11 ~3 ~:::1 J: ~:::1
~31"31 6C ~~f3: INC 'rsx =
SP + 1 ~ X
7JF5 -+-SP
7JF6 4 · . x
7JF7 1 • ••••••••• 1, X
7JF8 2 • ••••••••• 2. X
7JF9 Iii · J, X
More stack operations will be seen in the next chapter, Interrupt,
where the stack is used extensively.
 11-1 (a~

INTERRUPT
The simplest type of "interrupt" operation is that
produced when you start the 6800 microcomputer by pushing the
RESET button. This starts execution of a permanently stored
program or "service routine". as interrupt initiated programs are
called, this one servicing the RESEr button. When this button
is pushed the RESET line to the MPU is grounded. This causes
the computer to look in addresses FFFE and FFFF (called "vector"
addresses) for the address of the RESET service routine. The
RESET service routine is then started. typically clearing all
READY bits, initializing the stack pointer and setting up
input/output devices such as the PIA or ACIA for the required
mode of operation.
The RESET line also can be converted to force a restart
of this service routine automatically when power is first
applied, eliminating the RESET button. This is particularly
useful when the microcomputer controls an electronic subsystem
or an appliance (e.g., microwave oven).
Another form of interrupt provides the solution to the
problem of determining when a peripheral device has data or
requires data, without the continuous check of READY bits in an
ACIA or PIA. Under interrupt operation, such devices are ignored
by the computer until the device demands service, whereupon the
computer suspends its present operation. known as a "background"
program and executes the service routine or IIforeground program
ll

for the device which demanded service.

Such service may involve the transfer of one byte of data
or the change of several bits in a status register. When the
service routine is completed the computer resumes execution of
the background program.
 11-l(b)

Several points are relevant to interrupt operations.

(a) As stated above, READY bit polling or testing, as a routine
operation, is now eliminated permitting more flexible and
efficient use of the computer. With interrupt operation
the peripheral devices essentially say to the computer
"Don't call us. v~e' 11 call you.It

(b) The service routine is entered each time that a character

is transmitted or received by the interrupting device or
each time that a push button activates a PIA Control Line.
Such a service routine is short, typically requiring )0 to
60 microseconds to execute.
(c) The elapsed time between successive interrupts by a
particular device is usually long, compared to the execution
time for a service routine. Even at high data rates such as
960 Characters/sec., the time between successive interrupts
is approximately 1 millisecond. For push button activated
interrupts this time could be seconds to hours. Consequently
it is possible to service many devices via interrupt and
still execute background programs for a large percentage of
the computer's available time.
(d) Interrupt programs are not recommended initially because
programming errors are more difficult to find. Orderly
de-bugging, possible with nested subroutine type programs,
is less applicable here because the occurrence of interrupts
is essentially random in time. This makes it difficult to
determine the conditions of various registers at interrupt
time, if a service routine occasionally fails.
 11-1 (c)

Interrupt serv~c~ng of interfaces such as the ACIA or

PIA usually involves "Interrupt ReQuest" or "IRQ" operation, also
known as "Maskable Interrupt". Such an interrupt
request is made by grounding of the IRQ line to the
~SP MPU by the interrupting interface. This causes the
CCR present contents of the Program Counter, Index
Ace B Register, ACC A, ACe B and the CCR to be pushed
Ace A automatically on the stack in the above order.
IXH After p~oviding service to the interrupting device
IXL the IRQ service routine is terminated by the
PCH instruction
PCL RTI (ReTurn from Interrupt)
which automatically pulls the stored values from the
stack, restoring the above registers and accumulators to their
state when IRQ operation was requested. Resumption of the back-
ground program takes place as if nothing happened (except for the
slight delay to provide IRQ service).
IRQ operation first requires initialization of the IRQ
Vector Addresses, FFF8 and FFF9, with the address of the IRQ
Service Routine. IRQ operation (interrupt service) will then take
place if all the following are truel
(a) The Control Register of the appropriate interface (ACIA or
PIA) has been permitted to interrupt. For example bit #7 of
the ACIA Control Register is set to permit ACIA Receiver
Interrupt. PIA interrupt via CAl is permitted by setting
Control Register bit #0.
(b) The interface (ACIA or PIA) must activate (ground) the IRQ
line. This happens automatically when the READY bit is set,
indicating that data is ready from the ACIA Receiver, or
that data is needed by the ACIA T·ransmi tter, or that an input
Control Line in the PIA is now ACTIVE.
(c) The I (Interrupt) bit of the CCR must be cleared, e.g., via
the instruction
CLI (CLear Interrupt)
which permits all IRQ-connected interfaces to interrupt.
Hence IRQ operation is controlled "globally" via the I bit
and locally via each Control Register.
 ll-l(d)
The PIA and ACIA. connected for interrupt operation. are shown
in the block diagram below.

I EXTE~NAL
DEVICE
I c:,,, I 51! TS
I .7
f!A _
-1 &'T (bit.oal) XRQ
I fR~

sera•Q \ d0.t CI. ou t - '800 MPU

I ACtA m
0. \ d a. tel '" r' I(~ierr"pt EMbled)

Before the I bit is cleared to permit IRQ operation,

several preparations for interrupt operation must be made,
usually referred to as "background initialization". These area
(a) Set up the IRQ vector addresses FFF8 and FFF9 with the service
routine address.
(b) Set the Control Register bits of the appropriate interface
(ACIA or PIA) to permit an IRQ request via the receiver,
transmitter or Control Line.
(c) Set up any data pointers for storing or retrieving data.
Only now can the I bit be cleared to permit IRQ operation.
Write the background initialization to set the address
of ACIARX, the start of the ACIA service routine, in addresses
FFF8 and FFF9.

LDX IACIARX
---"/
STX $FFF8 INIT VECTOR FOR IRQ
When an interrupt occurs, the contents of the accumulators
and registers will be pushed on the stack. Then the address of
the next instruction to be executed will be obtained from FFF8
and FFF9, the IRQ vector address. In other words the next
instruction to be executed will be the first instruction of the
the IRQ service routine.
 11-2
....-
Continuing with the background initialization, set
the ACIA Receiver Interrupt bit, to permit interrupt to occur.
Then initialize MEMADD with the address one below address lAOO,
to permit storage of data from the ACIA Receiver. Assume, as
before, that ACIACR is the "original" for the "write only"
Control Register of the ACIA.

-----.;/
LDA A ACIACF.:
O~:A A #~10e00000 ENABLE RX INT
STA A ACIACR
STA A SERCSR
LD::.-:: #$1A0~1-1
STX MEMADD SET UP STORAGE POINTER.

So far the background initialization is.

131121121 CE 011C LDX #ACIARX

121103 FF FFF8 STX $FFF8 INIT VECTOR FOR IRQ
011216 86 738E LDA A ACIACR
011219 8A 80 ORA A #::-~1000001210 ENABLE R>-~ INT
01€1B B7 73E:E STA A ACIACR
010E B7 7FF4 STA A SERCSR
011:1 CE 19FF LDX #$:1A013-:1
12111.4 FF 01.1.A STX l'1El'lADD SET UP STORAGE POINTER.
 Now complete the background initialization by clearing
the interrupt bit in the Condition Code Register. At this point
a background task could be started. Since we have no background
task to do at this time, put the computer in an endless loop,
which will be interrupted from time to time by the ACIA, when
it receives another character.

CLI
-----..,,/
ENABLE INTERRUPT
HF.: E:F.:A HF.: BACKCiF.:OUNO LOOP

The complete background initialization to provide

interrupt service for the ACIA Receiver is then

10:1.12110 CE e:1.:1.C LL">~ #ACIARX

10:1.103 FF FFF8 STX $FFF8 INIT VECTOR FOR IRQ
0:1.06 86 73SE LDA A ACIACR
10:1.1219 SA 8121 ORA A #~~:1.0012112112100 ENABLE R>:: INT
12I:1.I2IB B7 738E STA A ACIACR
12I:1.0E B7 7FF4 STA A SEF.:CSR
121:1.:1.:1. CE :1.9FF LDX #$:1.A00-1.
1211:1.4 FF 011.A STX t1EMADD SET UP STORAGE POINTER.
0:1.17 €IE CLI ENABLE INTERRUPT
121:1.:1.8 2121 FE HR BRA HR BACKGROUND LOOP
e:1.:1.A 1211211212 t1Et1ADD RMB 2
 11-4
Now write the service routine ACIARX, which stores ~
byte via MEMADD each time that the service routine is entered.
Terminate this service routine with RTI, which returns control
to the interrupted background program.

--_----J/
* INTERRUPT SERVICE ROUTINE FOR ACIA RX.
* STORES ONE CHAR IN MEM VIA MEMADD POINTER.
0:1:1C FE 0:11A *ACIARX LDX t'1Et1ADD
01.iF 08 INX
0120 FF 01:1.A ST>:: t"lEt'lADI) GET NEXT ADDRESS
0:123: 86 7FF5 L[:IA A SEF~BUF GET DATA
0:126 A7 00 STA A>:: AND STORE VIA MEMADD
0128 38 F.~T I AND RETURN TO BACKGROUND.

Each time that the ACIA's Receiver is READY with another byte of
data, bit #0 of its Status Register will go to 1, indicating the
READY condition. Since bit #7 of the ACIA Control Register is
also set, permitting ACIA Receiver Interrupt, the setting of the
READY bit automatically activates the IRQ line to the iJIPU,
causing execution of the service routine whose starting address
is in FFF8 and FFF9. After the RTI instruction of this service
routine the background task, if there is one, will be resumed.
A long story isn't it?
 11-i
Printing a message via the ACIA under interrupt is
similar to data reception in the previous frame. Here the
ACIA Control Register bits #6 and 5 must be initialized to
provide "RTS = low, Transmitting Interrupt Enabled". (See
Appendix E).
Write the background initialization to permit printing
of the message INVALID HEX via the ACIA under interrupt.
Include the message in the background initialization.

------------------ /
~1:.1.. &.3~3 CE &.Z1:12A LD>~ #MESPRT GET INT ROUTINE ADDRESS
&':::':1&.Z1]: FF FFF8 ST;:-:: IRQVEC INIT MESSAGE POINTER
":::':1&.36 E"-.t,::• 73::=:E LDA A ACIACF.:
.31.(19 84 SF AND A #%1.0:1:1111:1. CLEAR BIT 6
":::'1 .:::,8 :=:A 2(1 oF.:A A #%130100000 SET BIT 5 TX INT ENABLED
(11.1-3D E'-.,::O 73E:E STA A ACIACR UPDATE ORIGINAL
(':1.1&,:::, ., 7FF4
Eo"::' STA A SERCSR SET UP ACIA
01.13 CE &.3:1.:1.8 LD::·:: #8ADHE::-::-:1.
1-)1:16 FF &.312S ST::-:: MEMADD SET UP POINTER
1-:::':1:1.9 "3E eLI
":;:'1:tA 213 FE HP 8 F.: A HR SPIN FOREVER
:+:
\.311C 49 BADHE::·:: FCC ••••1 I N\,'AL I D HE::·::.····
a.Z1:1.27 1.: :,&.:;:, FeE: 1-3
&.3:12S &.3(1&.32 t'lEt'lAO[) F.:t·18 2

11-6
Within the service routine how will you ensure that the
ACIA Transmitter will stop sending characters to the printer,
after the last character of the message is printed? /

----
Contd •••
 11-6
Peptd.

Disable the transmitter interrupt by clearing bits #6 and 5 of

the ACIA Control Register (see Appendix E). If another device
is still operating under interrupt, the above operation will
affect only the ACIA transmitter. If the ACIA transmitter was
the only interrupting interface, then all IRQ interfaces could
be interrupt disabled by the instruction SEI (SEt Interrupt),
the opposite to eLI.
11-7
Now write the service routine. entered each time ~o
print one character of the message. Assume the background
initialization shown in the previous fr~ne.

---_/ t'1F'U CYCLES

~3:12A FE (1:128 t'1ESPF.:T L(:I;:':: t1Et'1A()D 5
0:12(:1 (18 IN::-~ 4
0:12E FF 0:128 ST>:: MEMADD 6 GET CHAR ADDRESS
A X 5 GET CHAR
(11.3:1
(1:13:3
A6
.
.-0::..'...,.
"~10
04
LDR
BEG! NOt10F.~E 4
~~1:13:5 E:7 7FF5 STA A SEF.:8UF 5 PF.:INT IT
(1:13::: 38 PF.~TF.:T I F.:TI :1.0 TOTAL 39 MPU CYCLES
(11.39 86 73:=:E NOt10F~E LDA A ACIACF.:
01.3C 84 9F AN[) A #;·~:1.(u~1:t:1.:t:11
(1:1.3E
(1:141. 8-:0
,.'
'.
6'-::' 73:=:E
7FF4
5TA
STA
A
A
RCIACR
SEF.~CSF.~
DISABLE TX INT

(1:1.44 20 F'-'
c.. E:F.:A PF.~TF.~T I

At slow terminal rates e.g. 10 Characters/sec one character is

printed every 100 msec. At higher data rates e.g. 960 char/sec,
one character is printed every 'millisecond. The above service
routine requires 39 MPU cycles plus 9 to push and interrupt.
Assuming approximately 50 MPUcycles per interrupt, this is
still only 50 microseconds, using a 1MHz MPU clock. Hence
10 000 to 20 000 interrupts per second are theoretically
possible, supporting dozens of devices. Therein lies the power
of interrupt.
 So far we have looked at only one device operating undeL'
interrupt at one time. Consider an ACIA connected to a printer
-
11-8

(output) and a keyboard (input), both operating under interrupt.

When an IRQ operation is demanded by one of these devices, the
first task of the service routine is to determine which device
produced the in terrupt. Irhis is done by consecutively checking
the READY bit of each device capable of IRQ operation.
Write the first part of the IRQ service routine IRQSER
which determines whether the ACIA's receiver or transmitter
requires service, branching to KEYSER to service the keyboard or
PRTSER to service the transmitter.

:fi
--=-----~/
0200 86
7FF4 IRQSER LDA A SE(;'~CSR
12121213 85
1211 8IT A #$1211 R>~ READ.,.'?
12121215 26
49 BNE KE'r'SER
12121217 85
1212 BIT A #$1212 TX READY?
121209 26 65 8NE PRTSER
0208 38 INTRTN RTI RETURN POINT FOR ALL
Both servifYe
routines would
branch back
to here.
Although all IRQ controlled devices are theoretically equal for
interrupt service it is normal to poll the READY bit of the
fastest device first, if one is significantly faster than the
other to avoid losing data from the faster device while servicing
a slower device. Hence the first device polled effectively has a
slightly higher priority, this advantage increasing as more
devices requiring IRQ service are added to the system.
 11-9
PIA Control Lines acting as inputs can produce IRQ
operation if enabled for interrupt via the PIA's Control
Register. When bit #0 of Control Register A (or B) is set,
interrupt is then possible via CAl (CB1). Similarly CA2 (CB2)
is enabled via bit #3. CA2 (CB2) as an output line does not
produce an interrupt since interrupts originate with the external
device such as a keyboardttelling the computer that data is ready
to be moved or that some control action is needed.
Write the background initialization to permit CAl of the
PIA to interrupt when going high (1) and CA2 as an input to
interrupt when going low (O). The A half of the PIA should be
set to receive 8 bit parallel data.

* PROG TO SET UP PIA A HALF AS INPUT

:+:
------.1/
PINPUT L.[:tA A PI ACF.:A
A t-J [:t A # ~-~ 1.1I-Z1\.~11. ~1 :1.1.
5TA A PI ACF.:A CLEAF.: BIT 2 to DataBuffer
CLF.:
OF.: A A
5TA A
PIABFA INPUT t'100E
# ::-~ ~3 ~1I-:::n31.1.1.1.
PIACF.:A
! ~Al Active high
l_[:':;:: #PIASER
x X 0 o 1 1 1 1
$FFF8 t ~ tCAl interrupt
HR
5T::-::
CLI
E:~:A
REA:r
BITS •
, " ~enabled
CA2 CA2 CA2 Interrupt
input Acti va enabled
line low
 11-10
When an interrupt is produced by CAl of the PIA the
service routine is to store bits #0 to J of the Data Buffer in
LODATA. An interrupt by ~A2 should store bits #4 to 7 in
HIDATA. Assume that CAl and CA2 are the only source of interrupts.
Write the service routines.

0350
0352
HICJATA EQU
LODATA EQU
$0350
$0352
-------.i/
0100 86 *
7FF1 PIASER LDA A PIACRA
0103 2B 05 BMI CA1.INT CA1 INT F.:EGJ.UEST VIA BIT 7
0105 85 40 BIT A #~. ~010e0000
0107 26 0B SHE CA2INT CA2 INT F.:EQUEST VIA BIT 6
0109 38 PIARTN RTI
0i0A B6 7FF0 CAiINT LOA A PIABFA
010D 84 OF AND A #$0F ZAP HI BITS
0i0F 87 0352 STA A LODATA
0112 20 F5 BRA PIARTN
01i4 86 7FF0 CA2INT LOA A PIABFA
0117 84 F0 AND A #$F0 ZAP LO BITS
0119 87 0350 STA A HIDATA
0iiC 20 EB BRA PIARTN
If several PIA's are connected as IRQ devices. but capable of
interrupt via CAl only. the skip chain becomesl
LDA A PIACR5
BMI PIA5
LDA A PIACR6
BMI PIA6
etc.
 11-11
Another major use of IRQ operation is in controll1ng
the timing of specific computer operations. For example a
digital voltmeter m~y be required to make a measurement in a
lab experiment or in a process-control operation at the rate
of 10 measurements per second. Aside from the inaccuracy of
using timing loops for control of these measurements, the
computer is not available for other tasks.
The solution is in the use of a "Real Time Clock",
a device which produces interrupts at specific times or rates.
The service routine for the real time clock would then determine
which devices. get service at what times. In the example above,
the real time clock could be driven by the 60Hz line signal
producing 60 interrupts/sec. Write the background initialization
and service routine for this clock which causes the digital volt-
meter to make 10 measurements per second via the subroutine
DVMSER.

0:1.£10 86 06 LDA A
_ _ _-.--J/
#$(16
0:1£12 87 0:11C STA A COUNT
1211.1215 CE 0:1.0E LOX #CLKSER
0:108 FF FFF8 STX $FFFE:
01.08 0E CLI
01.0C 2121 FE HERE BRA HERE SPIN IN BACK

e1.0E 7A e1.1.C *'CL~(SER

DEC COUNT
121:111. 26 08 BNE CLKRTN NOT THIS TIME
£1113 E:6 1216 LOA A #$06 'TIES. RESET COUNTER
121:1:15 87 0:11C STA A COUNT
0:11.8 BD 0240 JSR DVt'1SER AND MEASURE VOLTAGE
£11.18 38 CLKRTN RTI ALL DONE
12I:1:1C 121001.
*'
COUNT Rt'18 1

This line frequency-controlled clock is a very simple timer.

Real Time Clocks, much more complex than this, are commercially
available.
 11-12
The Non Maskable Interrupt (NMI) is essentially the
same as the IRQ with the following exceptionsl
(a) It is always enabled (capable of interrupting), independent
of the I bit status.
(b) Its vector addresses are FFFC and FFFD.
(c) It will interrupt only when the MPU's NMI line changes
state from 1 to o. It will not re-interrupt until after
NMI has gone high and then is grounded again.
NMI operation is needed when a high speed device requires
high priority service, even if an IRQ service routine is
presently being executed, in which case the IRQ service routine
is interrupted to provide M~I service.
During an NMI service routine all other interrupts are
automatically disabled, hence NMI service routines cannot be
interrupted even for another NMI device. Upon return from an
NMI service routine, service will be provided for another NMI
device, if one is waiting; otherwise it will resume service to
an interrupted IRQ service routine, if one was interrupted. If
none of these are waiting,service will be provided to other
waiting IRQ devices, or to a background program, in that order.
Assuming that an NMI device interrupted an IRQ service
routine, show the state of the stack (in general terms) during
the NMI service routine.

_ _ _--.-J/
t-----1
. . SP DURING NMI UPON RETURN TO IRQ
SERVICE ROU'rINE
IRQ Status
7 bytes
}
1---1

Background Status Background Status

7 bytes 7 bytes
J...-- __
}
 11-13

In de-bugging a faulty program it is sometimes necessary

to know the status of internal registers (A, B, X, etc.) after
execution of a specific instruction within a program. This is
possible via the instruction
SWI (SoftWare Interrupt - operation code JF)
If JF (SWI) is placed in memory, in the byte following a specific
instruction, normal program execution will take place until this
)F is encountered, whereupon all internal registers will be
stored on the stack, as if entering an IRQ or NMI service routine.
In this case the program will transfer control via vector
addresses FFFA and FFFB to the SWI service routine, which usually
prints out the contents of the internal registers from the stack.
Insertion of the )F code destroys the original program, hence
most systems require RESET after an SWI service routine is
executed. An exception to this exists in some de-bugging programs
which save the byte which was replaced by 3F, and then restore it
after execution of the SWI service routine.
In some 6800 systems where the SWI routine is provided in
permanent or "Read Only Memory" (ROM) the vectors for SWI may also
be in ROM, rather than in Read/Write Memory, usually called R~~
(Random Access Memory), which can be initialized via RESET. If
vectors are permanent a user-written SWI routine cannot be
implemented.
Why is the stack essential to SWI operation?

------/
Data must be saved by MPU hardware rather than via software
(program) which itself would use some of these registers and
therefore modify their contents.
 11-14
Write the background initialization and the SWI serv~ce
routine to print the contents of CCR, ACe B, and ACC A simply as
6 ASCII characters, one after the other, when SWI is encountered
within the program. Assume an available subroutine, OBYTE,
which prints 2 ASCII characters, based on the 8 bit contents of
ACe A.

:+:
_ _ _-----J1,/
:+: SOFTWARE INTERRUPT SERVICE TO PRINT CCRJ
:+: ACC A AND B ON CONSOLE TERMINAL. CALLS OBYTE SUB.
:+:
FFFA SWIVEC EQU $FFFA
:+:
:+: BACKGROUND INITIALIZATION FOR SWI.
0200 CE 0240 LD>:: #Sl'~ I SEF.:
~321-33: FF FFFA
~3206 2"3 FE HF.: E:F.~A HF.~
:+:
:+: S~·JI SER'·lICE ROUTINE
:+:
024..:::' OF.:G $0240
~3240
-..::.....:::,- , PUL A GET CCR FF.~Ot'1 STACK
0241. BD ~11.42 .JSF.: OB'T'TE PF~INT CCF.:
0244 3:2 PUL A
0245 BD 01.42 .J 5F.: OB'r'TE PF.:INT B
024:3 32 PUL. A
..3 249 B[) ~11.42 .JSF.: OB'T'TE PRINT A
024C 20 FE HEF.:E BF.:A HEF.:E
:+:
01.42 OBYTE EQU
END
 11-15
Now write the first part of a different SWI service
routine SOFINT, which prints a more readable output of the
stored data, e.g.,
CCR= XX (where XX = stored CCR value)
Assume the following a~ailable subroutines I
OBYTE - prints contents of ACC A as 2 ASCII
character.
OUTMES - prints ASCII message terminated by
null. X = pointer.
CRLF - Carriage Return and Line Feed.

:+:
:+:
---------/
PRINTOUT OF REGISTERS AFTER SOFTWARE INTERRUPT
:+:
0200 CE 0250 LDX ISOFINT
02103 FF FFFA STX $FFFA INIT SWI VECTOR.
:+: NOW JUMP TO TARGET PROGRAM
:+:
0250 OF.:G $02510
0250 8D 0:179 SOFINT JSR CRLF
0253 CE 028:1 LDX ICCRt1ES
10256 BD 1.F0C JSF.~ OUTMES PRINT CCR=
0259 3:2 PUL A
025A 8D 0142 ..JSF.: OBYTE PRINT CCR CONTENTS
:+:
:+:
0281 43 CCF.:t1ES FCC: . . . eCR= I
0286 1Zn.3 FCE: ~3

Note that entry to OBYTE is at 0142, rather than at 0139, in

the original OBYTE routine (Subroutine Chapter), since the data
to be printed is already in ACC A. The CRLF routine is also
from the Subroutine Chapter. The OUTMES routine is from the
ACIA Chapter, bu~ in subroutine format.
 11-16
Execution of the OBYTE subroutine involves use of the
stack. Will this destroy data now on the stack, yet to be
printed within the SWI service routine? Use stack diagrams to
prove your answer.

No.
-_-------.#/
Data to be printed will not be destroyed •

. .SP
. .SP RH RH
CCR CCR ~SP RL RL ~SP

B B B B
A A A A
IXH IXH IXH IXH
IXL IXL IXL IXL
PCH PCR peH PCH
PCL peL peL peL
Within SWI After Within OBYTE sub. After return
service first RH and RL are from OBYTE
routine PUL A. return address subroutine.
before bytes. H = high, RL and RH will
I?rintout L = low. CCR data be overwritten
begins. on the stack is in future use
overwritten but of the stack.
only after it is
in ACC A for
printing.
 11-17
Cont inuin g with the same serv ice rout ine. assum e that
eCR. ACC B and ACe A have been pulle d and prin ted on one
line.
How woul d you prin t the Index Regi ster cont ents. stil l
cont inuin g
on the same line? Inclu de the mess age in your answ er.

0271.
0274
CE
BD
~1291
1.F~3C
LD::-::
.JSR OUTt1ES
- - - - - .. 1 /
# I ~·::t1ESS
PRINT ::.(=
121277 32 PlIL A
-BD
13278 0:1.42 JSF:: OB'r'TE PF.:INT HI B'T'TE OF ::.::
027E: .....-.
.::or:!. PUL A
027C BD 13:1.42 JSF~ OB'r'TE PF:~INT LO B'r'TE OF ::-::
:+;
:+;

13291 213 I >f,t1ESS FCC / ~

X= ~ Note spac e befo re
121295 13(1 FeB 0' and afte r mess age
to make mess age
read able .

Such a routi ne is norm ally inclu ded in the comp uter

syste m softw are and is esse ntial in "de-b uggin g" faul ty
prog rams .
By setti ng SWI (JF) in the main progr am. just afte r a
subr outin e
call. the resu lts of the subr outin e can be exam ined in
deta il to
deter mine how it perfo rmed . The place in the main progr
am wher e
the SWI occu rs is often calle d a brea kpoi nt.
More soph istic ated de-bu g rout ines perm it mult iple brea
k-
poin ts for testi ng of part ially comp leted prog rams . e.g
••
subr outin e calls for whic h the subr outin es have not yet
been
writ ten. The "loos e ends" or unwr itten code can be caug
ht by
brea kpoi nts.
 11-18
The complete listing for the SWI de-bug routine is
shown below.
:+:
1.F0C OUTMES EQU $lF0C
[1179 CRLF EQU $0179
~3142 OB'T'TE EQU $0142 LATE ENTRY. AVOIDS X.
:+:
:+: PRINTOUT OF REGISTERS AFTER SOFTWARE INTERRUPT
:+:
€120e CE ~~125~3 LD>!' #SOFINT
021213 FF FFFA STX $FFFA INIT Sl'~I VECTOFt
:+: NOl·~ ,JUto1P TO TAF::CiET PROCiRAt1
:+:
12125121 ORCi $~325€1
~325e 8D ~3179 SOFINT .JSR CRLF
121253 CE [12E:l LD~'~ #CCRt1ESS
t1256 BD 1F£1C .JSF~ OUTt1ES PF.:INT CCF.:=
13259 32 PUL A
e25A BD 0142 ,JSR 08'r'TE PF.:INT CCF.: CONTENTS
€125D CE 12128C LD>~ #8t1ESS
1212613 BD 1FeC SSR OUTt'1ES PF~INT 6'-
,-
12126::::~ 3:2 PUL A
0264 80 13142 .JSR OB'T'TE PF.:INT B CONTENTS
0267 CE ~3287 LDX #At1ESS
026A 8D 1F0C .JSR OUTt1ES PRINT A=
12126D 32 PUL A
026E 8D ~3142 .JSF.: OB'r'TE PF.:INT A CONTENTS
0271 CE 0291 LDX # I :x:t'1ESS
0274 BD 1F~3C .JSR OUTt'1ES PRINT ::.::=
0277 32 PUL A
121'0:::;,.
-' '? C''_' 8[) 121142 .JSF.: 08'r'TE PF.:INT HI B'TITE OF :)~

0278 <.-.
_.~ PUL A
~327C SO 13142 .JSF~ OB'r'TE PRINT LO B'r'TE OF X
1!:127F 2~3 FE HEF.:E BF.:A HEF.:E
:+:
13281 4~
.::. CCRt'1ES FCC ICCR= ,,/

0286 00 FCB 0
0287 20 At1ESS FCC I A= I
028B 0121 FCB €I
028C 2£1 Bt1ESS FCC ,~J E'-
,- (.J

132913 01!:1 FeB ~3

0291 21!:1 I::-::t1ESS FCC / :X:= (".,

0295 ~~n3 FeB ~3

END

The final printout of this could then look like.

CCR= 2F B= D3 A= F2 X= lC5S

Congratulations! You have completed the workbook. Good luck

with your programs.
 APPENDIX. A AND B

APPENDIX A

Hex Codes - 4 bits

0000 = 0 1000 = 8
0001 = 1 1001 = 9
0010 = 2 1010 = A
0011 = J 1011 = B
0100 = 4 1100 = C
0101 = 5 1101 = D
0110 = 6 1110 = E
0111 = 7 1111 = F

----~~-~-~-~~---------------~~~-
----~-----~---~-~~------~-~-

APPENDIX B

ASCII Code s

BIrrS 4 thru 6 0 1 2 3 4 5 6 7
0 NUL DLE SP 0 @ p
P
1 SOH DCI ! 1 A Q a q
2 STX DC2 " 2 B R b r
3 ETX DC3 # 3 C S c s
4 EOT DC4 $ 4 D T d t
5. Et\Q N.AK % 5 E U e u
BITS 0 thru 3 6 ACK SYN & 6 F V f v
7 BEL ETB 7 G W g w
8 BS CAN ( 8 H X h x
9 HT E~1 ) 9 I Y Y
A LF SUB * J Z j z
B VI ESC + K [ k {
C FF FS < L I I I
D CR GS = M ] m }
E SO RS > N ( n =
F 51 US I ? 0 0 DEL

Courtes y M~t0rol a Sc@ico nductor Produc ts, Inc.

 APPENDIX Cl
Instruction Set (2 pages)

ADORI. . ., MODIS COlO. COOi REG.

BOOLEAN/ARITHMETIC OPERATIOft
ACCUMULATOR AND MEMORY IMMED DIRECT INDEX EXTND INHER S 4 3 2 I 0
(AII'..ist. . . . .
OPERATIONS MNEMONIC OP - # 0' - # 0' - ,;,&,
0' - # OP - # rtfff to ClHltewts» H I
"t Z v C
Add ADOA 88 2 2 98 3 2 AS 5 2 BB 4 3 A+M-A t • t ~ t
ADDS CB 2 2 DB 3 2 EB 5 2 FB 4 3 B+Y"& I • t t : S
Add AcmltlS ABA 1B 2 1 A+B"A l • ~ t t t
Add with Carry AOCA 89 2 2 99 3 2 A9 5 2 89 4 3 A+M+C-A· I • I t t ~
AOCS C9 2 2 09 3 2 E9 5 2 f9 4 3 B +M + C"S t • J ~ J :
And ANOA
ANOa
84 2 2 94 3 2 A4 5 2 B4 4 3 A.M-A • • + t R •
C4 2 2 04 3 2 E4 5 2 f4 4 3 B· M-"8 • • t J R •
Bit Test BITA 85 2 2 95 3 2 AS 5 2 SS 4 3 A.M
• • t t R •
81TB CS 2 2 05 3 2 E5 5 2 F5 4 3 B.M
• • t t R •
Clear CLA 6F 7 2 7F . 6 3 00 -M • • R 5 R R
ClRA 4F 2 1 00 -A
- • • R S R R
CLRB 5F 2 1 00 -8 • • R ~ If R
Compare CMPA 81 2 2 91 3 2 Al 5 2 Bl 4 3 A-M • • t f t :
CMPB Cl 2 2 01 3 2 E1 5 2 Fl 4 3 B-M • ~ t t t t
Co mparl Acmltrs CBA 11 2 1 A-B • • t : t I
Complement. l's COM 63 7 2 13 S 3 M-M • • ~ t R S
COMA 43 2 1 A-A • • t t R S
COMB 53 2 1 i-B • • I t R S
Complement, 2's
(Negate)
NEG 60 7 2 10 S 3 00 -M-M • • t t<D ®
NEGA 40 2 1 00 -A-A • • t tCD ®
NEGB 50 2 1 00 - B-'B • • t f(D @
Decimal Adjust. A DAA 19 2 1 Converts Binary Add. of BCD Characten
into BCD Fo,mat • . t t t@
Oecrement OEC 6A 1 2 7A S 3 M -1-M. • • t t @ •
OECA 4A 2 1 A-l-A • • t 10 •
DeCa SA 2 1 8-1-a • • t t@ •
Exclusive OR EORA 88 2 2 98 3 2 A8 5 2 B8 4 3 A~M-A
• • t l R •
eDRB C8 2 2 08 3 2 E8 5 2 F8 4 3 B$M-B
• • f t R •
Incremena INC 6C 7 2 7C S 3 M+l-M • • t t ® •
INCA 4C 2 1 A+'l~A
• • t t ® .,
INCB SC 2 1 B +1-8 • • t t@ •
Load Ac:mhr LDAA 86 2 2 96 3 2 AS 5 2 86 4 3 M-A • • t t •
R
LOA8 C6 2 2 06 3 2 E6 5 2 F6 4 3 M-B • • t t •
R
0,. Inclusive DRAA SA 2 2 9A 3 2 AA 5 2 SA 4 3 A+M-A • • 1 : R •
DRAB CA 2 2 DA 3 2 EA 5 2 FA 4 3 S+M-B • • f ~ R •
Push Data

Pull Data
PSHA
PSHB
PULA
36
31
32
4
4
4
1
1
1
A-MSp, SP-l-SP
B -MSp,SP-l-SP
SP+ I-SP, MSp-A
•
•
•
0

11
~

• • • • •
• ·..
• • •

PUlB 33 4 ,1 SP + 1 -SP, MSp-B • • • •• •

• • t l ® t
:1 ~--
Rotate Left RDl 69 7 2 19 6 3
ROLA 49 2 1
..
111111' 11:1
D7 tlo • • t i ® t
ROLB 59 2 1 • • t t @ f
Rotate Right RDR 66 1 2 76 6 3
MI' • • t t @ t
RORA
RORB
46
56
2
2
1
1 :1 ~ - 1'1"'11
b7 bo ~
;:J •
•
•
•
t
t
t @ t
t @ t
Shih left. Arithmetic ASL 68 7 2 78 6 3 ..- • • t t ® t

Shift Right. Arithmetic

ASLA
ASlB
ASR 67 7 2 77 6 3
48
58
2
2
1
1 :1 o ..-
C
111111111"-0
b7 bo •
•
•
•
•
•
t
t
t
t ® ~
t
t@ :
® t
ASRA 47 2 1 =} 01117"" -
B b7 bo
0
c • • ~ :@ :
ASRB 57 2 1 • • J t @ t
Shift Right, logic. LSR
lSRA
64 7 2 74 6 3
44 2 1
:} 0-1111111"
~
- - bo
0
c
•
•
•
•
R l
R t ® t
@II
LSRB 54 2 1
• • R t @t
Store Atmltr. STAA 97 4 2 A7 6 2 87 5 3 A-M • • t f R •
STAB 07 4 2 E7 6 2 F7 5 3 B-M • • t I R •
Subtract SUBA 80 2 2 90 3 2 AD 5 2 80 4 3 A-M~A
• • 1 ~ ~ t
SUBS CO 2 2 DO 3 2 EO 5 2 FO 4 3 B-M-B • • t t t t
Subract Acmltrt. SeA 10 2 1 A-B .... A
• • t : t t
Subtr. with Carry SBCA 82 2 2 92 3 2 A2 S. 2 82 4 3 A-M-C-A • • ~ t l t
S8C8 C2 2 2 02 3 2 E2 5 2 F2 4 3 B-M-C-B • • l t t t
Transfer Ac:mltrs TAB 16 2 1 A-B • • t t R •
TBA 11 2 1 8-A • • t t R •
Test. Zero or Minus TST 60 7 2 70 6 3 M-OO • • ~ t R R
TSTA 40 2 1 A-DO • • t t R R
lSTa liD 2 1 B -00 • • t t R R
 APPENDIX C 2.
Instruction Set (2 pages)

INO£X REGISTER AND STACK IMMED· DIRECT INOEX EXTND IHHER 5 4

'OINTIA OPERATIONS MNEMONIC
Compar. Ind.. Reg CPX ac
0' -
3
11

3
0'
9C
-
4
:F

2
0'
AC
- # 0' - ~
'!'f" 0' - ~
~ BOOLEAN/ARITHMETIC OPERATION H I
3 2 1
N Z V C
I

Decrement Index Rig DEX

6 2 BC 5 3 (XH/XL) - (M/M + 1) • • (!)l @.
Decrement Stack 'nt' DES
09 4 1 X-l-X
• • • t • •
Increment Ind.. Reg INX
34 4 1 SP-l-SP • • • •• •
Increment Stack Pntr INS
08 4 1 X+ I-X
• • • ~ • •
31 4 1 5'+ I-SP
• •• •• •
~
load Inde". Reg LOX CE 3 3 DE 4 2 EE 6 2 I
load Stack Pntr lOS 8E 3 3 9E 4 AE
FE 5 M-XH. (M + 1)-Xl • • @t R •
Store Index Reg STX OF
2 S 2 BE 5 !II -S'H. (M + 11 -SPl • • @~ R •
Store Stack Pntf STS 9F
5 2 EF 7 2 F.F 6 3 XH -M. XL -(M + 1) • • @S R •
Indx Reg - St.ck Pntr TXS
5 2 AF 7 2 SF 6 .3 SPH -M. S'l -(M + 1) • • @t R •
35 4 1 X-l-SP • • • •• •
Stack Pntr .. Indx Reg

JUMP AND BRANCH

TSX

I RELATIVE INOEX EXTND

30 4

INHEA
I SP+l-X • • • • •
5 4 3 2 1
- 0
.OPERATIONS MNEfe'ONIC 0' - ::: 0' - ;; 0' - ~ 0' - :t BRANCH TEST H I N Z V C
Branch AlwaVs
Branch If Carry Clear
Branch If Carry Set
BRA
BCC
20
24
4
4
2
2
None
CzO
•
• - •• •• •• ••
•
Sranch If ~ Zero
BCS 25 4 2 C~l
• •• • • •
Branch If ;;. Zero
BEQ 21 4 2 Z2 1 • •• • • •
Branch If > Zero
BGE 2C 4 2 N'9V=O • •• • • •
Branch I f Higher
BGT 2E 4 2 Z+(N-itV)aO • •• • • •
Branch'f < Zero
BHI 22 4 2 C+Z :I 0 • •• • • •
BLE 2F 4 2 Z +fNav) = I • •• • • •
Branch If loWtf' Or Same
Branch If < Zero
BLS 23 4 2 C+Z= 1 • •• • • •
Sranch If Minus·'
alT
SMI
20
28
4
4
2
2
N'='V=l
N:zl
•
•
•
•
•
•
•
•
•
• -
•
Branch If Not Equal Zero SNE 26 4 2 Z-o • •• • • •
Branch If Overflow Clear BVC 28 .4 2 V=o • •• • • •
Branch If Overflow Set BVS 29 4 2 V= I • •• • • •
Branch If Plus
Branch To Subroutine
BPL
BSR
2A 4
80 8
2
2
N=O •
•
•
•
•
•
•
•
•
• -
•
Jump JMP SE 4 2 1E 3 3 } See Sptcial Operations • •• • • •
Jump To Subroutine
No Operation
JSR AD 8 2 BO 9 3
j
• • • • • •
Return From ,,,terrupt
NOP
RTI
01 2 Advances Prog. Cntr. Only • • • • • •
38 10 1 --@--
Retur~ From Subroutine

Software Interrupt
Wait for Interrupt
RTS
SWI
WAI
39
3F
3E
5
12
9
1
1
1
} See special Operation.
-I-fl-I-r
• S ••••
• @ ••••
CONDITIONS CODe REGISTER- INHER 5 4 3 2 1 0
CONDITION CODE REGIST£R NOTES:
,.OPE~ATIO~S MNEMONIC 0' - =
BGOL'EAN
OPERATION H I N Z V C
(Bit set if test's true .nd cleared otherwise)
Clear Carry ClC OC 2 1 O-C • • • • • R CD (Bit V) Test: Result.= 100000001
Clear Interrupt Mask CLI OE 2 1 0-1 • R • • • • @ (Bit C) Test: Result: 000000001
Clear Overflow ClV OA 2 I o-v • • • • R • @ (Bit C) Test: Decimal value of mOlt significant BCD Character gr~.ter than nine?
Set Carry
Set Interrupt Mask
SEC
SEI
00
OF
2
2
1
I
1-C
I-I -• • • • -
• • • •
S
S INot cleared if previously set.)
@ (Sit V) Test: Operand = 10000000 prior to execution?
Set Overffow
Acm~tr A-CCR
SEV
TAP
OB
06
2
2
1
1
I-V
A-CCR --• - •S ® IBitV) Test: Opennd: 01111111 prior to execution?
- - - @ - - ® (Bit V) Test: Set equal to rewlt of N $ Caft" shitt has occurred.
0~ (Bit N) Test: Sign bit of ",ost significant (MS) byte of result :II 1?
CCR -Acmltr A TPA 01 2 1 CeR -A -1·1-1·1-1· @8 Bit
() V Test: 's com plement overflow from sub traction f lS bytes?
® (Bat N) Test: Resun less than zero? (Bit 15 - 1)
LEGEND: 00 Byte =Zero; @ (AU) load Condition Code Register from Stack. (Se. Special Oplfations)
OP Operation Code (Hexadecimal); H Half-carry from bit 3; o
(Bit I) Set when int!mJpt occun. If previously Sit, a Non-Maskabl, Interrupt is
required to exit the wait state:
Number of MPU Cycles; I Interrupt mask
11 Number of Program Bytes; N Negative lsign bit) o (ALL) Set accordif'g to the contents of Accumulator A.
+ Ari.thmetic Plus; Z Zero (byte)
Arithmetic Minus; V Overflow. 2's complement
800lean AND; C Carry from bit 1
MSp Contents of memory loution R Reset Always
pointed to be Stack Pointer; Set Always -
S
+ Boolean Inclusive OR; ~ Test and 'itt if true. cleared otherwise
$ Boolean Exclusive OR; • Not Affected
fA tomp'ement of M; CCR Condition Cod. Register
Transfer Into; lS Least Significant
a Bit ~ Zero; MS Most Significant

Courtesy Motorola Semiconductor Products. Inc.

 APPENDIX D
Machine Code

00 * 40 ~EG A 80 SUB A 1t\1~1 co Sl~B II I~l~f

01 NOP 41 • 81 C~fPA I~t~f Cl CMP 8 IMM
02 • 42 • 82 SSC A I~tM C2 S8C B It-1M
03 • 43 COM A 883 • C3 •
04 • 44 LSR A 84 AND A l~fM C4 A~D B I~t~{
05 • 45 • 8S BIT A 1~IM CS BIT B I!\tM
06 TAP 46 ROR .... 86 LOA A I~f~f C6 LDA B L\1M
07 TPA 47 ASR A 88 .. C7 •
08 INX 48 ASL A 88 EOR A IM!\.t C8 EOR B l~fM
09 DEX 49 ROL A. 89 ADC A I~I~1 C9 ADC B I,.tM
OA CLV 4A DEC A 8A ORA A l!\-IM C.t\ ORA B IM~I
08 SEV 48 • 88 ADD A I~t~l CD ADD B I~'f
oc CLC 4C L~C A 8e CPX A I!\1M CC •
OD SEC 4D TST A 80 BSR REL CD •
OE CU 4E • 8E LDS IM~t CE LOX IMM
OF SEI 4F CLR A 8F • CF •
10 SBA 50 NEG B 90 SUB A DIR 00 SUB B DIR
11 CBA 52 • 91 CMP A DIR 01 C~·fP B DIR
12 • 52 • 92 SBC A DIR D2 sac B DIR
13 • 53 COM B 93 • 03 •
14 • 54 LSR B 94 Al~D A DIR D4 AND B DIR
15 • 55 • 95 BIT A DIR D5 BIT B DIR
16 TAB 56 ROR, B 96 LDA A DIR D6 LOA B DIR
17 TBA 57 ASR B 97 STA A DIR D7 STA B DIR
18 * 58 ASL B 98 EOR A DIR D8 EOR B DIR
19 DAA 59 ROL B 99 ADC A DIR D9 ADC B DIR
lA * 5A DEC B 9:\ ORA A DIR DA ORA B OIR
IB ABA 58 * 98 ADD A DIR DB ADD B DIR
IC • 5C INC B 9C CPX DIR DC •
ID * 50 TST B 90 • DD •
IE • SE • 9E LDS DIR DE LDX DIR
IF • 5F CLR B 9F STS DIR DF STX DIR
20 BRA REL 60 NEG L'iD AO SUB A IND EO SllB B IND
21 • 61 • Al CMP A IND El Clw1P B IND
22 BID REL 62 * A2 sac A IND E2 sac B IND
23 BLS REL 63 COM ISO A3 • E3 •
24 Bce REL 64 LSR L'-;O A4 AND A INO E4 AND B IND
25 BCS REL 65 4:
AS BIT A INO ES BIT a I~JD
26 BNE REL 66 ROR l'l> A6 LOA A IND E6 LDA B I~'D
27 BEQ REL 67 ASR L~D A7 STA A IND E7 STA B IND
28 BVC REL 68 ASL 1."0 AS EOR A IND E8 EOR B IND
29 BVS REL 69 ROL IXD A9 ADC A IND E9 ADC B IND
2A BPL REL 6A DEC L':D AA ORA A IND EA ORA B IND
2B B~fi REt 68 • AB ADD A IND EB ADD B IND
2C BGE REL 6C INC L"D AC CPX IND EC •
20 BLT REL 6D TST I~D AD JSR IND ED •
2E BGT REL 6E J~1P I~D AE LOS IND EE LOX ~O
2F BLE REL 6F CLR I~D AF STS IND EF STX L"D
30 TSX 70 NEG EXT BO SUB A EXT FO SUB B EXT
31
32
33
34
INS
PUL c.A
PUL B
DES
71
72
73
74
·
•
.:.~
Cb.~f EXT
LSR EXT
Bl
B2
B3
C~fP A
sac A
..
EXT
EXT
FI
F2
F3
F4
CMP B
sac a
•
EXT
EXT

B4 AND A EXT AND B EXT

35 TXS 75 • 85 BIT A EXT F5 BIT B EXT
36 PSH A 76 ROR EXT B6 LDA A EXT F6 LDA B EXT
37 PSH 8 77 ASR EXT B7 STA A EXT F7 STA B EXT
38 • 78 ASL EXT 88 EOR A EXT F8 ADe B EXT
39 RTS 79 ROL E.XT B9 ADC A EXT F9 ADC B EXT
3A * 7A DEC EXT BA ORA A EXT FA ORA B EXT
38 RTI 78 • BB ADD A EXT Fll ADD B EXT
3C • 7C INC EXT BC CPX EXT Fe •
3D
3E
* 7D TST EXT BD JSR EXT FD •
WAI 7E J~1P EXT BE lns EXT FE LDX EXT
3F SWI 7F CLR EXT BF STS EXT FF STX EXT
Notes: 1. Addressing ~Iodes; A = Ac:cumul,uor A l~tM Immediate REL Relative
B = Accumulator B DIR Direct IND Indexed
2. Unassigned code indicated by"." EXT Extended

Hexadecimal Values of Machine Codel

Courtesy Motorola Semiconductor Products. Inc.

 APPENDIX El
- ACIA -
Asynchronous Communications
Interface Adapter
DEF'INITION OF ACIA REGISTER CON·TENTS

Buffer Address
D~ta
Bus Transmit Receive
Line Data Data Control Status
Numb~r Register Regist.. Register Register
(Write Only) (Read Only') (Write Only) (Read Only)
0 Data Bit O· Qata Bit 0 Counter Divide Receive Data Register
Select 1 (CRO) Fuil (RORF)
; , Data Bit 1 Dat8 Bit 1 Counter 0 ivide Transmi~ .Data Register
Select 2 (CR 1) Empty (TORE)
2, Data Bit 2 Data Bit 2 Word Select 1 Data Carr ier Detect
(-CA2) (~CD)

3 Data' Bit 3 Data Bit 3 Word Select 2 Clear-to·Send

(CR3) (CTS)
4 Data Bit 4 Data Bit 4 Word Select 3 Framing Error
(CR4) (FE)

5 Data Bit 5 Data Bit 5 Transmit, Control 1 Receiver Overrun

(CRS) (OVRN)
6 Data Bit 6 Data Bit 6 Transmit Control 2 Parity. Error (PE)
(CA6)
7 Data Bit 7··· Data Bit 7·· Receive Interrupt I nterrupt Request
Enable (CR7) (IRQ)
,. Leading bit ~ LSB '-= Bit 0
•• Data bit will be zero in 7·bit plus parity modes.
• •• Data bit is "don't care" in' 7-bit plus parity modes.
---'
ACtA Control Register Format

Enable tor Receiver In terrupt Counter ratio and Master reset select used
in both transmitters and receiver sections
b7 c: \ : Enable~ Int errupt Output in
Receiving Mode b1 bO Function (Tx, Rx)
0 0 +1
b7 = O~ Disables Interrupt Output In
Receiving M ode 0 1 +16
1 0 +64
1 1 MASTER RESET

I
l b7 b6 b5 b4 b3 b2 bl bO

RIE TC2 TC1 \~S3 'y'''S2 WSl CDS2 CDSl

I
Word Length, Parity, and Stop Bit Select

Transmitter Control Bits: Controls the Interrupt Output· and RTS b4 b3 b2 Word Length + Parity + Stop Bits
Output, and providei for Transmission of a Break 0 0 0 7 Even 2

b6 b5 Fu nction 0 0 1 7 Odd 2

o o Sets RTS = 0 and inh ibits Tx interrupt (TI E) 0 1 0 7 Even 1

o 1 Sets RTS = 0 and en abies Tx interrupt (T' E) I 0 1 1 7 Odd 1

1 o Sets RTS = 1 and inh ibits Tx interrupt (TIE) 1 0 0 8 None 2

1 1 Sets RTS = 0, Transm its Sreal< and inhibits Tx 1 0 1 8 None 1

interrupt (T IE) 1 1 0 8 Even 1
-Tie is the enable for the interrup t output in transmit mode. 1 1 1 8 Odd 1
 APPENDIX E2
- ACIA -
Asynchronous Communications ACI A Status Register Format
Interface Adapter

~;~~arri;:~:~:::
b2 = 1:
carrip.r is presc~
Indicates the: I()$'; of carrier.
1. The low-to·high transition of the OeD in-
t. - --l
put C~\Jscs b2= 1 and g'::nera\es an interrupt
(b7=1), (IRQ=O)
2. Reading the Status Registe, ~r.d Rx Data
Register or master res~ttlng the AC~A
causes b2=O and b 7~O .
...-._---
Receiver Data Register Full
bO == 0: Indicates that the Receiver Data
Register is ernpty.

,----
! Interrupt Request
bO = 1: Indicates that data has been trans-
ferred to the Receiver Data Register
and status bits states are set (PE,
OVRN, FE).
1 The interrupt request bit is the complement of 1. The Read Data Command on the high-to-
I the i AQ Ol.'tput. Any in1errl.pt that is set and low E transition or a master reset causes
, enabled '.vill bE:. available in th~ status register bO = O.
{ in addition to the norrnal I RQ output. 2. A "high" 011 the OCD input causes bO-=O
L_--- and the receiver to be reset.

I
I
I b7
IRQ
I
b6
PE I
b5
OVRN
I
b4
FE
1
b3
CTS I I OeD
b2
I
bl
TxDAE
I bO
RxDRF
I
T 1 T
Framing Error
b4 = 1: Indicates the absence of the first stop
bit resulting from character synchro·
nization error, faulty transmission, or
I
'-- a Break condition. Transmitter Data Register Empty
1. The internal Rx data transfer signal causes
b1 = 1: 'ndicates that tha transmitter data
b4=1 due to the above conditions and causes
Register is empty.
b4=O on the next Rx data transfer signal if
b1 :: 0: Indicates t~at the transmitter data
conditions ha'ie been rectified. Register is full.
1. The internal Tx transfer signal forces b1==1.
2. The Write Data Command on the high·to-
Overrun Error low E transition causes b1 =0.
b5 = 1: Indicates that a character or a num- 3. A Uhigh" on the CTS input causes b1=O.
ber of characters V\'ere received but
not read from the R x data register
prier to subsequent characters being
~ received.
1. The Read Data Command on the high-to-
10V\' E transition causes b5=1 and bO=1 if an
overrun condition exists. The next Read
Data Command on the high-to-Iow E transi-
tion causes b5=O and bO=O.

l Parity Error
b6 = 1: Indicates that a parity error exists.
The parity error bit is inhibited if no
parity is selected.
1. The parity error status is updated during
Clear to Send
The CTS bit reflects the CTS input status for
use by the MPU for interfacing to a modem.
NOTE: The CTS input does not reset the
transmitter.
the Interna! receiver data trans1er signal.

Courtesy Motorola Semiconductor Products, Inc.

 APPENDIX Fl
- PIA -
Peripheral Interface Adapter

DATA DIRECTION REGISTER

Accessed via Data Buffer address when bit #2 of the Control

Register is o•.
1 = output)
.
o = J.nput J~ for each of the 8 data lines on the Data Buffer.

--------
CONTROL REGISTER

CAl (CB'l)
(input o~ly)
7 6 5 4 3 2 1 0

~~ft9?1
I
CA1(CB 1)
,READY BIT
~
O=DDR access
~ I l 0 for no interrupt
(0 = CAl (CB1) ACTIVE in
(read only) via Data Buff L( goin@; LOW'
l=Data Buffer (1 = CAl (CB1) ACTIVE in
access (going, HIGH .

CA2 (CB2) I
bit #5
INPurr mOde.,....__·O_=.......i_n....
Plllllllu_t_..-.",A.. 1 = outPu~
7 6 5 4 J 2 1 0 bit #4
=1,....J.. =0
~~llt~)~~JrgA PROGRAMMED mO-d-e----....... 1
1~~2) J
READY
BIT
t ~ t
0 1 0 for no
t
+
interrupt
f
CA2 (CB2)
f.ollows bi t /13 =0 l=
bit #)

_
1

mode
HANDSHAKE STROBE mode
CA2 (CB2) ACTIVE CA2 (CB2) goes HIGH CA2 goes LOW'
goin~ LOW ( ) momentarily after
CA2 (CB2) ACTIVE following CAl CBl ·
READ from A Buffer.
going HIGH CA2 goes LOW after
READ from A Buffer. CB2 goes LOW
CB2 goes LOW after 'momentarily after
WRITE to B Buffer. WRITE to B Buffer.
 APIENDIX F2
PIA -
Peripheral Interface Adapter
01 :.: 0 : I AQA(9, 1 se~ by high-to-tow transi'tion on
CAt (CB1).
bl·c, 1 : 1RCA(S" se! by low-to·high tr:tns;tion on
CAl (CB1). r
'------- 1____ I ~A1 (Cal) Inter~JPt REtQuest Enable/Disable
. bO = 0: DisdbJa:i I RCAtB) r~1PU Interrupt by CAl (Cal)

lI
active transition.'
bO = 1 : Enable I AQA{B} MPU Interrupt by CA 1 (CB 1)
IRQA(B) 1 Interrupt Flag (bit b7) a~:tive tran~i'dor,.

cleared by "',PU Read of Output Regtsti!r A(B). May also be transit:~n of bO if CA 1 (CB1) active transition occurred
cleared by hardware Reset. , V ' . ' h i l e interrupt was rjisabled.

'=1_ ---=t-
b7

IRQA{B)l
'---.
, b6

IRCA(B)2
b5 _~J
CA2(CB2)
b3 p I DDR
t--_b__l----.i_b_6--f
CA1(CS1)
Flag f_'a_g_._~ C_'~~~~..-L~._c_c_e_s_s C_o_n_t_r_o_1__
- .Io._ _

__~_=r__.. --Jt=
I RQA(B)2 Interrupt Flag (bit b6)
CA2 (C82) Estobl!shed as Input (bS = O}- Goes high on active
.--.---__,J~_~
Detcuoines VJhether Data Direction Register Or au tput
transition of CA2 (CB2); Automa~icaJl" clcared by MPU Read Re~~i is Addressed
of Output Register A(B). May also be cieared by hardware
Reset. b2 ::II 0 : Data Direction R~gister seJe~teCS.

CA2 (CB2) Established as OutPut (bS = 1): ~ RQA(B)2 ::: O.

not affected by CA2 (C82) trans,tior,s. b2 :.: 1 : Outpu t Register seiected.
"'------------_._-------------'
_-
operat~on ~" f
-----~,-_..
CA2 (~B21 Establislled as Output by 1,5 ~ 1
b5 b4

o
b3

T
CA2
(Note t [hDt
u

CA2 :;.nd Co
output fonct;ons are not identic-31)
_

.. 2
_ .,

'l CA2 (CB2) Established as Input b.y b5 = 0

b5

o
b4
T TL-f>
b3

C.A.2 (C82~ Intarrupt A9Guest Enablel

b3 = 0 : Re~S trobe \N~t~CA ~.:.!~

,CA2 goes 10.... on first high-to..

I 'O;sable

b3 = 0: Disables IAQA(B) MFU

low E transition follO'Ning an Interrupt by CA2 (CB2)
f\,1PU Read of Output Register active transit.;on. 1
A; returnee high by next
ac tive CA 1 transi tion. b3 = 1: Enables I RQA{B) MPU
Interrupt by CA2 {C82)
b3 = 1: Reed Strobe wi ttl E Restore active tran~ition.
CA"2 gees IO~"1 on first hi9h·t~
low E vansiticn following an 1. I ROA,B) w:ii occur ~n next (M?U
MPU Read of Output Register getlerat~d) p~itive trc:.i'\!ai~~on of b3
if CA2 (CB2) <It:.~j\te transitiGn
A; returned high by next I occurred vvt-.ile interrupt \"~S

CB~
high-to-Iow E tr"nsition.
IL -... disabled.

Determines Active CA2 (Ca2~

Transition
b3 = 0: 'IJrite Stro~e With Cal Restore
for St!t"t~-n; inter~~ThQAT8T~
CS2 goes on low on 1irst !OVJ- fbit bsT .
t~ hi~ E ~rai\sitio., foiiowing
an MPU \A.'n~e into Output b4 ~ 0: I RQA(B)2 !et t:y high-t·:>-Jo..v
Reg:stcar B; n:~urned high by transition on C,o\2 {CB2).
th~ ne;<t acti"e CBl t:-an.;ition.
b4 = 1: I R OA( 8)2 set by ! o't/-to-high
b3 = 1: 'tiri ... ~ Str'.j~e 'Nith E Restore
transition on CA2 fCB2).
CB2 goe$ 10\'1 0" fi,.st Ivw-to-
high E transition following an ---------
b3 MPU \"Jt;te ;nto Output
Rc~;5ter B; returned hi~h by the

l S'?t/Res~t
next io~·,.to-high E transition.

CA2 (C32)

CA2 (C62) ~C~~ lew as ~'PU vvriteos

b3 := 0 in to C,=,ntrof Aegi~ter.
Courtesy Motorola Semiconductor Products
CA2 (CB2i 9(.":\ high a~ ~'PU writes
b3 = 1 into Control Register.
 APPENDIX G & H
APPENDIX G
CHAR ACTE R SET

The characters used in the source language for the Motorola assembler form
a
sub-set of ASCII (American Standard Code for Information Interchange,
1968).
The ASCII Code is shown-in App B •. The follo\ving characters are recogn
ized
by the assembler:
I. The alphabet A through Z
2. The integers 0 through 9
3. Four arithmetic operators:
+ - * ,.
4. Characters used as special prefixes:
# (pounds sign) specifies the immediate mode of addressing
$ (dollar sign) specifies a hexadecimal number
@ (commercial at) specifies an octal number
% (percent) specifies a binary number
(apostrophe) specifies an ASCII liter-dl character
5. Characters used as special suffices:
B (letter B) specifies a binary number
H (letter H) specifies a hexadecimal number
o (letter 0) specifies an octal number
Q (letter Q) specifies a octal number
6. Four separating characters:
SPACE
Horizontal TAB
CR (carriage return)
, (comma)
The use of horizontal TAB is always optional, and can be replaced by
SPACE.
Courtos y Motoro la Se~icon ductor Produc ts, Inc.

APPENDIX H
Commonly Used Instr uctio ns

As a quick refer ence :+:

86 4[: Le'A A #$4[:
guide some of the more commonly :+:
used instr uctio ns, along E:7 1.2F3 STA A $1.2F 3
:+:
with thei r mach ine codes~ 86 1.2F3 LDA A $:12F 3
are shown here . :+:
FE :12A7 LDX $1.2A 7
:+:
08 I t·~>(
:+:
FF 1.2A7 ·ST>:: $12A 7
:+:
A7 00 STA A >(
:+:
87 1.2[)5 STA A $:1.2 [:a 5
:+:
A6 00 L[:aA A X
 MICROPROCESSOR GLOSSARY
ACCUMULATOR: 1"he register where arithmetic or EXECUTION TI M E: 'The time taken to perform an MICRO PROCESSOR: A CPU implemented by use of
logic re~ults are held. Most MPU instructions . instruction in terms of clock cycles. large scale integrated c~rcuits. Frequently
manipulate or test the accumulator contents. FIRMWARE: Instructions or data permanently ~tored implemented on a single chip.
ACCESS TIME: time take for specific byte of storage in ROM. MICRO PROGRAM: Program inside MPU which
to become available to processor. FLAG: A flip flop that may be set or reset ·under controls the M PU chip during its basic
ACIA: ; Asynchronous Communication Inter-face software control. fetch / execute sequence. _
Adapter. Inter-face between asynchronous peri- FLIP-FLOP: two state device that changes state when MNEMONIC: A word or phrase which stands for
pheral and an M PU. clocked. another (longer) phrase and is easier to remember.
ALU: Arithmetic and logic Unit. The part of the MPU FLOPPY (DISK): Mass storage which makes use of MODEM: Modulator / demodulator used to send and
where arithmetic and logic functions are flexible disks made of a material similar to receive serial data over an audio link.
~~m~. . magnetic tape. NON VOLATIVE: ;Memory which will retain data
ASCII: American Standard Code for Information FLOW CHART: A diagram representing the logic of a content after power supply is removed, e.g. ROM.
Interchange. Binary code to represent alphanu- computer program. OBJECT CODE: To- bit patterns that are presented to
meric, special and control characters. GLITCH: Noise pulse. the M PU as instructions and data.
ASSEMBLER: Software which converts assembly HALF DUPLEX: Data transfer in two directions but O/C: Open Collector. Means of tieing together O/P's
language statements into machine code and only one way at a time. from different devices on the same bus.
checks for non valid statements or incompl~te HAND SHAKE: System of data transfer between CPU OCTAL: Base 8 number system. Character
definitions. and peripheral whereby CPU "asks" peripheral if!t decimal 0-8.
ASSEMBLY LANG: Means of representing pro- will accept data and hnly transfers data If OP CODE: Operation Code. A bit pattern which
gramme statements in mnemonics and conven- '·answer'··is yes. specifies' a machine operation in the CPU.
iently handling memory addressing by use of HARD COPY: System output that is printed on paper. OPERAND: Data used by machine operations.
symbolic terms. _HARDWARE: All the electronic and mechanical PARALLEL: Transfer of two or more bits at the same
ASYNCHRONOUS: Operations that initiate.a new components making up a system. time.
operation immediately upon completion of current HARD WIRE: Circuits that are comprised of logic PARITY: Check bit added to data, can be odd or even
one - not timed by system clock. gates wired together, the wiring pattern parity. In odd parity sum of data 1's + parity bit is
BASIC: iBeginner's All Purpose Symolic Instruction . determining the overall logic ·operation. odd.
Code. An easy to learn, widely used high level HASH: Nois.y signal. PERIPHERAL: Equipment for inputing to or
language. HEXADECIMAL: The base 16 number system. outputting from the system (e.g., teletype, VDU,
BAUD: Measure of speed of transmission line~
j Character set is decimal 0 to 9 and letters A to F. etc.).
Number of times a line changes state per second. HIGH LEVEL LANGUAGE: Computer language that is PIA: Peripheral Interface Adapter.
Equal to bits per second if each ,line state easy to use, but which requires compiling into POP: Operation of removing data word from LIFO
rep(esents logic 0 or 1. . machine code before it can be used by an M PU. stack.
BAUDOT CODE: 5-bit code used. to encode HIGHWAY: As BUS. PORT: A terminal which _the MPU uses to
alphanumeric data. IMMEDIATE ADDRESSING: Addressing mode which communicate with the outside world.
BCD: Binary Coded Decimal. Means of representing uses part of the instruction itself as the operand PROGRAMS: Set of MPU instructions which instruct
decimal numbers where each figure is replaced by data. the MPU to carry out a particular task.
a binary equivalent. INDEXED ADDRESSING: A form of indirect PROGRAM COUNTER: Register which holds the
BENCHMARK: A common task. for the addressing which uses an Index Registe.r to hold address of next instruction (or data word) of the
implementation of which programmes can be the address of the operand. program being executed.
written for different MPUs in order to determine INDIRECT ADDRESSING: Addressing mode where PROM: Programmable read only memory. Proms are.
the efficiency of the different M PUs in the the address of the location where the address of special form of ROM. which can be individually
particular application. the operand may be found is contained in the programmed by user. .
BINARY: The two base number system. The digits are instruction. PUSH: Operation of putting data to LIFO stack.
o or 1. They are used inside a computer to INITIALISE: Set up all registers, flag, etc., to defined RAM: Random Access Memory. Read write memory.
represent the two states of an electric circuit. conditions. Data may be written to or read from' any location in
BIT: A single binary digit. INSTRUCTION: Bit pattern whith must be supplied this type of memory.
BREAKPOINT: Program address at which execution to an MPU to cause it to perform a particular REGISTER: 'General purpose MPU storage location
will be halted to allow debugging or data entry. function. that will hold one M PU word.
BUFFER: Circuit to provide isolation between INSTRUCTION REGISTER: MPU. register which is RELATIVE ADDRESSING: Mode of addressing
sensitive parts of a system and the rest of that used to hold instructions fetched from memory. whereby address of operand .is formed by
system. INSTRUCTION SET: 'The repertoire of instructions combining current program count with a
that a given MPU can perform. displacement value which is part of the instruction.
BUG: A program error that causes the program to INTERFACE: Circuit which·connects different parts of
malfunction. ROM: Read Only Memory. Memory device which has
system together and performs any processing of its data content established as part o{ manufacture
BUS: 'The interconnections in a system that carry signals in order to make transfer possible (ie, and cannot be changed. .
parallel binary data. Several bus users are serial - parallel conversion). SCRATCH PAD: Memory that has short access time
connected to the bus, but generally only one INTERPRETER: An intArpreter is a software routine and is used by system for short t~rm data storage.
"sender" and one "receiver" are active at anyone which accepts and executes a high level language SERIAL: Transfer of data one bit at a time.
instant. program, but unlike a compiler does not produce SIMPLEX: Data transmission in one direction only.
BYTE: A group of bits - the most common byte size intermediate machine code listing but converts SOFTWARE: Programs stored on any media.
is eight bits. each instruction as received. SOURCE CODE: The list of statements that make up a
CLOCK: The basic timing for a MPU chip. INTERRUPT: A signal to the MPU which will cause it program.' -
COMPILER: Software which converts' high level to change from its present task to another. STACK: A last in first out store made up of registers
language statements into either assembly I/O: Input/Output. or memory locations used for stack.
language statements, or into machine code. K: Abbreviation for 2 10 = 1024 STATUS REGISTER: Register that is used to store the
CPU: Central processor unit. The part of a system KANSAS CITY (Format): D~finition of a CUTS based condition of the atcumulator after an instruction
which performs calc,..lation and data manipulation cassette interface system. has been performed (e.g., Acc = 0).
'functions. LANGUAGE: 'A systemmatic means of communicat- SUB ROUTINE: A sequence of instructions which
CROM: Control Read Only Memory. ing with an MPU. perform an often required function, which can be
CRT: Cathode Ray Tube. Often taken to mean LATCH: 'Retains previous input state until overwrit- called from any point in the main program.
complete output device. ten. SYNTAX: The grammar of a programming language.
CUTS: Computer Users Tape System. Definition of LIFO: last In First Out. Used to describe data stack. TRAP (Vector): Pre-defined location in memory which
system for storing data on cassette tape as series of LOOPING: Program technique where one section of the processor will read jiS a result of particular
tones to represent binary l's and O·s. program (the loop) is performed many times over. condition or operation.
DEBUG: The process of checking and correcting any MACHINE LANG: The lowest level of program. T-he TRI STATE: Description of logic devices whose
program errors either in writing or in actual only language an MPU can understand without outputs may be disabled by placing them in a high
function. interpreter. . impedance state.
DIRECT ADDRESSING: An addressing mode where MASK: Bit pattern used in conjunction with a ·Iogic TTY: Teletype.
the address of the operand is contained in the operation to select a particular bit or bits from TWO'S COMPLEMENT ARITHMETIC: System of
instruction. (Ad4rcss below 100 in 6800) machine word. performing signed arithmetic with binary numbers.
DMA: Direct Memory Access. MEMORY: The part of a system which stores data UART: 'Universal Asynchronous Receiver Transmit-
DUPLEX: Transfer of data in two di(ections (working data or instruction object code). ter.
simultaneously. MEMORY MAP: Chart showing the memory VDU: Video Display Unit.
ENVIRONMENT: The conditions of all registers, allocation of a system. VECTOR: Memory address, provided to the processor
flags, etc., at any instant in program. MEMORY MAPPED I/O: A technique of implement- to direct it to a new area in memory.
EPROM: Electrically Programmable Read Only ing I/O facilities by addressing I/O ports as if they VOLATILE: Memory devices that will lose data
Memory. Memory that may be erased (usually by were memory locations. . content if power supply removed (Le., RAM).
ultra violet light) and reprogrammed electrically. MICRO CYCLE: Single program step in an MPUs WORD: Parallel collection of binary digits much as
EXECUTE: To perform a sequence of program steps. Micro program. The smallest level of machine byte.
pro~ram step.

Reprinted from the September 1917 edition of Electronics Today International magazine. Toronto. Ontario_
 APPENDIX Jl
Asse mble r Erro r Codes

281 NA" DIRECT lYE ERROR

"ESSACE: ** •• ERROR 2e1 AAAAAA
REAMING: THE H~M DIREC1IVE IS NOT THE FIRST SOURCE STATEMENTJ
11 IS I1ISSIH C .. OR IT OCCURS )l!ORE TH~N ONCE IN THE
SA"E SOURCE PROCRA".
282 LABEL OR OPCODE ERROR
"ESSAGE: •••• ERROR 292 AAAAAA
"EAMING: THE ~ABEL OR OPCODE SY"BOl DOES HOT BEGIN
WITH AH
ALPHABETIC CHARACTER.
283 STATEMENT ERROR
"ESSACE: ****ERROR 2e3 AAAAAA
"EAMINe: THE STATE"EKT IS BLANK OR ONLY COHTAIHS A LABEL.
284 SYHT4X ERROR
"ESS~CE: •••• ERROR 294 AAAAAA
KEAHIHG: THE STATEKEHT IS SYNTACTICALLY INCORRECT.
295 L~BEl ERROR
"ESS~CE: •••• ERKOR 29S AAAAAA
"EAHIHG: THE STATEMENT LABEL FIELD IS HOT iER"IHATED
WITH A SPACE.
286 REDE~IHED SV"BOl
"ESSAGE: •••• ERROR 286 AAAAAA
"EAHIHC~ THE SVM9QL HAS PREVIO USLY BEEN DEFIN ED.
THE FIRST
VALUE IS SAYED IN SY"BOL TABLE.
297 UHDEFINED OPCODE
"ESS~CE: •••• £RROR 291 AAAAAA
"EAHIHC: THE SY"B~l IH THE OPCODE FIELD IS NOT A VAllO
OPCODE "HE"OMIC OR DIRECTIVE.
)8~ BRANCH ERROR
··P1ESSAGE: •••• ERROR 298 AAAAAA
"EAHIHG: THE BRANCH COUNT IS BEYOND THE RELATIYE 8YTE·S
RAHGE. THE ALLOWABLE RANCE IS:
<*+2> - 128 < D < <*+2) + "127
WHERE: • = ~DDRESS OF THE FIRST BYTE OF
THE
BRANCH INSTRUCTION
D • ~DDRESS OF THE DESTINATION OF THE
BRANCH INSTRUCTION.
~

289 "'ILLEC AL ADDRESS "ODE

~iSSACE: ••• *ERROR 289 AAAAAA
"EAHIHG: THE "ODE OF AD~RESSIHC IS HOT ALLOWED WITH THE
CODE TYPE.
op-
218 BYTE OVERFLOW
"ESS~GE: •••• ERROR 219 AAAAAA
HEAHI~C: AN EXPRESSION COHVERTED TO A YALUE ~REATER THAN
255 <DECI"AL). THIS ERROR ALSO OCCURS ON CO~PUTER
SYSTEMS HAYING WORD LENGTHS OF 16 BITS UHEH USING
HEGATIVE OPERANDS IN THE I"KEDIATE ADDRESSING
"ODE.. EXA"P lE:
L DA ~ •-5 ; C.A USE S ERR 0 R 2 1 8
THE ERROR HAV BE AVOIDED BY USING THE 8
BIT TWO'S CO"PLE"EHT OF THE HU"BER.
EXA"P LE:
LDA A "FB ; ASSE"BLES OK
 APPENDIX J2
Assembler Error Codes

211 UNDEFINED SV"80l

"ESSAGE: ••• *ERROR 211 AAAAAA
"EAHIHG: THE SYMBOL DOES HOT APPEAR tH A LABEL FIELD.
212 DIRECTIYE OPERAHD ERROR
"ESS~CE: ** •• ERROR 212 AAAAAA
"EAHtHG: SYNTAX ERROR IN THE OPERAND FIELD OF A DIRECTIVE.
213 EQU DIRECTI~E SYHTAX ERROR
"ESSAGE: ****ERROR 213 ~AAAAA
"EAHIHG: THE STRUCTURE OF THE EQU DIRECTIYE IS SYNTACTI-
CALLY INCORRECT OR IT HAS NO LABEL.
214 FeB DIRECTIVE SYNTAX ERROR
"ESSAGE: •••• ERROR 214 AAAAAA
"EAHIHC: THE STRUCTURE OF THE FeB DIRECTIYE IS SYHT~CTI­
CALLY INCORRECT.
215 FDB DIRECTIVE SYNTAX ERROR
"ESSAGE: •••• ERROR 215 AAAAAA
ftEAHIHC: THE STRUCTURE OF THE FDB DIRECTIVE IS SYNTACTI-
CALLY INCORRECT.
216 DIRECTIYE OPERAND ERROR
"ESSACE: ••• *ERROR 216 AAAAAA
"EAHIHG: THE DIRECTIYE/S OPERAND FIELD IS IN ERROR.
211 OPT DIRECTIVE ERROR
"ESSACE: •••• ERROR 217 AAAAAA
"EANING: THE STRUCTURE OF THE OPT DIRECTIVE IS SYNTACTIC-
ALLY INCORRECT OR THE OPTION IS UNDEFINED.

228 PHASINC ERROR

"ESSAGE: •••• ERROR 228 AAAA~A
"EAMINe: THE VALUE OF THE P COUHTER DURING PASS 1 AND
PASS 2 FOR THE SAnE IHSTRUCTIOH IS DIFFERENT.
221 SYKBOl TA9LE OVERFLOW
"ESSAGE: •••• ERROR 221 AAAAAA
"EAHIHG: THE SY"BOl TABLE HAS OVERFLOWED. THE HEW SY"BOL
WAS HOT STORED AND ALL REFEREHCES TO IT WILL BE
FLACGED AS AN ERROR.
222 SYNTAX ERROR IN THE SYMBOL
"ESSACE: •• **EiROR 222 AAAAAA
"EAHIHG: THE ONE-CHARACTER SY"BOLS ~, B, AND X CAHNOT BE USED
FOR USER-DEFIHED SY"BOlS. THEIR USE IS RESTRICTED
FOR REFEREHCES TO THE ACCU"ULATORS (A & B) AHD TO THE
INDEX RECISTER (X). ERROR 222 ALSO FLAGS ALL SOURCE
STATE"ENTS CONTAININC A SYftBOL THAT HAS BEEN REDE-
FINED.
223 THE DIRECTIYE C~HHOT HAYE A LABEL
"ESSAGE: ***-ERROR 223 AAAAAA
"EAHIMG: THE DIRECT lYE CANNOT HAYE H LABEL. THE LABEL FIELD
"UST BE E"PTV (BLA~K).

Courtesy Motorola Semiconductor Products, Inc.

 Il~struction Set (spare copy)

ADDRESSING MODES CONDo CODE REG.

BOOLEAN/ARITHMETIC OPERATION
ACCUMULATOR AND MEMORY U'AMED DIRECT INDEX EXTND INHER S C 3 2 1 oJ
OPERATIONS MNEMONIC OP - 11 OP - # OP - # OP - # DP - #
(All r~tst.r

ref,r to contents)
l,b.ls
H , N Z V C
Add AODA 8B 2 2 9B 3 2 AB 5 2 8B 4 3 A+ M-A t • t t t t

Add Acmltrs
AOOB
ABA
C8 2 2 DB J 2 EB 5 2 FB 4 3
18 2 1
8 .. M-B
A+B-A
t
t
-- t t t t
t t t t

--
Add with Carry AOCA 89 2 2 99 3 2 A9 5 2 B9 4 3 A+M+C-A t t t t t
AOCB C9 2 2 09 J 2 E9 5 2 F9 4 3 B"'M+C-B t 1 t t 1
And ANDA
ANOB
84
C4
2
2
2
2
94
04
3
3
2
2
A4
E4
5
5
2
2
B4
F4
4
4
J
J
A. M-A
B· M-B
-- -• • 1
t
t
R
R
--
Bit Test BITA
BITB
85
C5
2
2
2
2
95
OS
3
3
2
2
AS
E5
5
5
2
2
B5
F5
4
4
3
3
A.M
B.M
-- •- t
1
t
1 R
R
-•
•- -
Clear CLR 6F 1 2 1F 6 3 00 -M • R S R R
CLRA 4F 2 1 00 -A R S R R
ClRB SF 2 1 00 -B • • R S R R
Compare CMPA
CMPB
81
C1
2
2
2
2
91
01
3
3
2
2
Al
E1
5
5
2
2
B1
F1
4
4
3
3
A-M
B-M
-- -• 1
t
t t 1
t t t
Compare Acmltrs
Complement, 1's
CBA
COM 63 1 2 13 6 3
11 2 1 A-B
M-M
-•
-• ·•
t
t
t t 1
t R S
COMA 43 2 1 A-A 1 t R S
COMB 53 2 1 B.... 8 • • 1 t R S
Complement. 2's NEG 60 7 2 10 6 3 00 - M - M • • t 1 0 0
(Negate) NEGA 40 2 1 00 - A-A • • t 1 0 0

Decimal Adjust, A
NEGB

DAA
50

19
2

2
1

1
00 - B - B
Converts Binary Add. of BCD Characters
- •
• •
t
t
t
t
0 0
1 0
IOto BCD Fa. mat
Decrement DEC 6A 1 2 7A 6 3 M -l-M • • 1 t
o0-•
DECA
OEca
4A
5A
2
2
1
1
A - l-A
B-1-8
- •
• •
t
t
t
t
o ••
Exclusive OR EORA 88 2 2 98 3 2 A8 5 2 88 4 3 A-vM-+A • • 1 t R

Increment
EORB
INC
C8 2 2 08 3 2 E8
6C
5
1
2
2
F8
7C
4
6
3
3
B~M-+B

M + 1-M ·- •- t
® •
1
t
t
R
-
INCA
INCB
4C
5C
2
2
1
1
A+l-+A
8 .. , .... B
• -
t t ® •
• • t t ® •
load Acmltr LDAA
LOAB
86
C6
2
2
2
2
96
06
J
3
2
2
A6
E6
5
5
2
2
B6
F6
4
4
3
3
oM .... A
M -B
•
•
•
•
1
t
t
t
R
R
-•
Or. Inclusive ORAA 8A 2 2 9A 3 2 AA 5 2 BA 4 3 A+M .... A • • t t R •
DRAB CA 2 2 OA 3 2 EA 5 2 FA 4 3 B+M -B • • t t R •
Push Data PSHA
PSHB
36
37
4
4
1
1
A -+ MSp. SP-1 .... SP
8 - MSp, SP-l -SP
- - -
• •
• • • • •
•
•
Pull Data PULA 32 4 1 SP .. 1 .... SP. MSp - A
-• • • • •

-- •• ®® -
PULB 33 4 1 SP .. l-SP. MSp .... B • • • • •
Rotate Left ROL 69 7 2 79 6 3 t t t
r~·- ~-~~;;~~L~-:J
ROLA
ROLB
49
59
2
2
1
1 :1 C b7 ~
be
• •
t
t
t t
t @ t
Rotate Right ROA
RORA
66 1 2 16 6 3
46 2 1 :: C O -:'- rnJllD:}=:J
B C b] be
-• •• t
t
t ® t
t ® t
ROR8 56 2 1
-+
• • t t ® t
Shift Left. Arithmetic ASL 68 1 2 78 6 3 ~ • • t t ® t

Shift RIght, Arithmetic

ASLA
ASLB
ASR 67 7 2 17 6 3
48
58
2
2
1
1 :1 0
c
~
lTIIIJIIJ - 0
b7 be
• •
• •
• •
t
t
t
t @ t
t @ t
f ® t
ASRA 41 2 1 MJ C6:rriuIJ
A - - 0 • • t t ® t
-
b7 b() C
ASRB 51 2 1 8 • t t @ t
Shih RIght. Logic. LSR 64 7 2 74 6 3 • • R t @ t

:]
-+

--
lSRA 44 2 1 o -+ ITD..ITlIJ -+ 0
c • R t @ t
b7 be
LSRB 54 2 1 • R t @ t
Store Acmltr. STAA 91 4 2 A1 6 2 81 5 3 A -M • • t t R •

Subtract
STA8
SUBA 80 2 2
07
90
4
3
2
2
E7
AD
6
5
2
2
F7
80
5
4
3
3
8-M
A-M-A ·- -• t
f
t R
t t
•
t

Subract Acmltrs.
SUBB
SBA
CO 2 2 00 3 2 EO 5 2 fO 4 3
10 2 1
B - M-8
A-B-A ·• ·• t
t
t t
t t
t
t
Subtr. with Carry SBCA 82 2 2 92 3 2 A2 5 2 B2 4 3 A-M-C-A • • t t t t

Transfer Acmltrs
SBCB
TAB
C2 2 2 02 3 2 E2 5 2 F2 4 3
16 2 1
B-M-C-+B
A -+B -• •• t
t
t t
t R •
t

TBA 11 2 1 B-A • • t t R •
Test. Zero or Minus TST 60 7 2 70 6 3 M - 00 • • t t R R

:. TSTA 40 2 1 A-DO • • t t R R
TST8 50 2 1 B - 00 • • t t R R
 Instruction Set (spare copy)

INDEX REGISTER AND ST~.CK IMMED DIRECT INDEX EXTND INHER 5 4 3 2 1 a

POINTER OPERATlO NS MNEMONIC OP - = OP - OP - !f" OP - # OP - :# BOOLEAN/ARITHMETIC OPERATION H I N Z V C

Compare Indel Reg CPX 8C 3 J 9C 4 2 AC 6 2 BC 5 3 (XH/X L) - (M/M + 1) • • 0 t @.

Decrement Index Reg DEX 09 4 1 X-1-X • • • t • •

·· ·· ·
Decrem~nt Stad Pntr DES 34 4 1 SP - 1 -SP • • • •
Increment Index Reg INX 08 4 1 X + l-X • • t •
Increment Stack Pntr INS 31 4 1 SP +- 1 - SP • • • • •
load Index Reg
Load Stac k Pntr
lOX
lOS
CE
BE
3
3
3
3
DE
9E
4
4
2
2
EE
AE
6
6
2
2
FE
BE
5
5
3
3
M - XH. (M +- 1) - XL
M -SPH. (M +- 1) -SP l
• ·® t R •
• • @ t R •
Store [ndel Reg STX OF 5 2 EF 7 2 FF 6 3 XH -M,Xl-(M+-1) • • ® : R •

-- · · ··
Store Stack Pntr STS 9F 5 2 AF 7 2 BF 6 3 SP H -M, SP L -(M ~ 1) • • ® : R
Indx Reg - Stack Pnlr TXS 3S 4 1 X-I .... SP • • • • •
Stact. Pntr -Indx Rt9 TSX 30 4 1 SP +- 1 - X • •
JUMP AND BRANCH RElA TlVE INDEX EXTNO INHER 5 4 3 2 1 0

OPERATIONS MNEMONIC OP - = OP - = OP - :; OP - ;:; BRANCH TEST H I N Z V C

Branch Always
Branch If Carry Clear
BRA
BCC
20
24
4
4
2
2
None
c=o -• •• •• •• ·• ··
Bra:lch If Carry Set BCS
8EQ
25
21
"
4 2
2
C =1
Z =1
• • • •
• • • • ·· ••
· · ·•
Branch If :: Zero
Branch If ~ Zero BGE 2C 4 2 Ni1V::O • • •
> BGT 2E 4 2 Z + (N.; V):: 0 • • • • •

- ·· ··
Branch If Zero
Branch If HIgher - "I\Sl!1\ del BHI 22 4 2 C + Z :: a • • •
Blanch If ~ Zero BlE 2F 4 2 Z +,N .;V) = 1 • • • •
Branch If Lower Or Same
Branch If < Zero
-u""9"e' BlS
BLT
23
20
4
4
2
2
C + Z:: 1
N'E-V:: 1 • • • ·
• • • •
· ·· •
•
•
Branch If MInus 8MI 2B 4 2 N:: 1 • • • •

· · · · · ••
Branch If Not Equal Zero BNE 26 4 2 Z=O • • • • •
Branch If Overflow Clear BVC 28 4 2 v=o • •
BVS 29 4 2 V:: 1 • • • •
· · ·· ·•
B, anch II Overflow Set
Branch If Plus BPL 2A 4 2 N=O • •
BSR 80 8 2 • •
·.
· ·-I-. ··· ··•
Branch T0 Subroulln~

Jump JMP 6E 4 2 1E 3 3 } See SpeCIal Operauons • •

Jump To Subrouhnt! JSR AD 8 2 BD 9 3 •
No Operation NOP 01 2 1 Advances Pro~. Cntt. Only • • • •
Return From Interrupt RTI 3B 10 1 --@--
Return From Subroutine
Sohware Interrupt
Wait for Interrupt
RTS
SWI
WAI
39
3F
3E 9
5
12
1
1
t
} See special Operations
-I-fl-rl-
• S
• @ ••••
• • • •

CONDITIONS CODE REGISTER INHER 5 4 3 2 1 a CONDITION CODE REGISTER NOTES:

BOOLEAN
OPERATIONS MNEMONIC OP - = OPERATION H I N Z V C (Bit set ,f test IS true and cleared otherwlsei

Clear Caery ClC OC 2 1 O-C • • • • • R o (Bit V) Test: Result = 10000000'1

=00000000'1
Clear Interrupt Mask CLI OE 2 1 0-1 • R • • • • @ (Bit C) Test: Result

Clear Overflow
Set Carry
CLV
SEe
OA
00
2
2
1
1
O-V
l-e
• ·
• • R • @
• • • • • S
(Bit CI Test: Oeclmal value of most sigl\lficant BCD Character greater than nrne'
(Not cleared .f prevIously set.)

Set Interrupt Mask SEI OF 2 1 1-1 • S • • • • o (Bit V) Test: Operand:: 10000000 ;lrior to oecutlon?

Set Overflow SEV OB 2 I 1-V • • • • S • ® (BIt VI Test: Operand = 011 till t prior to execution?

Acmlt( A - CCR TAP 06 2 1 A -CCR --@-- ® (BIt V) Test: Set equal to result of N.; Cafter shIft has occurred.

CCR -Acmltr A TPA 07 2 1 CCR -A CD

-1·1·1-1·1· ® tBlt NI. Test: Sign bil of most Significant (MS) byte of result:: P
lBlt V) Test: 2's complement overflow from subtraction of LS bytes?
® (Bit N) Test: Result less than zero? (BII 15 = 1)

LEGEND: 00 Byte:: Zero; @ (All) Load Condition Code Register from Stack. (See SpeCial Opp.!a(lons)

Operation Code IHexadecimal); H Half·carry from bit 3; ([9 (Bit I) Set when Interrupt occurs. If p,eviously ser, a Non·Maskabie Inlerruct I~
OP reqUIred ro eXIt (he walt slate.
NumbEr of MPU Cycles; I Interrupt mask
(ALL) Set according 10 the conlenls of Accumulato, A.
Number of Program Bytes; N NegatIve (sign bitl
Anthmetlc Plus; Z Zero (byte)
Arithmetic Minus; V Overflow, 2·s complement
Boolean AND; C Carry from bit 7
MSp Contents of memory location R Reset Always
pointed to be Stack Pointer; S Set Always
+ Boolean InclUSIve OR; t Test and set if true. cleared otherwise
oB Boolean Exclusive 0 R: • Not Affected
M Complement of M; eCR ConditIon Code Register
Transfer Into; lS least SignIficant
Bit = Zero; MS Most SigO/ficant

Courtesy Motorola Semiconductor Products, Inc.

 APPENDIX K
DAA INSTRUCTION
Decimal Adjust Accumulator
-K-l
A decimal digit may be represented as a 4 bit binary
number e.g. 9 = 1001. Similarly a 2 digit decimal number can be
represented by 8 bits, e.g. 49 10 = 01001001. This form is known
as Binary Coded Decimal or BCD, and is not to be interpreted as
a normal binary number.
Addition of decimal numbers, expressed in BCD, is
possible via the DAA ( Decimal Adjust Accumulator) instruction
as seen in this example:
L[)A A #$08
AD[) A #$(16
[)AA

The DAA instruction converts the normal hex sum, OE, to 14, the
expected decimal sum in BCD. This is accomplished internally by
adding 6 in this example (OE + 06 = 14). Details of the internal
operation of the DAA instruction are not essential to its use,
but are given at the bottom of this page. What is important is
that this instruction operates on ACC A, only after execution of
the ADD, ADC or ABA instructions.
Assuming that symbolic addresses OLDATA and NUDATA each
contain one BCD digit, write the instructions to produce the BCD
sum in ACC A.

----/
L[)A A OLDATA
ADD A NUDATA
DAA

DAA Details: When two 2 digit BCD numbers are added a "carry",
produced by the addition of the "least significant column, sets
lJ

the H bit of the CCR, e.g. 7 + 5 produces a carry and sets H,

while 7 + 2 clears H. This H bit is added to to the "most
significant" column, all operations being internal to the DAA
instruction.
 Decimal addition in~BCD is equally valid for
-
K-2
"2 digit lJ

decimal data, e.g. 47 10 + 78 10 , Here the BCD sum is 125, that is

25 plus a carry into the third column.
Write the instructions to add OLDATA and NUDATA, the
sum going to TOTAL+1 and the carry going to TOTAL. Assume that
OLDATA and NUDATA each contain 2 decimal digits in BCD form.

0100 7F 0150 eLF.: TOTAL

€11.€13: 86 0:152 LOA A OLOATA
€11.~36 88 €11.54 ADD A NUOATA
€11€19 19 DAA
(11.0A B'{ 0:15:1 STA A TOTAL+1
~3:10(:t 24 ((? E:CC FIN!
(11.0F 7C ~315(1 INC TOTAL
01:12 FINI
I
,I
~3:150 (u302 TOTAL F~t18
.-:.
c..
k1:152 0~302
121:154 012102
OL[)ATA F.:t18
NliDATA F.:t1B
2
.
.-.:!.

Lab instruments, such as digital voltmeters and

frequency counters, often use BCD format to present data to a
computer. Hence the DAA instruction vastly simplifies manipu-
lation of this data, directly in BCD form.
 Addi tion of 114 digiti' decimal data also requires the
-K-J
detection of the carry bit after the 2 least significant columns
are added. Use of the ADC (Add with Carry) instruction permits
this carry to be added in when the next 2 most significant digits
are added. Assume that OLDATA and NUDATA each contain 4 BCD
digits in 2 bytes. Write the instructions to produce the 4
digit sum in the 2 bytes labelled TOTAL.

_ _-----J/
:+:
:+: ADDITION OF 4 CHAf;.: BCD DATA. SUt'1 IN TOTAL.
:+:
l1:1l10 7F t1i50 eLF.: TOTAL
E:6 ~:::11.5]:
~31.~:::13 L[)A A OLDATA+1.
t11.£16 BE: (11.55 ADD A NU[)ATA+1.
_.
~31.(19 i'=t DAA BCD SUr1 OF 2 LO DIGITS
01.~3A Eo?" 0:151- STR A TOTAL+1.
01.li[) E:6 ~:::11.52 LDA A OLDATA
~31.1.0 89 ~31.54 ADC A NU[)ATA
ttl1.3 1.9 DAA BCD SUr1 OF .-.
~ HI DIGITS
011.4 B7 l31.5£1 STA A TOTAL
I
•
I

This process could be extended to 6, 8 or N digit BCD addition.

Note that the above program does not detect a carry beyond 4
digits; hence input should be limited to J BCD digits.
 I NDE X
Accumulator 2- 1 Label J- 5
ACIA 7- 1 LDA 2- 2
Addition - Binary 1- 2 LDX 4- 1
- Hexadecimal 1-16 Literal 2- 5
AND 2-20 Logical AND 2-20
ASCII 2- 3 LSB 1- 3
Assembler 2- 1
Mask Word 2-21
Background 11- 1 Maskable Interrupt 11- 1
Binary Number 1- 1 Machine Code 2- 2
Bit 1- 1 MSB 1- 3
Branch Offset 6- 6
Breakpoint 11-17 NEG 2-16
Byte 1-13 NOG 4-11
Non Maskable Interrupt 11-12
CCR-Condition Code Reg 5- 7 Null 4-11
Character Set- # 2- 2
- $ 2- 2 Operand 2- 3
- % 2-23 Operation Code (Op Code) 2- 3
CLR 2- 1 Operator 2- 3
Comment 3- 6 OPT 3- 7
Contact Bounce 8-16 ORA 2-25
Conversion-Bin to Dec 1- 2 ORG 3- 3
-Dec to Bin 1- 7
-Dec to Hex 1-33 Parity 7- 8
-Hex to Dec 1-14 PC (Program Counter) 6- 3
CTS 7-12 PIA 8- 1
Programmed Mode- PIA 8-10
DAA App. K PSH 10- 1
Data Buffer 7- 1 PUL 10- 1
DDR-Data Direct. Reg. 8- 1
Deferred 4-13 Read Only Buffer 7- 1
Delay 9-21 READY Bit 7- 5
DEX 4-10 Read Only Buffer 7- 1
Direct Mode 2-17 RlVIB 3- 4
RTI 11- 1
END 3- 7 RTS (Return from Sub.) 9- 1
EQU 7- 1 RTS (Request to Send) 7-12
Extended Mode 2- 9
Service Routine 11- 1
FCB 4-11 Signed Number 1-23
FCC 4-11 SP (Stack Pointer) 10- 1
FDB 4-12 STA 2-11
Foreground 11- 1 Start Bit 7- 1
Stop Bit 7- 1
Handshake Mode- PIA 8-11 Strobe lVIode- PIA 8-13
Hexadecimal (Hex) 1-12 Subtraction- Binary 1-35
- Hex 1-29
Immediate Mode 2- 2 SWI (Software Int.) 11-13
INC 2-19 Symbolic Address 3- 1
Inclusive OR 2-25
Index Mode 4- 7 TSX 10- 4
Index Register 4- 1
Initialization 2-13 Vector Address 11- 1
INX 4-10
IRQ- Interrupt Request 11- 1 Write Only Buffer 7- 1