1

€ Basics of Exceptions
€ Cortex-M4 Core Peripherals
› System Control Block (SCB)
x SCB Registers
› SysTick Timer
x Registers
x Configuration
x Code Example
› Nested Vectored Interrupt Controller (NVIC)
x Exception/Interrupt Vector Table
x Exception States
x NVIC Registers
2
€ Handling External Interrupts
› System Configuration Controller (SYSCFG)
x SYSCFG external interrupt configuration registers
(EXTICRx)
› Extended Interrupts and Events Controller (EXTI)
€ EXTI0
› Registers
› EXTI0 Configuration
› EXTI0 Code Example
€ COMP
› Registers
› Configuration
› Code Example

3
4
 • situations where the
Exceptions processor needs to stop
executing the current code

• asynchronous • synchronous
Hardware • also called Software • also called
interrupts exceptions

System Debug
Nonmaskable Maskable Fault
service call event
• cannot be • can be • related to an • used by operating
ignored ignored error condition systems
• signaled via • signaled via • caused by the SVC
RESET or NMI IRQ instruction

5
€ What is an exception?
› A special event that requires the CPU to stop normal
program execution and perform some service related to
the event.
› Examples of exceptions include
x I/O completion, timer time-out, end of conversion,
x illegal opcodes, arithmetic overflow, divide-by-0, etc.
€ Functions of exceptions
› Respond to infrequent but important events
x Alarm conditions like low battery power
x Error conditions
› I/O synchronization
x Trigger interrupt when signal on a port changes
› Periodic interrupts
x Generated by the timer at a regular rate
x Systick timer can generate interrupt when it hits zero
x Reload value + frequency determine interrupt rate
6
polling

interrupt
7
€ Interrupt maskability
› Interrupts that can be ignored by the CPU are called maskable
interrupts.
› A maskable interrupt must be enabled before it can interrupt the
CPU.
› An interrupt is enabled by setting an enable bit.
› Interrupts that can’t be ignored by the CPU are called
nonmaskable interrupts.
€ Exception priority
› Allow multiple pending interrupt requests
› Resolve the order of service for multiple pending interrupts
€ Interrupt service routine
› An interrupt handler, also known as an Interrupt Service Routine
(ISR), is a callback subroutine in microcontroller firmware whose
execution is triggered by the reception of an interrupt.
› Interrupt handlers have a multitude of functions, which vary
based on the reason the interrupt was generated.

8
 STM32 Vector Table
0x0000
€ Interrupt vector 0x0004
Initial Value of SP

Vector for Exception 1

› Starting address of the interrupt (0X8000)
handler 0x0008 Vector for Exception 2
(0X8200)
€ Interrupt vector table 0x000C
Vector for Exception 3
› table of interrupt vectors that
0x0010
associates an interrupt handler Interrupt Vector for Exception 4
with an interrupt request
€ Methods of determining interrupt 0x8000
vectors
› Predefined locations (Microchip Exception 1Handler
PIC18, 8051 variants)
› Fetching the vector from a
predefined memory location 0x8200

(HCS12, STM32)
› Executing an interrupt Exception 2 Handler
acknowledge cycle to fetch a
vector number in order to locate
the interrupt vector (68000 and
x86 families)

9
 A complete interrupt service cycle includes
€ Saving the program counter value in the stack
€ Saving the CPU status (including the CPU status
overhead

register and some other registers) in the stack

€ Identifying the cause of interrupt
€ Resolving the starting address of the
corresponding interrupt service routine
€ Executing the interrupt service routine
€ Restoring the CPU status and the program
overhead

counter from the stack

€ Restarting the interrupted program

10
€ Interrupt is a powerful concept in embedded systems for
separating the time-critical events from the others and execute
them in a prioritized manner.
€ In a typical embedded system, the embedded processor
(microcontroller) is responsible for doing more than one task (but
can do only one at a time).

Programmable Room Temperature Control 11

A thermoelectric cooler (TEC) is a device based on the Peltier effect. It typically comprises two
kinds of materials and transfers heat from one side of the device to the other while a DC
current is forced through it. The side from which heat is removed becomes cold. Contrastingly,
the side to which heat is moved becomes hot. When the current reverses its direction, the
previously "cold" side becomes hot and the previously "hot" side becomes cold.
A TEC has no moving parts or working fluids, so it is very reliable and can be very small in size.
TECs are used in many applications that require precision temperature control, including
optical modules.
12
13
Core peripheral Description
It provides system implementation information and
System Control
control. In particular It supports exception
Block
configuration, control, and processing.
Nested Vectored
It supports low latency interrupt configuration, control,
Interrupt
and processing.
Controller
Use this 24-bit count-down timer as a Real Time
System timer
Operating System (RTOS) tick timer or as a simple
(SysTick)
counter.
Memory It improves system reliability by defining the memory
Protection Unit attributes for different memory regions.
Floating-point It provides IEEE754-compliant operations on single-
Unit precision, 32-bit, floating-point values.

STM32F3 Microcontroller Programming Manual, pages 180-241 14

15
Provides:
€ Exception enables.
€ Setting or clearing exceptions to/from the pending state.
€ Exception status (Inactive, Pending, or Active). Inactive is
when an exception is neither Pending nor Active.
€ Priority setting (for configurable system exceptions)
€ The exception number of the currently executing code
and highest pending exception.

STM32F3 Microcontroller Programming Manual, pages 206-227

16
IRQ #

-14
-13
-12
-11
-10
-09
-08 Exceptions
-07
-06
-05
-04
-03
-02
-01

00
01
02
03
04
05
06

startup_stm32f30x.s
17
 Exc IRQn Exception Priority Description Vector
No. Type Address
0 Initial SP
1 Reset -3 (F) Reset 0x04
2 -14 NMI -2 (F) Non-Maskable Interrupt 0x08
3 -13 HardFault -1 (F) Default fault if other handler not 0x0C
implemented
4 -12 MemManage 0 (P) MPU violation or access to illegal 0x10
locations
5 -11 BusFault 1 (P) Fault if AHB interface receives error 0x14
6 -10 UsageFault 2 (P) Exception due to program errors 0x18
7-10 Reserved
11 -5 SVCall 3 (P) System service call via SWI instruction 0x2C
12 -4 Debug 4 (P) Break points, watch points, external 0x30
Monitor debug
13 -3 Reserved
14 -2 PendSV 4 (P) Pendable request for System Device 0x38
15 -1 SysTick 6 (P) System tick timer 0x3C

• These exceptions are controlled by the System Control Block (SCB).

• If the priority of an exception is programmable, its default value is zero.
18
Name Description Operation
ACTLR Auxiliary • disables certain aspects of functionality within
Control Register the processor.
CPUID CPUID Base • specifies the ID and version numbers, and
Register the implementation details of the processor
core.
ICSR Interrupt Control Used to:
State Register • set a pending Non-Maskable Interrupt (NMI)
• set or clear a pending PendSV
• set or clear a pending SysTick
• check for pending exceptions
• check the vector number of the highest
priority pended exception
• check the vector number of the active
exception.
VTOR Vector Table • indicates the offset of the vector table base
Offset Register address from memory address 0x00000000.
19
Name Description Operation
AIRCR Application • provides priority grouping control for the
Interrupt and exception model, endian status for data
Reset Control accesses, and reset control of the system.
Register
SCR System Control • controls features of entry to and exit from low
Register power state.

CCR Configuration • permanently enables stack alignment and

and Control causes unaligned accesses to result in a
Register Hard Fault.
SHPRx System handler • set the priority level of the exception
priority registers handlers that have configurable priority.

20
€ The SCB_AIRCR provides priority grouping control for
the exception model, endian status for data
accesses, and reset control of the system.
€ To write to this register, you must write 0x5FA to the
VECTKEY field, otherwise the processor ignores the
write.

STM32F3 Microcontroller Programming Manual, page 211

21
 Bits Name Type Reset Description
Value
31:16 VECTKEYSTAT/ R/W 0xFA05 Register key
VECTKEY Reads as 0xFA05
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
15 ENDIANESS R/W 0 Bit Data endianness. This bit reads as 0.
0: Little-endian
10:8 PRIGROUP R/W 0 Interrupt priority grouping field
This field determines the split of group priority from subpriority.
2 SYSRESETREQ R/W 0 System reset request
This is intended to force a large system reset of all major
components except for debug.
This bit reads as 0.
0: No system reset request
1: Asserts a signal to the outer system that requests a reset
1 VECTCLRACTIVE R/W 0 Reserved for Debug use. This bit reads as 0. When writing to the
register you must write 0 to this bit, otherwise behavior is
unpredictable.
0 VECTRESET R/W 0 Reserved for Debug use. This bit reads as 0. When writing to the
register you must write 0 to this bit, otherwise behavior is
unpredictable

22
€ The 3-bit PRIGROUP field allows you to split the 4-bit priority
fields into groups and subgroups.
€ For example, PRIGROUP value 6 (partition: [1:7]) creates 2
priority groups, each with 8 levels of subpriority.
€ Only the group priority determines preemption of interrupt
exceptions. When the processor is executing an interrupt
exception handler, another interrupt with the same group
priority as the interrupt being handled does not preempt
the handler.
€ If multiple pending interrupts have the same group priority,
the subpriority field determines the order in which they are
processed. If multiple pending interrupts have the same
group priority and subpriority, the interrupt with the lowest
IRQ number is processed first.
€ Configuring a peripheral interrupt is very similar to
configuring an internal Cortex exception.
23
PRIGROUP Interrupt priority level value Number of
[2:0]
Binary point Group Subpriority Group Sub
priority bits bits priorities priorities
0 0bxxxxxxx.y 7-1 0 16 None
1 0bxxxxxx.yy 7-2 1-0 16 None
2 0bxxxxx.yyy 7-3 2-0 16 None
3 0bxxxx.yyyy 7-4 3-0 16 None
4 0bxxx.yyyyy 7-5 4-0 8 2
5 0bxx.yyyyyy 7-6 5-0 4 4
6 0bx.yyyyyyy 7 6-0 2 8
7 0b.yyyyyyyy None 7-0 None 16

The NVIC_AIRCR PRIGROUP field allows us to change the size of the preemption
group field and priority subgroup. On reset this field defaults to priority group zero.
So, for example, if our MCU has four active priority bits we could select priority
group 5, which would give us four levels of preemption each with four levels of
subpriority. 24
€ The SHPR1-SHPR3 registers set the priority level (0 to 15), of
the exception handlers that have configurable priority.
€ SHPR1-SHPR3 are byte accessible.
€ The system fault handlers, the priority field and register for
each handler are:
Handler Field Register CMSIS
MemManage_Handler PRI_4 SCB_SHPR1 SCB->SHP[0]
BusFault_Handler PRI_5 SCB_SHPR1 SCB->SHP[1]
UsageFault_Handler PRI_6 SCB_SHPR1 SCB->SHP[2]
SVC_Handler PRI_11 SCB_SHPR2 SCB->SHP[7]
PendSV_Handler PRI_14 SCB_SHPR3 SCB->SHP[10]
SysTick_Handler PRI_15 SCB_SHPR3 SCB->SHP[11]

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of
each field, and bits[3:0] read as zero and ignore writes (where M=4).
SCB_SHPRx fields (PRI_y) are mapped to the SCB->SHP[z] array.

SHPRx reset value = 0x00000000 25

CMSIS name

Programming Manual name

26
 |

SCB->SHP[11]

STM32F3 Microcontroller Programming Manual, page 217

27
 28

STM32F3 Microcontroller Programming Manual, pages 228-233

€ The processor has a 24-bit system timer, SysTick, that counts
down from the reload value to zero, reloads (wraps to) the value
in the STK_LOAD register on the next clock edge, then counts
down on subsequent clocks.
€ When the processor is halted for debugging the counter does
not decrement.
€ Systick can be used to generate an exception (#15).
€ It can be used as the basic timer for an operating system, as an
alarm timer, for timing measurements, and more.

29
Bits Name Type Reset Value Description
16 COUNTFLAG R 0 Returns 1 if timer counted to 0 since
last time this register was read.
2 CLKSOURCE R/W 0 Clock source selection
0: AHB/8
1: Processor clock (AHB)
1 TICKINT R/W 0 SysTick exception request enable
0 ENABLE R/W 0 SysTick timer enable

30
€ The SysTick interrupt is an internal Cortex exception
and is handled in the system registers.
€ Some of the internal exceptions are permanently
enabled; these include the reset and NMI interrupts,
but also the SysTick timer, so there is no explicit action
required to enable the SysTick interrupt within the
NVIC.
€ To configure the SysTick interrupt we need to set the
timer going and enable the interrupt within the
peripheral itself:
SysTick->VAL = 72000-1; // Start value for the sys Tick counter
SysTick->LOAD = 72000-1; // Reload value
SysTick->CTR = 0x07; // Select AHB clock (bit 2),
// enable SysTick exception (bit 1) and
// enable Systick timer (bit 0)

31
€ This function initializes the System Timer and its interrupt, and starts
the System Tick Timer. Counter is in free running mode to generate
periodic interrupts.
› parameter: ticks Number of ticks between two interrupts
› return 0 Function succeeded
› 1 Function failed
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
/* Reload value impossible */
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1);
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);

/* set Priority for Systick Interrupt */

SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}

core_cm4.h 32
€ In the case of the SysTick timer we can create an
interrupt service routine by declaring a 'C' routine
with the matching symbolic name:

void SysTick_Handler (void)

{
….
}

€ Now with the vector table configured and the ISR

prototype defined, we can configure the NVIC to
handle the SysTick timer interrupt. Generally we need
to do two things: set the priority of the interrupt and
then enable the interrupt source.

stm32f30x_it.c 33
34
€ The NVIC is an integral part of all Cortex-M
processors and provides the processors'
outstanding interrupt handling abilities. The
Cortex-M4 supports up to 240 IRQs, 1 NMI and
further system exceptions.

35
IRQ

-14
-13
-12
-11
-10
-09
-08
-07
-06
-05
-04
-03
-02
-01

00
01
02
03
04
05
06

startup_stm32f30x.s
36
 Exc IRQn Exception Priority Description Associated
No. Type Peripheral in
the STM32F3
16 0 IRQ0 7 (P) Window Watchdog interrupt WWDG
17 1 IRQ1 8 (P) PVD through EXTI line 16 PVD
detection interrupt
18 2 IRQ2 9 (P) Tamper and TimeStamp interrupts TAMPER_STAMP
through the EXTI line 19
19 3 IRQ3 . . RTC_WKUP
20 4 IRQ4 . . FLASH
21 5 IRQ5 . . RCC
22 6 IRQ6 . . EXTI0
23 7 IRQ7 . . EXTI1
. . . . . .
. . . . . .
16+n n IRQn n+7 (P) Interrupción externa #n .

• These interrupts are controlled by the Nested Vector Interrupt

Controller (NVIC).
• If the priority of an exception is programmable, its default value is zero.
37
 IRQn Peripheral IRQn Peripheral IRQn Peripheral
0 WWDG 30 TIM4 60 DMA2_Channel5
1 PVD 31 I2C1_EV 61 ADC4
2 TAMPER_STAMP 32 I2C1_ER 62
3 RTC_WKUP 33 I2C2_EV 63
4 FLASH 34 I2C2_ER 64 COMP1_2_3
IRQ Number versus Peripheral interrupt

5 RCC 35 SPI1 65 COMP4_5_6

6 EXTI0 36 SPI2 66 COMP7
7 EXTI1 37 USART1 67
8 EXTI2_TS 38 USART2 68
9 EXTI3 39 USART3 69
10 EXTI4 40 EXTI15_10 70
11 DMA1_Channel1 41 RTC_Alarm 71

stm32f30x.h
12 DMA1_Channel2 42 USBWakeUp 72
13 DMA1_Channel3 43 TIM8_BRK 73
14 DMA1_Channel4 44 TIM8_UP 74 USB_HP
15 DMA1_Channel5 45 TIM8_TRG_COM 75 USB_LP
16 DMA1_Channel6 46 TIM8_CC 76 USBWakeUp_RMP
17 DMA1_Channel7 47 ADC3 77
18 ADC1_2 48 78
19 USB_HP_CAN1_TX 49 79
20 USB_LP_CAN1_RX0 50 80
21 CAN1_RX1 51 SPI3 81 FPU
22 CAN1_SCE 52 UART4
23 EXTI9_5 53 UART5
24 TIM1_BRK_TIM15 54 TIM6_DAC
25 TIM1_UP_TIM16 55 TIM7
26 TIM1_TRG_COM_TIM17 56 DMA2_Channel1
27 TIM1_CC 57 DMA2_Channel2
28 TIM2 58 DMA2_Channel3
38
29 TIM3 59 DMA2_Channel4
€ The NVIC is designed for fast and efficient interrupt
handling; on a Cortex-M4 you will reach the first line
of C code in your interrupt routine after 12 cycles for
a zero wait state memory system.
€ This interrupt latency is fully deterministic so from any
point in the background (non-interrupt) code you will
enter the interrupt with the same latency.
€ Multi-cycle instructions can be halted with no
overhead and then resumed once the interrupt has
finished.

39
€ Inactive:
› The exception is not active and not pending.
€ Pending:
› The exception is waiting to be serviced by the processor.
› An interrupt request from a peripheral or from software can
change the state of the corresponding interrupt to pending.
€ Active:
› An exception that is being serviced by the processor but has not
completed.
› An exception handler can interrupt the execution of another
exception handler. In this case both exceptions are in the active
state.
€ Active and pending
› The exception is being serviced by the processor and there is a
pending exception from the same source.

40
€ Each of the USER peripherals is controlled
by the IRQ register blocks.
› Each user peripheral has an Interrupt Enable
bit. These bits are located across two 32-bit
IRQ Set Enable registers.
› There are matching IRQ Clear Enable
registers that are used to disable an interrupt
source.
› The NVIC also includes pending and active
registers that allow you to determine the
current condition of an interrupt source.

41
Address Name Type Description
0xE000E100 - NVIC_ISER0 - RW Interrupt Set-Enable Registers
0xE000E10B NVIC_ISER2
0xE000E180 - NVIC_ICER0 - RW Interrupt Clear-Enable Registers
0xE000E18B NVIC_ICER2
0xE000E200 - NVIC_ISPR0 - RW Interrupt Set-Pending Registers
0xE000E20B NVIC_ISPR2
0xE000E280 - NVIC_ICPR0 - RW Interrupt Clear-Pending Registers
0xE000E28B NVIC_ICPR2
0xE000E300 - NVIC_IABR0 - RO Interrupt Active Bit Register
0xE000E30B NVIC_IABR2
0xE000E400 - NVIC_IPR0 - RW Interrupt Priority Register
0xE000E453 NVIC_IPR20
0xE000EF00 NVIC_STIR WO Software trigger interrupt register
Write to the STIR to generate a Software Generated Interrupt (SGI). The value to be written is the
Interrupt ID of the required SGI, in the range 0-239. For example, a value of 3 specifies interrupt
IRQ3. 42
€ In the STM32, there are 21 priority registers.
€ Each priority register is divided into four eight bit
priority fields, each field being assigned to an
individual interrupt vector.
€ The STM32 only uses half of this field to implement 16
levels of priority.
› However, you should note that the active priority bits are
in the upper nibble of each priority field.
€ By default the priority field defines 16 levels of priority
with level zero the highest and 15 the lowest.
€ It is also possible to format the priority field into priority
groups and subgroups, by programming the
PRIGROUP field in the Application Interrupt and Reset
Control Register (SCB->AIRCR).
7 6 5 4 3 2 1 0
D/C D/C D/C D/C
43
€ The NVIC_IPR0-IPR20 registers provide an 8-bit priority
field for each interrupt. These registers are byte-
accessible. Each register holds four priority fields, that
map to four elements in the CMSIS interrupt priority
array (NVIC->IP[0] to NVIC->IP[80])

Note. the lower the value, the greater the priority of the corresponding interrupt. 44
CMSIS Register Cortex-M3 and
Register Name
Name Cortex-M4
NVIC->ISER[] NVIC_ISER0..2 Interrupt Set-Enable Registers
NVIC->ICER[] NVIC_ICER0..2 Interrupt Clear-Enable Registers
NVIC->ISPR[] NVIC_ISPR0..2 Interrupt Set-Pending Registers
NVIC->ICPR[] NVIC_ICPR0..2 Interrupt Clear-Pending Registers
NVIC->IABR[] NVIC_IABR0..2 Interrupt Active Bit Register
NVIC->IP[] NVIC_IPR0..20 Interrupt Priority Register
NVIC->STIR STIR Software Triggered Interrupt Register
Write to the STIR to generate a Software Generated Interrupt (SGI). The value to
be written is the Interrupt ID of the required SGI, in the range 0-239. For example,
a value of 0x03 specifies interrupt IRQ3.

45
46
€ External events/interrupts are connected to NVIC through
the Extended Interrupts and Events Controller (EXTI), which
main features are:
› support generation of up to 36 event/interrupt requests(28
external and 8 internal lines);
› mapping of multiple GPIO lines to 16 NVIC external interrupt
inputs
› Independent configuration of each line as an external or an
internal event request;
› Independent mask on each event/interrupt line
› Automatic disable of internal lines when system is not in STOP
mode
› Independent trigger for external event/interrupt line
› Dedicated status bit for external interrupt line;
› Emulation for all the external event requests.
€ The STM32F30xx is able to handle external or internal
events in order to wake up the core (WFE).

STM32F3 Microcontroller Reference Manual, pages 186-198 47

48
€ The SYSCFG register manages the
external interrupt line connection to the
GPIOs –among other purposes.
€ Por this purpose, the SYSCFG clock
should be enabled.

49
Bit 0 SYSCFGEN: SYSCFG clock enable
0: SYSCFG clock disabled
1: SYSCFG clock enabled

50
STM32F3 Microcontroller Reference Manual, pages 156-161
51
SYSCFG->EXTICR1 (SYSCFG external interrupt configuration register 1)
bits[3:0] bits[7:4] bits[11:8] bits[15:12]
EXTI0 0 PA0 EXTI1 0 PA1 EXTI2 0 PA2 EXTI3 0 PA3
1 PB0 1 PB1 1 PB2 1 PB3
2 PC0 2 PC1 2 PC2 2 PC3
3 PD0 3 PD1 3 PD2 3 PD3
4 PE0 4 PE1 4 PE2 4 PE3
5 PF0 5 PF1 5 PF2 5 PF3

SYSCFG->EXTICR2 (SYSCFG external interrupt configuration register 2)

bits[3:0] bits[7:4] bits[11:8] bits[15:12]
EXTI4 0 PA4 EXTI5 0 PA5 EXTI6 0 PA6 EXTI7 0 PA7
1 PB4 1 PB5 1 PB6 1 PB7
2 PC4 2 PC5 2 PC6 2 PC7
3 PD4 3 PD5 3 PD6 3 PD7
4 PE4 4 PE5 4 PE6 4 PE7
5 PF5 5 PF6 5 PF7

52
 SYSCFG->EXTICR3 (SYSCFG external interrupt configuration register 3)

bits[3:0] bits[7:4] bits[11:8] bits[15:12]

EXTI8 0 PA8 EXTI9 0 PA9 EXTI10 0 PA10 EXTI11 0 PA11
1 PB8 1 PB9 1 PB10 1 PB11
2 PC8 2 PC9 2 PC10 2 PC11
3 PD8 3 PD9 3 PD10 3 PD11
4 PE8 4 PE9 4 PE10 4 PE11
5 PF9 5 PF10 5 PF11

SYSCFG->EXTICR4 (SYSCFG external interrupt configuration register 4)

bits[3:0] bits[7:4] bits[11:8] bits[15:12]

EXTI12 0 PA12 EXTI13 0 PA13 EXTI14 0 PA14 EXTI15 0 PA15
1 PB12 1 PB13 1 PB14 1 PB15
2 PC12 2 PC13 2 PC14 2 PC15
3 PD12 3 PD13 3 PD4 3 PD15
4 PE12 4 PE13 4 PE4 4 PE15
5 PF13 5 PF4 5 PF15

53
Register CMSIS
SYSCFG_EXTICR1 SYSCFG->EXTICR[0]
SYSCFG_EXTICR2 SYSCFG->EXTICR[1]
SYSCFG_EXTICR3 SYSCFG->EXTICR[2]
SYSCFG_EXTICR4 SYSCFG->EXTICR[3]

54
EXTI Connection EXTI Connection EXTI Connection EXTI Connection
Line Line Line Line
EXTI16 PVD output EXTI21 Comparator EXTI26* USART2 EXTI31 Comparator
1 output wakeup 5 output
EXTI17 RTC Alarm EXTI22 Comparator EXTI27* reserved EXTI32 Comparator
event 2 output 6 output
EXTI18 USB Device EXTI23* I2C1 EXTI28* USART3 EXTI33 Comparator
FS wakeup wakeup wakeup 7 output
event
EXTI19 RTC tamper EXTI24* I2C2 EXTI29 Comparator EXTI34* UART4
and wakeup 3 output wakeup
Timestamps
EXTI20 RTC wakeup EXTI25* USART1 EXTI30 Comparator EXTI35* UART5
wakeup 4 output wakeup
Note: EXTI lines 23, 24, 25, 26, 27, 28, 34 and 35 are internal.

55
€ The active edge of each external interrupt line can
be chosen independently, whilst for internal interrupt
the active edge is always the rising one.
€ An interrupt could be left pending
› In case of an external one, a status register is instantiated
and indicates the source of the interrupt; an event is
always a simple pulse and it’s used for triggering the core
wake-up.
› For internal interrupts, the pending status is assured by the
generating peripheral, so no need for a specific flag.
€ Each input line can be masked independently for
interrupt or event generation, in addition the internal
lines are sampled only in STOP mode. This controller
allows also to emulate the (only) external events by
software, multiplexed with the corresponding
hardware event line, by writing to a dedicated
register.
56
57
Register CMSIS Operation

Interrupt mask EXTI_IMR1 EXTI->IMR 0: Interrupt request from Line x is masked

register EXTI_IMR2 EXTI->IMR2 1: Interrupt request from Line x is not masked
Event mask EXTI_EMR1 EXTI->EMR 0: Event request from Line x is masked
register EXTI_EMR2 EXTI->EMR2 1: Event request from Line x is not masked
Rising trigger EXTI_RTSR1 EXTI->RTSR 0: Rising trigger disabled (for Event and Interrupt) for input line
selection register EXTI_RTSR2 EXTI->RTSR2 1: Rising trigger enabled (for Event and Interrupt) for input line.
Falling trigger EXTI_FTSR1 EXTI->FTSR 0: Falling trigger disabled (for Event and Interrupt) for input line
selection register EXTI_FTSR2 EXTI->FTSR2 1: Falling trigger enabled (for Event and Interrupt) for input line.
Software EXTI_SWIER1 EXTI->SWIER Writing a ‘1’ to this bit when it is at ‘0’ sets the corresponding
interrupt event EXTI_SWIER2 EXTI->SWIER2 pending bit in the EXTI_PR register. If the interrupt is enabled on
register this line on the EXTI_IMR and EXTI_EMR registers, an interrupt
request is generated. This bit is cleared by writing a ‘1’ into the
corresponding bit in the EXTI_PR register .
Pending register EXTI_PR1 EXTI->PR 0: No trigger request occurred
EXTI_PR2 EXTI->PR2 1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the
external interrupt line. This bit is cleared by writing a ‘1’ to the bit
or by changing the sensitivity of the edge detector.

Two configuration modes:

• Interrupt mode: generate interrupts with external lines edges
• Event mode: generate pulse to wake-up system from SLEEP and STOP modes

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59
€ To configure an external interrupt one must
configure the external interrupt (EXTI)
peripheral as well as the NVIC peripheral. The
general procedure is as follows:
› Configure the EXTIxx bits in the SYSCFG_EXTICRx
registers to map the GPIO pin(s) of interest to the
appropriate external interrupt lines (EXTI0-EXTI15).
› For the external interrupt lines (EXTIxx) of interest,
choose a signal change that will trigger the external
interrupt. The signal change can be a rising edge, a
falling edge or both. These can be set via the
EXTI_RTSR (rising) and the EXTI_FTSR (falling) registers.
› Unmask the external interrupt line(s) of interest. by
setting the bit corresponding to the EXTI line of
interest in the EXTI_IMR register.

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› Set the priority for the interrupt vector in question in
the NVIC either via the CMSIS based
“NVIC_SetPriority()” function or through the IPR0-IPR7
registers.
› Enable the interrupt in the NVIC either via the CMSIS
based “NVIC_EnableIRQ()” function or via the ISER
register.
› Write your interrupt service routine (ISR).
› Inside your interrupt service routine, check the source
of the interrupt…either the GPIO pin directly or the
external interrupt line. Once you figure out which one
triggered the interrupt, perform the interrupt
processing scheme associated with it. Make sure that
you clear the corresponding pending bit of the
external interrupt lines of interest in the EXTI_PR
(external interrupt pending register) register by writing
a ’1′ to it.
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# Action Registers to be modified
1 Enable GPIOx clock RCC->AHBENR.IOPxEN
2 Configure the GPIOx pin as floating input GPIOx->MODER.MODERy
GPIOx->PUPDR.PUPDRy
3 Enable SYSCFG clock RCC->APB2ENR.SYSCFGEN
4 Select the GPIOx pin as input for the SYSCFG->EXTICR[z]
interrupt line INTIy
5 Unmask INTy EXTI_IMRx
5 Select the edge or edges that could EXTI_RTSRx
trigger the interrupt EXTI_FTSRx
6 Enable the interrupt line NVIC->ISER[z]
7 Select the priority and subpriority of the SCB->AIRCR.PRIGROUP
interrupt NVIC->IP[y]

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 63

STM32F3 Microcontroller Reference Manual, pages 324-344

€ The STM32F30xxx embeds seven general purpose
comparators that can be used either as standalone
devices (all terminal are available on I/Os) or combined
with the timers.
€ They can be used for a variety of functions including:
› wake-up from low-power mode triggered by an analog signal;
› analog signal conditioning;
› cycle-by-cycle current control loop when combined with the
DAC and a PWM output from a timer.)
€ Rail-to-rail comparators
€ Each comparator has configurable positive and negative
inputs used for flexible voltage selection:
› Multiplexed I/O pins
› DAC channel 1 or DAC channel 2
› Internal reference voltage and three submultiple values (1/4, 1/2,
3/4) provided by scaler (buffered voltage divider).

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€ Programmable hysteresis
€ Programmable speed and consumption
€ The outputs can be redirected to an I/O or to multiple
timer inputs for triggering:
› Capture events
› OCref_clr events (for cycle-by-cycle current control)
› Break events for fast PWM shutdowns
€ COMP1 and COMP2, COMP3/COMP4, and
COMP5/COMP6 comparators can be combined in a
window comparator. COMP7 does not support the
window mode.
€ Comparators output with blanking source
€ Each comparator has interrupt generation capability with
wake-up from Sleep and Stop modes (through the EXTI
controller)

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6

COMP1INMSEL[2:0]

COMP1POL

COMP1OUTSEL[3:0]

COMP2INPSEL

0
6

COMP2POL
COMP2INMSEL[2:0]

COMP2OUTSEL[3:0]

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€ The COMP clock provided by the clock
controller is synchronous with the PCLK2 (APB2
clock).
€ There is no clock enable control bit provided in
the RCC controller. To use a clock source for
the comparator, the SYSCFG clock enable
control bit must be set in the RCC controller.
€ Note: The polarity selection logic and the
output redirection to the port works
independently from the PCLK2 clock. This
allows the comparator to work even in Stop
mode.
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€ The I/Os used as comparators inputs must be
configured in analog mode in the GPIOs registers.
€ The comparator output can be connected to the
I/Os using the alternate function channel given in
“Alternate function mapping” table in the datasheet.
€ The output can also be internally redirected to a
variety of timer input for the following purposes:
› Emergency shut-down of PWM signals, using BKIN and
BKIN2 inputs
› Cycle-by-cycle current control, using OCref_clr inputs
› Input capture for timing measures
€ It is possible to have the comparator output
simultaneously redirected internally and externally.

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€ The comparator outputs are internally
connected to the Extended interrupts and
events controller (EXTI). Each comparator has
its own EXTI line and can generate either
interrupts or events. The same mechanism is
used to exit from low power modes.

Power mode
€ The comparator power consumption versus
propagation delay can be adjusted to have
the optimum trade-off for a given application
using the bits COMPxMODE[1:0] in COMPx_CSR
registers

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 Bits NAME FUNCTION OPERATION

31 COMP1LOCK Comparator 1 0: COMP1_CSR is read-write.

lock 1: COMP1_CSR is read-only.
30 COMP1OUT Comparator 1 0: Output is low (non-inverting input below
output inverting input).
1: Output is high (non-inverting input above
inverting input).
20:18 COMP1_BLANKING Comparator 1 000: No blanking
blanking source 001: TIM1 OC5 selected as blanking source
010: TIM2 OC3 selected as blanking source
011: TIM3 OC3 selected as blanking source
17:16 COMP1HYST[1:0] Comparator 1 00: No hysteresis
hysteresis 01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
15 COMP1POL Comparator 1 0: Output is not inverted
output polarity 1: Output is inverted
13:10 COMP1OUTSEL[3:0] Comparator 1 These bits select which Timer input must be
output selection connected with the comparator1 output.

STM32F3 Microcontroller Reference Manual, pages 330-331 70

Bits NAME FUNCTION OPERATION

6:4 COMP1INMSEL[2:0] Comparator 1 inverting input 000: 1/4 of Vrefint

selection 001: 1/2 of Vrefint
010: 3/4 of Vrefint
011: Vrefint
100: COMP1_INM4 (PA4 or
DAC1 output if enabled)
101: COMP1_INM5 (PA5 or
DAC2 output if enabled)
110: COMP1_INM6 (PA0)
111: Reserved
3:2 COMP1MODE[1:0] Comparator 1 mode 00: High speed
01: Medium speed
10: Low power
11: Ultra-low power
1 COMP1SW1 Comparator 1 non inverting input 0: Switch open
connection to DAC output. 1: Switch closed
0 COMP1EN Comparator 1 enable 0: Comparator 1 disabled
1: Comparator 1 enabled

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